Ordering number : ENA1954A LC88F85D0A CMOS IC FROM 256K byte, RAM 8K byte on-chip 16-bit 1-chip Microcontroller http://onsemi.com Overview The LC88F85D0A is a 16-bit microcomputer that, centered around an Xstormy16 CPU core, integrates on a single chip a number of hardware features such as 256K bytes of flash ROM (onboard programmable), 8K bytes of RAM, five 16-bit timers, a time base timer, a synchronous SIO interface with automatic transfer function, a single-master I2C/synchronous SIO interface, two asynchronous SIO (UART) interfaces, a remote control receiver, LCD dedicated RAM, an LCD dot-matrix driver, a 12-bit-resolution 8-channel AD converter, a watchdog timer, a system clock frequency divider, and a 35-source 10-vector interrupt feature. Features Xstromy16 CPU • 4G-byte address space • General-purpose registers: 16 bits × 16 Flash ROM • Onboard programmable with a wide range of supply voltages: 3.0 to 5.5V • Block erasable in 512-byte/1K-byte units • Data writing in 2-byte units • 262144 × 8 bits RAM • Data: 8192 × 8 bits • LCD display: 128 × 16 bits * This product is licensed from Silicon Storage Technology, Inc. (USA). Semiconductor Components Industries, LLC, 2013 May, 2013 Ver.1.10 42512HKIM 20120328-S00010 No.A1954-1/31 LC88F85D0A Minimum instruction cycle time (tCYC) • 100ns (10MHz) VDD = 4.5 to 5.5V • 125ns (8MHz) VDD = 3.0 to 5.5V • 500ns (2MHz) VDD = 2.0 to 5.5V Ports • Normal withstand voltage I/O ports Ports whose I/O direction specifiable in 1-bit units: 20 (P0n, P1n, P20 to P23) • LCD (Pins COM16/SEG0 to COM31/SEG15 are multiplexed with COM and SEG.) LCD driver bias power supply pins 4 (VLCD1 to VLCD4) Step-up capacitor pins 2 (CUP00, CUP01) 16 common mode Segment output 64 (SEG0 to SEG63) Common output 16 (COM0 to COM15) 32 common mode Segment output 48 (SEG16 to SEG63) Common output 32 (COM0 to COM31) • Oscillation dedicated ports 4 (XT1, XT2, CF1, CF2) • Reset pin 1 (RESB) • TEST pin 1 (TEST) • LCD port power pins 2 (LCDVSS0, LCDVSS1) • Power pins 2 (VDD, VSS) LCD • LCD power supply • Number of dots • Contrast • LCD frame frequency : Capacitor step-up type : 1024 (64 segments × 16 commons) / 1536 (48 segments × 32 commons) : Selectable from 16 levels : Selectable from 4 frequencies Timers • Timer 0: 16-bit timer that supports PWM/toggle outputs <1> With 5-bit prescaler <2> 8-bit PWM × 2 / 8-bit timer + 8-bit PWM split mode selectable <3> Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 1: 16-bit timer with a capture register <1> With 5-bit prescaler <2> Can be divided into 8-bit timer × 2 channels <3> Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 3: 16-bit timer that supports PWM/toggle outputs <1> With 8-bit prescaler <2> 8-bit timer × 2 channels / 8-bit timer + 8-bit PWM split mode selectable <3> Clock source selectable from system clock, OSC0, OSC1, and external events • Timer 4: 16-bit timer that supports toggle output <1> Clock source selectable from system clock and prescaler 0 • Timer 5: 16-bit timer that supports toggle output <1> Clock source selectable from system clock and prescaler 0 * The prescaler 0 consists of 4 bits and its clock source is selectable from the system clock, OSC0, and OSC1. • Base timer <1> The clock can be selected from OSC0 (32.768kHz crystal oscillator) and the frequency-divided output of the system clock. <2> Interrupts can be generated in 7 time schemes. Realtime clock (RTC) <1> Calendar function from January 1, 2000 to December 31, 2799 (with automatic leap year compensation) <2> Independent counter configuration for century, year, month, day, hour, minute, and second <3> Programmable count clock correction function No.A1954-2/31 LC88F85D0A Serial interfaces • SIO0: 8-bit synchronous SIO <1> LSB first/MSB first selectable <2> Supports communication of less than 8 bits (1 to 8 bits specifiable). <3> Built-in 8-bit baudrate generator (transfer clock cycles of 4 tCYC to 512 tCYC) <4> Automatic continuous data transfer (9 to 32768 bits specifiable in 1-bit units) <5> Interval function (interval time specifiable in 0 to 64 tSCK units) <6> Wakeup function • SMIIC0: Single-master I2C/8-bit synchronous SIO Mode 0: Single-master master mode communication Mode 1: 8-bit synchronous serial I/O (MSB first) • UART0 <1> Data length: 8 bits (LSB first) <2> Start bits: 1 bit <3> Stop bits: 1 bit <4> Parity bits: None/even parity/odd parity <5> Transfer rate: 4/8 tCYC <6> Baudrate clock source: The P07 input signal is used as a 1 cycle signal (T0PWMH can be used as the clock source) or a timer 4 period. <7> Full duplex communication • UART2 <1> Data length: 8 bits (LSB first) <2> Start bits: 1 bit <3> Stop bits: 1/2 bit <4> Parity bit: None/even parity/odd parity <5> Transfer rate: 8 to 4096 tCYC <6> Baudrate clock source: System clock/OSC0/OSC1/P21 input signal <7> Wakeup function <8> Full duplex communication AD converter <1> 8/12-bit resolution selectable <2> Analog inputs: 12 channels <3> Comparator mode <4> Automatic reference voltage generation Watchdog timer <1> Runs on the base timer + internal watchdog timer dedicated counter. <2> Interrupt or reset signals selectable Infrared remote control receiver <1> Noise rejection function (Noise filter time constant: Approx. 120μs when the 32.768kHz crystal oscillator is selected as the reference clock source) <2> Supports PPM (Pulse Position Modulation), Manchester and other encoding systems. <3> HOLDX mode release function Interrupts (peripheral function) Either "Normal" or "LC888300 Compatible" mode is selectable by user option. * Note: The "LC888300 Compatible" mode is an option that is available to provide compatibility between this model and the LC888300. It is to be unavailable in future developed models. <1> Provides three levels of multiplex interrupt control. Any interrupt request of the level equal to or lower than the current interrupt is not accepted. <2> When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No.A1954-3/31 LC88F85D0A • Normal mode: 35 sources (15 modules), 10 vectors No. Vector Interrupt Module 1 08000H 2 08004H Base timer (2) 3 08008H Timer 0 (2) 4 08018H Timer 1 (2)/UART2 (4) 5 0801CH SMIIC0 (1) 6 08020H Timer 3 (2)/infrared remote control receiver (4) Watchdog timer (1) 7 08024H Timer 4 (1) 8 08030H ADC (1)/timer 5 (1) 9 08038H SIO0 (2) 10 0803CH Port 0 (3)/RTC2 (1)/SEGINT (8) • LC888300 Compatible mode: 35 sources (15 modules), 13 vectors No. Vector 1 08000H Interrupt Module Watchdog timer (1) 2 08004H Base timer (2) 3 08008H Timer 0 (2) 4 08018H SIO0 (2) 5 0801CH Timer 1 (2) 6 08020H UART2 (4) 7 08024H Timer 3 (2) 8 08028H Timer 4 (1) 9 0802CH Timer 5 (1) 10 08030H ADC (1) 11 08034H SMIIC0 (1) 12 08038H Infrared remote control receiver (4) 13 0803CH Port 0 (3)/RTC2 (1)/SEGINT (8) • Priority levels X > H > L • When interrupts of the same level occur at the same time, an interrupt with a smaller vector address is given priority. • The number in parentheses indicates the number of sources in a module. Subroutine stack: 8K-byte RAM area • Subroutine calls that automatically save the PSW, interrupt vector call: 6 bytes • Subroutine calls that do not automatically save the PSW: 4 bytes Multiplication/division instructions • 16 bits × 16 bits (18 tCYC execution time) • 16 bits ÷ 16 bits (18 to 19 tCYC execution time) • 32 bits ÷ 16 bits (18 to 19 tCYC execution time) ■Oscillator circuits • RC oscillator circuit (internal): • CF oscillator circuit: • RC oscillator circuit (external RCR1): • Crystal oscillator circuit (Rf built-in): • RC oscillator circuit (external RCR0): • SLRC oscillator circuit (internal): For system clock For system clock (OSC1) For system clock (OSC1) For low-speed system clock (OSC0) (option available) For low-speed system clock (OSC0) For system clock (used during exception processing) ■System clock frequency divider function • Can run on low consumption current. • Supports frequency-dividing of 1/1 to 1/128 of the system clock Standby function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) HALT mode is released by a system reset or an interrupt . Continued on next page. No.A1954-4/31 LC88F85D0A Continued from preceding page. • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) OSC1, RC, and OSC0 oscillations automatically stop. 2) There are five ways of releasing the HOLD mode: <1> Setting the reset pin to the low level <2> Having an interrupt source established at port 0 <3> Having an interrupt source established at SIO0 <4> Having an interrupt source established at UART2 <5> Having an interrupt source established at SEGINT • HOLDX mode: Suspends instruction execution and the operation of all the circuits except the peripheral circuits running on OSC0. 1) OSC1 and RC oscillators automatically stop operation. 2) OSC0 retains the state established when the HOLDX mode is entered. 3) There are seven ways of releasing the HOLDX mode: <1> Setting the reset pin to the low level <2> Having an interrupt source established at port 0 <3> Having an interrupt source established at SIO0 <4> Having an interrupt source established at UART2 <5> Having an interrupt source established at SEGINT <6> Having an interrupt source established in the base timer or RTC2 circuit <7> Having an interrupt source established in the infrared remote control receiver circuit On-chip debugger function • Supports software debugging with the microcontroller mounted on the target board. • Supports source line debugging, tracing, breakpoint manipulation, and realtime display. • Single-wire communication Operating temperature • -20 to +75°C Package form • TQFP120 (14×14) (lead-free type) Development tools • On-chip debugger: EOCUIF1 + LC88F85D0A Package Dimensions unit : mm (typ) 3257A 14.0 16.0 0.5 16.0 14.0 120 1 0.4 0.15 0.125 0.1 1.2MAX (1.0) (1.2) SANYO : TQFP120(14X14) No.A1954-5/31 LC88F85D0A Pad Assignment : 4.10mm × 3.40mm : 59μm : 80μm : 280μm ± 20μm □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 • Chip size (X × Y) • PAD opening siz • PAD pitch • Chip thickness X (0, 0) □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 62 61 60 59 58 57 56 55 54 53 □ □ □ □ □ □ □ □ 52 51 50 49 48 47 46 45 □ □ □ □ □ □ □ □ 44 43 42 41 40 39 38 37 □ □ □ □ □ □ □ Y 5 135 136 □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ 1 2 3 4 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 36 35 34 33 • Note: Package pin numbers differ from chip pad numbers. The numbers shown in the above figure are pad numbers. No.A1954-6/31 LC88F85D0A Table of PAD Coordinates Pad No. Pin Name 1 Coordinate Pad No. Pin Name -1569.9 48 -1567.9 -1569.9 -1483.2 -1569.9 VLCD1 -1403.2 -1569.9 5 TST -1184.0 -1569.9 52 6 XT2 -890.0 -1569.9 53 7 XT1 -781.5 -1569.9 54 SEG46 8 RESB X μm Y μm VLCD4 -1647.9 2 VLCD3 3 VLCD2 4 9 10 VDD 11 Coordinate X μm Y μm SEG52 1958.5 208.2 49 SEG51 1958.5 298.2 50 SEG50 1958.5 388.2 51 SEG49 1958.5 478.2 SEG48 1958.5 568.2 SEG47 1919.9 710.0 1919.9 790.0 -670.0 -1569.9 55 SEG45 1919.9 870.0 -494.5 -1569.9 56 SEG44 1919.9 950.0 -374.5 -1569.9 57 SEG43 1919.9 1030.0 1110.0 -263.5 -1569.9 58 SEG42 1919.9 12 CF1 -165.0 -1569.9 59 SEG41 1919.9 1190.0 13 CF2 -85.0 -1569.9 60 SEG40 1919.9 1280.0 10.0 -1569.9 61 SEG39 1919.9 1370.0 1460.0 14 15 VSS 16 110.0 -1569.9 62 SEG38 1919.9 210.0 -1569.9 63 LCDVSS1 1420.0 1569.9 17 P00 300.0 -1569.9 64 SEG37 1300.0 1569.9 18 P01 380.0 -1569.9 65 SEG36 1190.0 1569.9 19 P02 460.0 -1569.9 66 SEG35 1080.0 1569.9 20 P03 540.0 -1569.9 67 SEG34 990.0 1569.9 21 P04 620.0 -1569.9 68 SEG33 910.0 1569.9 22 P05 700.0 -1569.9 69 SEG32 830.0 1569.9 23 P06 780.0 -1569.9 70 SEG31 750.0 1569.9 24 P07 860.0 -1569.9 71 SEG30 670.0 1569.9 25 P10 940.0 -1569.9 72 SEG29 590.0 1569.9 26 P11 1020.0 -1569.9 73 SEG28 510.0 1569.9 27 P12 1100.0 -1569.9 74 SEG27 430.0 1569.9 28 P13 1180.0 -1569.9 75 SEG26 350.0 1569.9 29 P14 1260.0 -1569.9 76 SEG25 270.0 1569.9 30 P15 1340.0 -1569.9 77 SEG24 190.0 1569.9 31 P16 1420.0 -1569.9 78 SEG23 110.0 1569.9 32 P17 1500.0 -1569.9 79 SEG22 30.0 1569.9 33 P20 1919.9 -1415.0 80 SEG21 -50.0 1569.9 34 P21 1919.9 -1325.0 81 SEG20 -130.0 1569.9 35 P22 1919.9 -1192.0 82 SEG19 -210.0 1569.9 36 P23 1919.9 -1057.0 83 SEG18 -290.0 1569.9 37 SEG63 1958.5 -871.8 84 SEG17 -370.0 1569.9 38 SEG62 1958.5 -781.8 85 SEG16 -450.0 1569.9 39 SEG61 1958.5 -691.8 86 - - - 40 SEG60 1958.5 -601.8 87 COM31/SEG15 -620.0 1569.9 41 SEG59 1958.5 -511.8 88 - - - 42 SEG58 1958.5 -421.8 89 COM30/SEG14 -780.0 1569.9 43 SEG57 1958.5 -331.8 90 - - - 44 SEG56 1958.5 -241.8 91 COM29/SEG13 -940.0 1569.9 45 SEG55 1958.5 -61.8 92 - - - 46 SEG54 1958.5 28.2 93 COM28/SEG12 -1100.0 1569.9 47 SEG53 1958.5 118.2 94 - - - Continued on next page. No.A1954-7/31 LC88F85D0A Continued from preceding page. Coordinate Pad No. Pin Name X μm Y μm 95 COM27/SEG11 -1260.0 96 - 97 98 99 Coordinate Pad No. Pin Name 1569.9 116 - - - - - 117 COM16/SEG0 -1919.9 60.0 COM26/SEG10 -1420.0 1569.9 118 COM15 -1919.9 -20.0 - - - 119 COM14 -1919.9 -100.0 COM25/SEG9 -1580.0 1569.9 120 COM13 -1919.9 -180.0 -260.0 X μm Y μm 100 - - - 121 COM12 -1919.9 101 COM24/SEG8 -1919.9 1340.0 122 COM11 -1919.9 -340.0 102 - - - 123 COM10 -1919.9 -420.0 103 COM23/SEG7 -1919.9 1180.0 124 COM9 -1919.9 -500.0 104 - - - 125 COM8 -1919.9 -580.0 105 COM22/SEG6 -1919.9 1020.0 126 COM7 -1919.9 -660.0 106 - - - 127 COM6 -1919.9 -740.0 107 COM21/SEG5 -1919.9 860.0 128 COM5 -1919.9 -820.0 108 - - - 129 COM4 -1919.9 -900.0 109 COM20/SEG4 -1919.9 700.0 130 COM3 -1919.9 -980.0 110 - - - 131 COM2 -1919.9 -1060.0 111 COM19/SEG3 -1919.9 540.0 132 COM1 -1919.9 -1140.0 112 - - - 133 COM0 -1919.9 -1220.0 113 COM18/SEG2 -1919.9 380.0 134 LCSVSS0 -1919.9 -1320.0 114 - - - 135 CUP00 -1919.9 -1443.3 115 COM17/SEG1 -1919.9 220.0 136 CUP01 -1919.9 -1523.3 Note: • The coordinate values shown in the above table represent the coordinates of the pin pads measured with the center coordinates of the IC set to (0, 0). • There are three pads for each of the VDD and VSS pins. They should be triple bonded. No.A1954-8/31 LC88F85D0A 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 COM25/SEG9 COM26/SEG10 COM27/SEG11 COM28/SEG12 COM29/SEG13 COM30/SEG14 COM31/SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 LCDVSS1 Pin Assignment LC88F85D0A XT2 XT1 RESB VDD CF1 CF2 VSS P00/P0LI/AN8 P01/P0LI/AN9 P02/P0LI/AN10 P03/P0LI/AN11 P04/P0HLI/AN12 P05/P0HLI/AN13 P06/T0PWML/AN14 P07/T0PWMH/AN15 P10/SI0O P11/SI0IO P12/SI0CK P13/T3PWML P14/T3PWMH/U0RX P15/U0TX P16/U2RX P17/U2TX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 VLCD4 VLCD3 VLCD2 VLCD1 TEST COM24/SEG8 COM23/SEG7 COM22/SEG6 COM21/SEG5 COM20/SEG4 COM19/SEG3 COM18/SEG2 COM17/SEG1 COM16/SEG0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 LCSVSS0 CUP00 CUP01 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48/SGND15/SGIN15 SEG49/SGND14/SGIN14 SEG50/SGND13/SGIN13 SEG51/SGND12/SGIN12 SEG52/SGND11/SGIN11 SEG53/SGND10/SGIN10 SEG54/SGND9/SGIN9 SEG55/SGND8/SGIN8 SEG56/SGND7/SGIN7/SGINT7 SEG57/SGND6/SGIN6/SGINT6 SEG58/SGND5/SGIN5/SGINT5 SEG59/SGND4/SGIN4/SGINT4 SEG60/SGND3/SGIN3/SGINT3 SEG61/SGND2/SGIN2/SGINT2 SEG62/SGND1/SGIN1/SGINT1/T3IH SEG63/SGND0/SGIN0/SGINT0/T3IL P23/AN3/SM0DA P22/AN2/SM0CK P21/AN1/T5O P20/AN0/T4O/RMIN Top view TQFP120 (14×14) “Lead-free Type” No.A1954-9/31 LC88F85D0A System Block Diagram CF RC X’tal Clock generator RC RC Low speed RC Base timer Watchdog timer FLASH ROM Xstormy16 CPU Timer 0 RAM Timer 1 On-chip debugger Timer 3 Port 0 Timer 4 Port 1 Timer 5 Port 2 UART0 AD UART2 RTC2 SIO0 SMIIC0 LCD control Infrared remote control receiver LCD display RAM No.A1954-10/31 LC88F85D0A Pin Description Pin Name VSS I/O - Description - Power supply pin VDD - + Power supply pin VLCD1 to 4 - LCD bias power source (connected to capacitors) LCDVSS0, LCDVSS1 - LCD port power source (-) CUP00, CUP01 - Switching pins for generating the LCD drive voltage. A capacitor must be connected across both pins. PORT 0 I/O • 8-bit I/O port • I/O specifiable in 1 bit units P00 to P07 • Pull-up registers can be turned on and off in 1-bit units. • HOLD releaset inputs (P00 to P03, P04, P05) • Port 0 interrupt inputs (P00 to P03, P04, P05) • Pin functions P00 (AN8) to P07 (AN15): AD converter inputs P06: Timer 0L output P07: Timer 0H output/UART0 clock input PORT 1 I/O • 8-bit I/O port • I/O specifiable in 1-bit units P10 to P17 • Pull-up registers can be turned on and off in 1-bit units. • Pin functions P10: SIO0 data output P11: SIO0 data input/bus input/output P12: SIO0 clock input/output P13: Timer 3L output P14: Timer 3H output/UART0 receive P15: UART0 transmit P16: UART2 receive P17: UART2 transmit PORT 2 I/O • 4-bit I/O port • I/O specifiable in 1-bit units P20 to P23 • Pull-up registers can be turned on and off in 1-bit units. • Pin functions P20 (AN0) to P23 (AN3): AD converter inputs P20: Timer 4 output/remote controller receive P21: Timer 5 output P22: SMIIC0 clock input/output P23: SMIIC0 bus input/output/data input COM0 to COM15 O • LCD common output COM16/SEG0 to O • LCD common output/segment output SEG16 to SEG47 O • LCD segment output SEG48 to SEG63 I/O • LCD segment output COM31/SEG15 Common output/segment output switched by a register • SEG63-SEG48: General-purpose N-channel open drain output/general-purpose input SEG63-SEG48: LCD output in 4-bit units/general-purpose N-channel open drain output/general-purpose input selectable • SEG63-SEG56: Interrupt function (4-bit units) Chatter removal sampling frequency select (4-bit units) Level/edge sense mode select (4-bit units) Hi/low level or rising/falling edge sense mode select (1-bit units) • SEG63-SEG62: Timer 3 external input TEST I/O • TEST pin • On-chip debugger communication pin • An external 100kΩ pull-down resistor must be connected. RESB I Reset pin CF1 I Ceramic oscillator input/RC oscillator resistor to be connected CF2 O Ceramic oscillator output XT1 I 32.768kHz crystal oscillator input/RC oscillator resistor to be connected XT2 O 32.768kHz crystal oscillator output No.A1954-11/31 LC88F85D0A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Options Selected in Units of P00 to P07 1 bit P10 to P17 1 bit P20 to P23 Output Type Pull-up Resistor CMOS Programmable Multiplexed pin outputs are programmable either as CMOS Programmable or N-channel open drain output. SEG48 to SEG63 4 bits N-channel open drain None (LCD segment output) Table of User Options Option Name X'tal OSC (*1) Interrupt Vector (*2) Option Description Normal Normal XT mode Low Power Low power XT mode Normal Interrupt vector switching LC888300 Compatible *1 The circuit constant values of the external components and oscillation stabilization time differ between the normal XT mode and low power XT mode. *2 The "LC888300 Compatible" mode is an option that is available to provide compatibility between this model and the LC888300. It is to be unavailable in future models. No.A1954-12/31 LC88F85D0A Application circuit I/O UART device SEG63 SEG16 COM31/SEG15 COM16/SEG0 I/O P00 P01 P02 P03 P04 P05 P06 P07 COM15 COM0 LCD panel 64×16/48×32 CUP01 CUP00 LC88F85D0A C1 VLCD4 VLCD3 C2 C3 VLCD2 VLCD1 C4 C5 P10 (SIO0-OUT) P11 (SIO0-IN) P12 (SIO0-CLK) P13 P14 P15 P16 (UART2-RX) P17 (UART2-TX) VDD 2.3V to 5.5V + RESB I/O On-chip debugger CRES P20 P21 P22 P23 VSS LCDVSS0 LCDVSS1 XT2 RTST CF1 CF2 TST CGC *3 CDC X'tal Trimmer capacitor CDX Capacitor for X’tal oscillator CCR0 *5 CDX *4 CCR0 RCR0 Crystal resonator CGX RCR0 *1: Crystal oscillation *2: Internal RC oscillation *3: Ceramic oscillation CGX *1 X'tal CF CCR1 RCR1 XT1 Pulse output Resistor for low-speed oscillator *4: RC oscillation type Capacitor for low-speed oscillation stabilization *4: RC oscillation type (*1) (*1) 0.1μF capacitor is recommended when using XT1/XT2 as the system clock source. CF Ceramic resonator CGC Capacitor for CF oscillator CDC Capacitor for CF oscillator RCR1 Resistor for high-speed oscillation *5: RC oscillation type CCR1 Capacitor for high-speed oscillation stabilization *5: RC oscillation type C1 to C5 CDEN Capacitor CDEN Electrolytic capacitor CRES Capacitance for RESB RTST Resistor used when using the on-chip debugger No.A1954-13/31 LC88F85D0A Absolute Maximum Ratings at Ta = 25°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Maximum supply Symbol Pin/Remarks Conditions VDD max VDD VDD VLCD max VLCD2 to VLCD4 VDD SEG0 to SEG63 VDD, VLCD4 voltage LCD supply voltage Maximum LCD LCD max supply voltage COM0 to COM31 Input voltage VI(1) CF1, XT1, RESB Input/output VIO(1) Ports 0, 1, 2 voltage Peak output SEG63 to SEG48 IOPH(1) Ports 0, 2 Low level output current High level output current current Mean output Per 1 applicable pin IOPH(2) Port 1 Per 1 applicable pin IOMH(1) Ports 0, 2 CMOS output select current (Note 1-1) CMOS output select Per 1 applicable pin IOMH(2) Port 1 CMOS output select Per 1 applicable pin Specification VDD[V] min typ max unit -0.3 +6.5 -0.3 +6.5 -0.3 +6.5 -0.3 VDD+0.3 -0.3 VDD+0.3 -5 -14 -3 -9 Total output ΣIOAH(1) Ports 0, 2 Total of all applicable pins current ΣIOAH(2) Port 1 Total of all applicable pins -25 ΣIOAH(3) Ports 0, 1, 2 Total of all applicable pins -47.5 Peak output IOPL(1) Ports 0, 2 Per 1 applicable pin current IOPL(2) Port 1 Per 1 applicable pin 17 Mean output IOML(1) Ports 0, 2 Per 1 applicable pin 7.5 current IOML(2) Port 1 Per 1 applicable pin ΣIOAL(1) Ports 0, 2 Total of all applicable pins ΣIOAL(2) Port 1 Total of all applicable pins ΣIOAL(3) Ports 0, 1, 2 Total of all applicable pins -22.5 13 35 current Allowable power Pd max 60 80 Ta=-20 to +75°C 250 dissipation Operating ambient Topr temperature Storage ambient Tstg temperature mA 10.5 (Note 1-1) Total output V -20 +75 -65 +125 mW °C Note 1-1: The mean output current is a mean value measured over 100ms. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. No.A1954-14/31 LC88F85D0A Allowable Operating Conditions at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Operating Symbol VDD(1) Pin/Remarks VDD supply voltage (Note2-1) LCD drive VLCD(1) VLCD2 to VLCD4 VHD VDD Conditions Ratings VDD[V] min typ max 4.5 5.5 0.123μs≤tCYC≤66μs 3.0 5.5 0.490μs≤tCYC≤66μs 2.0 5.5 5.5 voltage Memory sustaining unit 0.098μs≤tCYC≤66μs RAM and register contents sustained in HOLD mode. 2.0 5.5 supply voltage High level VIH(1) Ports 0, 1, 2 Output disabled 0.30VDD input voltage Low level VIH(2) CF1, RESB Ports 0, 1, 2 VIL(2) CF1, RESB 0.75VDD Output disabled input voltage Instruction tCYC cycle time (Note 2-2) External FEXCF(1) CF1 • CF2 pin open • System clock frequency system clock frequency division ratio=1/1 • External system clock duty=50±5% Oscillation FmCF(1) CF1,CF2 10MHz ceramic oscillation See Fig. 1. frequency range VDD +0.70 VIL(1) FmCF(2) CF1,CF2 (Note 2-3) 8MHz ceramic oscillation See Fig. 1. FmCF(3) CF1,CF2 4MHz ceramic oscillation See Fig. 1. VSS VDD 0.10VDD +0.40 VSS 0.25VDD 4.5 to 5.5 0.098 66 3.0 to 5.5 0.123 66 2.0 to 5.5 0.490 66 4.5 to 5.5 0.1 10 3.0 to 5.5 0.1 8 2.0 to 5.5 0.1 2 4.5 to 5.5 10 3.0 to 5.5 8 2.4 to 5.5 4 Internal RC oscillation 2.0 to 5.5 0.5 1.0 2.0 FmSLRC Internal SLRC oscillation 2.0 to 5.5 18 30 45 XT1, XT2 32.768kHz crystal oscillation See Fig. 2. FmRC1(1) CF1 High-speed RC oscillation (Note 2-4) FmRC1(2) CF1 High-speed RC oscillation (Note 2-4) FsRC0 XT1 Low-speed RC oscillation (Note 2-4) 2.2 to 5.5 μs MHz MHz FmRC FsX'tal V 32.768 2.4 to 5.5 400 4200 2.0 to 5.5 400 2000 2.2 to 5.5 30 80 kHz Note2-1: VDD must be held greater than or equal to 3.0V when onboard writing to flash ROM. Note2-2: Relationship between tCYC and oscillation frequency is 1/FmCF at a frequency division ratio of 1/1 and 2/FmCF at a division ratio of 1/2. Note2-3: See Tables 1 and 2 for the oscillation constants. Note2-4: Ta=0°C to 60°C No.A1954-15/31 LC88F85D0A Electrical Characteristics at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter High level input Symbol IIH(1) current Pin/Remarks Conditions Ports 0, 1, 2 Output disabled RESB Pull-up resistor off VIN=VDD (including output Tr off Specification VDD[V] min typ max 2.0 to 5.5 unit 1 μA leakage current) Low level input IIL(1) Ports 0, 1, 2 current Output disabled Pull-up resistor off VIN=VSS (including output Tr off 2.7 to 5.5 μA -1 leakage current) High-level output VOH(1) Ports 0, 1, 2 IOH=-1.0mA 4.5 to 5.5 VDD-1 voltage VOH(2) IOH=-0.4mA 3.0 to 5.5 VDD-0.4 VOH(3) IOH=-0.1mA 2.0 to 5.5 2.0 to 5.5 VDD-0.4 VLCD4 VOH(4) COM0 to COM31 IOH=-25μA VOH(5) SEG0 to SEG63 IOH=-10μA 2.0 to 5.5 Low level output VOL(1) Ports 0, 1, 2 IOL(1)=10mA 4.5 to 5.5 1.5 voltage VOL(2) IOL(1)=1.6mA 3.0 to 5.5 0.4 VOL(3) IOL(1)=0.7mA 2.0 to 5.5 0.4 2.0 to 5.5 VSS +0.05 2.0 to 5.5 VSS +0.05 Pull-up resistance VOL(4) COM0 to COM31 IOLH=25μA VOL(5) SEG0 to SEG63 IOL=10μA Rpu(1) Ports 0, 1, 2 VOH=0.9VDD Rpu(2) Hysteresis voltage VHYS Ports 0, 1, 2 RESB Pin capacitance CP All pins -0.05 VLCD4 -0.05 4.5 to 5.5 15 35 80 2.0 to 4.5 18 55 180 V kΩ 2.0 to 5.5 0.1VDD V 2.0 to 5.5 10 pF For pins other than that under test VIN=VSS f=1MHz Ta=25°C No.A1954-16/31 LC88F85D0A LCD Drive Voltage at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Special notes: 0.1μF capacitors are connected to VLCD1, VLCD2, VLCD3, and VLCD4. (with no panel load) Parameter LCD drive voltage Symbol VLCD1 Pin/Remarks VDD VLCD1 Conditions Specification VDD[V] min typ Contrast “00” 1.030 Contrast “01” 1.045 Contrast “02” 1.060 Contrast “03” 1.075 Contrast “04” 1.090 Contrast “05” 1.105 Contrast “06” max 1.120 Contrast “07” Typ 1.135 Typ Contrast “08” ×0.88 1.150 ×1.10 Contrast “09” unit 2.0 to 5.5 1.165 Contrast “10” 1.180 Contrast “11” 1.195 Contrast “12” 1.210 Contrast “13” 1.225 Contrast “14” 1.240 Contrast “15” 1.255 VLCD2 2×VLCD1 VLCD3 3×VLCD1 VLCD4 4×VLCD1 V No.A1954-17/31 LC88F85D0A Serial I/O Characteristics at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V SIO0 Serial I/O Characteristics (When wakeup function is not in used) (Note 4-1-1) Parameter Symbol Frequency tSCK(1) Low level tSCKL(1) Pin/Remarks SCK0(P12) Conditions Specification VDD[V] • See Fig. 6. max unit 2 tSCKH(1) 2 pulse width Input clock typ 4 pulse width High level min • Automatic communication tSCKHA(1) mode 2.0 to 5.5 6 • See Fig. 6. tCYC • Automatic communication tSCKHBSY(1a) mode 23 • See Fig. 6. • Mode other than automatic tSCKHBSY(1b) communication mode 4 Serial clock • See Fig. 6. Frequency tSCK(2) SCK0(P12) • CMOS output type selected 4 • See Fig. 6. Low level tSCKL(2) 1/2 pulse width High level tSCK tSCKH(2) 1/2 pulse width • Automatic communication Output clock tSCKHA(2) mode • CMOS output type selected 2.0 to 5.5 6 • See Fig. 6. • Automatic communication tSCKHBSY(2a) mode 4 • CMOS output type selected 23 tCYC • See Fig. 6. • Mode other than automatic tSCKHBSY(2b) communication mode 4 • See Fig. 6. Serial input Data setup time SI0(P11), SB0(P11) • Specified with respect to rising edge of SIOCLK. • See Fig. 6. Data hold time thDI(1) 0.03 2.0 to 5.5 0.03 Output clock Input clock Output Serial output tsDI(1) tdD0(1) delay time SO0(P10), • (Note4-1-2) SB0(P11) 1tCYC μs +0.05 tdDO(2) • (Note4-1-2) 2.0 to 5.5 1tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-1-2: Specified with respect to the falling edge of SIOCLK. Specified as the time up to the time the output state is changed in the open drain output mode. See Fig. 6. No.A1954-18/31 LC88F85D0A SIO1 Serial I/O Characteristics (When wakeup function is not in used) (Note 4-2-1) Input clock Serial clock Parameter Symbol Period tSCK(3) Low level tSCKL(3) Pin/Remarks SCK0(P12) Conditions min • See Fig. 6. 2.0 to 5.5 tSCKH(3) tCYC Serial input 2 SI0(P11), SB0(P11) • Specified with respect to rising edge of SIOCLK. • See Fig. 6. Data hold time unit 1 tSCKHBSY(3) tsDI(2) max 2 pulse width Data setup time typ 1 pulse width High level Specification VDD[V] thDI(2) 0.03 2.0 to 5.5 0.03 Input clock Serial output μs Output tdD0(3) delay time SO0(P10), • (Note4-2-2) SB0(P11) 1tCYC 2.0 to 5.5 +0.05 Note 4-2-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-2-2: Specified with respect to the falling edge of SIOCLK. Specified as the time up to the time the output state is changed in the open drain output mode. See Fig. 6. SMIIC0 Simple SIO Mode I/O Characteristics Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Input clock tSCK(7) SM0CK • See Fig. 6. Low level tSCKL(7) 2.0 to 5.5 pulse width High level Period Low level SM0CK • CMOS output type selected (P22) • See Fig. 6. tSCKL(8) 4 2.0 to 5.5 1/2 tSCK tSCKH(8) 1/2 Serial input SM0DA (P23) • Specified with respect to rising edge of SIOCLK • See Fig. 6. Data hold time thDI(5) 0.03 2.0 to 5.5 0.03 Output delay time Serial output tsDI(5) unit 2 pulse width Data setup time max 2 pulse width High level typ tCYC tSCKH(7) tSCK(8) min 4 (P22) pulse width Output clock Serial clock Period tdD0(7) SM0DA (P23) μs • Specified with respect to falling edge of SIOCLK • Specified as the time up to the beginning of output 2.0 to 5.5 1tCYC +0.05 change . • See Fig. 6. Note 4-3-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. No.A1954-19/31 LC88F85D0A SMIIC0 I2C Mode I/O Characteristics Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Input clock Period tSCL SM0CK • See Fig. 8. tSCLL 2.0 to 5.5 pulse width High level Clock Output clock SM0CK (P22) Low level • Specified as the time up to 2.5 change. tSCLLx 10 the beginning of output 2.0 to 5.5 pulse width High level 1/2 tSCL tSCLHx 1/2 pulse width SM0CK, SM0DA pin tsp input spike suppression SM0CK(P22) • See Fig. 8. SM0DA(P23) 2.0 to 5.5 time period bus release time tBUF SM0CK(P22) 1 Tfilt • See Fig. 8. SM0DA(P23) Input Start-to-stop unit 2 pulse width tSCLx max Tfilt tSCLH Period typ 5 (P22) Low level min 2.5 tBUFx SM0CK(P22) • Standard clock mode SM0DA(P23) • Specified as the time up to 2.0 to 5.5 Output the beginning of output Tfilt 5.5 change. μs • High-speed clock mode • Specified as the time up to 1.6 the beginning of output change. Start/restart tHD;STA condition hold SM0DA(P23) • When SMIIC register control bit I2CSHDS=0 2.0 • See Fig. 8. Input time SM0CK(P22) Tfilt • When SMIIC register 2 control bit I CSHDS=1 2.5 • See Fig. 8. tHD;STAx SM0CK(P22) • Standard clock mode SM0DA(P23) • Specified as the time up to 2.0 to 5.5 4.1 Output the beginning of output change. μs • High-speed clock mode • Specified as the time up to 1.0 the beginning of output change. SM0CK(P22) • See Fig. 8. SM0DA(P23) 1.0 tSU;STAx SM0CK(P22) • Standard clock mode SM0DA(P23) • Specified as the time up to the beginning of output Output setup time tSU;STA Input Restart condition 2.0 to 5.5 5.5 change. μs • High-speed clock mode • Specified as the time up to the beginning of output Tfilt 1.6 change. Continued on next page. No.A1954-20/31 LC88F85D0A Continued from preceding page. Specification Parameter Symbol Pin/Remarks tSU;STO SM0CK(P22) Conditions setup time Input VDD[V] Stop condition SM0CK(P22) • Standard clock mode SM0DA(P23) • Specified as the time up to the beginning of output Output typ max 1.0 SM0DA(P23) tSU;STOx min Unit • See Fig. 8. 2.0 to 5.5 Tfilt 4.9 change. μs • High-speed clock mode • Specified as the time up to 1.1 the beginning of output SM0CK, SM0DA pin fall time Input Output Data setup time Input Output Input change. Data hold time tHD;DAT SM0CK(P22) • See Fig. 8. 0 SM0DA(P23) tHD;DATx SM0CK(P22) SM0DA(P23) • Specified as the time up to 2.0 to 5.5 the beginning of output Tfilt 1 1.5 change. tSU;DAT SM0CK(P22) • See Fig. 8. SM0DA(P23) tSU;DATx SM0CK(P22) SM0DA(P23) 1 • Specified as the time up to 2.0 to 5.5 the beginning of output 1.5Tfilt change. tF SM0CK(P22) • See Fig. 8. SM0DA(P23) tF SM0CK(P22) SM0DA(P23) • When SMIIC register control bits PSLW=1, P5V=1 Output • When SMIIC register control bits PSLW=1, P5V=0 Tfilt 1tSCL- 2.0 to 5.5 300 5 20+0.1Cb 250 3 20+0.1Cb 250 ns • When SM0CK and SM0DA port outputs are placed in fast mode 3.0 to 5.5 100 • Cb≤400pF Note 4-4-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-4-2: Tfilt denotes the value that is determined by the values of register SMIC0BRG, bits 7 and 6 (BRP1, BRP0) and the system clock frequency. BRP1 BRP0 Tfilt 0 0 tCYC×1 0 1 tCYC×2 1 0 tCYC×3 1 1 tCYC×4 Set up (BPR1, BPR0) so that Tfilt falls within the following range: 250ns ≥ Tfilt > 140ns Note 4-4-3: Cb denotes the total capacitance (in pF) of the loads connected to each bus. Cb ≤ 400pF Note 4-4-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG within the following ranges: 250ns ≥ Tfilt > 140ns BRDQ (bit 5) = 1 SCL frequency setting ≤ 100kHz The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows: 250ns ≥ Tfilt > 140ns BRDQ (bit 5) = 0 SCL frequency setting ≤ 400kHz No.A1954-21/31 LC88F85D0A UART0 Operating Conditions at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Transfer rate Symbol UBR0 Pin/Remarks Conditions U0RX(P14), U0TX(P15), U0BRG(P07) Specification VDD[V] min 2.0 to 5.5 typ max 4 unit 8 tBGCYC Note 4-5: tBGCYC denotes 1 period of the baudrate clock source. UART2 Operating Conditions at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Transfer rate Symbol UBR2 Pin/Remarks Conditions U2RX(P16), Specification VDD[V] min 2.0 to 5.5 U2TX(P17) typ max 8 unit 4096 tBGCYC Note 4-6: tBGCYC denotes 1 period of the baudrate clock source. Pulse Input Conditions at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Symbol tPIL(2) Pin/Remarks RESB Conditions Resettable. Specification VDD[V] min 2.0 to 5.5 typ max unit μs 10 AD Converter Characteristics at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V 12-bits AD Conversion Mode Parameter Symbol Pin/Remarks Resolution NAD AN0(P20), Absolute accuracy ETAD AN1(P21), Conversion time TCAD12 Analog input VAIN Conditions Specification VDD[V] min 2.9 to 5.5 typ max unit 12 bit (Note 6-1) 2.9 to 5.5 Conversion time is calculated. 4.5 to 5.5 27 209 AN8(P00) to 2.9 to 5.5 67 209 AN15(P07) 2.9 to 5.5 VSS VDD AN2(P22), AN3(P23), voltage range Analog port input IAINH VAIN=VDD 2.9 to 5.5 current IAINL VAIN=VSS 2.9 to 5.5 ±16 1 -1 LSB μs V μA • Conversion time calculation method: TCAD12= ((52/(AD division ratio))+2) × tCYC 8-bits AD Conversion Mode Parameter Symbol Pin/Remarks Resolution NAD AN0(P20), Absolute accuracy ETAD AN1(P21), Conversion time TCAD8 Analog input VAIN AN2(P22), Conditions Specification VDD[V] min 2.9 to 5.5 (Note 6-1) Conversion time is calculated. typ max unit 8 bit ±1.5 2.9 to 5.5 4.5 to 5.5 17 129 AN8(P00) to 2.9 to 5.5 42 129 AN15(P07) 2.9 to 5.5 VSS VDD AN3(P23), voltage range Analog port input IAINH VAIN=VDD 2.9 to 5.5 current IAINL VAIN=VSS 2.9 to 5.5 1 -1 LSB μs V μA • Conversion time calculation method: TCAD8= ((32/(AD division ratio))+2) × tCYC Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy. Note 6-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time the complete digital value against the analog input value is loaded in the result register. The conversion time is twice the normal value when one of the following conditions occurs: • The first AD conversion is executed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is executed after the AD conversion mode is switched from 8-bit to 12-bit AD conversion mode. No.A1954-22/31 LC88F85D0A Consumption Current Characteristics at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Normal mode Symbol IDDOP(1) consumption current IDDOP(2) Pin/ VDD Specification Conditions Remarks VDD[V] • FOSC0=32.768kHz LCD • System clock set to FOSC0 side display • Internal RC oscillation stopped ON • FOSC1=0Hz (oscillation stopped) (Note 7-1) • Frequency division ratio set to 1/1 LCD • Normal XT mode display IDDOP(4) [No panel load] OFF IDDOP(5) • FOSC0=32.768kHz LCD • System clock set to FOSC0 side display • Internal RC oscillation stopped ON IDDOP(3) IDDOP(6) • FOSC1=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 LCD • Low power XT mode display IDDOP(8) [No panel load] OFF IDDOP(9) • FmCF=10MHz ceramic oscillator IDDOP(7) min typ max 2.0 to 5.5 87 170 2.0 to 3.6 44 110 2.0 to 5.5 75 155 2.0 to 3.6 35 95 2.0 to 5.5 53 100 2.0 to 3.6 35 65 2.0 to 5.5 48 92 2.0 to 3.6 31 55 4.5 to 5.5 8.4 15.2 4.5 to 5.5 7.6 14.7 3.0 to 4.5 5.8 11 4.5 to 5.5 3.6 5.5 2.2 to 4.5 2.2 4.7 2.0 to 5.5 2.2 5.6 2.0 to 3.6 1.2 3.6 2.0 to 5.5 1.5 2.6 2.0 to 3.6 1.0 2.5 2.0 to 5.5 100 187 unit μA • FOSC0=0Hz (oscillation stopped) • System clock set to 10MHz side • Internal RC oscillation stopped • Frequency division ratio set to 1/1 IDDOP(10) • FmCF=8MHz ceramic oscillator oscillator • FOSC0=0Hz (oscillation stopped) IDDOP(11) • System clock set to 8MHz side • Internal RC oscillation stopped • Frequency division ratio set to 1/1 IDDOP(12) • FmCF=4MHz ceramic oscillator • FOSC0=0Hz (oscillation stopped) IDDOP(13) • System clock set to 4MHz • Internal RC oscillation stopped • Frequency division ratio set to 1/2 IDDOP(14) • System clock set to internal RC side • Internal RC oscillation oscillated IDDOP(15) • FOSC0=0Hz (oscillation stopped) • FOSC1=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 IDDOP(16) mA • FOSC1=1MHz RCR1=470kΩ • System clock set to FOSC1 side • Internal RC oscillation stopped IDDOP(17) • FOSC0=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 *Ta=0 to 60°C IDDOP(18) • FOSC0=64kHz RCR0=910kΩ • System clock set to FOSC0 side • Internal RC oscillation stopped IDDOP(19) μA • FOSC1=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 2.0 to 3.6 62 120 *Ta=0 to 60°C Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.A1954-23/31 LC88F85D0A Continued from preceding page. Parameter HALT mode Symbol IDDHALT(1) consumption current IDDHALT(2) Pin/ VDD Specification Conditions Remarks VDD[V] HALT mode LCD • FOSC0=32.768kHz display • System clock set to FOSC0 side ON • Internal RC oscillation stopped (Note 7-2) IDDHALT(3) IDDHALT(4) • FOSC1=0Hz (oscillation stopped) LCD • Frequency division ratio set to 1/1 display • Normal XT mode OFF [No panel load] IDDHALT(5) IDDHALT(6) HALT mode LCD • FOSC0=32.768kHz display • System clock set to FOSC0 side ON • Internal RC oscillation stopped IDDHALT(7) IDDHALT(8) • FOSC1=0Hz (oscillation stopped) LCD • Frequency division ratio set to 1/1 display • Low power XT mode OFF [No panel load] IDDHALT(9) min typ max 2.0 to 5.5 45 110 2.0 to 3.6 16 50 2.0 to 5.5 36 90 2.0 to 3.6 7.8 51 2.0 to 5.5 15.5 53 2.0 to 3.6 12 30 2.0 to 5.5 6.5 40 2.0 to 3.6 4 30 4.5 to 5.5 2.0 3.4 4.5 to 5.5 1.7 2.9 3.0 to 4.5 1.2 2.1 4.5 to 5.5 0.7 1.2 unit μA HALT mode • FmCF=10MHz ceramic oscillator • FOSC0=0Hz (oscillation stopped) • System clock set to 10MHz side • Internal RC oscillation stopped • Frequency division ratio set to 1/1 IDDHALT(10) HALT mode • FmCF=8MHz ceramic oscillator • Internal RC oscillation stopped IDDHALT(11) • FOSC0=0Hz (oscillation stopped) • System clock set to 8MHz side • Internal RC oscillation stopped • Frequency division ratio set to 1/1 IDDHALT(12) HALT mode • FmCF=4MHz ceramic oscillator • FOSC0=0Hz (oscillation stopped) IDDHALT(13) mA • System clock set to 4MHz side • Internal RC oscillation stopped 2.2 to 4.5 0.3 0.85 2.0 to 5.5 0.7 1.3 2.0 to 3.6 0.3 0.6 2.0 to 5.5 0.2 0.5 2.0 to 3.6 0.1 0.3 2.0 to 5.5 20 60 • Frequency division ratio set to 1/2 IDDHALT(14) HALT mode • System clock set to internal RC side • Internal RC oscillation oscillated IDDHALT(15) • FOSC0=0Hz (oscillation stopped) • FOSC1=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 IDDHALT(16) HALT mode • FOSC1=1MHz RCR1=470kΩ • System clock set to FOSC1 side IDDHALT(17) • Internal RC oscillation stopped • FOSC0=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 *Ta=0 to 60°C IDDHALT(18) HALT mode • FOSC0=64kHz RCR0=910kΩ • System clock set to FOSC0 side IDDHALT(19) μA • Internal RC oscillation stopped • FOSC1=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 2.0 to 3.6 10 40 *Ta=0 to 60°C Note 7-2: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.A1954-24/31 LC88F85D0A Continued from preceding page. Parameter Symbol HOLD mode IDDHOLD(1) consumption Pin/ VDD HOLDX mode VDD[V] HOLD mode • CF1=VDD or open (external clock mode) IDDHOLD(2) current Specification Conditions Remarks IDDHOLD(3) HOLDX mode • CF1=VDD or open (external clock mode) consumption current • FOSC0=32.768kHz IDDHOLD(4) • Normal XT mode IDDHOLD(5) HOLDX mode • CF1=VDD or open (external clock mode) • FOSC0=32.768kHz IDDHOLD(6) • Low power XT mode min typ max 2.0 to 5.5 0.08 35 2.0 to 3.6 0.02 25 2.0 to 5.5 30 65 2.0 to 3.6 5 55 2.0 to 5.5 0.6 35 2.0 to 3.6 0.4 25 unit μA Note 7-3: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. F-ROM Writing Characteristics at Ta = +10°C to +55°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Symbol Onboard writing IDDFW(1) current Writing time Pin/ VDD Specification Conditions Remarks VDD[V] • Excluding power dissipation in the microcontroller block min typ max unit 3.0 to 5.5 15 mA tFW(1) • 512-/1K-byte erase operation 3.0 to 5.5 30 ms tFW(2) • 2-byte writing operation 3.0 to 5.5 60 μs Characteristics of a Sample OSC1 System Clock Oscillation Circuit Sample main system clock oscillation circuit characteristics Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of the Main System Clock Oscillation Circuit that Uses a Ceramic Oscillator Nominal Frequency Circuit Constant Vendor Name 10MHz 8MHz MURATA Oscillator Name Operating Oscillation Voltage Stabilization Time C3 C4 Rf Rd2 Range typ max [pF] [pF] [Ω] [Ω] [V] [ms] [ms] CSTCE10M0G52-R0 (10) (10) OPEN 150 2.4 to 5.5 0.02 0.5 CSTCE8M00G52-R0 (10) (10) OPEN 470 2.4 to 5.5 0.02 0.5 CSTCR4M00G53-R0 (15) (15) OPEN 1.5K 2.2 to 5.5 0.02 0.5 CSTCR4M00G53095-R0 (15) (15) OPEN 1.5K 2.0 to 5.5 0.02 0.5 Manufacturing Co., Ltd. 4MHz Remarks C1 and C2 integrated type C1 and C2 integrated type C1 and C2 integrated type C1 and C2 integrated type The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD exceeds its lower limit operating voltage (see Figure 4). No.A1954-25/31 LC88F85D0A Characteristics of a Sample Subsystem Clock Oscillation Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit that uses a Crystal Oscillator (*5) Nominal Frequency Vendor Name Name SSP-T7-F 32.768kHz (*1) Seiko Instruments (*2) Circuit Constant Resonator VT-200-F SSP-T7-FL VT-200-FL Operating Oscillation Voltage Stabilization Time C3 C4 Rf2 Rd2 Range typ max [pF] [pF] [Ω] [Ω] [V] [s] [s] 18 22 OPEN 750K 2.0 to 5.5 1.4 3 2 3 OPEN 0 2.0 to 5.5 0.8 3 Remarks CL=12.5pF (*3) Normal XT mode CL=4.4pF(*4) Low power XT mode (*1) Normal XT mode (*3) or low power XT mode (*4) should be selected for the sub-system clock oscillator circuit. (*2) Contact Seiko Instruments, Inc., (http://www.sii-crystal.com) for further information about the use of the resonator. (*3) When considering the use of normal XT mode, use an resonator that has a large load capacitance. (*4) When considering the use of low power XT mode, use a resonator that has a small load capacitance. The applicable CL value of 4.4pF makes it possible to achieve a high time accuracy for the subclock oscillator as well as high-speed oscillation startup and low power dissipation. In addition to this value, 6.0pF and 7.0pF also fall within the applicable CL value range. (*5) A sample PCB trace pattern for a Seiko Instrument resonator is shown below. (Note 1) The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after an instruction for starting the subclock oscillator circuit is issued or the time interval that is required for the oscillation to get stabilized after the HOLD mode is released (see Figure 4). (Note 2) The circuit constants shown are the reference values that are provided by the resonator vendor for evaluation. To make final verification of the oscillation characteristics on production boards, call the resonator vendor for evaluation on printed circuit boards. (Note 3) When using an oscillator circuit, observe the following wiring precautions to avoid the possible adverse influence of wiring capacitance, especially in low power XT mode: • Place the components that are involved in oscillation as close to the resonator as possible with the shortest possible traces as the oscillation characteristics are subject to the variation of trace patterns. • Do not take a signal directly from the oscillator circuit. • Do not place the oscillator circuit in the vicinity of any lines that carry large current. • Exercise extreme care in the wiring method when using low power XT mode. No.A1954-26/31 LC88F85D0A Rf2 Rf1 CF2 CF1 XT1 XT2 Rd1 C1 C2 CF Rd2 C3 C4 X’tal Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point VDD Operating VDD lower limit 0V Power supply Reset time RESB Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operating mode Unpredictable Reset Initialization instruction executed User instruction executed Reset Time and Oscillation Stabilization Time No.A1954-27/31 LC88F85D0A HOLD release No HOLD release signal HOLD release signal valid Interrupt operation Internal RC oscillator tmsCF CF1, CF2 tmsX’tal XT1, XT2 HOLD State HALT Instruction executed HOLD Reset and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time VDD RRES RESB Note: Make sure that reset is in effect when power is turned on. Determine the values of CRES and RRES so that the reset is in effect for a period of 10μs after the power gets stabilized. CRES Figure 5 Reset Circuit No.A1954-28/31 LC88F85D0A tSCKHBSY tSCKHBSY RUN: SIOCLK: DATAIN: DI0 DI1 DI6 DI7 DI8 DIx DATAOUT: DO0 DO1 DO6 DO7 DO8 DOx Data transfer period (SIO0, 1 only) tSCK SIOCLK: tSCKL tSCKH tsDI thDI DATAIN: tdDO DATAOUT: Data transfer period (SIO0, 1 only) SIOCLK: tSCKL tSCKHA tsDI thDI DATAIN: tdDO DATAOUT: *: Remarks: DIx and DOx are the final communication bits. X = 0 to 32768 Figure 6 Serial I/O Waveforms Examples tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.A1954-29/31 LC88F85D0A P S Sr P SDA tBUF tHD;STA tR tF tHD;STA tsp SCK tLOW tHD;DAT tHIGH tSU;DAT tSU;STO tSU;STA S: Start condition P: Stop condition Sr: Restart condition Figure 8 I2C Timing Note: The oscillation frequency of any RC oscillator using OSC1 or OSC0 varies according to the printed circuit patterns and components mounted on the board. It also varies greatly according to the shape and form of the product (chip, plastic package, etc.) and board capacitance. Consequently, the characteristics charts given below should be used merely as reference values and the resistance value be determined after evaluating them with the actual product. Frequency - Resistor 10 5 5 3 3 2 1.0 7 5 2 100 7 5 3 3 2 2 0.1 0 200 400 600 Resistor - kΩ 800 1000 1200 ILC05653 Figure 9 OSC1 Oscillation Frequency vs. Resistance Characteristics Ta=25°C, typ 7 Frequency - kHz Frequency - MHz 7 Frequency - Resistor 1000 Ta=25°C, typ 10 0 200 400 600 Resistor - kΩ 800 1000 1200 ILC05654 Figure 10 OSC0 Oscillation Frequency vs. Resistance Characteristics No.A1954-30/31 LC88F85D0A ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No.A1954-31/31