Ordering number : ENA1228 LC88F83B0A CMOS IC FROM 128K byte, RAM 4096K byte on-chip 16-bit 1-chip Microcontroller Overview The LC88F83B0A is a 16-bit microcontroller, centered around an Xstormy16 CPU, integrates on a single chip a number of hardware features such as 32-bit program counter, 16 bits × 16 general purpose register, 128K-byte flash ROM (onboard programmable), 4096-byte RAM, LCD display dedicated RAM, LCD dot matrix driver, on-chip debugging function, programmable timer, a base timer serving as a time-of-day clock, a synchronous SIO interface with automatic transmission capability, an asynchronous SIO (UART) interface, a 12-/8-bit resolution 4-channel AD converter, and a 12-source 11-vector interrupt feature. Features Flash ROM • 128K × 8bit (Table data reside in the same space.) RAM • 4240 × 8bit • For data • For display 4096 × 8bit 72 × 16bit LCD Display • 64 segment × 16 common/72 segment × 8 common (1/4 bias) * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.0.7 40611HKIM 20110328-S00003 No.A1228-1/25 LC88F83B0A Instruction Execution Time (min) • 31.0μs : 32.768kHz crystal used • 15.6μs (typ) : Low speed RC oscillation (typ: 64kHz) • 0.25μs : 4.0MHz ceramic filter oscillation • 1.00μs (typ) : High speed RC oscillation (typ: 1MHz) Power Supply Voltage • 2.3V to 5.5V (Ta =-20 to 75°C) • 2.3V to 5.5V (Ta =0 to 60°C) • 2.4V to 5.5V (Ta =-20 to 75°C) • 2.3V to 5.5V (Ta =0 to 60°C) • 2.4V to 5.5V (Ta =-20 to 75°C) : 32.768kHz crystal used : Low speed RC oscillation (typ: 64kHz) : 4.0MHz ceramic filter oscillation : High-speed RC oscillation (typ: 1MHz) : When LCD ON Consumption Current (3.0V): • 10.5μA (typ) (Ta=25°C, crystal oscillation 32.768kHz, 1/1 dividing frequency, HALT, LCD: ON) • 300μA (typ) (Ta=25°C, crystal oscillation 32.768kHz, CF 4MHz, 1/2 dividing frequency, HALT, LCD: ON) • 2200μA (typ) (Ta=25°C, crystal oscillation 32.768kHz, CF 4MHz, 1/2 dividing frequency, continuous operation, LCD: ON) Ports • Normal withstand voltage I/O ports 20 (P0n, P1n, P20 to P23) • LCD (COM8/SEG0 to COM15/SEG7 pins are multiplexed with COMMON and SEGMENT) LCD drive bias power supply port 4 (VLCD1 to VLCD4) Step-up capacitor port 2 (CUP00, CUP01) 16 common mode Segment output 64 (SEG8 to SEG71) Common output 16 (COM0 to COM15) 8 common mode Segment output 72 (SEG0 to SEG71) Common output 8 (COM0 to COM7) • Oscillation pins 4 (XT1, XT2, CF1, CF2) • Reset pin 1 (RESB) • Test pin 1 (TST) • LCD port power pins 2 (LCDVSS0, LCDVSS1) • Power pins 2 (VDD, VSS) LCD • LCD power supply • Number of dots • Contrast • LCD frame frequency : Capacitor step-up type : 1024 (64 segments × 16 commons) / 576 (72 segments × 8 commons) : Adjustable in 16 steps : Selectable from 4 types No.A1228-2/25 LC88F83B0A Timers • Timer 0: 16-bit timer that supports PWM/toggle outputs 1) With 5-bit prescaler 2) 8-bit PWM × 2/8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 1: 16-bit timer with capture registers 1) With 5-bit prescaler 2) May be divided into 2 channels of 8-bit timer 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 3: 16-bit timer that supports PWM/toggle outputs 1) With 8-bit prescaler 2) 8-bit timer × 2ch/8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 4: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0 • Timer 5: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0 • Base timer 1) Clock may be selected from OSC0 (32.768kHz crystal oscillator) and frequency-divided output of system clock. 2) Interrupts can be generated in 7 timing schemes. Watchdog Timer 1) Driven by the base timer + internal watchdog timer dedicated counter. 2) Interrupt or reset mode selectable SIO0: 8-bit synchronous SIO 1) LSB first/MSB first mode selectable 2) It is possible to communicate with 8 bits or less. (1 to 8 bits specifiable in 1-bit units) 3) Built-in 8-bit baudrate generator (transfer clock cycle 4 tCYC to 512 tCYC) 4) Automatic continuous data transmission (9 to 32768 bits specifiable in 1-bit units) 5) Interval function (interval time: 0 to 64 SIOCLKs specifiable in 1 SIOCLK units) 6) Wakeup function UART2: Asynchronous SIO 1) Full duplex transmission 2) Start bit 1, data bit 8 (LSB first), stop bit 1 3) Parity bit: None/even parity/odd parity 4) Transfer rate: 8 to 4096 tCYC 5) Baudrate source clock: systemclock/OSC0/OSC1 6) Wakeup function AD converter: 12bit × 4 channels 1) 12-/8-bit resolution selectable 2) Analog input: 4 channels 3) Comparator mode 4) Automatic reference voltage generation No.A1228-3/25 LC88F83B0A Interrupts • 12 sources, 11 vector addresses 1) Provides three levels of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Interrupt Source 1 08000H WATCHDOGTIMER 2 08004H BASETIMER 3 08008H TIMER0 4 08018H SIO0 5 0801CH TIMER1 6 08020H UART2 7 08024H TIMER3 8 08028H TIMER4 9 0802CH TIMER5 10 08030H ADC 11 0803CH P00 to P05 SEG71 to SEG64 • The priority level can be specified by three levels. • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels • Max- whole RAM area (Stack is set in RAM) Oscillation Circuits • OSC1: For system clock ceramic oscillation with external CGC, CDC or RC oscillation (external RCR1) • OSC0: For low-speed system clock, base timer count, for LCD display 32kHz crystal oscillation with external CGX, CDX or RC oscillation (external RCR0) • Internal oscillation circuit: Internal RC * Depends on control resister for each oscillator operation and stop. Initial setting - External oscillation stop, internal RC oscillation operation No.A1228-4/25 LC88F83B0A Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Released by a system reset or occurrence of an interrupt. • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) OSC1, internal RC and X’tal oscillators automatically stop operation. 2) There are the following methods of resetting the HOLD. (1) Setting the reset pin to the low level (2) Having an interrupt source established in the SIO0 (3) Having an interrupt source established in the UART2 (4) Having an interrupt source established in the P00 to P05 (5) Having an interrupt source established in the SEG71 to SEG64 • X’tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except using OSC0. 1) The OSC1 and internal RC oscillators automatically stop operation. 2) The state of OSC0 oscillation established when the X'tal HOLD mode is entered is retained. 3) There are the following methods of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Having an interrupt source established in the base timer circuit (3) Having an interrupt source established in the timers 0, 1, 3, 4, 5 (4) Having an interrupt source established in the SIO0 (5) Having an interrupt source established in the UART2 (6) Having an interrupt source established in the P00 to P05 (7) Having an interrupt source established in the SEG71 to SEG64 On-chip debugger • Supports software debugging with the IC mounted on the target board. • Supports tracing, realtime monitoring, and breakpoint setting. • Single-wire communication Package Form • TQFP120(14×14): Lead-free type Development Tools • On-chip debugger : EOCUIF1 + LC88F83B0A • Programming boards : Package Dimensions unit : mm (typ) 3257A 14.0 16.0 0.5 16.0 14.0 120 1 0.4 0.15 0.125 0.1 1.2MAX (1.0) (1.2) SANYO : TQFP120(14X14) No.A1228-5/25 LC88F83B0A Pad Assignment : 3.40mm × 3.19mm : 59μm : 80μm : 280μm ± 20μm 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 • Chip size (X × Y) • Pad size • Pad pitch • Chip thickness Y X 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 (0, 0) 97 98 99 100 101 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Note: Pin numbers assigned to a package differ from pad numbers assigned to a chip. Numbers in the above figure show the pad numbers of the chip. No.A1228-6/25 LC88F83B0A Pad Coordinates Table Pad No. Pin Name 1 Coordinates Pad No. Pin Name -1308 48 1567.4 -1228 1567.4 -1147 P23 1567.4 5 SEG71 6 SEG70 7 X μm Y μm P20 1567.4 2 P21 3 P22 4 Coordinates X μm Y μm SEG29 -192 1462.4 49 SEG28 -272 1462.4 50 SEG27 -352 1462.4 -1067 51 SEG26 -432 1462.4 1606.99 -951.8 52 SEG25 -512 1462.4 1606.99 -863.6 53 SEG24 -592 1462.4 SEG69 1606.99 -775.4 54 SEG23 -672 1462.4 8 SEG68 1606.99 -606.8 55 SEG22 -752 1462.4 9 SEG67 1606.99 -518.6 56 SEG21 -832 1462.4 10 SEG66 1606.99 -430.4 57 SEG20 -912 1462.4 1462.4 11 SEG65 1606.99 -342.2 58 SEG19 -992 12 SEG64 1606.99 -254 59 SEG18 -1072 1462.4 13 SEG63 1606.99 -165.8 60 SEG17 -1152 1462.4 14 SEG62 1606.99 -77.6 61 SEG16 -1232 1462.4 15 SEG61 1606.99 10.6 62 SEG15 -1567.4 1335 16 SEG60 1606.99 98.8 63 SEG14 -1567.4 1255 17 SEG59 1606.99 187 64 SEG13 -1567.4 1175 18 SEG58 1606.99 275.2 65 SEG12 -1567.4 1095 19 SEG57 1606.99 363.4 66 SEG11 -1567.4 1015 20 SEG56 1606.99 451.6 67 SEG10 -1567.4 935 21 SEG55 1567.4 573 68 SEG9 -1567.4 855 22 SEG54 1567.4 653 69 SEG8 -1567.4 775 23 SEG53 1567.4 733 70 - - - 24 SEG52 1567.4 813 71 COM15/SEG7 -1567.4 615 25 SEG51 1567.4 893 72 - - - 26 SEG50 1567.4 973 73 COM14/SEG6 -1567.4 455 27 SEG49 1567.4 1053 74 - - - 28 SEG48 1567.4 1133 75 COM13/SEG5 -1567.4 295 29 SEG47 1567.4 1213 76 - - - 30 SEG46 1567.4 1293 77 COM12/SEG4 -1567.4 135 31 LCDVSS1 1190 1462.4 78 - - - 32 SEG45 1088 1462.4 79 COM11/SEG3 -1567.4 -25 33 SEG44 1008 1462.4 80 - - - 34 SEG43 928 1462.4 81 COM10/SEG2 -1567.4 -185 35 SEG42 848 1462.4 82 - - - 36 SEG41 768 1462.4 83 COM9/SEG1 -1567.4 -345 37 SEG40 688 1462.4 84 - - - 38 SEG39 608 1462.4 85 COM8/SEG0 -1567.4 -505 39 SEG38 528 1462.4 86 COM7 -1567.4 -585 40 SEG37 448 1462.4 87 COM6 -1567.4 -665 41 SEG36 368 1462.4 88 COM5 -1567.4 -745 42 SEG35 288 1462.4 89 COM4 -1567.4 -825 43 SEG34 208 1462.4 90 COM3 -1567.4 -905 44 SEG33 128 1462.4 91 COM2 -1567.4 -985 45 SEG32 48 1462.4 92 COM1 -1567.4 -1065 46 SEG31 -32 1462.4 93 COM0 -1567.4 -1145 47 SEG30 -112 1462.4 94 LCDVSS0 -1567.4 -1240 Continued on next page. No.A1228-7/25 LC88F83B0A Continued from preceding page. Coordinates Pad No. Pin Name X μm Y μm 95 CUP00 -1567.4 96 CUP01 97 98 Coordinates Pad No. Pin Name X μm Y μm -1335.8 111 P00 205 -1462.4 -1567.4 -1415.8 112 P01 285 -1462.4 VLCD4 -1295.45 -1462.4 113 P02 365 -1462.4 VLCD3 -1215.45 -1462.4 114 P03 445 -1462.4 99 VLCD2 -1130.8 -1462.4 115 P04 525 -1462.4 100 VLCD1 -1050.8 -1462.4 116 P05 605 -1462.4 101 TST -965 -1462.4 117 P06 685 -1462.4 102 XT2 -723 -1462.4 118 P07 765 -1462.4 103 XT1 -643 -1462.4 119 P10 845 -1462.4 104 RESB -563 -1462.4 120 P11 925 -1462.4 -383.5 -1462.4 121 P12 1005 -1462.4 -272.5 -1462.4 122 P13 1085 -1462.4 -1462.4 105 106 VDD 107 CF1 -172 -1462.4 123 P14 1165 108 CF2 -92 -1462.4 124 P15 1245 -1462.4 3 -1462.4 125 P16 1325 -1462.4 108 -1462.4 126 P17 1405 -1462.4 109 110 VSS Note: • Pad coordinates shown in above table are referenced at the center of the IC-chip as an origin. • There are two pads for each VDD and VSS, and each set of pads needs double-bonding. 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 LCDVSS1 Pin Assignment LC88F83B0A 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56/SNO15/SGIN15 SEG57/SNO14/SGIN14 SEG58/SNO13/SGIN13 SEG59/SNO12/SGIN12 SEG60/SNO11/SGIN11 SEG61/SNO10/SGIN10 SEG62/SNO9/SGIN9 SEG63/SNO8/SGIN8 SEG64/SNO7/SGIN7/SGINT7 SEG65/SNO6/SGIN6/SGINT6 SEG66/SNO5/SGIN5/SGINT5 SEG67/SNO4/SGIN4/SGINT4 SEG68/SNO3/SGIN3/SGINT3 SEG69/SNO2/SGIN2/SGINT2 SEG70/SNO1/SGIN1/SGINT1/T3IH SEG71/SNO0/SGIN0/SGINT0/T3IL P23/AN3 P22/AN2 P21/AN1/T5O P20/AN0/T4O XT2 XT1 RESB VDD CF1 CF2 VSS P00/P0LI P01/P0LI P02/P0LI P03/P0LI P04/P0HLI P05/P0HLI P06/T0PWML P07/T0PWMH P10/SI0O P11/SI0IO P12/SI0CLK P13/T3OL P14/T3OH P15 P16/U2RX P17/U2TX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 VLCD4 VLCD3 VLCD2 VLCD1 TST SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG8 SEG9 COM15/SEG7 COM14/SEG6 COM13/SEG5 COM12/SEG4 COM11/SEG3 COM10/SEG2 COM9/SEG1 COM8/SEG0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 LCDVSS0 CUP00 CUP01 Top view SANYO: TQFP120(14×14) “Lead-free Type” No.A1228-8/25 LC88F83B0A Pin No. Name Pin No. Name Pin No. Name Pin No. 1 VLCD4 31 P20/AN0/T4O 61 LCDVSS1 91 Name 2 VLCD3 32 P21/AN1/T5O 62 SEG45 92 SEG16 3 VLCD2 33 P22/AN2 63 SEG44 93 SEG15 4 VLCD1 34 P23/AN3 64 SEG43 94 SEG14 5 TST 35 SEG71/SNO0 65 SEG42 95 SEG13 66 SEG41 96 SEG12 67 SEG40 97 SEG11 68 SEG39 98 SEG10 69 SEG38 99 SEG9 70 SEG37 100 SEG8 71 SEG36 101 COM15/SEG7 72 SEG35 102 COM14/SEG6 73 SEG34 103 COM13/SEG5 74 SEG33 104 COM12/SEG4 75 SEG32 105 COM11/SEG3 76 SEG31 106 COM10/SEG2 77 SEG30 107 COM9/SEG1 78 SEG29 108 COM8/SEG0 79 SEG28 109 COM7 80 SEG27 110 COM6 /SGIN0/SGINT0 /T3IL 6 36 SEG70/SNO1 /SGIN1/SGINT1 /T3IH 7 XT2 37 SEG69/SNO2 /SGIN2/SGINT2 8 XT1 38 SEG68/SNO3 /SGIN3/SGINT3 9 RESB 39 SEG67/SNO4 /SGIN4/SGINT4 10 VDD 40 SEG66/SNO5 /SGIN5/SGINT5 11 CF1 41 SEG65/SNO6 /SGIN6/SGINT6 12 CF2 42 SEG64/SNO7 /SGIN7/SGINT7 13 VSS 43 SEG63/SNO8 /SGIN8 14 P00/P0LI 44 SEG62/SNO9 /SGIN9 15 P01/P0LI 45 SEG61/SNO10 /SGIN10 16 P02/P0LI 46 SEG60/SNO11 /SGIN11 17 P03/P0LI 47 SEG59/SNO12 /SGIN12 18 P04/P0HLI 48 SEG58/SNO13 /SGIN13 19 P05/P0HLI 49 SEG57/SNO14 /SGIN14 20 P06/T0PWML 50 SEG56/SNO15 /SGIN15 21 P07/T0PWMH 51 SEG55 81 SEG26 111 COM5 22 P10/SI0O 52 SEG54 82 SEG25 112 COM4 23 P11/SI0IO 53 SEG53 83 SEG24 113 COM3 24 P12/SI0CLK 54 SEG52 84 SEG23 114 COM2 25 P13/T3OL 55 SEG51 85 SEG22 115 COM1 26 P14/T3OH 56 SEG50 86 SEG21 116 COM0 27 P15 57 SEG49 87 SEG20 117 LCDVSS0 28 P16/U2RX 58 SEG48 88 SEG19 118 CUP00 29 P17/U2TX 59 SEG47 89 SEG18 119 CUP01 60 SEG46 90 SEG17 120 30 No.A1228-9/25 LC88F83B0A System Block Diagram RESB Interrupt control System control TST Standby control OSC0 XT2 CF1 CF2 OSC1 X’tal RC ROM CF (128K×8bit) RC Clock XT1 IR Internal RC PC Base timer RAM SEG 0 to 71 WD timer (4K×8bit) LCD display RAM 72×16bit PSW LCD segment driver 72 terminals ALU SEG 71 to 56 (I/O 16 terminals) R0 to R15 COM 0 to 15 Common driver 16 terminals Timer 0 Timer 1 CUP00, 01 LCD power supply Timer 3 VLCD1 to 4 Timer 4 P00 to 07 I/O Port P10 to 17 I/O Port P20 to 23 I/O Port (ADC 4 terminals) Timer 5 UART2 SIO0 On-chip debugger No.A1228-10/25 LC88F83B0A Pin Description Pin Name VDD I/O - Description + power supply pin VSS - - power supply pin VLCD1 to 4 - LCD bias power port (capacitor connection port) LCDVSS0, LCDVSS1 - LCD power supply pin CUP00, 01 - Switching pin for generating LCD driving voltage Connect capacitor between both ports. OSC0 XT1 I Oscillator circuit for system clock (low speed) XT2 O • XT1: Resistor connection for RC oscillation (RC model) CF1 I Oscillator circuit for system clock (high speed) CF2 O • CF1: Resistance connection for RC oscillator (RC model) I/O • 8-bit I/O port • 32.768kHz crystal oscillator and capacitor for oscillation connection OSC1 • Ceramic oscillator and capacitor for oscillator connection PORT 0 • I/O specifiable in 1-bit units P00 to P07 • Shared pins P00 to P05 : Interrupt function P06: Timer 0 PWML output P07: Timer 0 PWMH output PORT 1 I/O • 8-bit I/O port • I/O specifiable in 1-bit units P10 to P17 • Shared pins P10: SIO0 data output P11: SIO0 data input/Bus I/O P12: SIO0 Clock I/O P13: Timer 3 PWML output P14: Timer 3 PWMH output P16: UART 2 receive P17: UART 2 send PORT 2 I/O • 4-bit I/O port • I/O specifiable in 1-bit units P20 to P23 P20 to P23: AD converter input ports (AN0 to AN3) • Shared pins P20: Timer 4 output P21: Timer 5 output COM0 to COM7 O • LCD common output port COM8/SEG0 to O • LCD common output port/segment output port SEG8 to SEG55 O • LCD segment output port SEG56 to SEG71 I/O • LCD segment output port COM15/SEG7 common output/segment output is switched according to the register. • SEG71 to SEG56: General purpose Nch OD output/General purpose input SEG71 to SEG56 can switch LCD output, a general-purpose Nch OD output, and a general-purpose input (every 4 bits). • SEG71 to SEG64: Interrupt function (every 4 bits) Selecting sampling frequency for chattering removal (every 4 bits) Level/edge selection (every 4 bits) Hi/Low level or rise/fall selection (every 1 bit) • SEG71 to SEG70: Timer 3 external input RESB I • Input terminal for system initialization It operates reset by the “LOW” input. with pull-up resistor TST I/O • TEST pin • On-chip debugger communication terminal Used with pull-down or VSS *Connect 100kΩ between this pin and VSS when on-chip debugger is used. No.A1228-11/25 LC88F83B0A Application circuit I/O UART device SEG71 SEG8 COM15/SEG7 P00 P01 P02 P03 P04 P05 P06 P07 COM8/SEG0 I/O COM7 COM0 LCD panel 64×16/72×8 CUP01 CUP00 LC88F83B0A P10 (SIO0-OUT) P11 (SIO0-IN) P12 (SIO0-CLK) P13 P14 P15 P16 (UART2-RX) P17 (UART2-TX) C1 VLCD4 VLCD3 C2 C3 VLCD2 VLCD1 C4 C5 2.3V to 5.5V VDD + RESB I/O On-chip debugger CRES P20 P21 P22 P23 VSS LCDVSS0 LCDVSS1 CF1 CF2 RTST XT2 TST CGC *3 CDC CDX *5 X'tal Crystal oscillator CGX Trimmer capacitor CDX Capacitance for X’tal RCR0 Resistor for low-speed oscillation *4: RC oscillation specification Capacitor for low-speed oscillation *4: RC oscillation specification (**1) CCR0 (**1) CF *4 CCR0 RCR0 0.1μF capacitor is recommended when using XT1/XT2 as a system clock. Ceramic oscillator CGC Capacitance for CF CDC Capacitance for CF RCR1 Resistor for high-speed oscillation CCR1 Capacitor for high-speed oscillation *5: RC oscillation specification C1 to C5 *1: Crystal oscillation *2: Internal RC oscillation *3: Ceramic oscillation CGX *1 X'tal CF CCR1 RCR1 XT1 Pulse output CDEN *5: RC oscillation specification Capacitor CDEN Electrolytic capacitor CRES Capacitance for RESB RTST Resister when on-chip debugger is used No.A1228-12/25 LC88F83B0A Absolute Maximum Ratings at Ta = 25°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Maximum supply VDD max VDD VDD VLCD max VLCD2 to VLCD4 VDD SEG0 to SEG71 VDD, VLCD4 voltage LCD supply voltage LCD maximum LCD max supply voltage COM0 to COM15 Input voltage VI(1) RESB, XT1, CF1 Input/output VIO(1) PORT 0, 1, 2 voltage Peak output SEG71 to SEG56 IOPH(1) PORT0, 2 High level output current current Current at each pin IOPH(2) PORT1 CMOS output selected Current at each pin Mean output IOMH(1) PORT0, 2 current (Note 1-1) CMOS output selected Current at each pin IOMH(2) PORT1 CMOS output selected Current at each pin typ max unit -0.3 +6.5 -0.3 +6.5 -0.3 +6.5 -0.3 VDD+0.3 -0.3 VDD+0.3 -14 -3 -9 ΣIOAH(1) PORT0, 2 Total of all pins current ΣIOAH(2) PORT1 Total of all pins 25 ΣIOAH(3) PORT 0, 1, 2 Total of all pins 47.5 IOPL(1) PORT0, 2 Current at each pin current IOPL(2) PORT1 Current at each pin 17 Mean output IOML(1) PORT0, 2 Current at each pin 7.5 current IOML(2) PORT1 Current at each pin ΣIOAL(1) PORT0, 2 Total of all pins ΣIOAL(2) PORT1 Total of all pins ΣIOAL(3) PORT 0, 1, 2 Total of all pins Pd max TQFP120(14×14) Ta=-20 to +75°C 22.5 10.5 35 current Allowable power 60 80 250 dissipation Operating ambient Topg temperature Storage ambient Tstg temperature mA 13 (Note 1-1) Total output V -5 Total output Peak output Low level output current CMOS output selected min -20 75 -65 125 mW °C Note 1-1: The mean output current is a mean value measured over 100ms. Note: We assume that the measurements for the allowable operating ranges and electrical characteristics described in this document are performed with the chip mounted in a package. Although this product is shipped in chip form, the characteristic values listed in this document are measured with this IC mounted on a SANYO-designated package at operating ambient temperature range of -20°C to +70°C. The specifications of this product in package form or in chip forms are basically identical, however, the characteristics of the product in chip form may vary depending on the board on which the product is mounted, the bonding pressure, and the type of mold resin used. No.A1228-13/25 LC88F83B0A Allowable Operating Conditions at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Operating Pin Symbol VDD(1) VDD supply voltage (Note2-1) LCD drive VLCD(1) VLCD2 to VLCD4 VHD VDD Ratings Conditions /Remarks VDD[V] min typ sustaining unit 2.6 5.5 0.476μs≤tCYC≤100μs 2.4 5.5 0.909μs≤tCYC≤100μs 2.3 5.5 5.5 voltage Memory max 0.238μs≤tCYC≤100μs RAM and register contents sustained in HOLD mode. 2.0 5.5 V supply voltage High level VIH(1) Port 0, 1 Output disabled 0.30VDD input voltage Low level VIH(2) RESB VIL(1) Port 0, 1 VIL(2) RESB FOSC0 XT1, XT2 0.75VDD Output disabled Crystal oscillation Low speed RC oscillation range (Note2-2) FOSC1 FINTRC CF1, CF2 +0.40 VSS frequency (Note2-3) VDD 0.10VDD VSS input voltage Oscillating VDD +0.70 2.3 to 5.5 0.25VDD 32.768 2.3 to 5.5 30 80 Ceramic oscillation 2.4 to 5.5 400 4200 High-speed RC oscillation 2.4 to 5.5 400 4200 (Note2-2) 2.3 to 5.5 400 Internal RC oscillation kHz 1100 1000 Note2-1: VDD must be held greater than or equal to 2.7V in the flash ROM onboard programming mode. Note2-2: Ta=0°C to 60°C Note2-3: The parts value of oscillation circuit is shown in table 1 and table 2. No.A1228-14/25 LC88F83B0A Electrical Characteristics at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] High level input IIH(1) PORT 0, 1, 2 current min typ max unit Output disabled Pull-up resister OFF VIN=VDD (including OFF state leak 2.7 to 5.5 1 2.7 to 5.5 1 current of the output Tr.) Low level input IIH(2) RESB VIN=VDD IIL(1) PORT 0, 1, 2 Output disabled current Pull-up resister OFF VIN=VSS (including OFF state leak 2.7 to 5.5 -1 4.5 to 5.5 -117 μA current of the output Tr.) IIL(2) PORT 0, 1, 2 -25 Pull-up resister ON 2.7 to 3.0 -31 -5.8 RESB VIN=VSS (including OFF state leak 4.5 to 5.5 -10.2 -3.7 current of the output Tr.) 2.7 to 3.0 -6.3 VOH(1)=VDD-1.0V 4.5 to 5.5 -3.7 -1.6 IIL(3) IIL(4) Output disabled IIL(5) -2.4 High level output IOH(1) CMOS output mode current IOH(2) PORT0, 2 2.7 to 3.0 IOH(3) CMOS output mode 4.5 to 5.5 -10 IOH(4) PORT1 2.7 to 3.0 -4.5 Low level output IOL(1) PORT0, 2 current IOL(2) IOL(3) VOL(1)=VSS+1.0V 4.5 to 5.5 10 2.7 to 3.0 4.4 PORT1 4.5 to 5.5 14.5 2.7 to 3.0 6.5 SEG71 to SEG56 4.5 to 5.5 0.5 2.7 to 3.0 0.5 IOL(4) IOL(5) IOL(6) Common output IOH(5) current IOL(7) Segment output IOH(6) current IOL(8) Hysterisis voltage VHYS(1) COM0 to COM15 VOH(2)=VLCD4-0.05V VOL(2)=VSS+0.05V SEG0 to SEG71 VOH(2)=VLCD4-0.05V RESB Pin capacitance CP All pins -25 2.7 to 5.5 25 2.7 to 5.5 VOL(2)=VSS+0.05V PORT 0, 1, 2 mA μA -10 10 2.7 to 5.5 0.1VDD V 2.7 to 5.5 10 pF For pins other than that under test: VIN=VSS f=1MHz Ta=25°C No.A1228-15/25 LC88F83B0A LCD Drive Voltage at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Special notes: 0.1μF capacitor must be connected to VLCD1, VLCD2, VLCD3, and VLCD4. (with no panel load) Parameter Symbol Pin/Remarks Specification Conditions VDD[V] LCD drive voltage VLCD1 VDD VLCD1 min typ Contrast “00” 1.030 Contrast “01” 1.045 Contrast “02” 1.060 Contrast “03” 1.075 Contrast “04” 1.090 Contrast “05” 1.105 Contrast “06” 1.120 max Contrast “07” Typ 1.135 Typ Contrast “08” ×0.88 1.150 ×1.10 Contrast “09” 2.4 to 5.5 1.165 Contrast “10” 1.180 Contrast “11” 1.195 Contrast “12” 1.210 Contrast “13” 1.225 Contrast “14” 1.240 Contrast “15” 1.255 VLCD2 2×VLCD1 VLCD3 3×VLCD1 VLCD4 4×VLCD1 unit V No.A1228-16/25 LC88F83B0A Serial I/O Characteristics at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V 1. SIO0 Serial I/O Characteristics (Wake-up function is not in use) (Note 4-1-1) Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Frequency tSCK(1) Low level tSCKL(1) SCK0(P12) See Fig. 6. max unit 2 tSCKH(1) 2 pulse width Input clock typ 4 pulse width High level min tSCKHA(1) Automatic communication mode 2.3 to 5.5 6 tCYC See Fig. 6. tSCKHBSY(1a) Automatic communication 23 mode See Fig. 6. tSCKHBSY(1b) Excluding Automatic communication mode 4 Serial clock See Fig. 6. Frequency tSCK(2) SCK0(P12) CMOS output selected 4 See Fig. 6. Low level tSCKL(2) 1/2 pulse width High level tSCK tSCKH(2) 1/2 pulse width Output clock tSCKHA(2) Automatic communication mode CMOS output selected 2.3 to 5.5 6 See Fig. 6. tSCKHBSY(2a) Automatic communication mode 4 CMOS output selected 23 tCYC See Fig. 6. tSCKHBSY(2b) Excluding automatic 4 communication mode See Fig. 6. Serial input Data setup time SI0(P11), Must be specified with respect SB0(P11) to rising edge of SIOCLK. See Fig. 6. Data hold time thDI(1) 0.03 2.3 to 5.5 0.03 Output clock Input clock Output Serial output tsDI(1) tdD0(1) delay time SO0(P10), (Note4-1-2) SB0(P11) 1tCYC μs +0.05 tdDO(2) (Note4-1-2) 2.3 to 5.5 1tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig.6. No.A1228-17/25 LC88F83B0A 2. SIO1 Serial I/O Characteristics (Wake-up function is not in use) (Note 4-2-1) Parameter Symbol Pin/Remarks Specification Conditions Input clock Serial clock VDD[V] Frequency tSCK(3) Low level tSCKL(3) SCK0(P12) typ See Fig. 6. 2.3 to 5.5 tSCKH(3) tCYC 1 tSCKHBSY(3) Serial input tsDI(2) 2 SI0(P11), Must be specified with respect SB0(P11) to rising edge of SIOCLK. See Fig. 6. Data hold time unit 2 pulse width Data setup time max 1 pulse width High level min thDI(2) 0.03 2.3 to 5.5 0.03 Input clock Serial output μs Output tdD0(3) SO0(P10), (Note4-2-2) SB0(P11) delay time 1tCYC 2.3 to 5.5 +0.05 Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Note 4-2-2: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig.6. UART2 Operating Conditions at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Transfer rate UBR2 URX2(P16), min 2.3 to 5.5 UTX2(P17) typ 8 max 4096 unit tCYC Pulse Input Conditions at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] High/low level pulse width tPIL(1) RESB Resetting is enabled. 2.3 to 5.5 min 50 typ max unit μs No.A1228-18/25 LC88F83B0A AD Converter Characteristics at VSS = LCDVSS0 = LCDVSS1 = 0V <12-bits AD Converter Mode/Ta= -10°C to +75°C> Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Resolution N AN0(SEG71) Absolute accuracy ET to Conversion time TCAD 2.9 to 5.5 (Note7-1) AN3(SEG68) typ max See Conversion time calculation VAIN voltage range unit 12 2.9 to 5.5 formulas. (Note7-2) Analog input min bit ±16 LSB 2.9 to 5.5 90 130 μs 2.9 to 5.5 VSS VDD V Analog ports input IAINH VAIN=VDD 2.9 to 5.5 current IAINL VAIN=VSS 2.9 to 5.5 1 μA -1 <8-bits AD Converter Mode/Ta= -10°C to +75°C > Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Resolution N AN0(SEG71) Absolute accuracy ET to Conversion time TCAD (Note7-1) AN3(SEG68) See Conversion time calculation VAIN voltage range typ max unit 8 bit ±1.5 2.9 to 5.5 formulas. (Note7-2) Analog input min 2.9 to 5.5 LSB 2.9 to 5.5 55 75 μs 2.9 to 5.5 VSS VDD V Analog ports input IAINH VAIN=VDD 2.9 to 5.5 current IAINL VAIN=VSS 2.9 to 5.5 1 -1 μA <Conversion Time Calculation Formulas> 12-bits AD Converter Mode: TCAD (Conversion time) = ((52/(Division ratio))+2) × tCYC 8-bits AD Converter Mode: TCAD (Conversion time) = ((32/(Division ratio))+2) × tCYC <Recommended Operating Conditions> External Operating Supply System Division Oscillator Voltage Range Ratio FmCF[MHz] VDD[V] (SYSDIV) CF-4 2.9 to 4.0 Cycle Time AD Division Ratio tCYC [ns] (ADDIV) AD Conversion Time (TCAD)[μs] 12-bit AD 8-bit AD 1/1 250 1/8 104.5 64.5 1/2 500 1/4 105.0 65.0 Note 7-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 7-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: • The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode. No.A1228-19/25 LC88F83B0A Consumption Current Characteristics at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Consumption Symbol IDDOP(1) current during normal IDDOP(2) VDD Specification Conditions VDD[V] Crystal oscillation mode LCD • FOSC0=32.768kHz Display • System clock: FOSC0 ON • Internal RC oscillation stopped operation (Note 8-1) Pin/ Remarks • FOSC1=0Hz (Oscillation stop) LCD • 1/1frequency division ratio. Display IDDOP(4) [No panel load] OFF IDDOP(5) Ceramic oscillation mode IDDOP(3) • FOSC1=4MHz min typ max 2.4 to 5.5 70 150 2.4 to 3.6 50 80 2.3 to 5.5 70 120 2.3 to 3.6 40 70 2.4 to5.5 3000 4100 2.4 to 3.6 2200 2900 2.3 to 5.5 1900 3000 unit • System clock: FOSC1 IDDOP(6) • Internal RC oscillation stopped • FOSC0=0Hz (Oscillation stop) • 1/2 frequency division ratio. IDDOP(7) Internal RC oscillation mode • System clock: Internal RC • Internal RC oscillates IDDOP(8) μA • FOSC0=0Hz (Oscillation stop) • FOSC1=0Hz (Oscillation stop) 2.3 to3.6 1200 2000 2.3 to 5.5 1700 2300 2.3 to 3.6 1200 1700 2.3 to 5.5 110 170 2.3 to 3.6 70 110 • 1/1 frequency division ratio IDDOP(9) High-speed RC oscillation mode *Ta=0 to 60°C • FOSC1=1MHz RCR1=470kΩ IDDOP(10) • System clock: FOSC1 • Internal RC oscillation stopped • FOSC0=0Hz (Oscillation stop) • 1/1 frequency division ratio. IDDOP(11) Low-speed RC oscillation mode *Ta=0 to 60°C • FOSC0=64kHz RCR0=910kΩ IDDOP(12) • System clock: FOSC0 • Internal RC oscillation stopped • FOSC1=0Hz (Oscillation stop) • 1/1 frequency division ratio. Note 8-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.A1228-20/25 LC88F83B0A Continued from preceding page. Parameter Consumption Symbol IDDHALT(1) Pin/ VDD current during HALT mode IDDHALT(2) Specification Condition Remarks VDD[V] HALT mode LCD Crystal oscillation mode Display • FOSC0=32.768kHz ON • System clock: FOSC0 (Note 8-1) IDDHALT(3) IDDHALT(4) • Internal RC oscillation stopped LCD • FOSC1=0Hz (Oscillation stop) Display • 1/1frequency division ratio. OFF [No panel load] min typ max 2.4 to 5.5 32 93 2.4 to 3.6 15 35 2.3 to 5.5 22 59 2.3 to 3.6 6 21 2.4 to 5.5 700 1100 2.4 to 3.6 300 500 2.3 to 5.5 400 700 2.3 to 3.6 200 300 unit HALT mode IDDHALT(5) Ceramic oscillation mode • FOSC1=4MHz • System clock: FOSC1 IDDHALT(6) • Internal RC oscillation stopped • FOSC0=0Hz (Oscillation stop) • 1/2 frequency division ratio. HALT mode IDDHALT(7) Internal RC oscillation mode • System clock: Internal RC • Internal RC oscillates IDDHALT(8) • FOSC0=0Hz (Oscillation stop) • FOSC1=0Hz (Oscillation stop) • 1/1 frequency division ratio. IDDHALT(9) μA HALT mode High-speed RC oscillation mode *Ta=0 to 60°C 2.3 to 5.5 200 400 2.3 to 3.6 100 200 2.3 to 5.5 20 50 2.3 to 3.6 10 30 • FOSC1=1MHz RCR1=470kΩ • System clock: FOSC1 IDDHALT(10) • Internal RC oscillation stopped • FOSC0=0Hz (Oscillation stop) • 1/1 frequency division ratio. IDDHALT(11) HALT mode Low-speed RC oscillation mode *Ta=0 to 60°C • FOSC0=64kHz RCR0=910kΩ • System clock: FOSC0 IDDHALT(12) • Internal RC oscillation stopped • FOSC1=0Hz (Oscillation stop) • 1/1 frequency division ratio. Consumption current during HOLD mode Consumption IDDHOLD(1) VDD IDDHOLD(2) IDDHOLD(3) VDD Clock HOLD mode • CF1=VDD or OPEN (External clock mode) current during clock HOLD HOLD mode • CF1=VDD or OPEN (External clock mode) • FmX’tal=32.768kHz crystal oscillation IDDHOLD(4) mode mode 2.3 to 5.5 12 2.3 to 3.6 5 2.3 to 5.5 16 55 2.3 to 3.6 3 16 Note 8-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Onboard Symbol IDDFW(1) programming Pin/ Remarks VDD Specification Conditions VDD[V] min typ max unit The consumption current of the microcomputer is excluded. 2.7 to 5.5 5 10 mA current Programming tFW(1) Erasing time: 128 bytes 2.7 to 5.5 20 30 ms time tFW(2) Programming time: 2 bytes 2.7 to 5.5 40 60 μs No.A1228-21/25 LC88F83B0A Characteristics of a Sample OSC1 System Clock Oscillation Circuit Given below are the characteristics of a sample OSC1 system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample OSC1 System Clock Oscillator Circuit with a Ceramic Oscillator Nominal Vendor Oscillator Frequency Name Name 4.194MHz 4.000MHz MURATA MURATA Circuit Constant Operating Oscillation Voltage Stabilization Time C1 C2 Rf1 Rd1 Range typ max [pF] [pF] [Ω] [Ω] [V] [ms] [ms] CSTCR4M00G53-R0 (15) (15) OPEN 0 2.4 to 5.5 0.1 0.5 CSTLS4M00G53-B0 (15) (15) OPEN 0 2.4 to 5.5 0.1 0.5 CSTCR4M00G53-R0 (15) (15) OPEN 0 2.4 to 5.5 0.1 0.5 CSTLS4M00G53-B0 (15) (15) OPEN 0 2.4 to 5.5 0.1 0.5 Remarks Internal C1,C2 Internal C1,C2 The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the following reference timing points: (See Figure 4) • VDD goes above the operating voltage lower limit. • An instruction for starting the OSC1 clock oscillator circuit is executed. • Oscillation starts after the microcontroller exits the X'tal HOLD mode with the ENOSC1 bit (OCR0 register, bit 1) set to 1. Characteristics of a Sample OSC0 System Clock Oscillator Circuit Given below are the characteristics of a sample OSC0 system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample OSC0 System Clock Oscillator Circuit with a CF Oscillator Nominal Frequency 32.768kHz Circuit Constant Vendor Name EPSON TOYOCOM Oscillator Name Operating Oscillation Voltage Stabilization Time C3 C4 Rf2 Rd2 Range typ max [pF] [pF] [Ω] [Ω] [V] [s] [s] 18 18 OPEN 390k 2.3 to 5.5 1.3 3.0 Remarks Applicable MC-306 CL value=12.5pF SMD-type The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the OSC0 clock oscillation circuit is executed. (See Figure 4) Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. Rf2 Rf1 CF1 CF2 XT1 XT2 Rd1 C1 C2 Rd2 C3 C4 CF X’tal Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.A1228-22/25 LC88F83B0A VDD Operating VDD lower limit 0V Power supply Reset time RESB Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal absent HOLD reset signal valid Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 State HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time No.A1228-23/25 LC88F83B0A VDD Note: Select CRES and RRES values to assure that at least 50μs reset time is provided after the VDD becomes higher than the minimum operating voltage. RRES RESB CRES Figure 5 Reset Circuit tSCKHBSY tSCKHBSY RUN: SIOCLK: DATAIN: DI0 DI1 DI6 DI7 DI8 DIx DATAOUT: DO0 DO1 DO6 DO7 DO8 DOx Data RAM transfer period (SIO0 only) tSCK SIOCLK: tSCKL tSCKH tsDI thDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 only) SIOCLK: tSCKL tSCKHA tsDI thDI DATAIN: tdDO DATAOUT: *: Remarks: DIx and DOx are the final communication bits. X = 0 to 32768 Figure 6 Serial I/O Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.A1228-24/25 LC88F83B0A Note: The oscillation frequency changes with the board pattern and used parts when OSC1 and OSC0 are used as the RC oscillation. It also greatly depends on the product shape (chip and plastic package) and the board capacitance, and it is recommended to evaluate the resistor value with an actual product. Use the following characteristics as only for a reference. Frequency - Resistor Frequency - Resistor 1000 Ta=25°C, typ Ta=25°C, typ 7 7 5 5 3 3 Frequency - kHz Frequency - MHz 10 2 1.0 7 5 2 100 7 5 3 3 2 2 0.1 10 0 200 400 600 Resistor - kΩ 800 1000 1200 ILC05650 Figure 8 Characteristics of Resistor v.s. Frequency of OSC1 0 200 400 600 800 1000 Resistor - kΩ 1200 ILC05651 Figure 9 Characteristics of Resistor v.s. Frequency of OSC0 SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of March, 2011. Specifications and information herein are subject to change without notice. PS No.A1228-25/25