SANYO LC78605E

Ordering number : ENN7735
SANYO Semiconductors
DATA SHEET
CMOS IC
LC78605E
Compact Disc Player DSP with
Built-in Microcontroller
Overview
The LC78605E CMOS IC implements the signal processing, servo control, LCD display, button state acquisition, and
remote controller handling required by compact disc players without requiring a separate microcontroller. It provides
the following basic functions: demodulation of the EFM signal from the optical pickup, deinterleaving, error detection
and correction, 8× oversampling audio filters, D/A converter (with built-in analog low-pass filter), LCD display drivers,
key acquisition (A/D) and control processing, and automatic discrimination and playback of CD-RW discs. Thus the
LC78604E is ideal for implementing low-end CD players that support playback of CD-RW discs.
The LC78604E also provides a radio tuner frequency display function, and allows digital display of the selected
frequency in manual tuning CD radio/cassette players.
Functions
• Implements the CD play/pause, stop, track selection, fast forward/fast rewind, repeat 1/repeat all, program
setup/play/clear for up to 30 tracks, and shuffle play functions controlled from CD player buttons.
<Signal-Processing Block>
• The signal-processing block applies slicing at the correct level to the input HF signal, and converts that signal to an
EFM signal. At the same time it generates a PLL clock signal with an average frequency of 4.3218MHz by
comparing the phase with that of the internal VCO.
• A reference clock signal and all necessary timings can be generated using an external 16.9344MHz crystal.
• The disc motor speed is controlled by a frame phase difference signal created from the playback clock and the
reference clock.
• Performs frame sync signal detection, protection, and interpolation to assure stable data readout.
• Demodulates the EFM signal and converts the result to 8-bit symbol data.
• Separates the subcode data from the EFM signal and outputs that data to the internal control processing block.
• After applying a CRC check to the subcode Q data, outputs that data to the internal control processing block.
• Buffers the demodulated EFM signal in internal RAM and compensates for up to ±4 frames of jitter due to
fluctuations in the disc speed.
• Applies unscrambling and deinterleaving to the demodulated EFM signal in the stipulated order.
• Performs error detection, correction, and flag processing (C1: double, C2: double).
• Sets the C2 flags according to the C1 flags and the C2 check and applies interpolation and previous value hold
processing to the output signal according to the C2 flags. This interpolation circuit implements 2-value
interpolation. A previous value hold operation is applied if the C2 flags indicate errors for over 2 consecutive
samples.
• The internal control processing block controls the track jump, focus start, disc motor start/stop, muting on/off, track
count, and other operations.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
32504TN (OT) No.7735-1/11
LC78605E
• Uses 8× oversampling digital filters to produce output data with improved continuity for the D/A converter.
• Built-in third-order noise shaper ∆∑ D/A converter and built-in analog low-pass filters
• Digital deemphasis function
• Zero cross muting
• Automatic discrimination and playback of CD-RW discs
<Display Block>
• Built-in LCD display driver supports 7-segment 3-digit plus symbol displays
• Monitor display for the play, program, repeat, random, and tuner functions
<Control Processing Block>
• A/D based key acquisition for play/pause, stop, forward scan, backward scan, repeat, program, and random
functions.
Features
• 64-pin QIP
• Supply voltage: 3.3V single source
Specifications
Absolute Maximum Ratings at Ta=25°C, VSS=0V
Parameter
Symbol
Maximum supply voltage
Conditions
Ratings
Unit
VDD max
VSS – 0.3 to VSS + 4.0
V
VIN
VSS – 0.3 to VDD + 0.3
V
VOUT
VSS – 0.3 to VDD + 0.3
Input voltage
Output voltage
Allowable power dissipation
Pdmax
300
V
mW
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–40 to +125
°C
Allowable Operating Ranges at Ta=–20 to +75°C, VDD=3.0V to 3.6V, VSS=0V
Parameter
Supply voltage
Symbol
VDD
VIH (1)
Pin name
Conditions
DVDD, XVDD, LRVDD, AVDD
DRF, DEFI
Ratings
min
typ
Unit
max
3.0
3.6
V
0.7VDD
VDD
V
0.8VDD
VDD
V
0.6VDD
VDD
V
0
0.3VDD
V
0
0.2VDD
V
0
0.4VDD
HFL, TES, FMAMB, REMOTE,
Input high-level voltage
VIH (2)
PUIN, CLOSE, CDRESB,
TUNERESB, MONI1 to 3
VIH (3)
EFMI
VIL (1)
DRF, DEFI
HFL, TES, MODE, FMAMB,
Input low-level voltage
VIL (2)
REMOTE, PUIN, CLOSE,
CDRESB, TUNERESB, MONI1 to 3
VIL (3)
EFMIN
VIN (1)
EFMIN
VIN (2)
XIN16M, XIN32K
Input level
Input amplitude applied to the
VIN (3)
coupling capacitor connected to
the TUNERIN pin
Operating frequency range
Slice level control
Capacitor coupled
input
* Conditions 1
* Conditions 2
V
0.66
Vp-p
1.0
Vp-p
0.05
Vrms
Fop
EFMIN
10
MHz
Fam
TUNERIN
FMAMB=“L”
0.5
5
MHz
Ffm
TUNERIN
FMAMB=“H”
50
120
MHz
Crystal oscillator frequency
FX16
XIN16M, XOUT16M
16.9344
MHz
Crystal oscillator frequency
FX32
XIN32K, XOUT32K
32.768
kHz
* Conditions 1: The coupling capacitor must be located as close as possible to the TUNERIN pin.
* Conditions 2: Coupling capacitor: 100pF ±20 pF
No.7735-2/11
LC78605E
Electrical Characteristics at Ta=–20 to +75°C, VDD=3.0V to 3.6V, VSS=0V
Parameter
Symbol
Current drain
IDD
Pin name
Conditions
Ratings
min
typ
DVDD, XVDD, LRVDD, AVDD
Unit
max
20
30
mA
VIN=VDD
5
µA
VIN=VDD
100
µA
DRF, DEFI, HFL, TES, FMAMB,
IIH (1)
Input high-level current
REMOTE, PUIN, CLOSE,
CDRESB, TUNERSB, EFMIN,
TUNERIN
IIH (2)
MONI1 to 3
DRF, DEFI, HFL, TES, FMAMB,
REMOTE, CDRESB, TUNERSB,
IIL (1)
Input low-level current
MONI1 to 3, MODE, EFMIN,
VIN=0V
–5
µA
VIN=0V
–100
µA
IOH=–1mA
VDD–0.4
V
IOH=–2mA
VDD–0.4
V
TUNERIN
IIL (2)
PUIN, CLOSE
CLK, RWB, RWC, COIN, CQCKB,
VOH (1)
DEFINT, TOFF, TGL, AMUTEB,
DMUTEB
Output high-level voltage
VOH (2)
CLVO, JPO, SL+, SL–,
MONI1 to 3
VOH (3)
SEG1 to SEG7
IOH=–0.01mA
VDD–0.5
V
VOH (4)
COM1 to COM4
IOH=–0.01mA
VDD–0.5
V
CLK, RWB, RWC, COIN, CQCKB,
VOL (1)
DEFINT, TOFF, TGL, AMUTEB,
IOL=1mA
0.4
V
IOL=2mA
0.4
V
DMUTEB
Output low-level voltage
VOL (2)
Output off leakage current
CLVO, JPO, SL+, SL–,
MONI1 to 3
VOL (3)
SEG1 to SEG7
IOL=0.01mA
0.5
V
VOL (4)
COM1 to COM4
IOL=0.01mA
0.5
V
+5
µA
In the high-impedance
IOFF
PDO, CLVO, JPO
Pull-up resistance
RPU
PUIN, CLOSE
80
Pull-down resistance
RDW
MONI1 to 3
80
Charge pump output current
IPDOH
PDO
IPDOL
PDO
output state
ISET=100kΩ
–5
kΩ
kΩ
80
100
120
µA
–120
–100
–80
µA
Package Dimensions
unit : mm
3159A
33
32
64
17
14.0
49
1
17.2
48
0.8
17.2
14.0
16
0.8
0.35
0.15
0.1
3.0max
(2.7)
(1.0)
SANYO : QIP64E (14 × 14)
No.7735-3/11
LC78605E
1-Bit D/A Converter Block Analog Characteristics at Ta=25°C, VDD=3.3V, VSS=0V
Parameter
Symbol
Pin name
Ratings
Conditions
min
typ
Unit
max
With a 1kHz, 0dB signal input
Total harmonic distortion
THD+N
LCHO, RCHO
With the 20kHz low-pass filter
0.025
0.04
%
(built into the AD725D) used
With a 1kHz, –60dB signal input
Dynamic range
DR
LCHO, RCHO
With the 20kHz low-pass and A
85
87
dB
88
90
dB
80
82
dB
filters (built into the AD725D) used
With a 1kHz, 0dB signal input
Signal-to-noise ratio
S/N
LCHO, RCHO
With the 20kHz low-pass and A
filters (built into the AD725D) used
With a 1kHz, 0dB signal input
Crosstalk
CT
LCHO, RCHO
With the 20kHz low-pass filter
(built into the AD725D) used
* : Measured in normal playback mode in the Sanyo 1-bit D/A converter reference circuit.
1-bit D/A converter output block reference circuit
LC78605
LRVDD
4.7µF
2.2kΩ
LCHO(RCHO)
LPF
1500pF
100kΩ
Analog output
LCH (RCH)
Shibasoku Co., Ltd.
AD725D
LRVSS
XIN
C
XOUT
Oscillator
element
C
X’tal
Oscillator element: 16.9344MHz
The following oscillator elements are recommended :
CSTLS16M9X53-B0 (built-in capacitor) (Murata Mfg. Co., Ltd.)
CSTCE16M9V53-R0 (built-in capacitor) (Murata Mfg. Co., Ltd.)
No.7735-4/11
LC78605E
LC78605E
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DVSS
PUIN
CLOSE
REMOTE
FMAMB
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COM1
COM2
COM3
COM4
DVDD
SL+
SL–
DMUTEB
AMUTEB
MODE
LCHO
LRVDD
LRVSS
RCHO
XVSS
XOUT16M
XIN16M
XVDD
XOUT32K
XIN32K
EFMI
DRF
DEFI
CLK
RWB
RWC
COIN
CQCKB
FSEQ
CLVO
HFL
JPO
TES
TOFF
TGL
DVSS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SLCO
AVDD
FR
ISET
PDO
AVSS
AD3
AD2
AD1
CDRESB
TUNERESB
MONI1
MONI2
MONI3
TUNERIN
DVDD
Pin Assignment
Top view
No.7735-5/11
LC78605E
LRVDD
LRVSS
Subcode
Separator
Q, CRC
C1, C2 Error Detection
& Correction Flag
Processing
CLV Digital
Servo
CDRESB
TUNERESB
RAM
2K × 8bits
Clock
Generator
Interpolation Mute
8X Over Sampling
Digital Filter
1bit DAC
MODE
LPF
Commander
CONTROL
LCD
Controller
&
Driver
A/D
TUNER
Counter
Port I/F
XIN16M
XOUT16M
XIN32K
XOUT32K
LCHO
RCHO
COM1
COM2
COM3
COM4
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
TUNERIN
FMAMB
HFL
TES
RWB
TOFF
TGL
JPO
DRF
AD1
AD2
AD3
SL+
SL–
MONI1
MONI2
MONI3
Slice Level
Control
Synchronization Detection
EFM demodulation
REMOTE
CLVO
VCO Clock
Control
CLK
COIN
CQCKB
RWC
AMUTEB
DMUTEB
PUIN
CLOSE
FSEQ
ISET
FR
PDO
DEFI
EFMI
SLCO
AVDD
AVSS
DVDD
DVDD
DVSS
DVSS
XVDD
XVSS
Equivalent Block Diagram
No.7735-6/11
LC78605E
Pin Functions
Pin No.
Pin Name
I/O
1
EFMI
I
2
DRF
I
3
DEFI
I
4
CLK
O
Pin state when
Pin state when
CDRESB is low
TUNERESB is low
EFM signal input
—
—
DRF signal input
—
—
—
—
Clock output
Undefined
Low-level output
Undefined
Function
Defect detection signal (DEF) input
(Must be connected to ground if unused.)
ASP system clock output (132.3kHz [16.9344MHz/128])
RW support control signal
5
RWB
O
Low-level output: Indicates that a CD-RW disc is being played
High-level output: Indicates that a CD-DA/R disc is being played
6
RWC
O
Command write control signal output
Low-level output
Undefined
7
COIN
O
Command data signal output
High-level output
Undefined
8
CQCKB
O
Command data transfer clock signal output
High-level output
Undefined
Low-level output
Undefined
Sync signal detection output monitor
9
FSEQ
O
A high level is output when the sync signal detected from the EFM signal
matches the internally generated sync signal.
Spindle motor control signal output
10
CLVO
O
11
HFL
I
Low-level output: Decelerate
High-impedance
High-level output: Accelerate
output
Undefined
High-impedance output: Neither accelerate nor decelerate
Track detection signal input (Schmitt trigger input)
—
—
Track jump control signal output
Low-level output: When moving away from the center: decelerate
12
JPO
O
When moving towards the center: accelerate
High-level output: When moving away from the center: accelerate
High-impedance
output
Undefined
When moving towards the center: decelerate
High-impedance output: Neither accelerate nor decelerate
13
TES
I
Tracking error signal input (Schmitt trigger input)
Tracking off signal output
14
TOFF
O
Low-level output: Tracking on
High-level output: Tracking off
15
TGL
O
16
DVSS
—
17
DVDD
—
18
SL+
O
19
SL–
O
20
DMUTEB
O
21
AMUTEB
O
22
MODE
I
Tracking gain switching signal output
—
—
High-impedance
output
Undefined
Undefined
Undefined
Digital system ground. This pin must be connected to the 0V level.
—
—
Digital system power supply
—
—
Low-level output
Undefined
Low-level output
Undefined
Low-level output
Undefined
Low-level output
Undefined
—
—
Low-level output: Gain increase
Sled feed signal outputs
Driver muting control signal output
Low-level output: When the driver is muted
Audio muting control signal output
Low in audio mute mode
Operating mode selection
This pin must be connected to the 0V level.
23
LCHO
O
D/A converter left channel signal output
Undefined
Undefined
24
LRVDD
—
D/A converter power supply
—
—
25
LRVSS
—
D/A converter ground. This pin must be connected to the 0V level.
—
—
26
RCHO
O
D/A converter right channel signal output
Undefined
Undefined
27
XVSS
—
Digital system ground. This pin must be connected to the 0V level.
28
XOUT16M
O
Connections for a 16.9344MHz crystal oscillator element.
29
XIN16M
I
30
XVDD
—
31
XOUT32K
O
Connections for a 32.768kHz crystal oscillator element.
32
XIN32K
I
(Oscillation is stopped when CDRESB is high.)
33
COM4
O
Common driver output (4)
—
—
Clock output
Undefined
(Oscillation is stopped when TUNERESP is high.)
—
—
Digital system power supply
—
—
Undefined
Clock output
—
—
High-level output
High-level output
34
COM3
O
Common driver output (3)
High-level output
High-level output
35
COM2
O
Common driver output (2)
High-level output
High-level output
36
COM1
O
Common driver output (1)
High-level output
High-level output
37
SEG1
O
Segment output (1)
High-level output
High-level output
38
SEG2
O
Segment output (2)
High-level output
High-level output
39
SEG3
O
Segment output (3)
High-level output
High-level output
40
SEG4
O
Segment output (4)
High-level output
High-level output
41
SEG5
O
Segment output (5)
High-level output
High-level output
42
SEG6
O
Segment output (6)
High-level output
High-level output
43
SEG7
O
Segment output (7)
High-level output
High-level output
Continued on next page.
No.7735-7/11
LC78605E
Continued from preceding page.
Pin No.
Pin Name
I/O
44
FMAMB
I
45
REMOTE
I
Pin state when
Pin state when
CDRESB is low
TUNERESB is low
Tuner display switching selection input (Schmitt trigger input)
—
—
Remote control signal input (Schmitt trigger input)
—
—
—
—
—
—
Function
Close switch detection signal input.
46
CLOSE
I
47
PUIN
I
48
DVSS
—
Digital system ground. This pin must be connected to the 0 V level.
—
—
49
DVDD
—
Digital system 3.3V power supply
—
—
50
TUNERIN
I
Tuner frequency display input
—
—
(Low-level output)
Undefined
(Low-level output)
Undefined
(Low-level output)
Undefined
—
—
—
—
51
MONI3
I/O
52
MONI2
I/O
53
MONI1
I/O
54
TUNERESB
I
A pull-up resistor is built in. (Schmitt trigger input)
Limit switch detection signal input.
A pull-up resistor is built in. (Schmitt trigger input)
Internal signal monitor pin 3. (Schmitt trigger input)
A pull-down resistor is built in. (Default: input mode)
Internal signal monitor pin 2. (Schmitt trigger input)
A pull-down resistor is built in. (Default: input mode)
Internal signal monitor pin 1. (Schmitt trigger input)
A pull-down resistor is built in. (Default: input mode)
Reset input for this IC’s tuner display block.
A pull-down resistor is built in.
This pin must be set low briefly after power is first applied.
Reset input for this IC’s CD playback block.
55
CDRESB
I
A pull-down resistor is built in.
This pin must be set low briefly after power is first applied.
56
AD1
AI
Key operation A/D converter input 1
—
—
57
AD2
AI
Key operation A/D converter input 2
—
—
58
AD3
AI
Key operation A/D converter input 3
—
—
59
AVSS
—
Analog system ground. This pin must be connected to the 0V level.
—
—
60
PDO
AO
External VCO control phase comparator output
Undefined
Undefined
61
ISET
AI
—
—
—
—
PDO output current adjustment resistor connection
PLL system pins
62
FR
AI
VCO frequency range adjustment
An external resistor must be connected between this pin
and AVDD.
63
AVDD
—
Analog system power supply
64
SLCO
AO
Slice level control output
—
—
Undefined
Undefined
No.7735-8/11
LC78605E
Sample Application Circuit
To Function
VDD
VDD
EFMI
DRF
DEFI
CLK
RWB
RWC
COIN
CQCKB
FSEQ
CLVO
HFL
JPO
TES
TOFF
TGL
DVSS
LC78605E
DVSS
PUIN
CLOSE
REMOTE
FMAMB
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COM1
COM2
COM3
COM4
DVDD
SL+
SL–
DMUTEB
AMUTEB
MODE
LCHO
LRVDD
LRVSS
RCHO
XVSS
XOUT16M
XIN16M
XVDD
XOUT32K
XIN32K
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
To Mechanism
To LCD
DISPLAY
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
To ASP-LSI
(LV1605)
SLCO
AVDD
FR
ISET
PDO
AVSS
AD3
AD2
AD1
CDRESB
TUNERESB
MONI1
MONI2
MONI3
TUNERIN
DVDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
To TUNER
GND
Rch
To Driver-LSI
(LA6548)
Audio GND
Lch
Audio VDD
No.7735-9/11
LC78605E
Notes on Application Design
While it goes without saying that this IC’s absolute maximum ratings and allowable operating ranges (and
recommended operating conditions) must be strictly observed to achieve reliability as a total system, adequate care is
also required with respect to the operating environment and mounting conditions such as ambient temperature and static
electricity. This section presents notes on items that require care during end product design and IC mounting.
• Handling Unused Pins
If any unused input pins on this IC are left open the related internal circuits may become unstable. The instructions on
handling unused pins for specific pins given in the technical documentation must be followed. Also note that unused
output pins must not be shorted to power, ground, or other outputs.
• Latchup Prevention
— The stipulated supply voltage must be applied to each power supply pin. If there are multiple pins for which the
same supply voltage is stipulated, the same potential must be applied to all those pins.
— Overvoltages and abnormal noise must not be applied to this IC.
— In general, latchup can be prevented by holding unused input pins fixed at either V DD or VSS. However, the
handling of each pin must follow the specific instruction in the pin functions documentation.
— The outputs must not be shorted.
• Interface Notes
When the inputs and outputs of different devices are connected, malfunctions may occur if the input VIL/VIH levels
do not match the corresponding output VOL/VOH levels. Level shifters must be inserted to prevent destruction of the
devices if devices with differing supply voltages, such as may occur in two power supply system applications, are
connected.
• Load Capacitance and Output Current
— When connected to high capacitance loads, lines may be melted since the effect of such loads is the same as the
load being shorted for an extended period. Also, charge/discharge currents may result in noise that may degrade
equipment performance and cause malfunctions. The recommended load capacitance ratings must be observed.
— Excessive output sink or source currents can cause similar problems. Observe the maximum allowable power
dissipation ratings and use this IC within the recommended current value range.
• Notes on Power Application and Power-on Reset
— There are cases where special care is required at power on, during a reset, and after a reset is cleared. Refer to the
device specifications and design applications taking these concerns into account.
— This IC’s output pin states, I/O settings, and register values are undefined when power is first applied. The
operation of items that are defined by a reset operation or mode settings is only guaranteed after the corresponding
reset or setting operation. A reset must be applied to this IC after power is first applied. The states immediately
after power on of pins and registers that are not explicitly defined cannot be relied on: they may differ from
versions of the same product purchased at different times.
• Notes on thermal design
The failure rate of semiconductor devices is accelerated greatly by increases in ambient temperature or power
consumption. To assure high reliability, design the application heat dissipation system to provide adequate margin for
variations in ambient conditions.
• Notes on PCB pattern design
— Ideally, there should be separate power supply and ground lines for each system to reduce the influence of shared
impedances.
— The power supply and ground lines should be as wide and as short as possible, and the impedance to high
frequencies should be as small as possible. Ideally, decoupling capacitors (0.01 to 1µF) and 100 to 220µF
capacitors should be inserted between each power supply/ground pair. However, note that latchup may occur if
the values of these capacitors are too large.
*: In the servo systems, the same handling is required for the VREF reference voltage line as well as for the driver
VCC and ground lines. The driver ground lines must be especially wide and located under the device to provide a
heat dissipating effect.
No.7735-10/11
LC78605E
*: If a current output type pickup is used, the photoreceptor connector must be located as close as possible to the
ASP RF input. If a voltage output type pickup is used, the I/V conversion resistors located at the ASP input must
be located as close as possible to the ASP RF input.
— The EFM signal line must be made as short as possible, and must either be located well away from adjacent lines
or must be run between ground or power supply level lines as shield lines. Since the slice level controller output
(SLCO) can easily introduce noise in the EFM signal line, the resistor connected to the output pin must be located
as close to that pin as possible. Note that if that resistor has a relatively small value, spurious radiation problems
may be aggravated and that if the resistor has a larger value, the output level may become problematic.
— The crystal oscillator circuit must be surrounded by the ground pattern.
— The TUNER pin coupling capacitor must be located as close to the IC as possible.
• Other Notes
If there are any points that are unclear or if you have any questions, contact your Sanyo representative during the
design phase.
This IC is a special-purpose device designed for CD player applications, and has specifications that differ from those
of general-purpose logic devices. End products must be designed to operate in a failsafe manner appropriate for the
application, and application operation must be verified using test equipment.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products(including technical data,services) described or
contained herein are controlled under any of applicable local export control laws and regulations,
such products must not be expor ted without obtaining the expor t license from the authorities
concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of March, 2004. Specifications and information herein are subject to
change without notice.
PS No.7735-11/11