S i886xxIS O-E V B S i886 X X I S O - E V B U S E R ’ S G U I D E Description This document describes Si886xxISO-EVB. Si886xxISO-EVB Overview the operation of the Kit Contents The Si886xxISO Evaluation Kit contains the following items: Si886xxISO-EVB Si88621ED-IS installed on the evaluation board. Rev. 0.1 Copyright © 2015 by Silicon Laboratories Si886xxISO-EVB Si8 86xxI S O - E V B 1. Hardware Overview and Setup The default configuration of the Si886xxISO-EVB demonstrates the digital isolation capabilities of the installed Si88621ED-IS as well as its dc-dc converter performance. In this configuration, the dc-dc converter is enabled, the primary side digital supply is sourced by an external regulator circuit, and the secondary side digital supply is sourced by the output of the converter. This EVB configuration has a jumper installed at JP9 in the ON position, JP13 has a jumper installed, and the remaining jumpers not populated. Note: Do not place jumpers across JP10 or JP11. These are additional test points for VDDA, GNDA and GNDB, and VOUT respectively. 1.1. DC-DC Converter Input and Output Supply power to the EVB by applying 24 Vdc to VIN at terminal block J1. LED D21 above terminal block J1 illuminates to show power applied to primary side of the converter. The isolated dc-dc output, VOUT, is available at terminal block J2. The populated values for R5 and R6 produce a 5 V output at VOUT capable of sourcing up to 5 W to an external load connected to terminal block J2. LED D22 above the terminal block J2 illuminates when the dc-dc converter is operating. VIN and VOUT test points are available along the upper edge of the EVB. 1.2. Digital Isolator Supplies The A-side power is provided by a regulator circuit referenced to VREGA pin of the Si888621ED-IS. VIN is stepped down from 24 V to approximately 4.3 V and applied to VDDA pin. The B-side power is supplied by the output of the dc-dc converter through JP13. 1.3. Digital Signals The EVB has a series of header pins for connecting to each digital channel. The inside conductor of each 2x1 header is connected to the device pin and the outer conductor is tied to ground through a resistor of 499 . Connect digital signals to each side of the Si886xxISO-EVB through a two-row ribbon cable with one row grounded. Channel 1 transmits from A1 (JP1 pin 2) to B1 (JP4 pin 1). Channel 2 transmits from B2 (JP5 pin 1) to A2 (JP2 pin 2). Note: The digital input signal should not exceed the power supply of the respective side. 1.4. Transformer Current Sensing Primary side magnetizing current across the sense resistor R12, can be observed by probing TP20, RSNS with reference to TP33, GNDP. 2 Rev. 0.1 S i8 8 6 x x ISO-E V B 2. Alternative Configurations 2.1. Disabling the DC-DC Converter The SH_FC input (U1 pin 7) disables the dc-dc converter. JP9 controls the SH_FC input, enabling the converter when pulled low, ON, and disabling the converter when pulled high, OFF. To disable the dc-dc converter, place the jumper in the OFF position on JP9. If interfacing to an external controller through the JP9 header, the controller must drive SH low for normal operation and high to disable the dc-dc. Note: When the dc-dc converter is disabled, the B-side can be powered by an active high digital input on the B-side. Ensure B2 input is tri-state or driven low when VDDB is left floating or grounded. 2.2. 3.3 V DC-DC Converter Output To change VOUT to 3.3 V, change R5 to 43.2 k and R6 to 20.0 k. 2.3. Alternate Supply for VDDA To bypass the regulator circuit and supply VDDA from a separate supply, remove Q2 and connect positive power supply through JP9 pin 3 and connect the supply return to J1 pin 2. 2.4. Alternate Supply for VDDB To supply VDDB from a separate supply, remove the jumper on JP13 and supply desired power through JP13 pin 2 and connect the supply return to J2 pin 1. Rev. 0.1 3 Si8 86xxI S O - E V B 3. Quick Reference Tables Table 1. Test Point Descriptions Test Point Description Referenced to TP1 VIN GNDA/GNDP TP2 GNDA/GNDP N/A TP3 VOUT GNDB TP4 GNDB N/A TP5 SHDN GNDA/GNDP TP19 COMP GNDB TP20 RSNS GNDA/GNDP TP33 GNDP N/A Table 2. Jumper Descriptions Jumper PIN 1* PIN 2* PIN 3* Default Position Description JP1 GNDA (through 499 ) A1 — Not Installed Digital Isolator Connector JP2 GNDA (through 499 ) A2 — Not Installed Digital Isolator Connector JP5 B1 GNDB (through 499 ) — Not Installed Digital Isolator Connector JP6 B2 GNDB (through 499 ) — Not Installed Digital Isolator Connector JP9 GNDA SHDN VDDA Installed (SHDN - GNDA) DC-DC Converter Enabled JP10 VIN GNDA — Not Installed DO NOT SHORT – test points only JP11 GNDB VOUT — Not Installed DO NOT SHORT – test points only JP13 VDDB VOUT — Installed Connects VDDB to VOUT *Note: Pin numbering is from left to right. 4 Rev. 0.1 J1 D20 28V Valid range: 24V +/- 10% Input Power Supply 1 2 *1 D21 RED R21 69.8K Rev. 0.1 1 2 3 SH JP6 R28 HEADER 1x3 TP5 Si88621 SHDN VDDA 499 Figure 1. Si886xxISO-EVB Schematic (1 of 2) JS9 JP9 B2 JP5 JP11 TP4 GNDB R29 499 A2 B1 TP3 VOUT 499 JP2 A1 U1 VOUT VIN R25 JP1 TP1 VIN 499 R24 JP10 TP2 GNDA VIN GNDA VOUT GNDB VIN D22 RED *2 2 1 J2 DO NOT connect an external power supply to J2 This is an OUTPUT R22 10K VOUT S i8 8 6 x x ISO-E V B 4. Si886xxISO-EVB Schematics 5 Rev. 0.1 A2 A1 SHDN VDDA GNDA VIN 10uF C2 0.1uF C14 R14 19.6K D7 0 10uF 0.47uF 0.1uF C5 R13 TP20 RSNS TP33 GNDP R12 0.1 10 9 8 7 6 5 4 3 2 1 Q1 FDT3612 D6 NI R15 NI A2 A1 SS SH_FC VREGA GNDA VDDA ESW RSNS GNDP U1 R16 82.0 C19 68pF 1 T1 4 25uH 5 8 Si88621 B2 B1 NC NC COMP VSNS NC VREGB VDDB GNDB R8 27.4 11 12 13 14 15 16 17 18 19 20 C8 100pF COMP TP19 SBRT5A50SA D1 Figure 2. Si886xxISO-EVB Schematic (2 of 2) 4.32K C4 C6 Q2 MMBT2222LT1 NI C18 ISOLATION 6 For VOUT of 3.3V, change R5 to 43.2k and R6 to 20.0k Default EVB Converter Configuration: VIN = 24V +/- 10% VOUT = 5V R7 100K 0.1uF C12 22uF 0.1uF 1.5nF C11 C10 C9 R6 13.3K R5 49.9K JP13 JS13 B2 B1 GNDB VOUT Si8 86xxI S O - E V B S i8 8 6 x x ISO-E V B 5. Si886xxISO-EVB Layout Top Bottom Figure 3. Si886xxISO-EVB Layout Rev. 0.1 7 Si8 86xxI S O - E V B 6. Bill of Materials Table 3. Si886xxISO-EVB Bill of Materials Part Reference Description Manufacturer Manufacturer Part Number C2 CAP, 10 μF, 50 V, ±20%, X7R, 1210 Venkel C1210X7R500-106M C4 CAP, 10 μF, 10 V, ±20%, X7R, 1206 Venkel C1206X7R100-106M C5 C9 C12 C14 CAP, 0.1 μF, 10 V, ±10%, X7R, 0603 Venkel C0603X7R100-104K C6 CAP, 0.47 μF, 16 V, ±10%, X7R, 0805 Venkel C0805X7R160-474K C8 CAP, 100 pF, 50 V, ±10%, X7R, 0603 Venkel C0603X7R500-101K C10 CAP, 22 μF, 25 V, ±10%, X7R, 1210 Venkel C1210X7R250-226M C11 CAP, 1.5 nF, 25 V, ±10%, X5R, 0603 Venkel C0603X5R250-152K C18 CAP, 0.047 μF, 100 V, ±10%, X7R, 0805 Venkel C0805X7R101-473K C19 CAP, 68 pF, 100 V, ±10%, C0G, 0603 Venkel C0603C0G101-680K D1 DIO, SUPER BARRIER, 50 V, 5.0A, SMA Diodes Inc. SBRT5A50SA D6 DIO, FAST, 200 V, 1.0A, PowerDI-123 Diodes Inc. DFLU1200-7 D7 RES, 0 1A, ThickFilm, 0603 Venkel CR0603-16W-000 D20 DIO, ZENER, 28 V, 500 mW, SOD123 On Semi MMSZ5255BT1G D21 D22 LED, RED, 631 nM, 20 mA, 2 V, 54mcd, 0603 Lite-On LTST-C190KRKT J1 J2 CONN, TERM BLOCK 2POS, 5MM PCB Phoenix Contact 1729018 JP1 JP2 JP5 JP6 JP10 JP11 JP13 Header, 2x1, 0.1” pitch, Tin Plated Samtec TSW-102-07-T-S JP9 Header, 3x1, 0.1” pitch, Tin Plated Samtec TSW-103-07-T-S JS9 JS13 Shunt, 1x2, 0.1” pitch, Tin plating Samtec SNT-100-BK-T MH1 MH2 MH3 MH4 HDW, Screw, 4-40 x 1/4" Pan Head, Slotted, Nylon Richco Plastic Co NSS-4-4-01 Q1 TRANSISTOR, MOSFET, N-CHNL, 100 V, 3.7A, 3W, Switching, SOT223 Fairchild FDT3612 Q2 TRANSISTOR, NPN, 30 V, 600 mA, SOT23 On Semi MMBT2222LT1 R5 RES, 49.9K, 1/16W, ±1%, ThickFilm, 0603 Venkel CR0603-16W-4992F R6 RES, 13.3K, 1/16W, ±1%, ThickFilm, 0603 Venkel CR0603-16W-1332F R7 RES, 100K, 1/10W, ±1%, ThickFilm, 0603 Venkel CR0603-10W-1003F R8 RES, 27.4 ,1/10W, ±1%, ThickFilm, 0603 Venkel CR0603-10W-27R4F R12 RES, 0.1 , 1/2W, ±1%, ThickFilm, 1206 Venkel LCR1206-R100F R13 RES, 4.32K, 1/10W, ±1%, ThickFilm, 0603 Venkel CR0603-10W-4321F R14 RES, 19.6K, 1/16W, ±1%, ThickFilm, 0603 Venkel CR0603-16W-1962F 8 Rev. 0.1 S i8 8 6 x x ISO-E V B Table 3. Si886xxISO-EVB Bill of Materials Part Reference Description Manufacturer Manufacturer Part Number R15 RES, 10K, 1/10W, ±1%, ThickFilm, 0805 Venkel CR0805-10W-1002F R16 RES, 82.0 , 1/10W, ±1%, ThickFilm, 0603 Venkel CR0603-10W-82R0F R21 RES, 69.8K, 1/16W, ±1%, ThickFilm, 0603 Venkel CR0603-16W-6982F R22 RES, 10K, 1/10W, ±5%, ThickFilm, 0603 Venkel CR0603-10W-103J R24 R25 R28 R29 RES, 499 , 1/10W, ±1%, ThickFilm, 0603 Venkel CR0603-10W-4990F SO1 SO2 SO3 SO4 HDW, STANDOFF, 1/4" HEX, 4-40x3/4", NYLON Keystone 1902D T1 TRANSFORMER, Flyback, 25 μH Primary, 500 nH Leakage, 3:1, SMT UMEC UTB02205s TP1 TP2 TP3 TP4 TP5 TP19 TP20 TP33 TESTPOINT, BLACK, PTH Kobiconn 151-203-RC U1 IC, ISOLATOR, DC-DC External Switch, Freq Control, 2 Digital Ch, SO20 WB Silicon Labs Si88621ED-IS Rev. 0.1 9 Si8 86xxI S O - E V B 7. Si886xxISO-EVB Ordering Guide Table 4. Si886xxISO-EVB Ordering Guide 10 Ordering Part Number (OPN) Description Si886xxISO-KIT Si886xx dc-dc digital isolator evaluation board kit Rev. 0.1 S i8 8 6 x x ISO-E V B CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.siliconlabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. 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