SFH6318, SFH6319 www.vishay.com Vishay Semiconductors High Speed Optocoupler, 100 kBd, Low Input Current, High Gain FEATURES NC 1 8 VCC • High current transfer ratio, 300 % A 2 7 VB • Low input current, 0.5 mA C 3 6 VO NC 4 5 GND i179075_4 i179074 • High output current, 60 mA • TTL compatible output, VOL = 0.1 V • Adjustable bandwidth access to base • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 V D E DESCRIPTION APPLICATIONS Very high current ratio together with 4000 VRMS isolation are achieved by coupling an LED with an integrated high gain photo detector in a SOIC-8 package. Separate pins for the photo diode and output stage enable TTL compatible saturation voltages with high speed operation. Photodarlington operation is achieved by tying the VCC and VO terminals together. Access to the base terminal allows adjustment to the gain bandwidth. • Logic ground isolation - TTL / TTL, TTL / CMOS, CMOS / CMOS, CMOS / TTL • EIA RS 232C line receiver • Low input current line receiver long lines, party lines • Telephone ring detector • Line voltage status indication - low input power dissipation The SFH6318 is ideal for TTL applications since the 300 % minimum current transfer ratio with an LED current of 1.6 mA enables operation with one unit load-in and one unit load-out with a 2.2 kΩ pull-up resistor. • Low power systems - ground isolation AGENCY APPROVALS • UL1577, file no. E52744 The SFH6319 is best suited for low power logic applications involving CMOS and low power TTL. A 400 % current transfer ratio with only 0.5 mA of LED current is guaranteed from 0 °C to 70 °C. • cUL, file no. E52744 • DIN EN 60747-5-5 (VDE 0884-5) available with option 1 • CSA 93751 Caution: Due to the small geometries of this device, it should be handled with electrostatic discharge (ESD) precautions. Proper grounding would prevent damage further and / or degradation which may be induced by ESD. ORDERING INFORMATION SOIC-8 S F H 6 3 # # T PART NUMBER 6.1 mm AGENCY CERTIFIED / PACKAGE CTR (%) ≥ 300 ≥ 500 SOIC-8 SFH6318T SFH6319T SOIC-8, tube SFH6318 SFH6319 UL, CSA Rev. 2.0, 14-Jul-15 Document Number: 83678 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SFH6318, SFH6319 www.vishay.com Vishay Semiconductors ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITION PART SYMBOL VALUE UNIT VR 3 V SFH6318 VCC, VO -0.5 to 7 V SFH6319 VCC, VO -0.5 to 18 V Pdiss 35 mW INPUT Reverse voltage Supply and output voltage VCC (pin 8 to 5), VO (pin 6 to 5) Input power dissipation Derate linearly above 50 °C Free air temperature 0.7 mW/°C Average input current IF(AVG) 20 mA Peak input current 50 % duty cycle; 1 ms pulse width IFRM 40 mA Peak transient input current tp ≤ 1 μs, 300 pps IFSM 1 A 60 mA OUTPUT Output current (pin 6) IO Emitter-base reverse current (pin 5 to 7) Output power dissipation 0.5 V 150 mW 2 mW/°C Tstg -55 to +125 °C Tsld 260 °C Tj 100 °C Tamb -55 to +100 °C Pdiss Derate linearly from 25 °C COUPLER Storage temperature Lead soldering temperature t = 10 s Junction temperature Ambient temperature range Note • Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this document. Exposure to absolute maximum ratings for extended periods of the time can adversely affect reliability. ELECTRICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITION SYMBOL MIN. TYP. MAX. UNIT INPUT Forward voltage IF = 1.6 mA VF - 1.4 1.7 V Temperature coefficient, forward voltage IF = 1.6 mA ΔVF/ΔTamb - -1.8 - mV/°C IF = 1.6 mA, IO = 4.8 mA, VCC = 4.5 V VOL - 0.1 0.4 V IF = 1.6 mA, IO = 8 mA, VCC = 4.5 V VOL - 0.1 0.4 V V OUTPUT Logic low output voltage (1) Logic high output current (1) IF = 5 mA, IO = 15 mA, VCC = 4.5 V VOL - 0.15 0.4 IF = 12 mA, IO = 24 mA, VCC = 4.5 V VOL - 0.25 0.4 V IF = 0 mA, VO = VCC = 7 V IIO - 0.1 250 μA IF = 0 mA, VO = VCC = 18 V IIO - 0.05 100 μA Logic low supply current (1) IF = 1.6 mA, VO = OPEN, VCC = 18 V ICCL - 0.2 1.5 mA Logic high supply current (1) IF = 0 mA, VO = OPEN, VCC = 18 V ICCH - 0.01 10 μA f = 1 MHz CIO - 0.6 - pF f = 1 MHz, VF = 0 CIN - 25 - pF COUPLER Capacitance (input to output) (2) Input capacitance Notes • Minimum and maximum values are testing requirements. Typical values are characteristics of the device and are the result of engineering evaluation. Typical values are for information only and are not part of the testing requirements. Tamb = 0 °C to 70 °C. Typical values are specified at Tamb = 25 °C. (1) Pin 7 open. (2) Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. Rev. 2.0, 14-Jul-15 Document Number: 83678 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SFH6318, SFH6319 www.vishay.com Vishay Semiconductors CURRENT TRANSFER RATIO PARAMETER Current transfer ratio (1) TEST CONDITION PART SYMBOL MIN. TYP. MAX. UNIT IF = 1.6 mA, VO = 0.4 V, VCC = 4.5 V SFH6318 CTR 300 1600 2600 % IF = 0.5 mA, VO = 0.4 V, VCC = 4.5 V SFH6319 CTR 400 2000 3500 % IF = 1.6 mA, VO = 0.4 V, VCC = 4.5 V SFH6319 CTR 500 1600 2600 % Notes • Tamb = 0 °C to 70 °C. Typical values are specified at Tamb = 25 °C. DC current transfer ratio is defined as the ratio of output collector current, IO, to the forward LED input current, IF times 100 %. Pin 7 open. (1) Pin 7 open SWITCHING CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITION PART SYMBOL MIN. TYP. MAX. UNIT Propagation delay time to logic low at output IF = 1.6 mA, RL = 2.2 kΩ SFH6318 tPHL - 2 10 μs Propagation delay time to logic low at output (1) IF = 0.5 mA, RL = 4.7 kΩ SFH6319 tPHL - 6 25 μs Propagation delay time to logic low at output (1) IF = 12 mA, RL = 270 Ω SFH6319 tPHL - 0.6 1 μs Propagation delay time to logic high at output IF = 1.6 mA, RL = 2.2 kΩ SFH6318 tPLH - 2 35 μs Propagation delay time to logic high at output (1) IF = 0.5 mA, RL = 4.7 kΩ SFH6319 tPLH - 4 60 μs Propagation delay time to logic high at output (1) IF = 12 mA, RL = 270 Ω SFH6319 tPLH - 1.5 7 μs Note (1) Pin 7 open. Using a resistor between pin 5 and 7 will decrease gain and delay time. I 10 % duty cycle 1/f < 100 µs 0 1 Pulse generator ZO = 5 0 Ω tr = 5 n s +5V 8 5V V IF 2 (saturated response) 7 RL 3 6 0.1 µF I F = monitor 4 5 1.5 V VOL t PLH t PHL C L = 15 pF Rm 1.5 V VO 5V VO 90 % 90 % (non-saturated response) 10 % 10 % tr tf Fig. 1 - Switching Test Circuit COMMON MODE TRANSIENT IMMUNITY PARAMETER TEST CONDITION SYMBOL MIN. TYP. MAX. UNIT Common mode transient immunity at logic high level output (1)(2) IF = 0 mA, RL = 2.2 kΩ, VCM = 10 VP-P |CMH| - 1000 - V/μs Common mode transient immunity at logic low level output (1)(2) IF = 1.6 mA, RL = 2.2 kΩ, VCM = 10 VP-P |CML| - 1000 - V/μs Notes (1) Common mode transient immunity in logic high level is the maximum tolerable (positive) dV /dt cm on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a logic high state (i.e. VO > 2 V) common mode transient immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a logic low state (i.e.VO < 0.8 V). (2) In applications where dv/dt may exceed 50 000 V/μs (such as state discharge) a series resistor, R CC should be included to protect IC from destructively high surge currents. The recommended value is refer to figure 2. RCC ≅ [(IV)/0.15 IF (mA)] kΩ. Rev. 2.0, 14-Jul-15 Document Number: 83678 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SFH6318, SFH6319 www.vishay.com Vishay Semiconductors RCC (2) 1 8 2 7 IF +5V 220 Ω VCM RL A 3 6 4 5 90 % 90 % 0 V 10 % 0.1 µF 10 % tr VO B tf t f + t f =16 ns VO 5V Switch at A: IF = 0 mA VCC VCM + – VO VOL Switch at B: IF = 1.6 mA Pulse Generator Fig. 2 - Test Circuit for Transient Immunity and Typical Waveforms SAFETY AND INSULATION RATINGS PARAMETER TEST CONDITION Climatic classification According to IEC 68 part 1 Pollution degree According to DIN VDE 0109 Comparative tracking index Maximum rated withstanding isolation voltage SYMBOL VALUE UNIT 55/100/21 2 Insulation group IIIa CTI 175 According to UL1577, t = 1 min VISO 3333 VRMS Tested withstanding isolation voltage According to UL1577, t = 1 s VISO 4000 VRMS Maximum transient isolation voltage According to DIN EN 60747-5-5 VIOTM 6000 Vpeak Maximum repetitive peak isolation voltage According to DIN EN 60747-5-5 VIORM 560 Vpeak VIO = 500 V, Tamb = 25 °C RIO ≥ 1012 Ω VIO = 500 V, Tamb = 100 °C RIO ≥ Ω VIO = 500 V, Tamb = TS RIO ≥ 109 Ω PSO 350 mW Input safety current ISI 150 mA Safety temperature TS 165 °C ≥4 mm ≥4 mm Isolation resistance Output safety power Creepage distance Clearance distance 1011 Input to output test voltage, method B VIORM x 1.875 = VPR, 100 % production test with tM = 1 s, partial discharge < 5 pC VPR 1050 Vpeak Input to output test voltage, method A VIORM x 1.6 = VPR, 100 % sample test with tM = 10 s, partial discharge < 5 pC VPR 896 Vpeak Note • As per IEC 60747-5-5, § 7.4.3.8.2, this optocoupler is suitable for “safe electrical insulation” only within the safety ratings. Compliance with the safety ratings shall be ensured by means of protective circuits. Rev. 2.0, 14-Jul-15 Document Number: 83678 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SFH6318, SFH6319 www.vishay.com Vishay Semiconductors PACKAGE DIMENSIONS (in millimeters) 5.31 max. 6.10 ± 0.25 4.88 ± 0.13 1.27 typ. 7 6 Leads coplanarity 0.1 max. R0.13 5 0.36 8 0.51 ± 0.1 0.15 ± 0.05 0.41 0.20 typ. 3.18 ± 0.13 3.98 ± 0.13 0.91 1.27 Technical drawings according to DIN specifications 4.32 PIN ONE I.D 1.14 6.60 1 2 3 4 Fig. 3 - Package Drawing PACKAGE MARKING 6318 PIN ONE I.D V YWW Y 68 Fig. 4 - SFH6138 6319 PIN ONE I.D V YWW Y 68 Fig. 5 - SFH6139 Note • Tape and reel suffix (T) is not part of the package marking. Rev. 2.0, 14-Jul-15 Document Number: 83678 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SFH6318, SFH6319 www.vishay.com Vishay Semiconductors PACKING INFORMATION 1.5 2.0 ± 0.1 + 0.1 - 0.0 0.35 ± 0.05 4.0 ± 0.1 5.5 ± 0.1 PIN 1 5.25 ± 0.10 12.0 ± 0.3 1.75 ± 0.10 3.48 ± 0.10 8.0 ± 0.1 6.4 ± 0.1 3.78 ± 010 1.5 + 0.1 - 0.0 Fig. 6 - Tape and Reel Packing (2000 pieces on reel) 8.00 ± 0.25 4.70 ± 0.25 0.51 ± 0.13 0.51 ± 0.13 0.13R typ. 0.64R typ. 5.10 ± 0.25 4.10 ± 0.25 3.70 ± 0.25 1.4 ± 0.13 3.10 ± 0.25 4.32 ± 0.25 7.00 ± 0.25 123 ref. Ø 3.10 ± 0.10 6.35 513 ± 1 Fig. 7 - Tube Packing DEVICE PER TUBE TYPE SOIC-8 Rev. 2.0, 14-Jul-15 UNITS/TUBE TUBES/BOX UNITS/BOX 100 30 3000 Document Number: 83678 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SFH6318, SFH6319 www.vishay.com Vishay Semiconductors SOLDER PROFILE HANDLING AND STORAGE CONDITIONS ESD level: HBM class 2 300 255 °C 240 °C 217 °C 250 Temperature (°C) max. 260 °C 245 °C Floor life: unlimited Conditions: Tamb < 30 °C, RH < 85 % Moisture sensitivity level 1, according to J-STD-020 200 max. 30 s 150 max. 100 s max. 120 s 100 max. ramp down 6 °C/s 50 max. ramp up 3 °C/s 0 0 19841 50 100 150 200 250 300 Time (s) Fig. 8 - Lead (Pb)-free Reflow Solder Profile according to J-STD-020 Rev. 2.0, 14-Jul-15 Document Number: 83678 7 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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