BVA304

BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Product Description
Figure 2. Package Type
The BVA304 is a digitally controlled variable gain amplifier
(DVGA) is featuring high linearity using the voltage 3.3V
supply with a broadband frequency range of 50 to 4000
MHz.
Amplifier used in BVA304 is a high performance InGaP/
GaAs HBT MMIC amplifier, internally matched to 50 Ohms
and uses a patented temperature compensation circuit to
provide stable current over the operating temperature
range without the need for external components.
24-lead 4x4 mm QFN
Device Features










A serial output port enables cascading with other serial
controlled devices.
An integrated digital control interface supports both serial
and parallel programming of the attenuation,
including the capability to program an initial attenuation
state at power-up.
Covering a 31.5 dB attenuation range in 0.5 dB steps.





The BVA304 is targeted for use in wireless infrastructure,
point-to-point, or can be used for any general purpose
wireless application
Small 24-Pin 4 x 4 mm QFN Package
Intergrate DSA to Amp Functionality
Wide Power supply range of +2.7~5.5V(DSA)
Single Fixed +3.3V supply(Amp)
50-4000MHZ Broadband Performance
12.3dB Gain at 1.9GHz (No Matching Circuit)
3.6dB Noise Figure at max gain setting
19.3dBm P1dB at 1.9GHz (No Matching Circuit)
31.5dBm OIP3 at 1.9GHz(- 3dBm per tone, No Matching Circuit)
7.8dBm LTE 20Mhz ACLR at 1.9GHz (FDD E-TM1.1, 20MHz BW, ±20MHz
offset, PAR 9.81 at 0.01% Prob. , –50dBc)
Single Fixed 3.3V supply
Attenuation: 0.5 dB steps to 31.5 dB
Safe attenuation state transitions
Monotonicity: 0.5 dB up to 4 GHz
High attenuation accuracy(DSA to Amp)
±(0.10 + 2% x Atten) @ 1 GHz
±(0.15 + 2% x Atten) @ 2.2 GHz
±(0.15 + 8% x Atten) @ 4 GHz


VSS/GND
P/S
C8
RF2
C4
C2
Figure 1. Functional Block Diagram
24 23 22 21 20 19
GND
1
C1
2
C0.5
3
1.8V control logic compatible
Programming modes
- Direct Parallel
- Latched Parallel
- Serial
Unique power-up state selection(support Serial/Parallel)
17 GND
Digital Step Attenuation
16 VDD
C16
4
15 PUP2
GND
5
14 PUP1
Application
13 LE




Base station Infrastructure/RFID
3G/4G Wireless infrastructure and other high performance RF application
Microwave and Satellite Radio
General purpose Wireless
Clock
Data
9 10 11 12
GND
8
RF1
7
AMPIN
AMPOUT 6
BeRex

18 GND
GND
Preliminary Datasheet
The BVA304 integrates with a high performance digital
step attenuator and a high linearity broadband gain block.
It using the small package(4x4mm QFN package), and
operating VDD 3.3V voltage.
Also it designed for use in 3G/4G wireless infrastructure
and other high performance RF applications.
●website: www.berex.com
●email: [email protected]
1
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Table 1. Electrical Specifications1
Parameter
Condition
Operational Frequency Range
Min
Typ
50
Unit
4000
MHz
Gain
Attenuation = 0dB, at 1900MHz
12.3
dB
Attenuation Control range
0.5dB step
0.5
dB
31.5
dB
Attenuation Step
±(0.10 + 2% of atten setting)
50MHZ-1GHz
Preliminary Datasheet
Max
Attenuation
Accuracy
>1GHZ-2.2GHZ
±(0.15 + 2% of atten setting)
Any bit or bit combination
dB
±(0.15 + 8% of atten setting)
>2.2GHz-4GHZ
1GHZ-2.2GHZ
Return loss
(input or output
port)
2.2GHz-4GHZ
Attenuation = 0dB
Output Power for 1dB Compression
Attenuation = 0dB , at 1900MHz
13
18
10
16
dB
19.3
dBm
31.5
dBm
dB
Attenuation = 0dB, at 1900MHz
Output Third Order Intercept Point
two tones at an output of – 3 dBm per tone
separated by 1 MHz.
Noise Figure
Attenuation = 0dB, at 1900MHz
3.6
Switching time
50% CTRL to 90% or 10% RF
500
DSA
2.7
800
ns
5.5
V
Supply voltage
AMP
Supply Current
Control Interface
3.3
21
Serial / parallel mode
26
V
31
6
mA
Bit
Digital input high
1.17
3.6
V
Digital input low
-0.3
0.6
V
Control Voltage
Impedance
1
50
Ω
Device performance _ measured on a BeRex Evaluation board at 25°C, 50 Ω system, VDD=+3.3V, measure on Evaluation Board (DSA to AMP)
BeRex
●website: www.berex.com
●email: [email protected]
2
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Table 2. Typical RF Performance1
Parameter
Frequency
70
Preliminary Datasheet
6
7
2650
3500
5
MHz
11.6
10.5
7.2
dB
S11
-13.8
-21.6
-11.8
-11.9
-20
-13.1
dB
-14.9
-15.6
-12.8
-13.4
-14.7
-9.8
dB
2
32.3
29.5
31.5
31.9
33
32
dBm
P1dB
20.4
19.9
19.3
19.3
19.2
18.4
dBm
-9.7
2.3
5
6.9
6.2
3.8
dBm
0
3.6
7.8
8.8
8.2
6.3
dBm
3.5
3.5
3.6
3.6
3.7
4.6
dB
7
N.F
5
2140
5
12.3
LTE 20M ACLR
4
Unit
5
17.5
WCDMA ACLR6
3
1900
5
25.3
OIP3
2
900
4
Gain
S22
1
3
Device performance _ measured on a BeRex evaluation board at 25°C, VDD=+3.3V,50 Ω system. measure on Evaluation Board (DSA to AMP)
OIP3 _ measured with two tones at an output of –3 dBm per tone separated by 1 MHz.
70MHz measured with 50-500MHz IF application circuit.(refer to Table11.)
900MHz measured with 500-1600Mhz RF application circuit.(refer to Table 13.)
1900MHz,2140MHz,2650MHz,3500MHz measured with 1700-4000MHz RF application circuit.(refer to Table 15.)
WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob, @ACLR –50dBc
LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. @ACLR –50dBc
Table 3. Absolute Maximum Ratings
Parameter
Condition
Supply Volatge(VCC)
Amp/DSA
Supply Current
Amp
Digital input voltage
Typ
Amp/DSA
Operating Temperature
Amp/DSA
Storage Temperature
Junction Temperature
at 150℃, MCM(DSA+AMP)
Max
Unit
5.0/5.5
V
110
-0.3
Maximum input power
MTTF
Min
mA
3.6
V
+24/+30
dBm
-40
85/105
℃
-55
150
℃
220
℃
TBD
Hours
Operation of this device above any of these parameters may result in permanent damage.
BeRex
●website: www.berex.com
●email: [email protected]
3
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Programming Options
Preliminary Datasheet
Parallel/Serial Selection
Either a parallel or serial interface can be used to
control the BVA304. The P/S bit provides this
selection, with P/S = LOW selecting the parallel
interface and P/S = HIGH selecting the serial
interface.
Clock, and Latch Enable (LE). The Data and Clock
inputs allow data to be serially entered into the shift
register, a process that is independent of the state of
the LE input.
Parallel Mode Interface
The parallel interface consists of six CMOS compatible
control lines that select the desired
attenuation state, as shown in Table 4.
The parallel interface timing requirements are
defined by Figure 4 (Parallel Interface Timing
Diagram), Table 7 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
For latched parallel programming the Latch Enable
(LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Figure 3) to latch the new attenuation state into
the device.
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
attenuation state control values will change device
state to new attenuation. Direct Mode is ideal for
manual control of the device (using hardwire,
switches, or jumpers).
P/S
C16
C8
C4
C2
C1
0
0
0
0
0
0
0
Reference Loss
0
0
0
0
0
0
1
0.5 dB
0
0
0
0
0
1
0
1 dB
0
0
0
0
1
0
0
2 dB
0
0
0
1
0
0
0
4 dB
0
0
1
0
0
0
0
8 dB
0
1
0
0
0
0
0
16 dB
1
1
1
1
1
The shift register should be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data. The timing for this operation is defined by
Figure 3 (Serial Interface Timing Diagram) and
Table 6 (Serial Interface AC Characteristics).
Power-up Control Settings
The BVA304 always assumes a specifiable
attenuation setting on power-up. This feature exists
for both the Serial and Parallel modes of operation,
and allows a known attenuation state to be
established before an initial serial or parallel control
word is provided.
When the attenuator powers up in Serial mode
(P/S = 1), the six control bits are set to whatever
data is present on the six parallel data inputs (C0.5
to C16). This allows any one of the 64 attenuation
settings to be specified as the power-up state.
Table 4. Truth Table
0
The LE input controls the latch. When LE is HIGH,
the latch is transparent and the contents of the serial
shift register control the attenuator. When LE is
brought LOW, data in the shift register is latched.
C0.5 Attenuation state
1
31.5 dB
Note: Not all 64 possible combinations of C0.5-C16 are shown in table
Serial Interface
The serial interface is a 6-bit serial-in, parallel-out
shift register buffered by a transparent latch. It is
controlled by three CMOS-compatible signals: Data,
When the attenuator powers up in Parallel mode
(P/S = 0) with LE = 0, the control bits are
automatically set to one of four possible values.
These four values are selected by the two power-up
control bits, PUP1 and PUP2, as shown in Table 5
(Power-Up Truth Table, Parallel Mode).
Table 5. Parallel PUP Truth Table
P/S
LE
PUP2
PUP1
Attenuation state
0
0
0
0
Reference Loss
0
0
1
0
8 dB
0
0
0
1
16 dB
0
0
1
1
31.5 dB
0
1
X
X
Defined by C0.5-C16
Note: Power up with LE = 1 provides normal parallel operation with C0.5-C16, and PUP1 and PUP2
are not active
BeRex
●website: www.berex.com
●email: [email protected]
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Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Figure 3. Serial Interface Timing Diagram
Table 8. 6-Bit Attenuator Serial Programming
Register Map
B5
B4
B3
B3
B1
B0
C16
C8
C4
C2
C1
C0.5
MSB (first in)
fClk
Serial data clock frequency
10
MHz
ns
tClkL
Serial clock LOW time
30
ns
LE set-up time after last
clock falling edge
10
ns
tLEPW LE minimum pulse width
30
ns
Serial data set-up time
tSDSUP
before clock rising edge
10
ns
10
ns
Serial data hold time after
clock falling edge
Note: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern
are clocked at 10 MHz to verify fclk specification
Table 7. Parallel Interface AC Characteristics
VDD = 3.3V with DSA only, -40°C < TA < 105°C, unless otherwise specified
Symbol
tLEPW
Parameter
LE minimum pulse width
Data set-up time before
tPDSUP
rising edge of LE
Data hold time after falling
tPDHLD
edge of LE
BeRex
Min Max
Unit
10
ns
10
ns
10
ns
●website: www.berex.com
VSS/GND
C8
RF2
P/S
C4
20
19
18
GND
C1
2
17
GND
C0.5
3
16
VDD
C16
4
15
PUP2
GND
5
14
PUP1
AMPOUT
6
13
LE
10
11
12
Data
9
RF1
8
Clock
EXPOSED
Grounnd Pad
GND
Unit
30
tSDHLD
21
7
tClkH Serial clock HIGH time
tLESUP
22
AMPIN
Min Max
23
1
VDD = 3.3V with DSA only, -40°C < TA < 105°C, unless otherwise specified
Parameter
24
GND
Table 6. Serial Interface AC Characteristics
Symbol
C2
Figure 5. Pin Configuration(Top View)
GND
Preliminary Datasheet
Figure 4. Parallel Interface Timing Diagram
LSB (Last in)
Table 9. Pin Description
Pin
1,5,7,9,17,18
2
3
4
6
8
10
11
12
13
14
15
16
Pin name
GND
C1
C0.55
C163,5
AMPOUT
AMPIN
RF11
DATA3
Clock
LE4
PUP15
PUP2
VDD
Description
Ground
Attenuation control bit, 1dB
Attenuation control bit, 0.5dB
Attenuation control bit, 16dB
RF Amp out Port
RF Amp in Port
RF port(DSA output)
Serial interface data input
Serial interface clock input
Latch Enable input
Power-up selection bit 1
Power-up selection bit 2
Supply voltage (nominal 3.3V)
19
VSS/GND
External VSS negative voltage control or
ground
20
21
22
23
24
P/S
RF21
C8
C4
C2
Parallel/Serial mode select
RF port(DSA input)
Attenuation control bit, 8dB
Attenuation control bit, 4dB
Attenuation control bit, 2dB
Note: 1. RF pins 10 and 21 must be at 0V DC. The RF pins do not require DC blocking capacitors for proper
Operation if the 0V DC requirement is met
2. Use VssEXT (pin 12) to bypass and disable internal negative voltage generator.
Connect VssEXT (pin 12, VssEXT = GND) to enable internal negative voltage generator
3.Place a 10 kΩ resistor in series, as close to pin as possible to avoid frequency resonance
4. This pin has an internal 2 MΩ resistor to internal positive digital supply
5. This pin has an internal 200 kΩ resistor to GND
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Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical RF Performance Plot - BVA304 EVK - PCB(IF Circuit:50~500MHz)
Typical Performance Data @ 25°and VDD = 3.3V unless otherwise noted and RF Circuit
Table 10. Typical RF Performance(50~500Mhz)
Preliminary Datasheet
parameter
1
Frequency
Table 11. 50~500MHz IF Application Circuit
C4 C5 C6
Unit
50
70
200
MHz
Gain
25.3
25.3
23.6
dB
S11
-12.4
-13.8
-17.0
dB
S22
-12.6
-14.9
-20.0
dB
OIP31
31.9
32.3
29.2
dBm
P1dB
19.9
20.4
21.0
dBm
Noise Figure
3.5
3.5
3.4
dB
OIP3 _ measured with two tones at an output of -3 dBm per tone separated by 1 MHz.
L3
C1
Application Circuit
Values
U1
C3
Freq.
C1/C3
L3(1005 Chip Ind)
IF Circuit
50MHz ~ 500MHz
2.2nF
330nH
Figure 6. Gain vs Frequency
Figure 7. Gain vs Frequency
@ Major Attenuation Steps
Figure 8. Input Return Loss vs Frequency
@ Max Gain & Min Gain State
Figure 9. output Return Loss vs. Frequency
@ Max Gain & Min Gain State
BeRex
●website: www.berex.com
●email: [email protected]
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Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical RF Performance Plot - BVA304 EVK - PCB(IF Circuit:50~500MHz)
Preliminary Datasheet
Typical Performance Data @ 25°and VDD = 3.3V unless otherwise noted and RF Circuit
Figure 10. OIP3 vs Frequency
Figure 11. P1dB vs Frequency
Figure 12. Noise Figure vs Frequency
Figure 13. Attenuation Error vs Frequency
@ Major Attenuation Steps
Figure 14. Attenuation Error vs Attenuation Setting
Figure 15. 0.5dB Step Attenuation vs Attenuation
Setting
BeRex
●website: www.berex.com
●email: [email protected]
7
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical RF Performance Plot - BVA304 EVK - PCB(IF Circuit:50~500MHz)
Preliminary Datasheet
Typical Performance Data @ 25°and VDD = 3.3V unless otherwise noted and RF Circuit
Figure 16. OIP3 @ 70MHz vs Temperature
Figure 17. OIP3 @ 200MHz vs Temperature
Figure 18. Device performance Pin-Pout-Gain @
70MHz
Figure 19. Device performance Pin-Pout-Gain @
200MHz
Figure 20. ACLR@WCDMA 4FA1, 70MHz, -50dBc
Figure 21. ACLR @LTE20MHz1 70MHz, -50dBc
1
BeRex
WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob
●website: www.berex.com
1
LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob.
●email: [email protected]
8
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical RF Performance Plot - BVA304 EVK - PCB(RF Circuit:500~1600MHz)
Typical Performance Data @ 25°and VDD = 3.3V unless otherwise noted and RF Circuit
Table 12. Typical RF Performance(500~1600Mhz)
Preliminary Datasheet
parameter
800
900
1000
1100
MHz
Gain
18.9
18.2
17.5
16.8
16.3
dB
S11
-25.5
-24.7
-21.6
-19.1
-17.2
dB
-14.8
-15.2
-15.6
-15.8
-16.1
dB
1
29.2
28.7
29.5
30.7
31.1
dBm
P1dB
20.4
20.1
19.9
19.8
19.7
dBm
OIP3
Noise Figure
3.6
3.5
3.5
C4 C5 C6
Unit
700
S22
1
Frequency
Table 13. 500~1600MHz RF Application Circuit
3.5
3.5
OIP3 _ measured with two tones at an output of -3 dBm per tone separated by 1 MHz.
dB
L3
C1
Application Circuit
Values
U1
C3
Freq.
C1/C3
L3(1005 Chip Ind)
RF Circuit
500MHz ~ 1600MHz
56pF
22nH
Figure 22. Gain vs Frequency
Figure 23. Gain vs Frequency
@ Major Attenuation Steps
Figure 24. Input Return Loss vs Frequency
@ Max Gain & Min Gain State
Figure 25. output Return Loss vs. Frequency
@ Max Gain & Min Gain State
* RF Circuit application refer to Table 10.
BeRex
●website: www.berex.com
●email: [email protected]
9
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical RF Performance Plot - BVA304 EVK - PCB(RF Circuit:500~1600MHz)
Preliminary Datasheet
Typical Performance Data @ 25°and VDD = 3.3V unless otherwise noted and RF Circuit
Figure 26. OIP3 vs Frequency
Figure 27. P1dB vs Frequency
Figure 28. Noise Figure vs Frequency
Figure 29. Attenuation Error vs Frequency
@ Major Attenuation Steps
Figure 30. Attenuation Error vs Attenuation Setting
Figure 31. 0.5dB Step Attenuation vs Attenuation
Setting
BeRex
●website: www.berex.com
●email: [email protected]
10
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical RF Performance Plot - BVA304 EVK - PCB(RF Circuit:500~1600MHz)
Preliminary Datasheet
Typical Performance Data @ 25°and VDD = 3.3V unless otherwise noted and RF Circuit
Figure 32. OIP3 @ 700MHz vs Temperature
Figure 33. OIP3 @ 900MHz vs Temperature
Figure 34. Device performance Pin-Pout-Gain @
700MHz
Figure 35. Device performance Pin-Pout-Gain @
900MHz
Figure 36. ACLR@WCDMA 4FA1, 900MHz, -50dBc
Figure 37. ACLR @LTE20MHz1 900MHz, -50dBc
1
BeRex
WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob
●website: www.berex.com
1
LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob.
●email: [email protected]
11
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical RF Performance Plot - BVA304 EVK - PCB(RF Circuit:1700~4000MHz)
Typical Performance Data @ 25°and VDD = 3.3V unless otherwise noted and RF Circuit
Table 14. Typical RF Performance(1700~4000Mhz)
Preliminary Datasheet
parameter
Gain
S11
S22
OIP31
P1dB
WCDMA ACLR2
LTE 20M ACLR3
Noise Figure
1
2
3
1700
15
-20.3
-10.8
30.4
19.9
6.4
8.6
3.6
1900
12.3
-11.8
-12.8
31.5
19.3
5
7.8
3.6
Frequency
2140
11.6
-11.9
-13.4
31.9
19.3
6.9
8.8
3.6
2650
10.5
-20
-14.7
33
19.2
6.2
8.2
3.7
3500
7.2
-13.1
-9.8
32
18.4
3.8
6.3
4.6
OIP3 _ measured with two tones at an output of -3 dBm per tone separated by 1 MHz.
WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob
Unit
MHz
dB
dB
dB
dBm
dBm
dBm
dBm
dB
Table 15. 1700~4000MHz RF Application Circuit
C4 C5 C6
L3
C1
Application Circuit
Values
U1
C3
Freq.
C1/C3
L3(1005 Chip Ind)
RF Circuit
1700MHz ~ 4000MHz
10pF
7.5nH
LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob.
Figure 38. Gain vs Frequency
Figure 39. Gain vs Frequency
@ Major Attenuation Steps
Figure 40. Input Return Loss vs Frequency
@ Max Gain & Min Gain State
Figure 41. output Return Loss vs. Frequency
@ Max Gain & Min Gain State
* RF Circuit application refer to Table 10.
BeRex
●website: www.berex.com
●email: [email protected]
12
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical RF Performance Plot - BVA304 EVK - PCB(RF Circuit:1700~4000MHz)
Preliminary Datasheet
Typical Performance Data @ 25°and VDD = 3.3V unless otherwise noted and RF Circuit
Figure 42. OIP3 vs Frequency
Figure 43. P1dB vs Frequency
Figure 44. Noise Figure vs Frequency
Figure 45. Attenuation Error vs Frequency
@ Major Attenuation Steps
Figure 46. Attenuation Error vs Attenuation Setting
Figure 47. 0.5dB Step Attenuation vs Attenuation
Setting
BeRex
●website: www.berex.com
●email: [email protected]
13
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical RF Performance Plot - BVA304 EVK - PCB(RF Circuit:1700~4000MHz)
Preliminary Datasheet
Typical Performance Data @ 25°and VDD = 3.3V unless otherwise noted and RF Circuit
Figure 48. OIP3 @ 1900MHz vs Temperature
Figure 49. OIP3 @ 2140MHz vs Temperature
Figure 50. OIP3 @ 2650MHz vs Temperature
Figure 51. OIP3 @ 3500MHz vs Temperature
Figure 52. Device performance Pin-Pout-Gain
@1900MHz
Figure 53. Device performance Pin-Pout-Gain
@2140MHz
BeRex
●website: www.berex.com
●email: [email protected]
14
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical RF Performance Plot - BVA304 EVK - PCB(RF Circuit:1700~4000MHz)
Preliminary Datasheet
Typical Performance Data @ 25°and VDD = 3.3V unless otherwise noted and RF Circuit
Figure 54. Device performance Pin-Pout-Gain
@2650MHz
Figure 55. Device performance Pin-Pout-Gain
@3500MHz
Figure 56. ACLR@WCDMA 4FA1, 1900MHz, -50dBc
Figure 57. ACLR @LTE20MHz1 1900MHz, -50dBc
1
WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob
1
Figure 59. ACLR @LTE20MHz1 2140MHz, -50dBc
Figure 58. ACLR@WCDMA 4FA1, 2140MHz, -50dBc
1
BeRex
WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob
●website: www.berex.com
LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob.
1
LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob.
●email: [email protected]
15
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical RF Performance Plot - BVA304 EVK - PCB(RF Circuit:1700~4000MHz)
Typical Performance Data @ 25°and VDD = 3.3V unless otherwise noted and RF Circuit
Preliminary Datasheet
Figure 60. ACLR@WCDMA 4FA1, 2650MHz, -50dBc
1
WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob
Figure 61. ACLR @LTE20MHz1, 2650MHz, -50dBc
1
Figure 62. ACLR@WCDMA 4FA1, 3500MHz, -50dBc
1
BeRex
WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob
●website: www.berex.com
LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob.
Figure 63. ACLR @LTE20MHz1 3500MHz, -50dBc
1
LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob.
●email: [email protected]
16
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical RF Performance Plot - BVA304 EVK - PCB(RF Circuit:1700~2140MHz)
Typical Performance Data @ 25°and VDD = 3.3V unless otherwise noted and RF Circuit
Table 16. Typical RF Performance(1700~2140Mhz)
Preliminary Datasheet
parameter
Unit
1900
2140
MHz
Gain
11.9
10.6
dB
S11
-16.5
-13.8
dB
S22
-7.6
-7.1
dB
1
33.8
33.7
dBm
P1dB
19.1
19.5
dBm
OIP3
Noise Figure
1
Frequency
3.9
4.4
Table 17. 1700~2140MHz High OIP3
RF Matching Application Circuit
dB
OIP3 _ measured with two tones at an output of -3 dBm per tone separated by 1 MHz.
Freq.
Application Circuit
Values
RF Matching Circuit
1700MHz ~ 2140MHz
C1/C3
10pF
C7
1.2pF
L3(1005 Chip Ind)
7.5nH
Figure 64. Gain vs Frequency
Figure 65. OIP3 vs Frequency
Figure 66. OIP3 @ 1900MHz vs Temperature
Figure 67. OIP3 @ 2140MHz vs Temperature
* RF Circuit application refer to Table 10.
BeRex
●website: www.berex.com
●email: [email protected]
17
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical Performance Plot - BVA304 EVK - PCB(RF Matching Circuit*:1700~2140MHz)
Preliminary Datasheet
Typical Performance Data @ 25°and VDD = 3.3V unless otherwise noted and RF Circuit
Figure 68. Device performance Pin-Pout-Gain
@1900MHz
Figure 69. Device performance Pin-Pout-Gain
@2140MHz
Figure 70. ACLR@WCDMA 4FA1, 1900MHz, -50dBc
Figure 71. ACLR @LTE20MHz1 1900MHz, -50dBc
1
WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob
1
Figure 73. ACLR @LTE20MHz1 2140MHz, -50dBc
Figure 72. ACLR@WCDMA 4FA1, 2140MHz, -50dBc
1
BeRex
WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob
●website: www.berex.com
LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob.
1
LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob.
●email: [email protected]
18
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Preliminary Datasheet
Figure 74. Evaluation Board Schematic
Figure 75. PCB Evaluation Board
Table 18. Bill of Material - Evaluation Board
: RF circuit application with freq 1700MHz~4GHZ
BeRex
●website: www.berex.com
Part
Part Number
Qty
4 CAP 0402 100pF J 50V
1 CAP 0402 1000pF J 50V
No.
Ref Des
1
2
C4,C15
C5
3
C1,C3
4
C6
1 TANTAL 3216 10uF 16V
5
C7
1 RES 1608 J 0 ohm
6
7
8
C22
L1
R2,R3
9
R1,R4,R6
10
CON1
11
U1
12
J1,J3
REMARK
2 CAP 0402 10pF J 50V
1 TANTAL 3216 0.1uF 35V
1 IND 1608 7.5nH
2 RES 1005 J 10K ohm
3 RES 1608 J 0 ohm
1 15P-MALE-D-sub connector
1 QFN4X4_24L_BVA304
2 SMA_END_LAUNCH
●email: [email protected]
19
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Preliminary Datasheet
Figure 76. Evaluation Board PCB Layer Information
Figure 77. Application Circuit schematic*
(Use only Serial mode)
* notice. The serial mode PUP state of this Fig. 77 is setting in reference Loss and each combinations of C0.5-C16 are shown in the Table 4. Truth Table.
BeRex
●website: www.berex.com
●email: [email protected]
20
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Preliminary Datasheet
Figure 78. Packing outline drawing
Figure 79. Package Marking
BVA304
YYWWXX
YY = Year, WW = Working
Week, XX = Wafer No.
BeRex
●website: www.berex.com
●email: [email protected]
21
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2
BVA304
50-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Preliminary Datasheet
Figure 80. Tape & Reel
Packaging information:
Tape Width (mm): 12 / Reel Size (inches): TBD
Device Cavity Pitch (mm): 8 / Devices Per Reel: TBD
Lead plating finish
100% Tin Matte finish
(All BeRex products undergoes a 1 hour, 150 degree C, Anneal bake to eliminate thin whisker growth concerns.)
MSL / ESD Rating
ESD Rating:
TBD
Value:
TBD
Test:
TBD
Standard:
TBD
MSL Rating:
Level 1 at +265°C convection reflow
Standard:
JEDEC Standard J-STD-020
NATO CAGE code:
2
BeRex
N
9
6
F
●website: www.berex.com
●email: [email protected]
22
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.2