BVA305

BVA305
40-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Figure 2. Package Type
Product Description
The BVA305 is a digitally controlled variable gain amplifier
(DVGA) is featuring high linearity using the voltage 3V
supply with a broadband frequency range of 40 to 4000
MHz.
Both stages are internally matched to 50 Ohms and It is
easy to use with no external matching components required
A serial output port enables cascading with other serial
controlled devices.
An integrated digital control interface supports both serial
and parallel programming of the attenuation,
including the capability to program an initial attenuation
state at power-up.
Covering a 31.5 dB attenuation range in 0.5 dB steps.
The BVA305 is targeted for use in wireless infrastructure,
point-to-point, or can be used for any general purpose
wireless application
VSS/GND
P/S
C8
RF2
C4
C2
Figure 1. Functional Block Diagram
24-lead 4x4 mm QFN
Device Features















18 GND
C1
2
17 GND
3



16 VDD
C16
4
15 PUP2
GND
5
14 PUP1
Single Fixed +3V supply(Amp)
40-4000MHZ Broadband Performance
13.8dB Gain at 2.14GHz
4dB Noise Figure at max gain setting
14.2dBm P1dB at 2.14GHz
27.6dBm OIP3 at 2.14GHz
Single Fixed 3V supply
No matching circuit needed
Attenuation: 0.5 dB steps to 31.5 dB
Safe attenuation state transitions
Monotonicity: 0.5 dB up to 4 GHz
High attenuation accuracy(DSA to Amp)

1.8V control logic compatible
105°C operating temperature
Programming modes
- Direct Parallel
- Latched Parallel
- Serial
Unique power-up state selection
13 LE
Clock
Data
9 10 11 12
GND
8
RF1
7
AMPIN
AMPOUT 6
BeRex
Wide Power supply range of +2.7~5.5V(DSA)
±(0.15 + 8% x Atten) @ 4 GHz
1
C0.5
Integrate DSA to Amp Functionality
±(0.15 + 2% x Atten) @ 2.2 GHz
GND
Digital Step Attenuation
Small 24-Pin 4 x 4 mm QFN Package
±(0.10 + 2% x Atten) @ 1 GHz
24 23 22 21 20 19
GND
Preliminary Datasheet
The BVA305 integrates a high performance digital step
attenuator and a high linearity, broadband gain block.
using the small package(4x4mm QFN package) and operating VDD 3V voltage.
and designed for use in 3G/4G wireless infrastructure and
other high performance RF applications
●website: www.berex.com
Application



3G/4G Wireless infrastructure and other high performance RF application
Microwave and Satellite Radio
General purpose Wireless
●email: [email protected]
1
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.3
BVA305
40-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Table 1. Electrical Specifications1
Parameter
Condition
Operational Frequency Range
Min
Typ
40
Gain
Attenuation = 0dB, at 1900MHz
Attenuation Control range
0.5dB step
13
Attenuation Step
14
Preliminary Datasheet
Unit
4000
MHz
15
dB
31.5
dB
0.5
dB
±(0.10 + 2% of atten setting)
40MHZ-1GHz
Attenuation
Accuracy
Max
>1GHZ-2.2GHZ
±(0.15 + 2% of atten setting)
Any bit or bit combination
dB
±(0.15 + 8% of atten setting)
>2.2GHz-4GHZ
Return loss 1GHZ-2.2GHZ
(input or output
port)
2.2GHz-4GHZ
Attenuation = 0dB
Output Power for 1dB Compression
Attenuation = 0dB, at 1900MHz
16
19
11
16
dB
14.8
dBm
28
dBm
dB
Attenuation = 0dB, at 1900MHz
Output Third Order Intercept Point
two tones at an output of 0 dBm per tone
separated by 1 MHz.
Noise Figure
Attenuation = 0dB, at 1900MHz
4.1
Switching time
50% CTRL to 90% or 10% RF
500
DSA
2.7
800
ns
5.5
V
Supply voltage
AMP
Supply Current
Control Interface
3
48
Serial / parallel mode
54
V
60
6
mA
Bit
Digital input high
1.17
3.6
V
Digital input low
-0.3
0.6
V
Control Voltage
Impedance
1
BeRex
50
Ω
Device performance _ measured on a BeRex Evaluation board at 25°C, 50 Ω system, VDD=+3V, measure on Evaluation Board (DSA to AMP)
●website: www.berex.com
●email: [email protected]
2
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.3
BVA305
40-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Table 2. Typical RF Performance1
Parameter
Frequency
70
Unit
900
1900
2140
2650
MHz
Gain
16.9
15.6
14.2
13.8
12.5
dB
S11
-15.3
-12.3
-15.6
-16.4
-17.3
dB
S22
-20.7
-15.5
-25.6
-18.7
-12.9
dB
2
32.3
31.3
28.0
27.6
25.5
dBm
P1dB
15.2
15.6
14.8
14.2
13.4
dBm
Noise Figure
3.4
3.6
4.1
4.2
5.1
dB
OIP3
Preliminary Datasheet
3
1
Device performance _ measured on a BeRex evaluation board at 25°C, VDD=+3V,50 Ω system. measure on Evaluation Board (DSA to AMP)
2
OIP3 _ measured with two tones at an output of 0 dBm per tone separated by 1 MHz.
3
70MHz measured with IF application circuit.(refer to table 10.)
Table 3. Absolute Maximum Ratings
Parameter
Condition
Supply Voltage(VCC)
Amp/DSA
Supply Current
Amp
Digital input voltage
Min
Typ
Amp/DSA
Operating Temperature
Amp/DSA
Storage Temperature
Unit
V
110
-0.3
Maximum input power
Max
3.6/5.5
mA
3.6
V
+12/+30
dBm
-40
85/105
℃
-55
150
℃
Junction Temperature
150
℃
Operation of this device above any of these parameters may result in permanent damage.
BeRex
●website: www.berex.com
●email: [email protected]
3
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.3
BVA305
40-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Programming Options
Preliminary Datasheet
Parallel/Serial Selection
Either a parallel or serial interface can be used to
control the BVA305. The P/S bit provides this
selection, with P/S = LOW selecting the parallel
interface and P/S = HIGH selecting the serial
interface.
Clock, and Latch Enable (LE). The Data and Clock
inputs allow data to be serially entered into the shift
register, a process that is independent of the state of
the LE input.
Parallel Mode Interface
The parallel interface consists of six CMOS compatible
control lines that select the desired
attenuation state, as shown in Table 4.
The parallel interface timing requirements are
defined by Figure 4 (Parallel Interface Timing
Diagram), Table 7 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
For latched parallel programming the Latch Enable
(LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Figure 3) to latch the new attenuation state into
the device.
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
attenuation state control values will change device
state to new attenuation. Direct Mode is ideal for
Table 4. Truth Table
Power-up Control Settings
The BVA305 always assumes a specifiable
attenuation setting on power-up. This feature exists
for both the Serial and Parallel modes of operation,
and allows a known attenuation state to be
established before an initial serial or parallel control
word is provided.
When the attenuator powers up in Serial mode
(P/S = 1), the six control bits are set to whatever
data is present on the six parallel data inputs (C0.5
to C16). This allows any one of the 64 attenuation
settings to be specified as the power-up state.
C16
C8
C4
C2
C1
0
0
0
0
0
0
0
Reference Loss
0
0
0
0
0
0
1
0.5 dB
0
0
0
0
0
1
0
1 dB
0
0
0
0
1
0
0
2 dB
0
0
0
1
0
0
0
4 dB
When the attenuator powers up in Parallel mode
(P/S = 0) with LE = 0, the control bits are
automatically set to one of four possible values.
These four values are selected by the two power-up
control bits, PUP1 and PUP2, as shown in Table 5
(Power-Up Truth Table, Parallel Mode).
0
0
1
0
0
0
0
8 dB
Table 5. Parallel PUP Truth Table
0
1
0
0
0
0
0
16 dB
P/S
LE
PUP2
PUP1
Attenuation state
31.5 dB
0
0
0
0
Reference Loss
0
0
1
0
8 dB
0
0
0
1
16 dB
0
0
1
1
31.5 dB
0
1
X
X
Defined by C0.5-C16
1
1
1
1
1
1
Note: Not all 64 possible combinations of C0.5-C16 are shown in table
Serial Interface
The serial interface is a 6-bit serial-in, parallel-out
shift register buffered by a transparent latch. It is
controlled by three CMOS-compatible signals: Data,
BeRex
The shift register should be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data. The timing for this operation is defined by
Figure 3 (Serial Interface Timing Diagram) and
Table 6 (Serial Interface AC Characteristics).
P/S
0
C0.5 Attenuation state
The LE input controls the latch. When LE is HIGH,
the latch is transparent and the contents of the serial
shift register control the attenuator. When LE is
brought LOW, data in the shift register is latched.
●website: www.berex.com
Note: Power up with LE = 1 provides normal parallel operation with C0.5-C16, and PUP1 and PUP2
are not active
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Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.3
BVA305
40-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Figure 3. Serial Interface Timing Diagram
Table 8. 6-Bit Attenuator Serial Programming
Register Map
B5
B4
B3
B3
B1
B0
C16
C8
C4
C2
C1
C0.5
MSB (first in)
fClk
Serial data clock frequency
10
MHz
ns
tClkL Serial clock LOW time
30
ns
10
ns
tLEPW LE minimum pulse width
30
ns
Serial data set-up time
tSDSUP
before clock rising edge
10
ns
10
ns
tSDHLD
Serial data hold time after
clock falling edge
Note: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern
are clocked at 10 MHz to verify fclk specification
Table 7. Parallel Interface AC Characteristics
VDD = 3.3V with DSA only, -40°C < TA < 105°C, unless otherwise specified
Symbol
tLEPW
Parameter
LE minimum pulse width
Data set-up time before
tPDSUP
rising edge of LE
Data hold time after falling
tPDHLD
edge of LE
BeRex
Min Max
Unit
10
ns
10
ns
10
ns
●website: www.berex.com
VSS/GND
C8
RF2
P/S
C4
20
19
18
GND
C1
2
17
GND
C0.5
3
16
VDD
C16
4
15
PUP2
GND
5
14
PUP1
AMPOUT
6
13
LE
10
11
12
Data
9
RF1
8
Clock
EXPOSED
Grounnd Pad
GND
Unit
30
LE set-up time after last
clock falling edge
21
7
tClkH Serial clock HIGH time
tLESUP
22
AMPIN
Min Max
23
1
VDD = 3.3V with DSA only, -40°C < TA < 105°C, unless otherwise specified
Parameter
24
GND
Table 6. Serial Interface AC Characteristics
Symbol
C2
Figure 4. Pin Configuration(Top View)
GND
Preliminary Datasheet
Figure 4. Parallel Interface Timing Diagram
LSB (Last in)
Table 9. Pin Description
Pin
1,5,7,9,17,18
2
3
4
6
8
10
11
12
13
14
15
16
Pin name
GND
C1
C0.55
C163,5
AMPOUT
AMPIN
RF11
DATA3
Clock
LE4
PUP15
PUP2
VDD
Description
Ground
Attenuation control bit, 1dB
Attenuation control bit, 0.5dB
Attenuation control bit, 16dB
RF Amp out Port
RF Amp in port
RF port(DSA output)
Serial interface data input
Serial interface clock input
Latch Enable input
Power-up selection bit 1
Power-up selection bit 2
Supply voltage (nominal 3V)
19
VSS/GND
External VSS negative voltage control or
ground
20
21
22
23
24
P/S
RF21
C8
C4
C2
Parallel/Serial mode select
RF port(DSA input)
Attenuation control bit, 8dB
Attenuation control bit, 4dB
Attenuation control bit, 2dB
Note: 1. RF pins 10 and 21 must be at 0V DC. The RF pins do not require DC blocking capacitors for proper
Operation if the 0V DC requirement is met
2. Use VssEXT (pin 12) to bypass and disable internal negative voltage generator.
Connect VssEXT (pin 12, VssEXT = GND) to enable internal negative voltage generator
3.Place a 10 kΩ resistor in series, as close to pin as possible to avoid frequency resonance
4. This pin has an internal 2 MΩ resistor to internal positive digital supply
5. This pin has an internal 200 kΩ resistor to GND
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Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.3
BVA305
40-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical Performance Plot - BVA305 EVK - PCB(RF Circuit*:500~4000MHz)
Preliminary Datasheet
Typical Performance Data @ 25°and VDD = 3.0V unless otherwise noted and RF Circuit
Figure 5. Gain vs Frequency
Figure 6. Gain vs Frequency
@ Major Attenuation Steps
Figure 7. Input Return Loss vs Frequency
Figure 8. Input Return Loss vs Frequency
@ Max Gain & Min1 Gain State
Note: 1. Min Gain was measured in the state is set with attenuation 31.5dB
Figure 9. output Return Loss vs. Frequency
Figure 10. output Return Loss vs. Frequency
@ Max Gain & Min Gain1 State
Note: 1. Min Gain was measured in the state is set with attenuation 31.5dB
* RF Circuit application refer to Table 10.
BeRex
●website: www.berex.com
●email: [email protected]
6
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.3
BVA305
40-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical Performance Plot - BVA305 EVK - PCB(RF Circuit*:500~4000MHz)
Preliminary Datasheet
Typical Performance Data @ 25°and VDD = 3.0V unless otherwise noted and RF Circuit
Figure 11. OIP3 vs Frequency
Figure 12. P1dB vs Frequency
Figure 13. Noise Figure vs Frequency
Figure 14. Attenuation Error vs Frequency
@ Major Attenuation Steps
Figure 15. Attenuation Error vs Attenuation Setting
Figure 16. 0.5dB Step Attenuation vs Attenuation
Setting
* RF Circuit application refer to Table 10.
BeRex
●website: www.berex.com
●email: [email protected]
7
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.3
BVA305
40-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical Performance Plot - BVA305 EVK - PCB(RF Circuit*:500~4000MHz)
Preliminary Datasheet
Typical Performance Data @ 25°and VDD = 3.0V unless otherwise noted and RF Circuit
Figure 17. Attenuation Error @ 900MHz vs
Temperature
Figure 18. Attenuation Error @ 1.9GHz vs
Temperature
Figure 19. Attenuation Error @ 2.1GHz vs
Temperature
Figure 20. Attenuation Error @ 2.6GHz vs
Temperature
Figure 21. Attenuation Error @ 3.9GHz vs
Temperature
* RF Circuit application refer to Table 10.
BeRex
●website: www.berex.com
●email: [email protected]
8
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.3
BVA305
40-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical Performance Plot - BVA305 EVK - PCB(IF Circuit*:50~500MHz)
Preliminary Datasheet
Typical Performance Data @ 25°C, Maximum gain state and VDD = 3.0V unless otherwise noted
Figure 22. Gain vs Frequency
Figure 23. Gain vs Frequency
@ Major Attenuation Steps
Figure 24. Input Return Loss vs Frequency
Figure 25. Input Return Loss vs Frequency
@ Max Gain & Min Gain1 State
Note: 1. Min Gain was measured in the state is set with attenuation 31.5dB
Figure 26. output Return Loss vs. Frequency
Figure 27. output Return Loss vs. Frequency
@ Max Gain & Min Gain1 State
Note: 1. Min Gain was measured in the state is set with attenuation 31.5dB
* RF Circuit application refer to Table 10.
BeRex
●website: www.berex.com
●email: [email protected]
9
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.3
BVA305
40-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical Performance Plot - BVA305 EVK - PCB(IF Circuit*:50~500MHz)
Preliminary Datasheet
Typical Performance Data @ 25°C, Maximum gain state and VDD = 3.0V unless otherwise noted
Figure 28. OIP3 vs Frequency
Figure 29. P1dB vs Frequency
Figure 30. Noise Figure vs Frequency
Figure 31. Attenuation Error vs Frequency
@ Major Attenuation Steps
Figure 32. Attenuation Error vs Attenuation Setting
Figure 33. 0.5dB Step Attenuation vs Attenuation
Setting
* IF Circuit application refer to Table 10.
BeRex
●website: www.berex.com
●email: [email protected]
10
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.3
BVA305
40-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Typical Performance Plot - BVA305 EVK - PCB(IF Circuit*:50~500MHz)
Preliminary Datasheet
Typical Performance Data @ 25°C, Maximum gain state and VDD = 3.0V unless otherwise noted
Figure 34. Attenuation Error @ 40MHz vs
Temperature
Figure 35. Attenuation Error @ 70MHz vs
Temperature
Figure 36. Attenuation Error @ 100MHz vs
Temperature
Figure 37. Attenuation Error @ 200MHz vs
Temperature
Figure 38. Attenuation Error @ 300MHz vs
Temperature
Figure 39. Attenuation Error @ 400MHz vs
Temperature
* IF Circuit application refer to Table 10.
BeRex
●website: www.berex.com
●email: [email protected]
11
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.3
BVA305
40-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Evaluation Board PCB Information
Figure 40. Evaluation Board PCB Layer Information
COPPER :1oz + 0.5oz (plating), Top Layer
EM825B ER: 4.6~4.8
P.P : (0.2+0.06+0.06) TOTAL = 0.32mm
COPPER :1oz (GND), Inner Layer
Preliminary Datasheet
MTC Er:4.6
CORE : 0.73mm
FINISH TICKNESS :1.55T
COPPER :1oz, Inner Layer
EM825B Er:4.6~4.8
P.P : (0.2+0.06+0.06) TOTAL = 0.32mm
COPPER :1oz + 0.5oz (plating), Bottom Layer
Figure 41. Evaluation Board PCB
* IF Circuit application refer to Table 10.
BeRex
●website: www.berex.com
●email: [email protected]
12
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.3
BVA305
40-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Preliminary Datasheet
Figure 42. Evaluation Board Schematic
Table 10. Application Circuit
Application Circuit Values Example
Freq.
IF Circuit
RF Circuit
C1/C3
L3(1005 Chip Ind)
2nF
820nH
100pF
12H
Table 11. Bill of Material - Evaluation Board
No.
Ref Des
Part
Qty
Part Number
1 C1,C3,C4,C15
4 CAP 0402 100pF J 50V
2
C5
1 CAP 0402 1000pF J 50V
3
C6
1 TANTAL 3216 10UF 16V
4
C22
1 TANTAL 3216 0.1uF 35V
5
L1
1 IND 1608 12nH
7
R2,R3
2 RES 1005 J 10K
8
R1,R4,R6
9
CON1
20
U1
22
J1,J3
REMARK
IF circuit refer to table 10
IF circuit refer to table 10
3 RES 1608 J 0ohm
15P-MALE-D-sub con1 nector
1
QFN4X4_24L_BVA303
2 SMA_END_LAUNCH
Notice: Evaluation Board for Marketing Release was set to RF circuit application
BeRex
●website: www.berex.com
●email: [email protected]
13
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.3
BVA305
40-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Preliminary Datasheet
Figure 43. Packing outline drawing
Figure 44. Package Marking
BVA303
YYWWXX
YY = Year, WW = Working
Week, XX = Wafer No.
BeRex
●website: www.berex.com
●email: [email protected]
14
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.3
BVA305
40-4000 MHz DIGITAL VARIABLE GAIN AMPLIFIER
Preliminary Datasheet
Figure 45. Tape & Reel
Packaging information:
Tape Width (mm): 12 / Reel Size (inches): TBD
Device Cavity Pitch (mm): 8 / Devices Per Reel: TBD
Lead plating finish
100% Tin Matte finish
(All BeRex products undergoes a 1 hour, 150 degree C, Anneal bake to eliminate thin whisker growth concerns.)
MSL / ESD Rating
ESD Rating:
Class 1C
Value:
Passes<2000V
Test:
Human Body Model(HBM)
Standard:
JEDEC Standard JESD22-A114B
MSL Rating:
Level 1 at +265°C convection reflow
Standard:
JEDEC Standard J-STD-020
NATO CAGE code:
2
BeRex
N
9
6
F
●website: www.berex.com
●email: [email protected]
15
Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex.
All other trademarks are the property of their respective owners. © 2016 BeRex
Rev. 0.3