Product Specification PE4306 50 Ω RF Digital Attenuator 5-bit, 31 dB, DC – 4.0 GHz Product Description Features • Attenuation: 1 dB steps to 31 dB • Flexible parallel and serial programming interfaces • Latched or direct mode • Unique power-up state selection • Positive CMOS control logic • High attenuation accuracy and linearity over temperature and frequency • Very low power consumption • Single-supply operation • 50 Ω impedance • Pin compatible with PE430x series • Packaged in a 20 Lead 4x4 mm QFN The PE4306 is a high linearity, 5-bit RF Digital Step Attenuator (DSA) covering a 31 dB attenuation range in 1dB steps, and is pin compatible with the PE430x series. This 50-ohm RF DSA provides both parallel (latched or direct mode) and serial CMOS control interface, operates on a single 3-volt supply and maintains high attenuation accuracy over frequency and temperature. It also has a unique control interface that allows the user to select an initial attenuation state at power-up. The PE4306 exhibits very low insertion loss and low power consumption. This functionality is delivered in a 4x4 mm QFN footprint. The PE4306 is manufactured in Peregrine’s patented Ultra Thin Silicon (UTSi®) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram Figure 2. Package Type 4x4mm -20 Lead QFN Switched Attenuator Array RF Input RF Output Parallel Control 5 Serial Control 3 Power-Up Control 2 Control Logic Interface Table 1. Electrical Specifications @ +25°C, VDD = 3.0 V Parameter Test Conditions Frequency Operation Frequency Insertion Loss DC - 2.2 GHz Any Bit or Bit Combination 3 1 dB Compression 1, 2 Input IP3 Two-tone inputs +18 dBm Return Loss Switching Speed Typical DC 2 Attenuation Accuracy Minimum 50% control to 0.5 dB DC ≤ 1.0 GHz - 1.5 Maximum Units 4000 MHz 2.25 dB ±(0.3 + 3% of atten setting) dB ±(0.3 + 5% of atten setting) dB - - 1 MHz - 2.2 GHz 30 34 - dBm 1 MHz - 2.2 GHz - 52 - dBm DC - 2.2 GHz 15 20 - dB - - 1 µs 1.0 < 2.2 GHz Notes: 1. Device Linearity will begin to degrade below 1 Mhz 2. See Max input rating in Table 2 & Figures on Pages 2 to 4 for data across frequency. 3. Note Absolute Maximum in Table 3. Document No. 70/0160~02C │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 PE4306 Product Specification Typical Performance Data (25°C, VDD=3.0 V unless otherwise noted) Figure 4. Attenuation at Major steps Figure 3. Insertion Loss 0 35 31 dB 30 -1 Normalized Error (dB) Insertion Loss (dB) 25 -2 -3 insertion loss @ 25 C insertion loss @ -40 C insertion loss @ 85 C -4 -5 0 500 1000 1500 2000 2500 3000 3500 20 16 dB 15 10 8 dB 5 4 dB 0 2 dB 1 dB 4000 0 500 1000 Frequency (MHz) -10 -10 -20 -20 S22 (dB) 0 s11 (dB) 2500 3000 3500 4000 3500 4000 Figure 6. Output Return Loss at Major Attenuation Steps 0 16 dB -30 31 dB 31 dB -40 2000 Frequency (MHz) Figure 5. Input Return Loss at Major Attenuation Steps -30 1500 16 dB -40 -50 -50 0 500 1000 1500 2000 2500 3000 Frequency (MHz) ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 11 3500 4000 0 500 1000 1500 2000 2500 3000 Frequency (MHz) Document No. 70/0160~02C │ UltraCMOS™ RFIC Solutions PE4306 Product Specification Typical Performance Data (25°C, VDD=3.0 V unless otherwise noted) Figure 8. Attenuation Error Vs. Attenuation Setting at 10 MHz and 510 MHz 2 1.5 0 1 -2 0.5 31 dB Error (dB) Error (dB) Figure 7. Attenuation Error Vs. Frequency -4 0 -6 -0.5 -8 -1 -10 10 MHz @ 25 C 510 MHz @ 25 C 10 MHz @ -40 C 510 MHz @ -40 C 10 MHz @ 85 C 510 MHz @ 85 C -1.5 0 500 1000 1500 2000 2500 3000 3500 4000 0 5 10 Frequency (MHz) 25 30 35 Figure 10. Attenuation Error Vs. Attenuation Setting at 1510 MHz and 2010 MHz 1.5 1.5 1 1 0.5 0.5 Error (dB) Error (dB) 20 Attenuation State (dB) Figure 9. Attenuation Error Vs. Attenuation Setting 1010 MHz and 1210 MHz 0 -0.5 0 -0.5 1210 MHZ @ 25 C 1210 MHz @ -40 C 1210 MHz @ 85 C 1010 MHz @ 25 C 1010 MHz @ -40 C 1010 MHz @ 85 C -1 15 1510 MHz @ 25 C 2010 MHz @ 25 C 1510 MHz @ -40 C 2010 MHz @ -40 C 1510 MHz @ 85 C 2010 MHz @ 85 C -1 -1.5 -1.5 0 5 10 15 20 Attenuation State (dB) Document No. 70/0160~02C │ www.psemi.com 25 30 35 0 5 10 15 20 25 30 35 Attenuation State (dB) ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 11 PE4306 Product Specification Typical Performance Data (25°C, VDD=3.0 V unless otherwise noted) Figure 11. Attenuation Error vs. Attenuation Setting at 2010 MHz and 2510 MHz Figure 12. 1 dB Compression vs. Frequency 40 1.5 1 1 dB Compression (dBm) 35 Error (dB) 0.5 0 -0.5 2210 MHz @ 25 C 2510 MHz @ 25 C 2210 MHz @ -40 C 2510 MHz @ -40 C 2210 MHz @ 85 C 2510 MHz @ 85 C -1 30 0 dB 1 dB 2 dB 31 dB 25 -1.5 20 0 5 10 15 20 25 30 35 Attenuation State (dB) 1000 1500 2000 2500 3000 Frequency (MHz) Figure 13. Input IP3 vs. Frequency 60 55 50 IP3 (dBm) 45 40 35 30 25 0 dB 8 dB 1 dB 16 dB 2 dB 31 dB 4 dB 20 1000 1500 2000 2500 3000 Frequency (MHz) ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 11 Document No. 70/0160~02C │ UltraCMOS™ RFIC Solutions PE4306 Product Specification C16 1 RF1 2 Data 3 C4 16 C2 VDD 20-lead QFN 4x4 mm Exposed Solder Pad Clock 4 LE 5 Table 3. Absolute Maximum Ratings Symbol 17 GND 18 19 20 C1 N/C Figure 14. Pin Configuration (Top View) V V -0.3 TST Storage temperature range -65 150 °C Operating temperature range -40 85 °C Input power (50Ω) 24 dBm ESD voltage (Human Body Model) 500 V RF2 TOP 13 P/S PIN GND Units 4.0 Voltage on any input 14 11 Max -0.3 VI C8 Vss/GND Min VDD+ 0.3 15 12 Parameter/Conditions Power supply voltage VESD 10 Parameter GND 9 VDD 8 PUP2 7 PUP1 VDD 6 Table 4. DC Electrical Specifications VDD Power Supply Voltage Table 2. Pin Descriptions Min Typ Max Units 2.7 3.0 3.3 V 100 µA IDD Power Supply Current Pin No. Pin Name 1 C16 Attenuation control bit, 16 dB (Note 4). 2 RF1 RF port (Note 1). Description 3 Data Serial interface data input (Note 4). 4 Clock Serial interface clock input. 5 LE Latch Enable input (Note 2). 6 VDD Power supply pin. 7 PUP1 Power-up selection bit. 8 PUP2 Power-up selection bit. 9 VDD 10 GND Ground connection. 11 GND Ground connection. 12 Vss/GND Digital Input High 0.7xVDD Digital Input Low Digital Input Leakage V 0.3xVDD V 1 µA Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. Electrostatic Discharge (ESD) Precautions Power supply pin. 13 P/S Negative supply voltage or GND connection (Note 3) Parallel/Serial mode select. 14 RF2 RF port (Note 1). 15 C8 Attenuation control bit, 8 dB. 16 C4 Attenuation control bit, 4 dB. 17 C2 Attenuation control bit, 2 dB. 18 GND 19 C1 Attenuation control bit, 1 dB. 20 N/C No connect. Can be connected to any bias. Paddle GND Ground for proper operation Ground connection. Notes: 1: Both RF ports must be held at 0 VDC or DC blocked with an external series capacitor. 2: Latch Enable (LE) has an internal 100 kΩ resistor to VDD. 3: Connect pin 12 to GND to enable internal negative voltage generator. Connect pin 12 to VSS (-VDD) to bypass and disable internal negative voltage generator. 4. Place a 10 kΩ resistor in series, as close to pin as possible to avoid frequency resonance. See “Resistor on Pin 1 & 3” paragraph Document No. 70/0160~02C │ www.psemi.com When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rate specified in Table 3. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Switching Frequency The PE4306 has a maximum 25 kHz switching rate. Resistor on Pin 1 & 3 A 10 kΩ resistor on the inputs to Pin 1 & 3 (see Figure 16) will eliminate package resonance between the RF input pin and the two digital inputs. Specified attenuation error versus frequency performance is dependent upon this condition. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 11 PE4306 Product Specification Programming Options Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE4306. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. Parallel / Direct Mode Interface The parallel interface consists of five CMOScompatible control lines that select the desired attenuation state, as shown in Table 5. The parallel interface timing requirements are defined by Figure 18 (Parallel Interface Timing Diagram), Table 9 (Parallel Interface AC Characteristics), and switching speed (Table 1). For parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Figure 18) to latch new attenuation state into device. For direct programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Table 5. Truth Table P/S C16 C8 C4 C2 C1 Attenuation State 0 0 0 0 0 0 Reference Loss 0 0 0 0 0 1 1 dB 0 0 0 0 1 0 2 dB 0 0 0 1 0 0 4 dB 0 0 1 0 0 0 8 dB 0 1 0 0 0 0 16 dB 0 1 1 1 1 1 31 dB Note: Not all 32 possible combinations of C1-C16 are shown. Serial Interface The PE4306’s serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. The latch is controlled by three CMOScompatible signals: Data, Clock, and Latch Enable (LE). The Data and Clock inputs allow data to be ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 11 serially entered into the shift register, a process that is independent of the state of the LE input. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data. The start bit (B0) of the data should always be low to prevent an unknown state in the device. The timing for this operation is defined by Figure 17 (Serial Interface Timing Diagram) and Table 8 (Serial Interface AC Characteristics). Power-up Control Settings The PE4306 always assumes a specifiable attenuation setting on power-up. This feature exists for both the Serial and Parallel modes of operation, and allows a known attenuation state to be established before an initial serial or parallel control word is provided. When the attenuator powers up in Serial mode (P/ S=1), the five control bits and a stop bit are set to whatever data is present on the five parallel data inputs (C1 to C16). This allows any one of the 32 attenuation settings to be specified as the power-up state. When the attenuator powers up in Parallel mode (P/ S=0) with LE=0, the control bits are automatically set to one of four possible values. These four values are selected by the two power-up control bits, PUP1 and PUP2, as shown in Table 6 (Power-Up Truth Table, Parallel Mode). Table 6. Power-Up Truth Table, Parallel Interface Mode P/S LE PUP2 PUP1 Attenuation State 0 0 0 0 Reference Loss 0 0 0 1 8 dB 0 0 1 0 16 dB 0 0 1 1 31 dB 0 1 X X Defined by C1-C16 Note: Power up with LE=1 provides normal parallel operation with C1-C16, and PUP1 and PUP2 are not active. Document No. 70/0160~02C │ UltraCMOS™ RFIC Solutions PE4306 Product Specification Figure 15. Evaluation Board Layout Evaluation Kit The Digital Attenuator Evaluation Kit board was designed to ease customer evaluation of the PE4306 DSA. J9 is used in conjunction with the supplied DC cable to supply VDD, GND, and –VDD. If use of the internal negative voltage generator is desired, then connect –VDD (black banana plug) to ground. If an external –VDD is desired, then apply -3V. J1 should be connected to the LPT1 port of a PC with the supplied control cable. The evaluation software is written to operate the DSA in serial mode, so switch 7 (P/S) on the DIP switch SW1 should be ON with all other switches off. Using the software, enable or disable each attenuation setting to the desired combined attenuation. The software automatically programs the DSA each time an attenuation state is enabled or disabled. To evaluate the power up options, first disconnect the control cable from the evaluation board. The control cable must be removed to prevent the PC port from biasing the control pins. VCC 16 C4 17 PS VNEG GND CLK LE C2 18 GND 19 C1 U1 QFN4X4 VDD_D 5 DATA C8 RFout GND 15 C8 13 12 J5 Z=50 Ohm 14 PS 1 SMA 11 10 4 RFin PUP2 3 C16 9 LE 2 PUP2 10 kohm CLK 1 C2 C4 8 DATA 10kohm PUP1 SMA Z=50 Ohm PUP1 C16 1 VDD J4 N/C 20 C1 7 During power up with P/S=0 high and LE=0, the control bits are automatically set to one of four possible values presented through the PUP interface. These four values are selected by the two power-up control bits, PUP1 and PUP2, as shown in the Table 6. Figure 16. Evaluation Board Schematic 6 During power up with P/S=1 high and LE=0 or P/ S=0 low and LE=1, the default power-up signal attenuation is set to the value present on the five control bits on the five parallel data inputs (C1 to C16). This allows any one of the 32 attenuation settings to be specified as the power-up state. Pin 20 is open and can be connected to any bias. Resistor on Pin 1 & 3 A 10 kΩ resistor on the inputs to pins 1 & 3 (Figure 16) will eliminate package resonance between the RF input pin and the two digital inputs. Specified attenuation error versus frequency performance is dependent upon this condition. Document No. 70/0160~02C │ www.psemi.com 100 pF Note: Resistors on pins 1 and 3 are required and should be placed as close to the part as possible to avoid package resonance and meet error specifications over frequency. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 11 PE4306 Product Specification Table 7. 5-Bit Attenuator Serial Programming Register Map Figure 17. Serial Interface Timing Diagram LE B5 B4 B3 B2 B1 C16 C8 C4 C2 C1 ↑ MSB (first in) Clock Data MSB B0 0 ↑ LSB (last in) LSB tSDSUP tLESUP tSDHLD tLEPW Note: The stop bit (B0) must always be low to prevent the attenuator from entering an unknown state. Figure 18. Parallel Interface Timing Diagram LE Parallel Data C16:C1 tPDSUP tLEPW tPDHLD Table 8. Serial Interface AC Characteristics Table 9. Parallel Interface AC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter Min Max Unit 10 MHz fClk Serial data clock frequency (Note 1) tClkH Serial clock HIGH time 30 ns tClkL Serial clock LOW time 30 ns tLESUP LE set-up time after last clock falling edge 10 ns tLEPW LE minimum pulse width 30 ns tSDSUP Serial data set-up time before clock rising edge 10 ns tSDHLD Serial data hold time after clock falling edge 10 ns Symbol tLEPW tPDSUP tPDHLD Parameter Min LE minimum pulse width 10 Max Unit ns Data set-up time before rising edge of LE Data hold time after falling edge of LE 10 ns 10 ns Note: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 11 Document No. 70/0160~02C │ UltraCMOS™ RFIC Solutions PE4306 Product Specification Figure 19. Package Drawing 4.00 INDEX AREA 2.00 X 2.00 2.00 4.00 2.00 -B- 0.25 C 0.80 -A- 0.10 C 0.08 C SEATING PLANE 0.20 REF -C- 2.00 TYP 0.55 2.00 TYP 0.50 0.020 EXPOSED PAD & TERMINAL PADS 1.00 0.435 1.00 10 11 2.00 4.00 0.435 0.18 6 5 0.18 1 15 20 DETAIL A EXPOSED PAD 16 DETAIL A 2 0.23 1 0.10 C A B 1. Dimension applies to metallized terminal and is measured between 0.25 and 0.30 from terminal tip. 2. Coplanarity applies to the exposed heat sink slug as well as the terminals. 3. Dimensions are in millimeters. Document No. 70/0160~02C │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 11 PE4306 Product Specification Figure 20. Marking Specifications 4306 YYWW ZZZZZ YYWW = Date Code ZZZZZ = Last five digits of PSC Lot Number Figure 21. Tape and Reel Drawing Table 10. Ordering Information Order Code Part Marking Description Package Shipping Method 4306-01 4306-02 4306-00 4306-51 4306-52 4306 4306 PE4306-EK 4306 4306 PE4306-20MLP 4x4mm-75A PE4306-20MLP 4x4mm-3000C PE4306-20MLP 4x4mm-EK PE4306G-20MLP 4x4mm-75A PE4306G-20MLP 4x4mm-3000C 20-lead 4x4mm QFN 20-lead 4x4mm QFN Evaluation Kit Green 20-lead 4x4mm QFN Green 20-lead 4x4mm QFN 75 units / Tube 3000 units / T&R 1 / Box 75 units / Tube 3000 units / T&R ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 11 Document No. 70/0160~02C │ UltraCMOS™ RFIC Solutions PE4306 Product Specification Sales Offices United States Japan Peregrine Semiconductor Corp. Peregrine Semiconductor K.K. 9450 Carroll Park Drive San Diego, CA 92121 Tel 1-858-731-9400 Fax 1-858-731-9499 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: 011-81-3-3502-5211 Fax: 011-81-3-3502-5213 Europe China Peregrine Semiconductor Europe Peregrine Semiconductor Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: 011- 33-1-47-41-91-73 Fax : 011-33-1-47-41-91-73 28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: 011-86-21-5836-8276 Fax: 011-86-21-5836-7652 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70/0160~02C │ www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS is a trademark of Peregrine Semiconductor Corp. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 11