Product Specification PE43404 75 Ω RF Digital Attenuator 4-bit, 15 dB, DC – 2.0 GHz Product Description Features • Attenuation: 1.0 dB steps to 15 dB • Flexible parallel and serial programming interfaces • Parallel latched or direct mode • High attenuation accuracy and linearity over temperature and frequency • Unique power-up state selection • Very low power consumption • Single-supply operation • Positive CMOS control logic • 75 Ω impedance • Packaged in a 20 Lead 4x4 mm QFN The PE43404 is a high linearity, 4-bit RF Digital Step Attenuator (DSA) covering a 15 dB attenuation range in 1.0 dB steps. This 75-ohm RF DSA provides both parallel (latched or direct mode) and serial CMOS control interface, operates on a single 3-volt supply and maintains high attenuation accuracy over frequency and temperature. It also has a unique control interface that allows the user to select an initial attenuation state at power-up. The PE43404 exhibits very low insertion loss and low power consumption. This functionality is delivered in a 4x4 mm QFN footprint. The PE43404 is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram Figure 2. Package Type 20 Lead 4x4 mm QFN Switched Attenuator Array RF Input RF Output Parallel Control 5 Serial Control 3 Power-Up Control 1 Control Logic Interface Table 1. Electrical Specifications @ +25°C, VDD = 3.0 V Parameter Test Conditions Frequency Operation Frequency Insertion Loss Any Bit or Bit Combination 1 dB Compression3,4 Input IP31,2,4 Two-tone inputs up to +18 dBm Return Loss Zo = 75 ohms Switching Speed Notes: 1. 2. 3. 4. Typical DC 1 Attenuation Accuracy Minimum 50% control Maximum Units 2000 MHz DC ≤ 1.2 GHz - 1.4 1.95 dB DC ≤ 1.2 GHz - - ±(0.25+ 7% of atten setting) dB 1 MHz ≤ 1.2 GHz 30 34 - dBm 1 MHz ≤ 1.2 GHz - 52 - dBm DC ≤ 1.2 GHz 10 13 - dB - - 1 µs Device Linearity will begin to degrade below 1MHz Max input rating in Table 3 & Figures on Pages 4 to 6 for data across frequency. Note Absolute Maximum in Table 3. Measured in a 50 Ω system. Document No. 70-0258-02 │ www.psemi.com ©2008 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 PE43404 Product Specification GND C1 GND C2 C4 19 18 17 16 10 5 GND LE Exposed Solder Pad 9 4 VDD Clock 8 3 PUP2 Data 15 C8 14 RF2 13 P/S 12 Vss/GND 11 GND Table 2. Pin Descriptions Pin No. Pin Name Table 3. Absolute Maximum Ratings Symbol 20-lead QFN 4x4mm 7 2 N/C RF1 6 1 VDD N/C 20 Figure 15. Pin Configuration (Top View) Description Parameter/Conditions Min Max Units VDD Power supply voltage -0.3 4.0 V VI Voltage on any input -0.3 VDD+ 0.3 V TST Storage temperature range -65 150 °C PIN Input power (50Ω) +30 dBm ESD voltage (Human Body Model) 500 V VESD Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Table 4. Operating Ranges Parameter 1 N/C No connect 2 RF1 RF port (Note 1). 3 Data Serial interface data input (Note 4). 4 Clock Serial interface clock input. 5 LE Latch Enable input (Note 2). 6 VDD Power supply pin. Digital Input High 7 N/C No connect Digital Input Low 8 PUP2 9 VDD 10 GND Ground connection. 11 13 GND Vss/ GND P/S Ground connection. Negative supply voltage or GND connection (Note 3) Parallel/Serial mode select. 14 RF2 RF port (Note 1). 15 C8 Attenuation control bit, 8 dB. 16 C4 Attenuation control bit, 4 dB. 17 C2 18 GND 12 Typ Max Units 2.7 3.0 3.3 V 100 µA IDD Power Supply Current 0.7xVDD V 0.3xVDD V 1 µA +24 dBm 85 °C Power-up selection bit. Power supply pin. Attenuation control bit, 2 dB. Ground connection. 19 C1 Attenuation control bit, 1 dB. 20 GND Ground for proper operation Paddle GND Ground for proper operation Notes: 1. Both RF ports must be held at 0 VDC or DC blocked with an external series capacitor. 2. Latch Enable (LE) has an internal 100 kΩresistor to VDD. 3. Connect pin 12 to GND to enable internal negative voltage generator. Connect pin 12 to VSS (-VDD) to bypass and disable internal negative voltage generator. 4. Place a 10 kΩresistor in series, as close to pin as possible to avoid frequency resonance. See “Resistor on 3” paragraph Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. ©2008 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 11 VDD Power Supply Voltage Min Digital Input Leakage Input Power Temperature range -40 Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rate specified in Table 3. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Switching Frequency The PE43404 has a maximum 25 kHz switching rate. Resistor on Pin 3 A 10 kΩ resistor on the input to Pin 3 (see Figure 5) will eliminate package resonance between the RF input pin and the digital input. Specified attenuation error versus frequency performance is dependent upon this condition. Document No. 70-0258-02 │ UltraCMOS™ RFIC Solutions PE43404 Product Specification Figure 4. Evaluation Board Layout Evaluation Kit Peregrine Specification 101-0112 The Digital Attenuator Evaluation Kit was designed to ease customer evaluation of the PE43404 DSA. J9 is used in conjunction with the supplied DC cable to supply VDD, GND, and –VDD. If use of the internal negative voltage generator is desired, then connect – VDD (black banana plug) to ground. If an external –VDD is desired, then apply -3V. J1 should be connected to the LPT1 port of a PC with the supplied control cable. The evaluation software is written to operate the DSA in serial mode, so switch 7 (P/S) on the DIP switch SW1 should be ON with all other switches off. Using the software, enable or disable each attenuation setting to the desired combined attenuation. The software automatically programs the DSA each time an attenuation state is enabled or disabled. Note: Jumper J6 supplies power to the evaluation board support circuits. To evaluate the Power Up options, first disconnect the control cable from the evaluation board. The control cable must be removed to prevent the PC port from biasing the control pins. During power up with P/S=1 high and LE=1, the default power-up signal attenuation is set to the value present on the four control bits on the four parallel data inputs (C1 to C8). This allows any one of the 32 attenuation settings to be specified as the power-up state. During power up with P/S=0 high and LE=0, the control bits are automatically set to one of two possible values presented through the PUP interface. These two values are selected by the power-up control bit, PUP2, as shown in Table 6. Figure 5. Evaluation Board Schematic 6 C4 16 18 19 17 PS VNEG GND 15 14 13 C8 1 PS -VDD 12 Document No. 70-0258-02 │ www.psemi.com J20 SUPPLY VDD 4 3 2 1 PUP2 PUP1 or GND 11 C14 100pF Note: Resistor on pin 3 is required and should be placed as close to the part as possible to avoid package resonance and meet error specifications over frequency. J19 SMA Z=75 Ohm R24 0 OHM 2 LE C4 5 LE C2 CLK VDD_D GND 4 CLK RFOUT U4 MLPQ4X4 9 DATA C8 10 3 GND 10K PUP2 20 RFIN R23 N/C C1 2 8 DATA GND 1 0 OHM PUP1 2 N/C R25 Z=75 Ohm 1 VDD J18 SMA 7 Pins 1 and 7 are open and may be connected to any bias. C2 C1 Peregrine Specification 102-0142 C12 0.1µF VDD C10 100pF C9 0.1µF ©2008 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 11 PE43404 Product Specification Typical Performance Data @ 25°C, VDD = 3.0 V Figure 7. Attenuation at Major steps Figure 6. Insertion Loss (Zo=75 ohms) 16 0 15dB 14 -0.5 -40C 12 25C 85C -1.5 10 Attenuation (dB) Insertion Loss (dB) -1 -2 -2.5 6 -3 4 -3.5 2 -4 0 0 500 1000 1500 8dB 8 2000 4dB 2dB 1dB 0 500 RF Frequency (MHz) 1500 2000 RF Frequency (MHz) Figure 8. Input Return Loss at Major Attenuation Steps (Zo=75 ohms) Figure 9. Output Return Loss at Major Attenuation Steps (Zo=75 ohms) 0 0 -5 -10 Output Return loss (dB) Input Return Loss (dB) 1000 -10 -15 -20 4dB 8dB -20 -30 -40 -25 15dB -50 -30 0 500 1000 1500 RF Frequency (MHz) ©2008 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 11 2000 0 500 1000 1500 2000 RF Frequency (MHz) Document No. 70-0258-02 │ UltraCMOS™ RFIC Solutions PE43404 Product Specification Typical Performance Data @ 25°C, VDD = 3.0 V Figure 10. Attenuation Error Vs. Frequency Figure 11. Attenuation Error Vs. Attenuation Setting 0.5 1 10Mhz 250Mhz 500Mhz 750Mhz 1010Mhz 1210Mhz 0 Attenuation Error (dB) Attenuation Error (dB) 0.5 -0.5 8dB 15dB -1 0 -0.5 -1.5 -2 -1 0 500 1000 1500 2000 0 2 4 RF Frequency (MHz) 8 10 12 14 16 Attenuation Setting (dB) Figure 12. Input IP3 vs. Frequency (Zo=50 ohms) Figure 13. Input 1 dB Compression (Zo=50 ohms) 60 40 55 35 50 30 1dB Compression (dBm) Input IP3 (dBm) 6 45 40 35 25 20 15 30 10 25 5 0 20 0 500 1000 1500 2000 RF Frequency (MHz) 0 500 1000 1500 2000 RF Frequency (MHz) Note: Positive attenuation error indicates higher attenuation than target value Document No. 70-0258-02 │ www.psemi.com ©2008 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 11 PE43404 Product Specification Typical Performance Data @ 25°C, VDD = 3.0 V Figure 15. Attenuation Error Vs. Attenuation Setting 0.4 0.4 0.3 0.3 0.2 0.2 Attenuation Error (dB) Attenuation Error (dB) Figure 14. Attenuation Error Vs. Attenuation Setting 0.1 0 -0.1 10MHz, -40C 10MHz, 25C -0.2 0.1 0 -0.1 500MHz, -40C -0.2 10MHz, 85C 500MHz, 25C -0.3 -0.3 -0.4 0 2 4 6 8 10 12 14 500MHz, 85C -0.4 16 0 2 4 Attenuation Setting (dB) 0.4 0.3 0.3 0.2 0.2 1000MHz, -40C 1000MHz, 25C -0.1 -0.2 Attenuation Error (dB) Attenuation Error (dB) 10 12 14 16 Figure 17. Attenuation Error Vs. Attenuation Setting 0.4 0 8 Attenuation Setting (dB) Figure 16. Attenuation Error Vs. Attenuation Setting 0.1 6 0.1 0 1200MHz, -40C -0.1 -0.2 -0.3 -0.3 1200MHz, 85C 1200MHz, 25C 1000MHz, 85C -0.4 -0.4 0 2 4 6 8 10 12 14 16 Attenuation Setting (dB) 0 2 4 6 8 10 12 14 16 Attenuation Setting (dB) Note: Positive attenuation error indicates higher attenuation than target value ©2008 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 11 Document No. 70-0258-02 │ UltraCMOS™ RFIC Solutions PE43404 Product Specification Programming Options Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE43404. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. Parallel / Direct Mode Interface The parallel interface consists of four CMOScompatible control lines that select the desired attenuation state, as shown in Table 5. The parallel interface timing requirements are defined by Figure 19 (Parallel Interface Timing Diagram), Table 9 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched parallel programming, the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Figure 19) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Table 5. Truth Table P/S C8 C4 C2 C1 Attenuation State 0 0 0 0 0 Reference Loss 0 0 0 0 1 1 dB 0 0 0 1 0 2 dB 0 0 1 0 0 4 dB 0 1 0 0 0 8 dB 0 1 1 1 1 15 dB Note: Not all 16 possible combinations of C1-C8 are shown in table Serial Interface The PE43404’s serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. The latch is controlled by three CMOScompatible signals: Data, Clock, and Latch Enable (LE). The Data and Clock inputs allow data to be Document No. 70-0258-02 │ www.psemi.com serially entered into the shift register, a process that is independent of the state of the LE input. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data. The start bit (B5) and stop bit (B0) of the data should always be low to prevent an unknown state in the device. The timing for this operation is defined by Figure 18 (Serial Interface Timing Diagram) and Table 8 (Serial Interface AC Characteristics). Power-up Control Settings The PE43404 always assumes a specifiable attenuation setting on power-up. This feature exists for both the Serial and Parallel modes of operation, and allows a known attenuation state to be established before an initial serial or parallel control word is provided. When the attenuator powers up in Serial mode (P/ S=1), the four control bits are set to whatever data is present on the four parallel data inputs (C1 to C8). This allows any one of the 16 attenuation settings to be specified as the power-up state. When the attenuator powers up in Parallel mode (P/ S=0) with LE=0, the control bits are automatically set to one of two possible values. These two values are selected by the power-up control bit, PUP2, as shown in Table 6 (Power-Up Truth Table, Parallel Mode). Table 6. Power-Up Truth Table, Parallel Interface Mode P/S LE PUP2 Attenuation State 0 0 0 Reference Loss 0 0 1 8 dB 0 1 X Defined by C1-C8 Note: Power up with LE=1 provides normal parallel operation with C1-C8, and PUP2 is not active. ©2008 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 11 PE43404 Product Specification Table 7. 4-Bit Attenuator Serial Programming Register Map Figure 18. Serial Interface Timing Diagram LE Clock Data MSB tLESUP tSDHLD B4 B3 B2 B1 0 C8 C4 C2 C1 ↑ MSB (first in) LSB tSDSUP B5 tLEPW B0 0 ↑ LSB (last in) Note: The start bit (B5) and stop bit (B0) must always be low to prevent an unknown state in the device . Figure 19. Parallel Interface Timing Diagram LE Parallel Data C8:C1 tPDSUP tLEPW tPDHLD Table 8. Serial Interface AC Characteristics Table 9. Parallel Interface AC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter Min Max Unit 10 MHz fClk Serial data clock frequency (Note 1) tClkH Serial clock HIGH time 30 ns tClkL Serial clock LOW time 30 ns tLESUP LE set-up time after last clock falling edge 10 ns tLEPW LE minimum pulse width 30 ns tSDSUP Serial data set-up time before clock rising edge 10 ns tSDHLD Serial data hold time after clock falling edge 10 ns Note: Symbol Parameter Min Max Unit tLEPW LE minimum pulse width 10 -- ns tPDSUP Data set-up time before rising edge of LE 10 -- ns tPDHLD Data hold time after falling edge of LE 10 -- ns fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. ©2008 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 11 Document No. 70-0258-02 │ UltraCMOS™ RFIC Solutions PE43404 Product Specification Figure 20. Package Drawing 20 Lead 4x4 mm QFN 4.00 INDEX AREA 2.00 X 2.00 2.00 4.00 2.00 -B- 0.25 C 0.80 -A- 0.10 C 0.08 C SEATING PLANE 0.20 REF -C- 2.00 TYP 0.55 2.00 TYP 0.50 0.020 EXPOSED PAD & TERMINAL PADS 1.00 0.435 1.00 10 11 2.00 4.00 0.435 0.18 6 5 0.18 1 15 20 DETAIL A EXPOSED PAD 16 DETAIL A 2 0.23 1 0.10 C A B 1. Dimension applies to metallized terminal and is measured between 0.25 and 0.30 from terminal tip. 2. Coplanarity applies to the exposed heat sink slug as well as the terminals. 3. Dimensions are in millimeters. Document No. 70-0258-02 │ www.psemi.com ©2008 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 11 PE43404 Product Specification Figure 21. Marking Specifications 43404 YYWW ZZZZZ YYWW = Date Code ZZZZZ = Last five digits of PSC Lot Number Figure 22. Tape and Reel Drawing Table 10. Ordering Information Order Code Part Marking Description Package Shipping Method PE43404MLI 43404 PE43404G-20MLP 4x4mm-75A Green 20-lead 4x4 mm QFN Tape or loose PE43404MLI-Z 43404 PE43404G-20MLP 4x4mm-3000C Green 20-lead 4x4 mm QFN 3000 units / T&R EK43404-01 PE43404-EK PE43404-20MLP 4x4mm-EK Evaluation Kit 1 / Box ©2008 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 11 Document No. 70-0258-02 │ UltraCMOS™ RFIC Solutions PE43404 Product Specification Sales Offices The Americas North Asia Pacific Peregrine Semiconductor Corporation Peregrine Semiconductor K.K. 9380 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Europe Peregrine Semiconductor, Korea Peregrine Semiconductor Europe #B-2402, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305 Bâtiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 South Asia Pacific Space and Defense Products Peregrine Semiconductor, China Americas: Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Tel: 858-731-9453 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence Cedex 3, France Tel: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0258-02 │ www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. ©2008 Peregrine Semiconductor Corp. All rights reserved. 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