Product Specification PE4304 75 Ω RF Digital Attenuator 6-bit, 31.5 dB, DC – 2.0 GHz Product Description Features • 75 Ω impedance • Attenuation: 0.5 dB steps to 31.5 dB • Low distortion for CATV and multi-carrier applications • Flexible parallel and serial programming interfaces • Unique power-up state selection • Positive CMOS control logic • High attenuation accuracy and linearity over temperature and frequency • Very low power consumption • Single-supply operation • Packaged in a 20 lead 4x4 mm QFN The PE4304 is a 75-ohm high-linearity, 6-bit RF Digital Step Attenuator (DSA) covering a 31.5 dB attenuation range in 0.5 dB steps. The PE4304 provides both a parallel (latched or direct mode) and serial CMOS control interface, operates on a single 3-volt supply and maintains high attenuation accuracy over frequency and temperature. It also has a unique control interface that allows the user to select an initial attenuation state at power-up. The PE4304 exhibits very low insertion loss and low power consumption. This functionality is delivered in a 4x4 mm QFN footprint. The PE4304 is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram Figure 2. Package Type 4x4 mm -20 Lead QFN Switched Attenuator Array RF Input RF Output Parallel Control 6 Serial Control 3 Power-Up Control 2 Control Logic Interface Table 1. Electrical Specifications @ +25 °C, VDD = 3.0 V, Zo = 75 Ω Parameter Test Conditions Frequency Operation Frequency Insertion Loss Any Bit or Bit Combination 1 dB Compression3,4 Input IP31,2,4 Two-tone inputs up to +18 dBm Return Loss Switching Speed Notes: 1. 2. 3. 4. Typical DC 2 Attenuation Accuracy Minimum 50% control to 0.5 dB of final value Maximum Units 2000 MHz DC ≤ 1.2 GHz - 1.4 1.8 dB DC ≤ 1.2 GHz - - ±(0.15 + 4% of attenuation setting) dB 1 MHz ≤ 1.2 GHz 30 34 - dBm 1 MHz ≤ 1.2 GHz - 52 - dBm DC ≤ 1.2 GHz 10 13 - dB - - 1 µs Device Linearity will begin to degrade below 1Mhz Max input rating in Table 2 & Figures on Pages 4 to 6 for data across frequency. Note Absolute Maximum in Table 3. Measured in a 50 Ω system. Document No. 70-0066-03 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 PE4304 Product Specification Figure 3. Pin Configuration (Top View) Table 3. Absolute Maximum Ratings C0.5 C1 GND C2 C4 VDD 20 19 18 17 16 Symbol VI Parameter/Conditions Min Max Units Power supply voltage -0.3 4.0 V Voltage on any input -0.3 VDD+ V 15 C8 TST Storage temperature range -65 150 °C 14 RF2 TOP Operating temperature -40 85 °C 13 P/S PIN Input power (50 Ω) 24 dBm 4 12 Vss/GND ESD voltage (Human Body 500 V 5 11 GND C16 1 RF1 2 Data 3 Clock LE 20-lead QFN 4x4mm 6 7 8 9 10 VDD PUP1 PUP2 VDD GND Exposed Solder Pad Table 4. DC Electrical Specifications Parameter VDD Power Supply Voltage Table 2. Pin Descriptions Digital Input High Pin Name 1 C16 Attenuation control bit, 16dB (Note 4). 2 RF1 RF port (Note 1). 3 Data Serial interface data input (Note 4). 4 Clock Serial interface clock input. 5 LE Latch Enable input (Note 2). 6 VDD Power supply pin. 7 PUP1 Power-up selection bit, MSB. 8 PUP2 Power-up selection bit, LSB. 9 VDD 10 GND GND 12 Vss/GND Min Typ Max Units 2.7 3.0 3.3 V 100 µA IDD Power Supply Current Pin No. 11 VESD Description Power supply pin. Ground connection. Ground connection. Negative supply voltage or GND connection(Note 3) 13 P/S Parallel/Serial mode select. 14 RF2 RF port (Note 1). 15 C8 Attenuation control bit, 8 dB. 16 C4 Attenuation control bit, 4 dB. 17 C2 Attenuation control bit, 2 dB. 18 GND 19 C1 Ground connection. 0.7xVDD Digital Input Low Input Leakage V 0.3xVDD V 1 µA Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rate specified in Table 3. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Switching Frequency 20 C0.5 Attenuation control bit, 0.5 dB. The PE4304 has a maximum 25 kHz switching rate. Paddle GND Ground for proper operation Resistor on Pin 1 & 3 Attenuation control bit, 1 dB. Note 1: Both RF ports must be DC blocked with an external series capacitor or held at 0 VDC. 2: Latch Enable (LE) has an internal 100 kΩ resistor to VDD. 3: Connect pin 12 to GND to enable internal negative voltage generator. Connect pin 12 to VSS (-VDD) to bypass and disable internal negative voltage generator. 4. Place a 10 kΩ resistor in series, as close to pin as possible. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 11 A 10 kΩ resistor on the inputs to Pin 1 & 3 (see Figure 5) will eliminate package resonance between the RF input pin and the two digital inputs. Specified attenuation error versus frequency performance is dependent upon this condition. Document No. 70-0066-03 │ UltraCMOS™ RFIC Solutions PE4304 Product Specification Figure 4. Evaluation Board Layout Evaluation Kit The Digital Attenuator Evaluation Kit board was designed to ease customer evaluation of the PE4304 Digital Step Attenuator. Peregrine Specification 101/0112 J9 is used in conjunction with the supplied DC cable to supply VDD, GND, and –VDD. If use of the internal negative voltage generator is desired, then do not connect –VDD (Black banana plug). If an external – VDD is desired, then apply -3V. J1 should be connected to the parallel port of a PC with the supplied ribbon cable. The evaluation software is written to operate the DSA in serial mode, so Switch 7 (P/S) should be ON with all other switches off. Using the software, enable or disable each attenuation setting to the desired combined attenuation. The software automatically programs the DSA each time an attenuation state is enabled or disabled. To evaluate the Power up options, first disconnect the parallel ribbon cable from the evaluation board. The parallel cable must be removed to prevent the PC parallel port from biasing the control pins to unknown states. During power up in serial mode (P/ S=1 and LE=0) or in parallel mode with P/S=0 and LE=1, the default power-up signal attenuation is set to the value present on the six control bits on the six parallel data inputs (C0.5 to C16). This allows any one of the 64 attenuation settings to be specified as the power-up state. To power up in Parallel mode (P/S=0) with LE=0, the control bits are automatically set to one of four possible values. These four values are selected by the two power-up control bits, PUP1 and PUP2, as shown in the Parallel PUP Truth Table (Table 6). Figure 5. Evaluation Board Schematic Peregrine Specification 102/0142 Note: Resistors on pins 1 and 3 are required to avoid package resonance and meet error specifications over frequency. Document No. 70-0066-03 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 11 PE4304 Product Specification Typical Performance Data @ 25°C, VDD = 3.0 V (unless otherwise specified) Figure 6. Insertion Loss Figure 7. Attenuation at Major steps 35 0 31.5dB 30 -1 Attenuation (dB) Insertion Loss (dB) 25 -2 -3 20 16dB 15 0.5dB 10 1dB 2dB 8dB -4 5 -5 4dB 0 0 400 800 1200 1600 0 2000 400 RF Frequency (MHz) 1200 1600 2000 RF Frequency (MHz) Figure 8. Input Return Loss at Major Attenuation Steps Figure 9. Output Return Loss at Major Attenuation Steps 0 0 -5 -5 -10 -10 Return Loss (dB) Input Return Loss (dB) 800 -15 -20 8dB -25 16dB -15 -20 -25 -30 31.5dB -30 -35 -40 -35 0 400 800 1200 1600 RF Frequency (MHz) ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 11 2000 0 400 800 1200 1600 2000 RF Frequency (MHz) Document No. 70-0066-03 │ UltraCMOS™ RFIC Solutions PE4304 Product Specification Typical Performance Data @ 25°C, VDD = 3.0 V (unless otherwise specified) Figure 10. Attenuation Error Vs. Frequency Figure 11. Attenuation Error Vs. Attenuation Setting 1 0.5 0.5 0.25 10MHz 8dB -0.5 16dB -1 31.5dB Attenuation Error (dB) Attenuation Error (dB) 250MHz 0 -1.5 0 510MHz -0.25 750MHz -0.5 1010MHz 1210MHz -0.75 -2 -1 0 400 800 1200 1600 2000 0 5 10 RF Frequency (MHz) 20 25 30 35 40 Attenuation Setting (dB) Figure 12. Attenuation Error Vs. Attenuation Setting Figure 13. Attenuation Error Vs. Attenuation Setting 0.6 0.4 0.4 0.2 10MHz, -40C 10MHz, 25C 0.2 10MHz, 85C 0 Error 510 Mhz Attenuation Error (dB) 15 500MHz, -40C 0 500MHz, 25C -0.2 500MHz, 85C -0.2 -0.4 -0.4 -0.6 0 5 10 15 20 25 Attenuation Setting (dB) Document No. 70-0066-03 │ www.psemi.com 30 35 40 0 5 10 15 20 25 30 35 40 10Mhz error 85 ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 11 PE4304 Product Specification Typical Performance Data @ 25°C, VDD = 3.0 V (unless otherwise specified) Figure 15. Input IP3 Vs. Frequency 0.2 0.2 0 0 -0.2 -0.4 1000MHz, -40C 1000MHz, 25C -0.6 Attenuation Error (dB) Attenuation Error (dB) Figure 14. Attenuation Error Vs. Frequency -0.2 -0.4 1200MHz, -40C -0.6 1000MHz, 85C 1200MHz, 25C -0.8 -0.8 1200MHz, 85C -1 -1 0 5 10 15 20 25 30 35 40 0 5 10 Attenuation Setting (dB) 15 20 25 30 40 Attenuation Setting (dB) Figure 16. Input 1dB Compression Figure 17. Input IP3 Vs. Frequency (Major attenuation states, 50 Ω System) (Major attenuation states, 50 Ω System) 40 60 35 55 30 50 25 45 Input IP3 (dBm) Compression (dB) 35 20 15 40 35 10 30 5 25 0 20 0 400 800 1200 1600 RF Frequency (MHz) ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 11 2000 0 400 800 1200 1600 2000 RF Frequency (MHz) Document No. 70-0066-03 │ UltraCMOS™ RFIC Solutions PE4304 Product Specification Programming Options Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE4304. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. Parallel Mode Interface The parallel interface consists of five CMOScompatible control lines that select the desired attenuation state, as shown in Table 5. The parallel interface timing requirements are defined by Figure 19 (Parallel Interface Timing Diagram), Table 9 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Figure 19) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Table 5. Truth Table P/S C16 C8 C4 C2 C1 Attenuation C0.5 State 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reference Loss 0.5 dB 0 0 0 0 0 1 0 1 dB 0 0 0 0 1 0 0 2 dB 4 dB 0 0 0 1 0 0 0 0 0 1 0 0 0 0 8 dB 0 1 0 0 0 0 0 16 dB 0 1 1 1 1 1 1 31.5 dB Note: Not all 64 possible combinations of C0.5-C16 are shown in table Serial Interface The serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. It is controlled by three CMOS-compatible signals: Data, Document No. 70-0066-03 │ www.psemi.com Clock, and Latch Enable (LE). The Data and Clock inputs allow data to be serially entered into the shift register, a process that is independent of the state of the LE input. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data. The timing for this operation is defined by Figure 18 (Serial Interface Timing Diagram) and Table 8 (AC Characteristics). Power-up Control Settings The PE4304 always assumes a specifiable attenuation setting on power-up. This feature exists for both the Serial and Parallel modes of operation, and allows a known attenuation state to be established before an initial serial or parallel control word is provided. When the attenuator powers up in Serial mode (P/ S=1), the six control bits are set to whatever data is present on the six parallel data inputs (C0.5 to C16). This allows any one of the 64 attenuation settings to be specified as the power-up state. When the attenuator powers up in Parallel mode (P/ S=0) with LE=0, the control bits are automatically set to one of four possible values. These four values are selected by the two power-up control bits, PUP1 and PUP2, as shown in Table 6 (Power-Up Truth Table, Parallel Mode). Table 6. Parallel PUP Truth Table P/S LE PUP2 PUP1 Attenuation State 0 0 0 0 Reference Loss 0 0 1 0 8 dB 0 0 0 1 16 dB 0 0 1 1 31 dB 0 1 X X Defined by C0.5-C16 Note: Power up with LE=1 provides normal parallel operation with C0.5-C16, and PUP1 and PUP2 are not active. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 11 PE4304 Product Specification Figure 18. Serial Interface Timing Diagram Table 7. 6-Bit Attenuator Serial Programming Register Map LE Clock Data MSB tLESUP tSDHLD B4 B3 B2 B1 B0 C8 C4 C2 C1 C0.5 ↑ MSB (first in) LSB tSDSUP B5 C16 ↑ LSB (last in) tLEPW Figure 19. Parallel Interface Timing Diagram LE Parallel Data C16:C0.5 tPDSUP tLEPW tPDHLD Table 8. Serial Interface AC Characteristics Table 9. Parallel Interface AC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter Min Max Unit 10 MHz fClk Serial data clock frequency (Note 1) tClkH Serial clock HIGH time 30 ns tClkL Serial clock LOW time 30 ns tLESUP LE set-up time after last clock falling edge 10 ns tLEPW LE minimum pulse width 30 ns tSDSUP Serial data set-up time before clock rising edge 10 ns tSDHLD Serial data hold time after clock falling edge 10 ns Note: Symbol Parameter Min Max Unit tLEPW LE minimum pulse width 10 ns tPDSUP Data set-up time before rising edge of LE 10 ns tPDHLD Data hold time after falling edge of LE 10 ns fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 11 Document No. 70-0066-03 │ UltraCMOS™ RFIC Solutions PE4304 Product Specification Figure 20. Package Drawing 4.00 INDEX AREA 2.00 X 2.00 2.00 4.00 2.00 -B- 0.25 C 0.80 -A- 0.10 C 0.08 C SEATING PLANE 0.20 REF -C- 2.00 TYP 0.55 2.00 TYP 0.50 0.020 EXPOSED PAD & TERMINAL PADS 1.00 0.435 1.00 10 11 2.00 4.00 0.435 0.18 6 5 0.18 1 15 20 DETAIL A EXPOSED PAD 16 DETAIL A 2 0.23 1 0.10 C A B 1. Dimension applies to metallized terminal and is measured between 0.25 and 0.30 from terminal tip. 2. Coplanarity applies to the exposed heat sink slug as well as the terminals. 3. Dimensions are in millimeters. Document No. 70-0066-03 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 11 PE4304 Product Specification Figure 21. Marking Specifications 4304 YYWW ZZZZZ YYWW = Date Code ZZZZZ = Last five digits of PSC Lot Number Figure 22. Tape and Reel Drawing Table 10. Ordering Information Order Code Part Marking Description Package Shipping Method 4304-01 4304-02 4304-00 4304-51 4304-52 4304 4304 PE4304-EK 4304 4304 PE4304-20MLP 4x4mm-75A PE4304-20MLP 4x4mm-3000C PE4304-20MLP 4x4mm-EK PE4304G-20MLP 4x4mm-75A PE4304G-20MLP 4x4mm-3000C 20-lead 4x4 mm QFN 20-lead 4x4 mm QFN Evaluation Kit Green 20-lead 4x4 mm QFN Green 20-lead 4x4 mm QFN 75 units / Tube 3000 units / T&R 1 / Box 75 units / Tube 3000 units / T&R ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 11 Document No. 70-0066-03 │ UltraCMOS™ RFIC Solutions PE4304 Product Specification Sales Offices The Americas North Asia Pacific Peregrine Semiconductor Corp. Peregrine Semiconductor K.K. 9450 Carroll Park Drive San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Europe Peregrine Semiconductor Europe Commercial Products: Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: +33-1-47-41-91-73 Fax : +33-1-47-41-91-73 Space and Defense Products: 180 Rue Jean de Guiramand 13852 Aix-En-Provence cedex 3, France Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227 South Asia Pacific Peregrine Semiconductor 28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0066-03 │ www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS is a trademark of Peregrine Semiconductor Corp. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 11