BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Product Description Figure 2. Package Type The BVA2140 is a digitally controlled variable gain amplifier (DVGA) in a small 4x4mm QFN package, with a broadband frequency range of 700 to 4000 MHz and an operating VDD of 5.0V at 150mA. The BVA2140 is an integration of a high performance digital 6-step attenuator (DSA) that provides a 31.5 dB attenuation range in 0.5 dB steps, and high linearity broadband gain block amplifiers featuring high ACLR and P1. 24-lead 4x4 mm QFN Device Features The BVA2140 digital control interface supports serial programming of the attenuator, and includes the ability to define the initial attenuation state at power-up. Implementation requires only a few external components, such as DC blocking capacitors on the Input and Output pins, plus a bypass capacitor and a RF choke for the Output port. Small 24-Pin 4 x 4 mm QFN Package Integrate Amp1 to DSA and DSA to Amp2 Functionality Wide Power supply range of +2.7~5.5V(DSA) Single Fixed +5.0V supply(Amp) 700-4000MHz Broadband Performance 30.2dB Gain at 2.14GHz (Matching Circuit) 2.9dB Noise Figure at max gain setting at 2.14GHz(Matching Circuit) 25.1dBm P1dB at 2.14GHz (Matching Circuit) 40dBm OIP3 at 2.14GHz(10dBm per tone, Matching Circuit) 15.2dBm LTE 20MHz ACLR at 1.9GHz (FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. , –50dBc) Attenuation: 0.5 dB steps to 31.5 dB Safe attenuation state transitions Monotonicity: 0.5 dB up to 4 GHz High attenuation accuracy(DSA to Amp) ±(0.3dB + 5% x Atten) @ 0.7~4GHz 1.8V control logic compatible Programming modes - Serial Unique power-up state selection LE PUP1 PUP2 GND DSA_VDD GND Figure 1. Functional Block Diagram 18 17 16 15 14 13 VSS/GND 12 CLOCK 19 P/S 20 DSAIN 21 10 DSAOUT GND 22 9 GND AMP1OUT 23 8 AMP2IN GND 24 BeRex 11 DATA DSA AMP2 Application 1 2 3 4 5 6 GND GND GND AMP2OUT 7 GND GND AMP1 AMP1IN Preliminary Datasheet BVA2140 is high performance and high dynamic range makes it ideally suited for use in WCDMA/LTE wireless infrastructure point-to-point and other demanding wireless applications. ●website: www.berex.com Base station/Repeater Infrastructure LTE/WCDMA/CDMA Wireless infrastructure and other high performance RF application Commercial/Industrial/Military Wireless system General purpose Wireless ●email: [email protected] 1 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Table 1. Electrical Specifications1 Parameter Condition Preliminary Datasheet Operational Frequency Range Min Typ 700 Gain Attenuation = 0dB, at 2140MHz Attenuation Control range 0.5dB step >0.7GHz-4GHz Unit 4000 MHz 30.2 dB dB Attenuation Step Attenuation Accuracy Max Any bit or bit combination 31.5 dB ±(0.3 + 5% of atten setting) dB Input Return Loss Return loss (input or output Attenuation = 0dB Output Return port) Loss 17 dB 13 Output Power for 1dB Compression Attenuation = 0dB , at 2140MHz 25.1 dBm 40 dBm dB Attenuation = 0dB, at 2140MHz Output Third Order Intercept Point Pout= +10dBm/tone △f = 1 MHz. Noise Figure Attenuation = 0dB, at 2140MHz 2.9 Switching time 50% CTRL to 90% or 10% RF 500 DSA 2.7 800 ns 5.5 V Supply voltage AMP Supply Current MCM(AMP1+DSA+AMP2) Control Interface Serial mode 5 V 150 mA 6 Bit Digital input high 1.17 3.6 V Digital input low -0.3 0.6 V Control Voltage Impedance 1 BeRex 50 Ω Device performance _ measured on a BeRex Evaluation board at 25°C, 50 Ω system, VDD=+5.0V, measure on Evaluation Board (AMP1 to DSA and AMP2) ●website: www.berex.com ●email: [email protected] 2 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Table 2. Typical RF Performance1 Parameter Frequency 700 Preliminary Datasheet 5 2650 3500 3700 MHz 31.3 30.2 28.3 24.4 23.5 dB S11 -24.1 -18.9 -19.1 -20.6 -16.5 -18.8 -18.6 dB -8.9 -10.5 -14.7 -18.5 -10.9 -28.2 -23.4 dB 45 45 39 40 37 36.5 37 dBm 2 25.7 25.9 25.4 25.1 25.6 24.1 23.9 dBm 3 14.7 15.1 14.6 14.2 13.9 13.4 13.1 dBm LTE 20M ACLR4 15.4 16 15.5 15.2 15.4 14.8 14.5 dBm N.F 2.6 2.6 2.7 2.9 3.0 3.4 3.5 dB WCDMA ACLR 4 2140 38.6 P1dB 3 1900 41 OIP3 2 900 Unit 3 Gain S22 1 3 Device performance _ measured on a BeRex evaluation board at 25°C, VDD=+5.0V,50 Ω system. measure on Evaluation Board (DSA to AMP) OIP3 _ measured with two tones at an output of +10 dBm per tone separated by 1 MHz. OIP3 _ tuned for max OIP3. WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob, @ACLR –50dBc LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. @ACLR –50dBc Table 3. Absolute Maximum Ratings Parameter Condition Min Typ -0.3 Max Unit 5.5 V 440 mA 3.6 V +12 dBm Supply Voltage(VCC) MCM(AMP1+DSA+AMP2) Supply Current MCM(AMP1+DSA+AMP2) Digital input voltage DSA Maximum input power MCM(AMP1+DSA+AMP2) Operating Case Temperature MCM(AMP1+DSA+AMP2) -40 85 ℃ Storage Temperature MCM(AMP1+DSA+AMP2) -55 150 ℃ Junction Temperature MCM(AMP1+DSA+AMP2) 220 ℃ MTTF at 150℃, MCM(AMP1+DSA+AMP2) -0.3 TBD Hours Operation of this device above any of these parameters may result in permanent damage. Table 4. Recommended Operating Conditions Parameter Condition Min Bandwidth MCM(AMP1+DSA+AMP2) 700 Supply Voltage(VCC) MCM(AMP1+DSA+AMP2) 4.75 Operating Case Temperature MCM(AMP1+DSA+AMP2) -40 RTH MCM(AMP1+DSA+AMP2) BeRex ●website: www.berex.com Typ 5 38.5 Max Unit 4000 MHz 5.25 V 85 ˚C ˚C/W ●email: [email protected] 3 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Programming mode Table 5. PUP Truth Table Preliminary Datasheet Serial Interface The serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. It is controlled by three CMOS-compatible signals: Data, Clock, and Latch Enable (LE). The Data and Clock inputs allow data to be serially entered into the shift register, a process that is independent of the state of the LE input. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. P/S LE PUP2 PUP1 Attenuation state 0 0 0 0 Reference Loss 0 0 1 0 8 dB 0 0 0 1 16 dB 0 0 1 1 31.5 dB 0 1 X X Defined by C0.5-C16 Note: If Power up with LE = 1 or P/S=1, PUP1 and PUP2 are not active Figure 3. Serial Interface Timing Diagram The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data. The timing for this operation is defined by Figure 3 (Serial Interface Timing Diagram) and Table 6 (Serial Interface AC Characteristics). Power-up Control Settings The BVA2140 always assumes a specifiable attenuation setting on power-up. This feature exists for Parallel modes of operation, and allows a known attenuation state to be established before an initial serial or parallel control word is provided. When the attenuator powers up in LE=1 or P/S = 1, PUP1 and PUP2 are not active. But When the attenuator powers up in P/S = 0 with LE = 0, the control bits are automatically set to one of four possible values. These four values are selected by the two power-up control bits, PUP1 and PUP2, as shown in Table 5 (Power-Up Truth Table). Table 6. Serial Interface AC Characteristics VDD = 5.0V with DSA only, -40°C < TA < 105°C, unless otherwise specified Symbol fClk Parameter Min Max Serial data clock frequency 10 Unit MHz tClkH Serial clock HIGH time 30 ns tClkL 30 ns LE set-up time after last tLESUP clock falling edge 10 ns tLEPW LE minimum pulse width 30 ns Serial data set-up time tSDSUP before clock rising edge 10 ns 10 ns tSDHLD Serial clock LOW time Serial data hold time after clock falling edge Note: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification Table 7. 6-Bit Attenuator Serial Programming B5 B4 B3 B3 B1 B0 C16 C8 C4 C2 C1 C0.5 MSB (first in) BeRex ●website: www.berex.com ●email: [email protected] LSB (Last in) 4 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Preliminary Datasheet Figure 4. Pin Configuration(Top View) Table 8. Pin Description Pin Pin name 2,3,4,5,7,9,1 7,18,22,24 GND 1 AMP1IN 6 AMP2OUT 8 AMP2IN 1 Description Ground RF Amp1 in Port RF Amp2 out Port RF Amp in Port 10 RF1 11 DATA RF port(DSA output) Serial interface data input 12 Clock Serial interface clock input 13 LE3 Latch Enable input 14 PUP1 4 Power-up selection bit 1 15 PUP2 Power-up selection bit 2 16 VDD 19 VSS/GND 20 P/S DSA Supply voltage (nominal 5.0V) External VSS negative voltage control or ground Parallel/Serial mode select 21 RF21 RF port(DSA input) 23 AMP1OUT RF Amp1 out Port Note: 1. RF pins 10 and 21 must be at 0V DC. The RF pins do not require DC blocking capacitors for proper Operation if the 0V DC requirement is met 2. Use VssEXT (pin 12) to bypass and disable internal negative voltage generator. Connect VssEXT (pin 12, VssEXT = GND) to enable internal negative voltage generator 3. This pin has an internal 2 MΩ resistor to internal positive digital supply 4. This pin has an internal 200 kΩ resistor to GND BeRex ●website: www.berex.com ●email: [email protected] 5 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(700MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Table 9. Application Circuit : 700MHz Preliminary Datasheet 18 17 16 15 CLOCK 12 20 21 C13 L2 11 DSA 9 23 C11 C10 C9 C14 C12 8 24 7 1 C5 RF_IN C15 10 22 2 3 4 5 C7 C8 6 C4 C3 RF_OUT C6 C16 L1 BOM(700MHz) Size Value NC 0402 22pF 0402 C9 14 13 19 VDD_AMP1 C5 DATA PUP1 Ref C6 LE PUP2 P/S VDD_DSA Schematic Diagram C1 C2 0402 NC L2 0402 22nH C10 0402 22pF C11 0402 1nF C13 0402 22pF C14 0402 0ohm C15 0402 NC C12 0402 10pF C7 0402 9pF C8 0402 3.0nH L1 0402 33nH C1 0402 100pF C2 0402 1uF C4 C3 C16 0402 0402 0402 4.3nH Remark 9.0pF 1.2pF NOTE: BOM’s Information refer to table 23. VDD_AMP2 NOTE 1. R1, R2, R3, R4 is 0ohm(0805) C15 C14 C12 C13 C8 C7 C9 C10 C11 L2 C4 C16 L1 C6 C5 C3 C1 C2 R4 R3 R2 BeRex ●website: www.berex.com R1 ●email: [email protected] 6 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(700MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Preliminary Datasheet Table 10. Typical Performance : 700MHz parameter Frequency Gain S11 S22 S12 OIP31 P1dB Noise Figure LTE20MHz ACLR2 1 2 Typical Values 700 41 -24.1 -8.9 -52.2 45 25.7 2.6 15.4 Figure 5. Gain vs Frequency @Max Gain state Units MHz dB dB dB dB dBm dBm dB dBm OIP3 _ measured with two tones at an output of 10 dBm per tone separated by 1 MHz. LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. @ACLR –50dBc . Figure 6. Input Return Loss vs Frequency @Max Gain & Min Gain state Figure 7. Output Return Loss vs Frequency @Max Gain & Min Gain state Figure 8. Attenuation Error vs Attenuation Setting @700MHz Figure 9. Attenuation Error vs Frequency @Major Attenuation Steps Note: Upper Limit & Lower Limit is the value converted to a graph 0.3dB+0.5% BeRex ●website: www.berex.com ●email: [email protected] 7 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(700MHz Application Circuit) Preliminary Datasheet Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Figure 10. 0.5dB Step Attenuation vs Attenuation Setting @700MHz Figure 11. Noise Figure vs Frequency Figure 12. OIP3 vs Output Power @700MHz Figure 13. Device performance Pin-Pout-Gain @700MHz Figure 14. 3GPP WCDMA ACLR vs Output Power @700MHz, WCDMA 1FA, TM1+64DPCH ±5MHz offset BeRex ●website: www.berex.com ●email: [email protected] 8 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(700MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Preliminary Datasheet Figure 15. ACLR @700MHz, WCDMA4FA1, -50dBc 1 BeRex WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob ●website: www.berex.com Figure 16. ACLR @700MHz, LTE20MHz1, -50dBc 1 LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. ●email: [email protected] 9 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(900MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Table 11. Application Circuit : 900MHz Preliminary Datasheet 18 17 16 15 CLOCK 12 20 21 C13 L2 C11 C10 C9 9 23 8 24 7 1 2 3 C15 10 22 C5 RF_IN 11 DSA 4 5 C14 C12 C7 C8 6 C4 C3 RF_OUT C6 C16 L1 BOM(900MHz) Size Value NC 0402 22pF 0402 C9 14 13 19 VDD_AMP1 C5 DATA PUP1 Ref C6 LE PUP2 P/S VDD_DSA Schematic Diagram C1 C2 0402 NC L2 0402 22nH C10 0402 22pF C11 0402 1nF C13 0402 10pF C14 0402 0ohm C15 0402 NC C12 0402 20pF C7 0402 7.5pF C8 0402 1.0nH L1 0402 27nH C1 0402 100pF C2 0402 1uF C4 C3 C16 0402 0402 0402 2.0nH Remark 100pF 1.8pF NOTE: BOM’s Information refer to table 23. VDD_AMP2 NOTE 1. R1, R2, R3, R4 is 0ohm(0805) C15 C14 C12 C13 C8 C7 C9 C10 C11 L2 C4 C16 L1 C6 C5 C3 C1 C2 R4 R3 R2 BeRex ●website: www.berex.com R1 ●email: [email protected] 10 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(900MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Preliminary Datasheet Table 12. Typical Performance : 900MHz parameter Frequency Gain S11 S22 S12 OIP31 P1dB Noise Figure LTE20MHz ACLR2 1 2 Typical Values 900 38.6 -18.9 -10.5 -52.0 45 25.9 2.6 16 Figure 17. Gain vs Frequency @Max Gain state Units MHz dB dB dB dB dBm dBm dB dBm OIP3 _ measured with two tones at an output of 10 dBm per tone separated by 1 MHz. LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. @ACLR –50dBc . Figure 18. Input Return Loss vs Frequency @Max Gain & Min Gain state Figure 19. Output Return Loss vs Frequency @Max Gain & Min Gain state Figure 20. Attenuation Error vs Attenuation Setting @900MHz Figure 21. Attenuation Error vs Frequency @Major Attenuation Steps Note: Upper Limit & Lower Limit is the value converted to a graph 0.3dB+0.5% BeRex ●website: www.berex.com ●email: [email protected] 11 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(900MHz Application Circuit) Preliminary Datasheet Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Figure 22. 0.5dB Step Attenuation vs Attenuation Setting @900MHz Figure 23. Noise Figure vs Frequency Figure 24. OIP3 vs Output Power @900MHz Figure 25. Device performance Pin-Pout-Gain @900MHz Figure 26. 3GPP WCDMA ACLR vs Output Power @900MHz, WCDMA 1FA, TM1+64DPCH ±5MHz offset BeRex ●website: www.berex.com ●email: [email protected] 12 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(900MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Preliminary Datasheet Figure 27. ACLR @900MHz, WCDMA4FA1, -50dBc 1 BeRex WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob ●website: www.berex.com Figure 28. ACLR @900MHz, LTE20MHz1, -50dBc 1 LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. ●email: [email protected] 13 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(1900MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Table 13. Application Circuit : 1900MHz Preliminary Datasheet 18 17 16 15 CLOCK 14 13 19 12 20 C13 L2 11 DSA 21 VDD_AMP1 C10 22 C9 9 C14 C12 8 24 7 1 C5 RF_IN C15 10 23 C11 DATA PUP1 Ref C6 LE PUP2 P/S VDD_DSA Schematic Diagram 2 3 4 5 C7 C8 6 C4 C3 RF_OUT C6 C16 L1 C1 C2 BOM(1900MHz) Size Value NC 0402 Remark 22pF C5 0402 C9 0402 NC L2 0402 22nH C10 0402 22pF C11 0402 1nF C13 0402 22pF C14 0402 0ohm C15 0402 NC C12 0402 1.2pF C7 0402 1.3pF C8 0402 1.0nH L1 0402 15nH C1 0402 62pF C2 0402 1uF C4 C3 C16 0402 0402 0402 1.5nH 22pF 1.0pF NOTE: BOM’s Information refer to table 23. VDD_AMP2 NOTE 1. R1, R2, R3, R4 is 0ohm(0805) C15 C14 C12 C13 C8 C7 C9 C10 C11 L2 C4 C16 L1 C6 C5 C3 C1 C2 R4 R3 R2 BeRex ●website: www.berex.com R1 ●email: [email protected] 14 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(1900MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Preliminary Datasheet Table 14. Typical Performance : 1900MHz parameter Frequency Gain S11 S22 S12 OIP31 P1dB Noise Figure LTE20MHz ACLR2 1 2 Typical Values 1900 31.3 -19.1 -14.7 -48.8 39 25.4 2.7 15.5 Figure 29. Gain vs Frequency @Max Gain state Units MHz dB dB dB dB dBm dBm dB dBm OIP3 _ measured with two tones at an output of 10 dBm per tone separated by 1 MHz. LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. @ACLR –50dBc . Figure 30. Input Return Loss vs Frequency @Max Gain & Min Gain state Figure 31. Output Return Loss vs Frequency @Max Gain & Min Gain state Figure 32. Attenuation Error vs Attenuation Setting @1900MHz Figure 33. Attenuation Error vs Frequency @Major Attenuation Steps Note: Upper Limit & Lower Limit is the value converted to a graph 0.3dB+0.5% BeRex ●website: www.berex.com ●email: [email protected] 15 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(1900MHz Application Circuit) Preliminary Datasheet Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Figure 34. 0.5dB Step Attenuation vs Attenuation Setting @1900MHz Figure 35. Noise Figure vs Frequency Figure 36. OIP3 vs Output Power @1900MHz Figure 37. Device performance Pin-Pout-Gain @1900MHz Figure 38. 3GPP WCDMA ACLR vs Output Power @1900MHz, WCDMA 1FA , TM1+64DPCH ±5MHz offset BeRex ●website: www.berex.com ●email: [email protected] 16 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(1900MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Preliminary Datasheet Figure 39. ACLR @1900MHz, WCDMA4FA1, -50dBc 1 BeRex WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob ●website: www.berex.com Figure 40. ACLR @1900MHz, LTE20MHz1, -50dBc 1 LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. ●email: [email protected] 17 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(2140MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Table 15. Application Circuit : 2140MHz Preliminary Datasheet 18 17 16 15 CLOCK 14 13 19 12 20 C13 L2 11 DSA 21 VDD_AMP1 C10 22 C9 9 C14 C12 8 24 7 1 C5 RF_IN C15 10 23 C11 DATA PUP1 Ref C6 LE PUP2 P/S VDD_DSA Schematic Diagram 2 3 4 5 C7 C8 6 C4 C3 RF_OUT C6 C16 L1 C1 C2 BOM(2140MHz) Size Value NC 0402 Remark 22pF C5 0402 C9 0402 NC L2 0402 22nH C10 0402 22pF C11 0402 1nF C13 0402 22pF C14 0402 0ohm C15 0402 NC C12 0402 0.75pF C7 0402 0.5pF C8 0402 1.0nH L1 0402 5.1nH C1 0402 62pF C2 0402 1uF C4 C3 C16 0402 0402 0402 0ohm 22pF 0.5pF NOTE: BOM’s Information refer to table 23. VDD_AMP2 NOTE 1. R1, R2, R3, R4 is 0ohm(0805) C15 C14 C12 C13 C8 C7 C9 C10 C11 L2 C4 C16 L1 C6 C5 C3 C1 C2 R4 R3 R2 BeRex ●website: www.berex.com R1 ●email: [email protected] 18 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(2140MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Preliminary Datasheet Table 16. Typical Performance : 2140MHz parameter Frequency Gain S11 S22 S12 OIP31 P1dB Noise Figure LTE20MHz ACLR2 1 2 Typical Values 2140 30.2 -20.6 -18.5 -49.5 40 25.1 2.9 15.2 Figure 41. Gain vs Frequency @Max Gain state Units MHz dB dB dB dB dBm dBm dB dBm OIP3 _ measured with two tones at an output of 10 dBm per tone separated by 1 MHz. LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. @ACLR –50dBc . Figure 42. Input Return Loss vs Frequency @Max Gain & Min Gain state Figure 43. Output Return Loss vs Frequency @Max Gain & Min Gain state Figure 44. Attenuation Error vs Attenuation Setting @2140MHz Figure 45. Attenuation Error vs Frequency @Major Attenuation Steps Note: Upper Limit & Lower Limit is the value converted to a graph 0.3dB+0.5% BeRex ●website: www.berex.com ●email: [email protected] 19 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(2140MHz Application Circuit) Preliminary Datasheet Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Figure 46. 0.5dB Step Attenuation vs Attenuation Setting @2140MHz Figure 47. Noise Figure vs Frequency Figure 48. OIP3 vs Output Power @2140MHz Figure 49. Device performance Pin-Pout-Gain @2140MHz Figure 50. 3GPP WCDMA ACLR vs Output Power @2140MHz, WCDMA 1FA, TM1+64DPCH ±5MHz offset BeRex ●website: www.berex.com ●email: [email protected] 20 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(2140MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Preliminary Datasheet Figure 51. ACLR @2140MHz, WCDMA4FA1, -50dBc 1 BeRex WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob ●website: www.berex.com Figure 52. ACLR @2140MHz, LTE20MHz1, -50dBc 1 LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. ●email: [email protected] 21 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(2650MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Table 17. Application Circuit : 2650MHz Preliminary Datasheet 18 17 16 15 CLOCK 14 13 19 12 20 C13 L2 11 DSA 21 VDD_AMP1 C10 22 C9 9 C14 C12 8 24 7 1 C5 RF_IN C15 10 23 C11 DATA PUP1 Ref C6 LE PUP2 P/S VDD_DSA Schematic Diagram 2 3 4 5 C7 C8 6 C4 C3 RF_OUT C6 C16 L1 C1 C2 BOM(2650MHz) Size Value NC 0402 Remark 22pF C5 0402 C9 0402 NC L2 0402 22nH C10 0402 22pF C11 0402 1nF C13 0402 22pF C14 0402 0ohm C15 0402 NC C12 0402 0.75pF C7 0402 0.75pF C8 0402 0ohm L1 0402 4.3nH C1 0402 22pF C2 0402 1uF C4 C3 C16 0402 0402 0402 0ohm 22pF 1.0pF NOTE: BOM’s Information refer to table 23. VDD_AMP2 NOTE 1. R1, R2, R3, R4 is 0ohm(0805) C15 C14 C12 C13 C8 C7 C9 C10 C11 L2 C4 C16 L1 C6 C5 C3 C1 C2 R4 R3 R2 BeRex ●website: www.berex.com R1 ●email: [email protected] 22 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(2650MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Preliminary Datasheet Table 53. Typical Performance : 2650MHz parameter Frequency Gain S11 S22 S12 OIP31 P1dB Noise Figure LTE20MHz ACLR2 1 2 Typical Values 2650 28.3 -16.5 -10.9 -47.3 37 25.6 3.0 15.4 Figure 54. Gain vs Frequency @Max Gain state Units MHz dB dB dB dB dBm dBm dB dBm OIP3 _ measured with two tones at an output of 10 dBm per tone separated by 1 MHz. LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. @ACLR –50dBc . Figure 55. Input Return Loss vs Frequency @Max Gain & Min Gain state Figure 56. Output Return Loss vs Frequency @Max Gain & Min Gain state Figure 57. Attenuation Error vs Attenuation Setting @2650MHz Figure 58. Attenuation Error vs Frequency @Major Attenuation Steps Note: Upper Limit & Lower Limit is the value converted to a graph 0.3dB+0.5% BeRex ●website: www.berex.com ●email: [email protected] 23 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(2650MHz Application Circuit) Preliminary Datasheet Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Figure 59. 0.5dB Step Attenuation vs Attenuation Setting @2650MHz Figure 60. Noise Figure vs Frequency Figure 61. OIP3 vs Output Power @2650MHz Figure 62. Device performance Pin-Pout-Gain @2650MHz Figure 63. 3GPP WCDMA ACLR vs Output Power @2650MHz, WCDMA 1FA , TM1+64DPCH ±5MHz offset BeRex ●website: www.berex.com ●email: [email protected] 24 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(2650MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Preliminary Datasheet Figure 64. ACLR @2650MHz, WCDMA4FA1, -50dBc 1 BeRex WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob ●website: www.berex.com Figure 65. ACLR @2650MHz, LTE20MHz1, -50dBc 1 LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. ●email: [email protected] 25 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(3500MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Table 19. Application Circuit : 3500MHz Preliminary Datasheet 18 17 16 15 CLOCK 14 13 19 12 20 C13 L2 11 DSA 21 VDD_AMP1 C10 22 C9 9 C14 C12 8 24 7 1 C5 RF_IN C15 10 23 C11 DATA PUP1 Ref C6 LE PUP2 P/S VDD_DSA Schematic Diagram 2 3 4 5 C7 C8 6 C4 C3 RF_OUT C6 C16 L1 C1 C2 BOM(3500MHz) Size Value NC 0402 Remark 22pF C5 0402 C9 0402 NC L2 0402 15nH C10 0402 22pF C11 0402 1nF C13 0402 22pF C14 0402 0ohm C15 0402 NC C12 0402 0ohm C7 0402 1pF C8 0402 2pF L1 0402 10nH C1 0402 22pF C2 0402 1uF C4 C3 C16 0402 0402 0402 Copper 22pF 0.75pF NOTE: BOM’s Information refer to table 23. VDD_AMP2 C15 NOTE 1. R1, R2, R3, R4 is 0ohm(0805) 2. C4 place piece of trace to cover the gap 3. C16 moves to the left 19.7mil(0.5mm) (refer to the left figure) C14 C12 C13 C8 C7 C9 C10 C11 L2 C4 C16 L1 C6 C5 C3 C1 C2 R4 R3 R2 BeRex ●website: www.berex.com R1 ●email: [email protected] 26 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(3500MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Preliminary Datasheet Table 20. Typical Performance : 3500MHz parameter Frequency Gain S11 S22 S12 OIP31 P1dB Noise Figure LTE20MHz ACLR2 1 2 Typical Values 3500 24.4 -18.8 -28.2 -37.9 36.5 24.1 3.4 14.8 Figure 66. Gain vs Frequency @Max Gain state Units MHz dB dB dB dB dBm dBm dB dBm OIP3 _ measured with two tones at an output of 10 dBm per tone separated by 1 MHz. LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. @ACLR –50dBc . Figure 67. Input Return Loss vs Frequency @Max Gain & Min Gain state Figure 68. Output Return Loss vs Frequency @Max Gain & Min Gain state Figure 69. Attenuation Error vs Attenuation Setting @3500MHz Figure 70. Attenuation Error vs Frequency @Major Attenuation Steps Note: Upper Limit & Lower Limit is the value converted to a graph 0.3dB+0.5% BeRex ●website: www.berex.com ●email: [email protected] 27 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(3500MHz Application Circuit) Preliminary Datasheet Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Figure 71. 0.5dB Step Attenuation vs Attenuation Setting @3500MHz Figure 72. Noise Figure vs Frequency Figure 73. OIP3 vs Output Power @3500MHz Figure 74. Device performance Pin-Pout-Gain @3500MHz Figure 75. 3GPP WCDMA ACLR vs Output Power @3500MHz, WCDMA 1FA , TM1+64DPCH ±5MHz offset BeRex ●website: www.berex.com ●email: [email protected] 28 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(3500MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Preliminary Datasheet Figure 76. ACLR @3500MHz, WCDMA4FA1, -50dBc 1 BeRex WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob ●website: www.berex.com Figure 77. ACLR @3500MHz, LTE20MHz1, -50dBc 1 LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. ●email: [email protected] 29 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(3700MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Table 21. Application Circuit : 3700MHz Preliminary Datasheet 18 17 16 15 CLOCK 14 13 19 12 20 C13 L2 C11 C10 C9 9 23 8 24 7 1 2 3 C15 10 22 C5 RF_IN 11 DSA 21 VDD_AMP1 DATA PUP1 Ref C6 LE PUP2 P/S VDD_DSA Schematic Diagram 4 5 C14 C12 C7 C8 6 C4 C3 RF_OUT C6 C16 L1 C1 C2 BOM(3700MHz) Size Value NC 0402 Remark 22pF C5 0402 C9 0402 NC L2 0402 15nH C10 0402 22pF C11 0402 1nF C13 0402 22pF C14 0402 0ohm C15 0402 NC C12 0402 0ohm C7 0402 0.75pF C8 0402 1.8pF L1 0402 10nH C1 0402 22pF C2 0402 1uF C4 C3 C16 0402 0402 0402 Copper 22pF 0.75pF NOTE: BOM’s Information refer to table 23. VDD_AMP2 C15 NOTE 1. R1, R2, R3, R4 is 0ohm(0805) 2. C4 place piece of trace to cover the gap 3. C16 moves to the left 19.7mil(0.5mm) (refer to the left figure) C14 C12 C13 C8 C7 C9 C10 C11 L2 C4 C16 L1 C6 C5 C3 C1 C2 R4 R3 R2 BeRex ●website: www.berex.com R1 ●email: [email protected] 30 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(3700MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Preliminary Datasheet Table 22. Typical Performance : 3700MHz parameter Frequency Gain S11 S22 S12 OIP31 P1dB Noise Figure LTE20MHz ACLR2 1 2 Typical Values 3700 23.5 -18.6 -23.4 -37.1 37 23.9 3.5 14.5 Figure 78. Gain vs Frequency @Max Gain state Units MHz dB dB dB dB dBm dBm dB dBm OIP3 _ measured with two tones at an output of 10 dBm per tone separated by 1 MHz. LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. @ACLR –50dBc . Figure 79. Input Return Loss vs Frequency @Max Gain & Min Gain state Figure 80. Output Return Loss vs Frequency @Max Gain & Min Gain state Figure 81. Attenuation Error vs Attenuation Setting @3700MHz Figure 82. Attenuation Error vs Frequency @Major Attenuation Steps Note: Upper Limit & Lower Limit is the value converted to a graph 0.3dB+0.5% BeRex ●website: www.berex.com ●email: [email protected] 31 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(3700MHz Application Circuit) Preliminary Datasheet Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Figure 83. 0.5dB Step Attenuation vs Attenuation Setting @3700MHz Figure 84. Noise Figure vs Frequency Figure 85. OIP3 vs Output Power @3700MHz Figure 86. Device performance Pin-Pout-Gain @3700MHz Figure 87. 3GPP WCDMA ACLR vs Output Power @3700MHz, WCDMA 1FA , TM1+64DPCH ±5MHz offset BeRex ●website: www.berex.com ●email: [email protected] 32 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Typical RF Performance Plot - BVA2140 EVK - PCB(3700MHz Application Circuit) Typical Performance Data @ 25°and VDD = 5.0V unless otherwise noted and RF Circuit Preliminary Datasheet Figure 88. ACLR @3700MHz, WCDMA4FA1, -50dBc 1 BeRex WCDMA set-up: 3GPP WCDMA, TM1+64DPCH, +5MHz offset, PAR 10.11 at 0.01% Prob ●website: www.berex.com Figure 89. ACLR @3700MHz, LTE20MHz1, -50dBc 1 LTE set-up: 3GPP LTE, FDD E-TM1.1, 20MHz BW, ±20MHz offset, PAR 9.81 at 0.01% Prob. ●email: [email protected] 33 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Preliminary Datasheet Figure 90. Evaluation Board PCB Layer Information Table 23. Bill of material Information No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BeRex Value 1.0nF 1.2nH 1.5nH 2.0nH 3.0nH 4.3nH 4.7nH 5.1nH 10nH 15nH 22nH 27nH 33nH 0.5pF 0.75pF 1.0pF 1.2pF 1.3pF 1.5pF 1.8pF 2.0pF 7.5pF 9pF 10pF 20pF 22pF 62pF 100pF 1nF 1uF 0ohm Description IND, 0402, CHIP, 5% IND, 0402, CHIP, 5% IND, 0402, CHIP, 5% IND, 0402, CHIP, 5% IND, 0402, CHIP, 5% IND, 0402, CHIP, 5% IND, 0402, CHIP, 5% IND, 0402, CHIP, 5% IND, 0402, CHIP, 5% IND, 0402, CHIP, 5% IND, 0402, CHIP, 5% IND, 0402, CHIP, 5% IND, 0402, CHIP, ±5% CAP, 0402, CHIP Ceramic, ±0.25% CAP, 0402, CHIP Ceramic, ±0.25% CAP, 0402, CHIP Ceramic, ±0.25% CAP, 0402, CHIP Ceramic, ±0.25% CAP, 0402, CHIP Ceramic, ±0.25% CAP, 0402, CHIP Ceramic, ±0.25% CAP, 0402, CHIP Ceramic, ±0.25% CAP, 0402, CHIP Ceramic, ±0.25% CAP, 0402, CHIP Ceramic, ±0.25% CAP, 0402, CHIP Ceramic, ±0.25% CAP, 0402, CHIP Ceramic, ±0.25% CAP, 0402, CHIP Ceramic, ±0.25% CAP, 0402, CHIP Ceramic, ±0.25% CAP, 0402, CHIP Ceramic, ±0.25% CAP, 0402, CHIP Ceramic, ±0.25% CAP, 0402, CHIP Ceramic, ±0.25% CAP, 0402, (105Z 10V) RES, 0402, CHIP, ±5% ●website: www.berex.com Manuf. murata murata murata murata murata murata murata murata murata murata murata murata murata samsung samsung samsung samsung samsung samsung samsung samsung WALSIN tech samsung samsung samsung samsung samsung samsung samsung WALSIN tech samsung Part Number LQG15HS1N0S02D LQG15HS1N2S02D LQG15HS1N5S02D LQG15HS2N0S02D LQG15HS3N0S02D LQG15HS4N3S02D LQG15HS4N7S02D LQG15HS5N1S02D LQG15HS10NJ02D LQG15HS15NJ02D LQG15HS22NJ02D LQG15HS27NJ02D LQG15HS33NJ02D CL05C0R5CB5NNNC CL05CR75CB5NNNC CL05C1R0CB5NNNC CL05C1R2CB5NNNC CL05C1R3CB5NNNC CL05C1R5CB5NNNC CL05C1R8CB5NNNC CL05C020CB5NNNC 0402N7RD500CT CL05C090CB5NNNC CL05C100CB5NNNC CL05C200CB5NNNC CL05C220CB5NNNC CL05C620CB5NNNC CL05C101CB5NNNC CL05C102CB5NNNC 0402F105Z100CT RC1005J000CS ●email: [email protected] 34 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Preliminary Datasheet Figure 91. Packing outline Dimension Figure 92. Package Marking BVA2140 YYWWXX YY = Year, WW = Working Week, XX = Wafer No. BeRex ●website: www.berex.com ●email: [email protected] 35 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Preliminary Datasheet Figure 93. Suggested PCB Land Pattern and PAD Layout BeRex ●website: www.berex.com ●email: [email protected] 36 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1 BVA2140 0.7- 4GHz 1/4W Medium Power DIGITAL VARIABLE GAIN AMPLIFIER Preliminary Datasheet Figure 94. Tape & Reel Packaging information: Tape Width (mm): 12 / Reel Size (inches): TBD Device Cavity Pitch (mm): 8 / Devices Per Reel: TBD Lead plating finish 100% Tin Matte finish (All BeRex products undergoes a 1 hour, 150 degree C, Anneal bake to eliminate thin whisker growth concerns.) MSL / ESD Rating ESD Rating: Class 1C Value: Passes<2000V Test: Human Body Model(HBM) Standard: JEDEC Standard JESD22-A114B MSL Rating: Level 1 at +265°C convection reflow Standard: JEDEC Standard J-STD-020 NATO CAGE code: 2 BeRex N 9 6 F ●website: www.berex.com ●email: [email protected] 37 Specifications and information are subject to change and products may be discontinued without notice. BeRex is a trademark of BeRex. All other trademarks are the property of their respective owners. © 2016 BeRex Rev. 0.1