USER GUIDE ATWINC1500 HW Design Guidelines - IEEE 802.11 b/g/n IoT Module Atmel SmartConnect This document details the hardware design guidelines for a customer to design the ATWINC1500 IC onto their board. VDDIO VBAT Load Switch VDDIO Antenna Chip_En Reset_n Wake SPI IRQn ATWINC1500 802.11 B/G/N SOC Balun UART 26 MHz GPIO_15,16,18 Block Diagram Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 Reference Schematic Schematic Figure 1-1 shows the reference schematic for a system using the ATWINC1500. Note that there are several 0Ω resistors (R1 – R10) shown in series with signals to the module. These are place holders in case filtering of these lines is necessary due to high frequency in band (2.4GHz) noise is on these lines, which can get into the RF path and degrade receiver sensitivity. If the signals coming from the host MCU are noise free, then these placeholders are not required and can be removed. Figure 1-1. Reference Schematic Notes on Interfacing to the ATWINC1500 Programmable Pullup Resistors The ATWINC1500 provides programmable pullup resistors on various pins. The purpose of these resistors is to keep any unused input pins from floating which can cause excess current to flow through the input buffer from the VDDIO supply. Any unused module pin on the ATWINC1500 should leave these pullup resistors enabled so the pin will not float. The default state at power up is for the pullup resistor to be enabled. However, any pin which is used should have the pullup resistor disabled. The reason for this is that if any pins are driven to a low level while the ATWINC1500 is in the low-power sleep state, current will flow from the VDDIO supply through the pullup resistors, increasing the current consumption of the module. Since the value of the pullup resistor is approximately 100KΩ, the current through any pullup resistor that is being driven low will be VDDIO/100K. For VDDIO = 3.3V, the current through each pullup resistor that is driven low would be approximately 3.3V/100K = 33µA. Pins which 2 ATWINC1500 Hardware Design Guide – IEEE 802.11 b/g/n IoT Module [USER GUIDE] 2 Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 are used and have had the programmable pullup resistor disabled should always be actively driven to either a high or low level and not be allowed to float. See the ATWINC1500 Programming Guide for information on enabling/disabling the programmable pull up resistors. VDDIO Load Switch The ATWINC1500 should be designed with a load switch in series with the VDDIO supply. This load switch is shown as U3 in the reference schematic. The reason for using this load switch is that the GPIO pins, which control the FLASH inside the ATWINC1500 package will float when the ATWINC1500 is powered down by setting Chip_En low. These floating control inputs to the FLASH will cause it to consume a large amount of current from the VDDIO supply. The load switch is controlled by the Chip_En pin of the module (Module pin 22). When Chip_En is high, the load switch is turned on. When Chip_En is low the load switch is open and VDDIO is disconnected from the ATWINC1500. When the VDDIO supply to the ATWINC1500 is disconnected it is important that none of the pins to the ATWINC1500 is in a high state. Figure 1-2 shows the ESD structure of the pins of the ATWINC1500 and Figure 1-3 shows the current path through the ESD diode from a pin that is being driven high to the VDDIO supply of the device. In effect, if VDDIO is disconnected from the external power supply and a high level is driven on to a pad of the device, the device will be powered up through the pad. Figure 1-2. ATWINC1500 Pad ESD Structure This shows why it is important that any time Chip_En to the module is low, all pins interfacing to the module must not be driven or pulled high. They should either be set to a low level or high impedance state. This means that if any external pullup resistors are attached to any pins they should be disconnected from the supply when Chip_En is low. ATWINC1500 Hardware Design Guide – IEEE 802.11 b/g/n IoT Module [USER GUIDE] Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 3 3 Figure 1-3. Current Path through ESD Diode Restrictions for Power States When no power is supplied to the device, i.e., the DC/DC Converter output and VDDIO are both off (at ground potential). In this case, a voltage cannot be applied to the device pins because each pin contains an ESD diode from the pin to supply. This diode will turn on when voltage higher than one diode-drop is supplied to the pin. If a voltage must be applied to the signal pads while the chip is in a low-power state, the VDDIO supply must be on, so the SLEEP or Power_Down state must be used. Similarly, to prevent the pin-to-ground diode from turning on, do not apply a voltage that is more than one diode-drop below ground to any pin. Power-up/-down Sequence The power-up/-down sequence for ATWINC1500A is shown in Figure 1-4. The timing parameters are provided in Table 1-1. Figure 1-4. Power-up/-down Sequence VBATT tA t A' VDDIO tB t B' CHIP_EN tC t C' RESETN XO Clock 4 ATWINC1500 Hardware Design Guide – IEEE 802.11 b/g/n IoT Module [USER GUIDE] 4 Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 Table 1-1. Parameter Power-up/-down Sequence Timing Min. Max. Unit Description Notes tA 0 VBATT rise to VDDIO rise VBATT and VDDIO can rise simultaneously or can be tied together. VDDIO must not rise before VBATT. tB 0 VDDIO rise to CHIP_EN rise CHIP_EN must not rise before VDDIO. CHIP_EN must be driven high or low, not left floating. 5 CHIP_EN rise to RESETN rise This delay is needed because XO clock must stabilize before RESETN removal. RESETN must be driven high or low, not left floating. tC ms tA’ 0 VDDIO fall to VBATT fall VBATT and VDDIO can fall simultaneously or can be tied together. VBATT must not fall before VDDIO. tB’ 0 CHIP_EN fall to VDDIO fall VDDIO must not fall before CHIP_EN. CHIP_EN and RESETN can fall simultaneously. tC’ 0 RESETN fall to VDDIO fall VDDIO must not fall before RESETN. RESETN and CHIP_EN can fall simultaneously. Digital I/O Pin Behavior during Power-Up Sequences Table 1-2 represents digital I/O pin states corresponding to device power modes. Table 1-2. Digital I/O Pin Behavior in Different Device States Pullup/down Resistor (96kΩ) VDDIO CHIP_EN RESETN Output Driver Input Driver Power Down: core supply off High Low Low Disabled (Hi-Z) Disabled Disabled Power-On Reset: core supply on, hard reset on High High Low Disabled (Hi-Z) Disabled Enabled Power-On Default: core supply on, device out of reset but not programmed yet High High High Disabled (Hi-Z) Enabled Enabled On Sleep/On Transmit/On Receive: core supply on, device programmed by firmware High High High Programmed by firmware for each pin: Enabled or Disabled Opposite of Output Driver state Programmed by firmware for each pin: Enabled or Disabled Device State ATWINC1500 Hardware Design Guide – IEEE 802.11 b/g/n IoT Module [USER GUIDE] Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 5 5 Placement and Routing Guidelines It is critical to follow the recommendations listed below to achieve the best RF performance: The board should have a solid ground plane. The center ground pad of the device must be solidly connected to the ground plane by using a 3 x 3 grid of vias. Keep away from antenna, as far as possible, large metal objects to avoid electromagnetic field blocking Do not enclose the antenna within a metal shield Keep any components which may radiate noise or signals within the 2.4 – 2.5GHz frequency band far away from the antenna or better yet, shield those components. Any noise radiated from the main board in this frequency band will degrade the sensitivity of the module. Power and Ground Dedicate one layer as a ground plane. Make sure that this ground plane does not get broken up by routes. Power can route on all layers except the ground layer. Power supply routes should be heavy copper fill planes to insure the lowest possible inductance. The power pins of the NMC1000 should have a via directly to the power plane as close to the pin as possible. Decoupling capacitors should have a via right next to the capacitor pin and this via should go directly down to the power plane – that is to say, the capacitor should not route to the power plane through a long trace. The ground side of the decoupling capacitor should have a via right next to the pad which goes directly down to the ground plane. Each decoupling capacitor should have its own via directly to the ground plane and directly to the power plane right next to the pad. The decoupling capacitors should be placed as close to the pin that it is filtering as possible. RF Traces and Components The RF traces that go from the ATWINC1500 tuner to the balun must be 50Ω differential controlled impedance. These are pins 7 and 8 of the ATWINC1500. The route from the balun to the antenna connector must be a 50Ω controlled impedance trace. These controlled impedance traces must reference a ground plane on a lower layer. To achieve 50Ω impedance, a typical design might be 20 mil traces referenced to a ground plane on an inner layer which is 10.7 mils below the traces. This must be adjusted depending on the dielectric and copper weight used. No other traces must route through the RF area on layers between the RF traces and the ground reference plane. In fact, try not to route any other traces in the RF area on any layer. This ground reference plane must extend entirely under the tuner. Be sure to add as many ground vias as possible, tying all ground layers together (ground stitching) all along the RF traces and throughout the area where the RF traces are routed. Add at least two ground vias for every ground pad around the RF components. Place ground vias all along the RF traces on either side. Tie the center ground pad of the ATWINC1500 to the inner ground layer using a grid of nine vias. The ground path going from the ground pad down to the ground plane must be absolutely as low impedance as possible. Do not use thermal relief pads for the ground pads of all components in the RF path. These component pads must be completely filled in with ground copper. Be sure to place the matching components and balun as close to the RFIOP and RFION pins as possible (these C33, C23, C24, C17, C32, L8, and L9 in the reference schematic). Figure 1-5 shows the placement and routing of these components. Note that they are placed as close as possible to the ATWINC1500’s pins 7 and 8. The components used for this design are 0201. Note that the width of the 6 ATWINC1500 Hardware Design Guide – IEEE 802.11 b/g/n IoT Module [USER GUIDE] 6 Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 route matches the width of the component pads. This will avoid impedance discontinuities which would occur if there is a large mismatch in trace width versus the component pad size. Figure 1-5. Placement and Routing of Balun and Matching Components Be sure that the route from the antenna to the ATWINC1500 is as short as possible and is completely isolated from all other signals on the board. No signals should route under this trace on any layer of the board. Make sure that all digital signals that may be toggling while the ATWINC1500 active are placed as far away from the antenna as possible. No connectors, which have digital signals going to them should be near the antenna. All digital components and switching regulators on the board should be shielded so they do not radiate noise that is picked up by the antenna. In summary, make sure anything that switches is shielded and kept away from the antenna, the ATWINC1500 or the route from the ATWINC1500 to the antenna. Sensitive Routes Signals The following signals are very sensitive to noise and you must take care to keep them as short as possible and keep them isolated from all other signals by routing them far away from other traces or using ground to shield them. Be sure that they are also isolated from noisy traces on the layers above and below them: XO_N XO_P RFIOP RFION ATWINC1500 Hardware Design Guide – IEEE 802.11 b/g/n IoT Module [USER GUIDE] Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 7 7 Supplies The following power supply pins for the ATWINC1500 are sensitive to noise and care should be taken to isolate the routes to these pins from other noisy signals both on the same layer as the route and on layers above and below. Use ground between these sensitive signals to isolate them from other signals. It is important that the decoupling capacitors for these supplies are placed as close to the ATWINC1500 pin as possible. This is necessary to reduce the trace inductance between the capacitor and ATWINC1500 power pin to an absolute minimum: VDDRF_RX (pin 2) VDDRF_TX (pin 4) VDD_AMS (pin 3) VDD_SXDIG (pin 37) VDD_VCO (pin 38) Additionally, while the VDDC (pins 14 and 27) and VBAT_BUCK (pin 20) supplies are not sensitive to picking up noise, they are noise generating supplies. Therefore, be sure to keep the decoupling capacitors for these supply pins as close as possible to the VDDC and VBAT_BUCK pins and make sure that the routes for these supplies stay far away from sensitive pins and supplies. Additional Suggestions Make sure that traces route directly through the pads of all filter capacitors and not by way of a stub route. The following routes are extremely critical and should be routed first. C) is a power route and should be a heavy copper route. These routes must not have anything above, below, or to the side of them except ground. They must be as short as possible. Make sure that the filter capacitor for these pins is placed right next to the pin. A. The 50Ω differential pair from NMC1000 pins 7 and 8 to the balun. Be sure that this route is as short as possible and that both routes of the differential pair are matched in length. B. The 50Ω unbalanced route from the balun to the antenna. C. The routes to the XO_P and XO_N pins (pins 35 and 36). These must be isolated with ground above, below, and to the sides of the routes. D. The route from ATWINC1500 pin 21 (VSW) to the 15nH inductor (L5) must be as short and wide as possible. Make sure this inductor is placed right next to pin 21. The route from the other side of this inductor to the 1.0µH inductor (L1) must also be as short and heavy as possible. Then the route from L1 to the 2.2µF capacitor (C10) and to pin 22 must also be as short and heavy as possible. E. The loop created from ATWINC1500 pin 21 through the inductors the capacitor and back to pin 22 must be as small as possible. F. Make sure the ground return path from the 2.2µH capacitor connected to pin 22 back to the ground pad of the ATWINC1500 is as short and wide as possible. This is critical. The ground return path must have extremely low inductance. Failure to provide a short, heavy ground return between the capacitor and the ATWINC1500 ground pad will result in incorrect operation of the on chip switching regulator. Be sure to place the power supply decoupling capacitors so that there is a capacitor very close to each power supply pin of the device. This requires making the copper as short and wide as possible – use copper fills for the power supply routing from the pins to the filter capacitors, not narrow traces. 8 ATWINC1500 Hardware Design Guide – IEEE 802.11 b/g/n IoT Module [USER GUIDE] 8 Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 Interferers One of the biggest problems with RF receivers is poor performance due to interferers on the board radiating noise into the antenna or coupling into the RF traces going to input LNA. Care must be taken to make sure that there is no noisy circuitry placed anywhere near the antenna or the RF traces. All noise generating circuits should also be shielded so they do not radiate noise that is picked up by the antenna. Also, make sure that no traces route underneath the RF portion of the ATWINC1500. Also, make sure that no traces route underneath any of the RF traces from the antenna to the ATWINC1500 input. This applies to all layers. Even if there is a ground plane on a layer between the RF route and another signal, the ground return current will flow on the ground plane and couple into the RF traces. Thermal Considerations Table 1-3 lists the thermal resistance from junction to ambient (JA) and from junction to case (JC) for 5x5 40L QFN. Table 1-3. Thermal Resistance JA Package 5x5mm 40L QFN JC 29.5ºC/W 3.7ºC/W Junction-to-ambient thermal resistance JA is a one-dimensional value that measures the conduction of heat from the junction (hottest temperature on die) to the environment near the package. The heat that is generated on the die surface reaches the immediate environment along two paths: (1) convection and radiation off the exposed surface of the package and (2) conduction into and through the test board followed by convection and radiation off the exposed board surfaces. JA reported here assumes the package is mounted on a board with two signal layers and two internal planes (2s2p). External Interfaces General Digital Pad Characteristics (1) Table 1-4. Symbol Characteristics Min. Typ. Max. I/O Supply Voltage Low Range 1.62 1.80 2.00 VDDIOM(2) I/O Supply Voltage Mid Range 2.00 2.50 3.00 VDDIOH(2) I/O Supply Voltage High Range 3.00 3.30 3.60 VBATT(3) Battery Supply Voltage 2.5(4) 3.6 4.2 Operating Temperature -30 VDDIOL Notes: (2) 1. 2. 3. 4. Unit V 85 ºC Refer to the datasheet for details of power connections. I/O supply voltage is applied to the following pins: VDDIO_A, VDDIO_0, and VDDIO_1. Battery supply voltage is applied to following pins: VDDBATT_PPA/PA, VBATT_BUCK. Device is functional across this range of voltages; however, optimal RF performance is guaranteed for VBATT in the range 3.0V < VBATT < 4.2V. ATWINC1500 Hardware Design Guide – IEEE 802.11 b/g/n IoT Module [USER GUIDE] Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 9 9 Table 1-5. SPI Timing VDDIO Condition Characteristics Min. Max. Input Low Voltage VIL -0.30 0.60 Input High Voltage VIH VDDIO-0.60 VDDIO+0.30 Unit V Output Low Voltage VOL 0.45 VDDIOL Output High Voltage VOH VDDIO-0.50 I2C Pad Drive Strength (1) 4 All other Digital Pad Drive Strength 2 mA Input Low Voltage VIL -0.30 0.63 Input High Voltage VIH VDDIO-0.60 VDDIO+0.30 V Output Low Voltage VOL 0.45 VDDIOM Output High Voltage VOH I 2C Pad Drive Strength VDDIO-0.50 (1) 8 mA All other Digital Pad Drive Strength 4 Input Low Voltage VIL -0.30 0.65 Input High Voltage VIH VDDIO-0.60 VDDIO+0.30 (up to 3.60) Output Low Voltage VOL VDDIOH V 0.45 Output High Voltage VOH VDDIO-0.50 I2C Pad Drive Strength (1) 12 All other Digital Pad Drive Strength 6 mA All Output Loading 20 All Digital Input Load 6 pF Note: 1. I2C Pad Drive Strength applies to the following pins: I2C_SDA, I2C_SCL. SPI Interface Overview ATWINC1500-MR210PA has a Serial Peripheral Interface (SPI) that operates as a SPI slave. The SPI interface can be used for control and for serial I/O of 802.11 data. The SPI pins are mapped as shown in Table 1-6. The SPI is a full-duplex slave-synchronous serial interface that is available immediately following reset when pin 10 (SPI_CFG) is tied to VDDIO. Table 1-6. SPI Interface Pin Mapping Pin # 10 SPI Function 10 CFG: Must be tied to VDDIO 16 SSN: Active Low Slave Select 15 MOSI(RXD): Serial Data Receive 18 SCK: Serial Clock 17 MISO(TXD): Serial Data Transmit ATWINC1500 Hardware Design Guide – IEEE 802.11 b/g/n IoT Module [USER GUIDE] 1 Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 0 When the SPI is not selected, i.e., when SSN is high, the SPI interface will not interfere with data transfers between the serial-master and other serial-slave devices. When the serial slave is not selected, its transmitted data output is buffered, resulting in a high impedance drive onto the MISO line. The SPI interface responds to a protocol that allows an external host to read or write any register in the chip as well as initiate DMA transfers. The SPI SSN, MOSI, MISO, and SCK pins of the ATWINC1500-MR210PA have internal programmable pullup resistors. These resistors should be programmed to be disabled. Otherwise, if any of the SPI pins are driven to a low level while the ATWINC1500-MR210PA is in the low power sleep state, current will flow from the VDDIO supply through the pullup resistors, increasing the current consumption of the module. SPI Timing The SPI timing is provided in Table 1-7 and Figure 1-6. Table 1-7. SPI Slave Timing Parameters Parameter Symbol Min. Max. Unit 48 MHz Clock Input Frequency fSCK Clock Low Pulse Width tWL 15 Clock High Pulse Width tWH 15 Clock Rise Time tLH 10 Clock Fall Time tHL 10 Input Setup Time tISU 5 Input Hold Time tIHD 5 Output Delay tODLY 0 Slave Select Setup Time TSUSSN 5 Slave Select Hold Time tHDSSN 5 Remarks ns 20 ATWINC1500 Hardware Design Guide – IEEE 802.11 b/g/n IoT Module [USER GUIDE] Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 11 1 1 Figure 1-6. SPI Timing Diagram (SPI Mode CPOL=0, CPHA=0) fSCK tLH tWH SCK tWL tHL TXD t ODLY RXD tISU SSN SPI Master SSN SPI Slave tIHD tSSODLY t SUSSN t HDSSN SPI PCB Trace Constraints In general, the SPI PCB trace layout must ensure that the total capacitance (trace and load of other pin) on the SPI lines (SPI_RXD, SPI_SSN, SPI_TXD, and SPI_SCK) are less than the maximum pin capacitance of 20pF (see the datasheet referred to in Table 1-9). As this is heavily dependent on the board type and lithography, no single constraint of trace length can be given. It is, however, preferable to minimize the trace length as much as possible. For further guidance, consult your Atmel® FAE. Be sure to have all information on the application PCB layout design rules. UART Interface The ATWINC1500-MR210PA has a Universal Asynchronous Receiver / Transmitter (UART) interface available on pins J14 and J19. It can be used for control or data transfer if the baud rate is sufficient for a given application. The UART is compatible with the RS-232 standard, where ATWINC1500MR210PA operates as Data Terminal Equipment (DTE). It has a two-pin RXD/TXD interface. The UART features programmable baud rate generation with fractional clock division, which allows transmission and reception at a wide variety of standard and non-standard baud rates. The UART input clock is selectable between 10MHz, 5MHz, 2.5MHz, and 1.25MHz. The clock divider value is programmable as 13 integer bits and three fractional bits (with 8.0 being the smallest recommended value for normal operation). This results in the maximum supported baud rate of 10MHz / 8.0 = 1.25MBd. The UART can be configured for seven or eight bit operation, with or without parity, with four different parity types (odd, even, mark, or space), and with one or two stop bits. It also has Rx and Tx FIFOs, which ensure reliable high speed reception and low software overhead transmission. FIFO size is 4 x 8 for both Rx and Tx direction. The UART also has status registers showing the number of received characters available in the FIFO and various error conditions, as well the ability to generate interrupts based on these status bits. 12 ATWINC1500 Hardware Design Guide – IEEE 802.11 b/g/n IoT Module [USER GUIDE] 1 Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 2 An example of UART receiving or transmitting a single packet is shown in Figure 1-7. This example shows 7-bit data (0x45), odd parity, and two stop bits. See the ATWINC1500-MR210PA Programming Guide for information on configuring the UART. Figure 1-7. Example of UART Rx or Tx packet Wi-Fi / Bluetooth Coexistence ATWILC1000A supports 2-wire and 3-wire Wi-Fi/Bluetooth® Coexistence signaling conforming to the IEEE® 802.15.2-2003 standard, Part 15.2. The type of coexistence interface used (2-wire or 3-wire) is chosen to be compatible with the specific Bluetooth device used in a given application. Table 1-8 shows a usage example of the 2-wire interface using the GPIO3 and GPIO4 pins; 3-wire interface using the GPIO3, GPIO4, and GPIO5 pins; for more specific instructions on configuring Coexistence, refer to ATWILC1000A Programming Guide. Table 1-8. Pin Name Coexistence Pin Assignment Example Function Target Pin # 2-wire 3-wire GPIO3 BT_Req BT is requesting to access the medium to transmit or receive. Goes high on TX or RX slot 28 Used Used GPIO4 BT_Pri Priority of the BT packets in the requested slot. High to indicate high priority and low for normal. 29 Not Used Used GPIO5 WL_Act Device response to the BT request. High - BT_req is denied and BT slot blocked. 30 Used Used GPIO6 Ant_SW Direct control on Antenna (coex bypass) 31 Optional Optional Antenna Make sure to choose an antenna that covers the proper frequency band; 2.400GHz to 2.500GHz. Talk to the antenna vendor and make sure he understands the full frequency range that must be covered by the antenna. Make sure the antenna is designed for a 50Ω system. Make sure the PCB pad that the antenna is connected to is properly designed for 50Ω impedance. This is extremely important. The antenna vendor must specify the pad dimensions, the spacing from the pad to the ground reference plane, and the spacing from the edges of the pad to the ground fill on the same layer as the pad. Also, since the ground reference plane for the 50 trace going from the antenna pad to the ATWINC1500 will probably be on a different layer than the ground reference for the antenna pad, make sure the pad design has a proper transition from the pad to the 50Ω trace. Make sure that the antenna matching components are placed as close to the antenna pad as possible. The antenna cannot be properly matched if the matching components are far away from the antenna. ATWINC1500 Hardware Design Guide – IEEE 802.11 b/g/n IoT Module [USER GUIDE] Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 13 1 3 FCC, TELEC, ETSI Compliance The reference design provided is compliant with FCC, TELEC, and ETSI regulations. No Calibrations are needed by the device maker if the 26MHz crystal used meets the 802.11 requirements (±20ppm). For crystals variations outside this range, consult your Atmel FAE. Reference Documentation and Support Reference Documents Atmel offers a set of collateral documentation to ease integration and device ramp. The following list of documents available on Atmel web or integrated into development tools. Table 1-9. Reference Documents Title Content Datasheet Design Files User Guide, Schematic, PCB layout, Gerber, BOM, and System notes on: RF/Radio Full Test Report, radiation pattern, design guidelines, temperature performance, ESD. Package How to use package: Out of the Box starting guide, HW limitations and notes, SW Quick start guidelines Platform Getting started Guide This document HW Design Guide Integration guide with clear description of: High level Arch, overview on how to write a networking application, list all API, parameters and structures. Features of the device, SPI/handshake protocol between device and host MCU, with flow/sequence/state diagram, timing. SW Design Guide Explain in details the flow chart and how to use each API to implement all generic use cases (e.g. start AP, start STA, provisioning, UDP, TCP, http, TLS, p2p, errors management, connection/transfer recovery mechanism/state diagram) - usage and sample application note. For a complete listing of development-support tools and documentation, visit http://www.atmel.com/ or contact the nearest Atmel field representative. 14 ATWINC1500 Hardware Design Guide – IEEE 802.11 b/g/n IoT Module [USER GUIDE] 1 Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 4 Bill of Materials (BOM) Item Qty. Reference Value 1 Description 1 C1 0.01µF CAP,CER,0.01µF,10%, X5R,0201,10V,-55-125ºC Murata GRM033R61A103KA01D CS0201 2 8 C2,C3,C5, C6,C8,C11, C12,C19 0.1µF CAP,CER,0.1µF,10%, X5R,0201,10V,-55-125ºC Murata GRM033R60J104KE19D CS0201 3 2 C3,C10 2.2µF CAP,CER,2.21µF,10%, X5R,0402,6.3V,-55-85ºC TDK C1005X5R0J225K CS0402 4 1 C7 1.0µF CAP,CER,1.0µF,10%, X5R,0402,6.3V,-55-85ºC GRM155R60J105 GRM155R60J105KE19D KE19D CS0402 5 4 C15,C16, C23,C24 6.8pF CAP,CER,6.8pF,0.5pF, NPO,0201,25V,-55-125ºC TDK C0603C0G1E6R8D030BA CS0201 6 2 C17,C32 1.0pF CAP,CER,1.0pF,0.1pF, NPO,0201,25V,-55-125ºC Murata GRM0335C1E1ROBA01J CS0201 7 1 C21 DNI CAP,CER,1.0pF,0.1pF, NPO,0201,25V,-55-125ºC Murata GRM0335C1E1ROBA01J CS0201 8 2 R3,C22 DNI CAP,CER,0.5pF,0.1pF, NPO,0201,25V,-55-125ºC Murata 500RGRM0335C1ER50BAD CS0201 9 1 C33 0.7pF CAP,CER,0.5pF,0.1pF, NPO,0201,25V,-55-125ºC Murata 500RGRM0335C1ER70BAD01D07S0R5AV4T CS0201 10 1 E1 11 3 FB1,FB2, BB3 12 1 L1 13 1 14 ANTENNA Manufacturer Part Number Footprint Murata FERRITE,120Ω@100MHz, 200Ma,0201,-55-125ºC Murata BLM03AG121SN1 FBS0201 1µH Power inductor,1µH,20%, 940mA,0.125Ω,0603,shielded,40-85ºC Murata LQM18PN1ROMFRL LS0603 L2 0 Power inductor,1µH,20%, 940mA,0.125Ω,0603,shielded,40-85ºC Murata LQM18PN1ROMFRL LS0603 1 L3 2.0nH Inductor,2.0nH,0.2nH,Q=13@500MHz, Taiyo Yuden SRF=8.1GHz,0201,-55-125ºC HKQO503S2N3C-T RS0201 15 1 L5 15nH Inductor,Multilayer,15nH,5%,350mA, Q=8@100MHz,0402 LQG15HS15NJ02D LS0402 16 2 L8,L9 3.3nH Inductor,3.3nH,0.2nH,Q=13@500MHz, Taiyo Yuden SRF=8.1GHz,0201,-55-125ºC HKQO503S3N3C-T LS0201 17 1 R2 0.5pF CAP,CER,0.5pF,0.1pF, NPO,0201,25V,-55-125ºC Murata 500RGRM0335C1ER50BAD CS0201 19 1 R7 1M Resistor,Thick film,1M,5%,0201 Vishay CRCW0201-105J RS0201 20 2 R9,R10 DNI Resistor,Thick film,0Ω,0201 Panasonic ERJ-1GN0R00C RS0201 21 10 R11,R16, R17,R18, R5,R6,R8, R12,R13, R14 0 Resistor,Thick film,0Ω,0201 Panasonic ERJ-1GN0R00C RS0201 22 2 R19,R20 Resistor,Thick film,4.7K,5%,0201 Vishay CRCW0201-472J RS0201 23 1 U1 ATWINC1500 IC,Wi-Fi,40QFN Atmel ATWINC1500 40QFN 24 1 U3 SI1865DDL IC, loaded switch,1.8V-12V In, RDSon=0.3Ω@2.5V,SC70-6 Vishay SI1865DDL SC70-6 25 1 Y1 26MHz NX3225SA-26.000000MHZ-G3 3.2x2.5mm BLM03AG121SN1 Murata 18 4.7K XTAL,26MHz,CL=7.36pF,10ppm, NDK -20-85ºC,ESR=50,3.2x2.5mm ATWINC1500 Hardware Design Guide – IEEE 802.11 b/g/n IoT Module [USER GUIDE] Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 15 1 5 Ta bl e of Conte nts Reference Schematic ......................................................................................................... 2 Notes on Interfacing to the ATWINC1500 .......................................................................... 2 Placement and Routing Guidelines ................................................................................... 6 Interferers ..................................................................................................................... 9 Thermal Considerations ..................................................................................................... 9 External Interfaces.............................................................................................................. 9 Antenna ................................................................................................................... 13 FCC, TELEC, ETSI Compliance........................................................................................ 14 Reference Documentation and Support .......................................................................... 14 Bill of Materials (BOM)...................................................................................................... 15 Table of Contents ............................................................................................................. 16 Revision History ............................................................................................................... 17 16 ATWINC1500 Hardware Design Guide – IEEE 802.11 b/g/n IoT Module [USER GUIDE] 1 Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 6 Revision History Doc Rev. Date 42416A 03/2015 Comments Initial document release. ATWINC1500 Hardware Design Guide – IEEE 802.11 b/g/n IoT Module [USER GUIDE] Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015 17 1 7 Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 │ www.atmel.com © 2015 Atmel Corporation. / Rev.: Atmel-42416A-ATWINC1500-Hardware-Design-Guide-IEEE802.11-bgn-IoT-Module_UserGuide_032015. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. ARM®, ARM Connected® logo, and others are the registered trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. 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