LTC6090/LTC6090-5 - 140V CMOS Rail-to-Rail Output, Picoamp Input Current Op Amp

LTC6090/LTC6090-5
140V CMOS Rail-to-Rail
Output, Picoamp Input
Current Op Amp
DESCRIPTION
FEATURES
Supply Range: ±4.75V to ±70V (140V)
n 0.1Hz to 10Hz Noise: 3.5μV
P-P
n Input Bias Current: 50pA Maximum
n Low Offset Voltage: 1.25mV Maximum
n Low Offset Drift: ±5µV/°C Maximum
n CMRR: 130dB Minimum
n Rail-to-Rail Output Stage
n Output Sink and Source: 50mA
n12MHz Gain Bandwidth Product
n21V/µs Slew Rate
n11nV/√Hz Noise Density
n Thermal Shutdown
n Available in Thermally Enhanced SOIC-8E or
TSSOP-16E Packages
The LTC®6090/LTC6090-5 are high voltage, precision
monolithic operational amplifiers. The LTC6090 is unity
gain stable. The LTC6090-5 is stable in noise gain configurations of 5 or greater. Both amplifiers feature high
open loop gain, low input referred offset voltage and noise,
and pA input bias current and are ideal for high voltage,
high impedance buffering and/or high gain configurations.
n
The amplifiers are internally protected against overtemperature conditions. A thermal warning output, TFLAG,
goes active when the die temperature approaches 150°C.
The output stage may be turned off with the output disable
pin OD. By tying the OD pin to the thermal warning output
(TFLAG), the part will disable the output stage when it is
out of the safe operating area. These pins easily interface
to any logic family.
APPLICATIONS
n
n
n
n
n
Both amplifiers may be run from a single 140V or spit
±70V power supplies and are capable of driving up to
200pF of load capacitance. They are available in either an
8-lead SO or 16-lead TSSOP package with exposed pad
for low thermal resistance.
ATE
Piezo Drivers
Photodiode Amplifier
High Voltage Regulators
Optical Networking
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
High Voltage DAC Buffer Application
140VP-P Sine Wave Output
80
3V
DIN
16
LTC2641
10k
+
470pF
LTC6090
VOUT = ±70V
–
VREF
2.5V
16.2k
OUTPUT VOLTAGE (V)
60
70V
40
20
0
–20
–40
–60
–70V
–80
453k
6090 TA01a
25µs/DIV
6090 TA01b
16.9k
10pF
6090fe
For more information www.linear.com/LTC6090
1
LTC6090/LTC6090-5
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Total Supply Voltage (V+ to V–)................................150V
COM.................................................................... V– to V+
Input Voltage
OD....................................................... V– to V+ + 0.3V
+IN, –IN,................................... V– – 0.3V to V+ + 0.3V
OD to COM................................................... –3V to 7V
Input Current
+IN, –IN............................................................ ±10mA
TFLAG Output
TFLAG.......................................V – – 0.3V to V+ + 0.3V
TFLAG to COM............................................. –3V to 7V
Output Current
Continuous (Note 2).................................... 50mARMS
Operating Junction Temperature Range
(Note 3)....................................................–40°C to 125°C
Specified Junction Temperature Range (Note 4)
LTC6090C................................................. 0°C to 70°C
LTC6090I..............................................–40°C to 85°C
LTC6090H........................................... –40°C to 125°C
Junction Temperature (Note 5).............................. 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
COM 1
–IN 2
+IN 3
V–
9
V–
4
COM
1
16 OD
GUARD
2
15 GUARD
14 V+
8
OD
GUARD
3
7
V+
–IN
4
6
OUT
+IN
5
GUARD
6
11 GUARD
GUARD
7
10 GUARD
V–
8
9
5
TFLAG
S8E PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJC = 5°C/W
EXPOSED PAD (PIN 9) IS V–, MUST BE SOLDERED TO PCB
17
V–
13 GUARD
12 OUT
TFLAG
FE PACKAGE
16-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJC = 10°C/W
EXPOSED PAD (PIN 17) IS V–, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
JUNCTION TEMPERATURE RANGE
LTC6090CS8E#PBF
LTC6090CS8E#TRPBF
6090
8-Lead Plastic SO
0°C to 70°C
LTC6090IS8E#PBF
LTC6090IS8E#TRPBF
6090
8-Lead Plastic SO
–40°C to 85°C
LTC6090HS8E#PBF
LTC6090HS8E#TRPBF
6090
8-Lead Plastic SO
–40°C to 125°C
LTC6090CFE#PBF
LTC6090CFE#TRPBF
6090FE
16-Lead Plastic TSSOP
0°C to 70°C
LTC6090IFE#PBF
LTC6090IFE#TRPBF
6090FE
16-Lead Plastic TSSOP
–40°C to 85°C
LTC6090HFE#PBF
LTC6090HFE#TRPBF
6090FE
16-Lead Plastic TSSOP
–40°C to 125°C
2
6090fe
For more information www.linear.com/LTC6090
LTC6090/LTC6090-5
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
JUNCTION TEMPERATURE RANGE
LTC6090CS8E-5#PBF
LTC6090CS8E-5#TRPBF
60905
8-Lead Plastic SO
0°C to 70°C
LTC6090IS8E-5#PBF
LTC6090IS8E-5#TRPBF
60905
8-Lead Plastic SO
–40°C to 85°C
LTC6090HS8E-5#PBF
LTC6090HS8E-5#TRPBF
60905
8-Lead Plastic SO
–40°C to 125°C
LTC6090CFE-5#PBF
LTC6090CFE-5#TRPBF
6090FE-5
16-Lead Plastic TSSOP
0°C to 70°C
LTC6090IFE-5#PBF
LTC6090IFE-5#TRPBF
6090FE-5
16-Lead Plastic TSSOP
–40°C to 85°C
LTC6090HFE-5#PBF
LTC6090HFE-5#TRPBF
6090FE-5
16-Lead Plastic TSSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
ELECTRICAL
CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications and all typical values are at TJ = 25°C. Test conditions are V+ = 70V, V– = –70V, VCM =
VOUT = 0V, VOD = Open unless otherwise noted.
C-, I-SUFFIXES
SYMBOL PARAMETER
VOS
CONDITIONS
MIN
Input Offset Voltage
l
∆VOS /∆T Input Offset Voltage Drift
TA = 25°C, ∆TJ = 70°C
IB
Input Bias Current (Note 6)
Supply Voltage = ±70V
Supply Voltage = ±15V
Supply Voltage = ±15V
IOS
Input Offset Current (Note 6)
Supply Voltage = ±15V
–5
MAX
±330
±330
±1000
±1250
±3
5
3
0.3
l
0.5
l
en
H-SUFFIX
TYP
MIN
–5
TYP
MAX
UNITS
±330
±330
±1000
±1250
μV
μV
±3
5
3
0.3
50
0.5
30
µV/°C
800
pA
pA
pA
120
pA
pA
Input Noise Voltage Density
f = 1kHz
f = 10kHz
14
11
14
11
Input Noise Voltage
0.1Hz to 10Hz
3.5
3.5
µVP-P
1
1
fA/√Hz
in
Input Noise Current Density
VCM
Input Common Mode Range
Guaranteed by CMRR
l
V –+3V
±68
V+ –3V
V –+3V
±68
nV/√Hz
nV/√Hz
V+ –3V
V
V
CIN
Common Mode Input
Capacitance
9
9
pF
CDIFF
Differential Input Capacitance
5
5
pF
CMRR
Common Mode Rejection Ratio VCM = –67V to 67V
PSRR
VOUT
AVOL
Power Supply Rejection Ratio
130
126
>140
130
126
>140
l
dB
dB
112
106
>120
112
106
>120
l
dB
dB
VS = ±4.75V to ±70V
Output Voltage Swing High (VOH) No Load
(Referred to V+)
ISOURCE = 1mA
ISOURCE = 10mA
l
l
l
10
50
450
25
140
1000
10
50
450
25
140
1000
mV
mV
mV
Output Voltage Swing Low (VOL) No Load
(Referred to V –)
ISINK = 1mA
ISINK = 10mA
l
l
l
10
40
250
25
80
600
10
40
250
25
80
600
mV
mV
mV
Large-Signal Voltage Gain
RL = 10k,
VOUT from –60V to 60V
l
1000
1000
>10000
1000
1000
>10000
V/mV
V/mV
6090fe
For more information www.linear.com/LTC6090
3
LTC6090/LTC6090-5
ELECTRICAL
CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications and all typical values are at TJ = 25°C. Test conditions are V+ = 70V, V– = –70V, VCM =
VOUT = 0V, VOD = Open unless otherwise noted.
C-, I-SUFFIXES
SYMBOL PARAMETER
ISC
SR
GBW
CONDITIONS
MIN
TYP
Output Short-Circuit Current
(Source and Sink)
Supply Voltage = ±70V
Supply Voltage = ±15V
l
50
Slew Rate
AV = –4, RL = 10k
LTC6090
LTC6090-5
l
l
10
18
21
37
fTEST = 20kHz, RL = 10k
LTC6090
LTC6090-5
l
l
5.5
11
12
24
Gain-Bandwidth Product
ΦM
Phase Margin
RL = 10k, CL = 50pF
FPBW
Full Power Bandwidth
VO = 125VP–P
LTC6090
LTC6090-5
tS
Settling Time 0.1%
∆VOUT = 1V
LTC6090, AV = 1V/V
LTC6090-5, AV = 5V/V
IS
Supply Current
No Load
H-SUFFIX
MAX
90
MIN
20
34
40
68
2.8
VS
Supply Voltage Range
Guaranteed by the PSRR Test l
ODH
ODL
OD Pin Voltage, Referenced to
COM Pin
VIH
VIL
Amplifier DC Output
Impedance, Disabled
DC, OD = COM
9.5
9
16
21
37
V/μs
V/μs
5
10
12
24
MHz
MHz
60
Deg
40
68
kHz
kHz
2
2.5
µs
µs
18
32
3.9
4.3
140
l COM+1.8V
l
COM+0.65V
2.8
9.5
COM+1.8V
>10
V–
3.9
4.3
mA
mA
140
V
COM+0.65V
V
V
>10
V+ – 5
UNITS
mA
mA
2
2.5
l
MAX
90
50
60
l
l
TYP
V–
MΩ
V+ – 5
COMCM
COM Pin Voltage Range
l
17
21
25
17
21
25
V
500
665
850
500
665
850
kΩ
COMV
COM Pin Open Circuit Voltage
l
COMR
COM Pin Resistance
l
TEMPF
Die Temperature Where TFLAG
Is Active
TEMPHYS TFLAG Output Hysteresis
ITFLAG
TFLAG Pull-Down Current
TFLAG Output Voltage = 0V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6090/LTC6090-5 is capable of producing peak output
currents in excess of 50mA. Current density limitations within the IC require
the continuous RMS current supplied by the output (sourcing or sinking)
over the operating lifetime of the part be limited to under 50mA (Absolute
Maximum). Proper heat sinking may be required to keep the junction
temperature below the absolute maximum rating. Refer to Figure 7, the
Power Dissipation section, and the Safe Operating Area section of the data
sheet for more information.
Note 3: The LTC6090C/LTC6090I are guaranteed functional over the
operating junction temperature range –40°C to 85°C. The LTC6090H
is guaranteed functional over the operating junction temperature range
–40°C to 125°C. Specifying the junction temperature range as an operating
condition is applicable for devices with potentially significant quiescent
power dissipation.
4
l
70
V
145
145
°C
5
5
°C
200
330
70
200
330
µA
Note 4: The LTC6090C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6090C is designed, characterized, and expected
to meet specified performance from –40°C to 85°C but is not tested or
QA sampled at these temperatures. The LTC6090I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6090H is guaranteed
to meet specified performance from –40°C to 125°C.
Note 5: This device includes over temperature protection that is intended
to protect the device during momentary overload conditions. Operation
above the specified maximum operating junction temperature is not
recommended.
Note 6: Input bias and offset current is production tested with ±15V
supplies. See Typical Performance Characteristics curves of actual typical
performance over full supply range.
6090fe
For more information www.linear.com/LTC6090
LTC6090/LTC6090-5
TYPICAL PERFORMANCE CHARACTERISTICS
Open Loop Gain and Phase
vs Frequency
CMRR vs Frequency
100
100
80
PHASE
60
60
40
40
20
20
–20
0.1
1
–40
10000
10
100
1000
FREQUENCY (kHz)
LTC6090
60
0
0.1
1
10
100
FREQUENCY (kHz)
60
200
150
100
40
50
20
–500
0
500
VOS (µV)
0
1000
500
200
100
0
–100
4
300
200
0
–300
–400
–400
50
25
0
75
TEMPERATURE (°C)
100
125
6090 G07
–500
5
125°C
85°C
25°C
–50°C
–50
–25
0
25
50
INPUT COMMON MODE VOLTAGE (V)
75
6090 G06
Minimum Supply Voltage
100
–300
VS = ±70V
–10
6090 G05
–200
–25
0
–20
–75
6
–100
–200
–500
–50
–2
0
2
TCVOS (µV/°C)
TA = 25°C
5 SAMPLES
V+ = – V –
VCM = 0V
400
OFFSET VOLTAGE (µV)
300
–4
SPECIFIED COMMON
MODE RANGE= ±67V
10
Offset Voltage
vs Total Supply Voltage
VS = ±70V
VCM = 0V
5 SAMPLES
400
–6
6090 G04
Offset Voltage vs Temperature
VOLTAGE OFFSET (µV)
CHANGE IN OFFSET VOLTAGE (µV)
80
1000
20
VS = ±70V
T = 25°C
300 A
∆TJ = 70°C
VCM = 0V
250
NUMBER OF UNITS
NUMBER OF UNITS
100
10
100
FREQUENCY (kHz)
Change in Offset Voltage
vs Input Common Mode Voltage
350
VS = ±70V
180 TA = 25°C
V = 0V
160 CM
120
1
PSRR–
6090 G03
TCVOS Distribution
200
500
0
0.1
1000
LTC6090-5
LTC6090-5
LTC6090
LTC6090
6090 G02
VOS Distribution
0
–1000
60
20
6090 G01
140
PSRR+
80
40
20
–20
LTC6090
LTC6090-5
100
30
80
105
130
55
TOTAL SUPPLY VOLTAGE (V)
6090 G08
100
CHANGE IN OFFSET VOLTAGE (µV)
0
LTC6090-5
40
0
14
AV = 1V/V
120
80
CMRR (dB)
GAIN
PSRR vs Frequency
140
VS = ±70V
100
PHASE (DEG)
GAIN (dB)
80
120
PSRR (dB)
120
75
50
25
0
–25
–50
125°C
85°C
25°C
–50°C
–75
–100
5
6
7
9
8
TOTAL SUPPLY VOLTAGE (V)
10
6090 G09
6090fe
For more information www.linear.com/LTC6090
5
LTC6090/LTC6090-5
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current
vs Total Supply Voltage
3.0
2.9
2.5
2.8
VS = ±70V
2.7
VS = ±4.75V
2.6
2.5
Output Disable Supply Current
vs Total Supply Voltage
800
OUTPUT DISABLE CURRENT (µA)
3.0
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
Supply Current vs Temperature
2.0
1.5
1.0
0.5
2.4
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
0
125
TA = 25°C
0
25
50
75
100
SUPPLY VOLTAGE (V)
125
6090 G10
10
10
15
150
100
50
10
100
1000
FREQUENCY (kHz)
100
1000
FREQUENCY (kHz)
10000
LTC6090-5 Small Signal
Frequency Response
vs Closed Loop Gain
30
GAIN (dB)
GAIN (dB)
GAIN (dB)
10
40
10
–10
10000
1
50
20
–5
6090 G16
6
5
–5
10000
40
0
100
1000
FREQUENCY (kHz)
10
6090 G15
0
10
RF = 40.2k
RI = 10k
CF = 2pF
0
30
1
LTC6090
LTC6090-5
6090 G14
15
–10
50
75
100
125
25
TOTAL SUPPLY VOLTAGE (V)
Small Signal Frequency Response
50
5
0
6090 G12
LTC6090 Small Signal Frequency
Response vs Closed Loop Gain
RF = 40.2k
RI = 10k
125°C
85°C
25°C
–50°C
100
200
0
100
CF = 0pF
CF = 1pF
CF = 2pF
10
200
20
LTC6090-5 Small Signal
Frequency Response
vs Feedback Capacitance
20
300
250
6090 G13
25
400
0
150
GAIN (dB)
INTEGRATED NOISE (µVRMS)
VOLTAGE NOISE DENSITY (nV/√Hz)
100
0.1
1
FREQUENCY (kHz)
500
Integrated Noise vs Frequency
1000
0.010
600
6090 G11
Voltage Noise Density
vs Frequency
1
0.001
700
–20
20
10
AV = 101V/V
AV = 11V/V
AV = 1V/V
1
10
100
1000
FREQUENCY (kHz)
101V/V
33V/V
11V/V
5V/V
0
10000
6090 G17
–10
1
10
100
1000
FREQUENCY (kHz)
10000
6090 G18
6090fe
For more information www.linear.com/LTC6090
LTC6090/LTC6090-5
TYPICAL PERFORMANCE CHARACTERISTICS
1000
10
1
0.01
AV = 101V/V
AV = 11V/V
AV = 1V/V
1
10
1000
100
10
1
100
1000 10000 100000
FREQUENCY (kHz)
1
10
100
FREQUENCY (kHz)
60
DIRECTION OF THE CURRENT
IS OUT OF THE PIN
50°C
25°C
0.1
–15
–10
–5
0
10
5
COMMON MODE VOLTAGE (V)
15
100°C
80°C
DIRECTION OF THE CURRENT
IS OUT OF THE PIN
50°C
25°C
LTC6090-5 Large Signal Transient
Response
80
AV = –10V/V
VS = ±70V
OUTPUT
60
40
20
0
INPUT
–20
0
INPUT
–20
–60
–60
–80
6090 G23
AV = –10V/V
VS = ±70V
RF = 100kΩ
RI = 10kΩ
CF = 2pF
20
–40
5µs/DIV
OUTPUT
40
–40
–80
80
6090 G21
OUTPUT, INPUT (V)
85°C
1
80
VS = ±15V
100°C
10
1
LTC6090 Large Signal Transient
Response
OUTPUT, INPUT (V)
INPUT BIAS CURRENT (|pA|)
100
10
125°C
6091 G20
Input Bias Current vs Common
Mode Voltage and Temperature
125°C
100
VS = ±70V
5°C
0.1
20 40 60
–80 –60 –40 –20 0
COMMON MODE VOLTAGE (V)
1000
6090 G19
1000
10000
CL = 10pF
INPUT BIAS CURRENT (|pA|)
100
OUTPUT IMPEDANCE (kΩ)
OUTPUT IMPEDACNE (Ω)
1000
0.1
Input Bias Current vs Common
Mode Voltage and Temperature
Output Impedance vs Frequency
with Output Disabled (OD = COM)
Output Impedance vs Frequency
6090 G24
5µs/DIV
6090 G22
LTC6090 Falling Edge
Settling Time
Small Signal Transient Response
AV = 1V/V
LTC6090 Rising Edge
Settling Time
6090 G16
500ns/DIV
6090 G26
INPUT STEP (0.5V/DIV)
INPUT STEP (0.5V/DIV)
1µs/DIV
INPUT
OUTPUT STEP (20mV/DIV)
OUTPUT
50mV/DIV
OUTPUT STEP (20mV/DIV)
OUTPUT
INPUT
50mV/DIV
AV = 1V/V
AV = 1V/V
OUTPUT
INPUT
500ns/DIV
6090 G27
6090fe
For more information www.linear.com/LTC6090
7
LTC6090/LTC6090-5
TYPICAL PERFORMANCE CHARACTERISTICS
LTC6090-5 Rising Edge
Settling Time
LTC6090-5 Small Signal
Transient Response
LTC6090-5 Falling Edge
Settling Time
INPUT (100mV/DIV)
INPUT (100mV/DIV)
INPUT
AV = 5V/V
RF = 40.2kΩ
RI = 10kΩ
CF = 2pF
OUTPUT
6090 G28
1µs/DIV
OUTPUT (50mV/DIV)
OUTPUT
100mV/DIV
OUTPUT (50mV/DIV)
INPUT
25mV/DIV
INPUT
OUTPUT
AV = 5V/V
RF = 40.2kΩ
RI = 10kΩ
CF = 2pF
AV = 5V/V
RF = 40.2kΩ
RI = 10kΩ
CF = 2pF
6090 G29
500ns/DIV
500ns/DIV
6090 G30
Output Disable (OD) Response
Time
OD-COM
OUTPUT
ENABLED
0.1Hz to 10Hz Voltage Noise
160
AV = –10V/V
VIN = –0.5V
AV = –10V/V
VS = ±70V
RF = 100kΩ
RI = 10kΩ
CF = 2pF
140
120
OUTPUT
DISABLED
VOUT (VP-P)
2V/DIV
OD-COM
= 0V
Output Voltage Swing
vs Frequency
VOUT
VOUT
= 0V
100
OUTPUT
NOISE
2µV/DIV
80
60
40
20
20µs/DIV
0
6090 G31
LTC6090
LTC6090-5
1
10
100
FREQUENCY (kHz)
1000
6090 G33
TIME (1s/DIV)
6090 G32
SUPPLY CURRENT (mA)
2.5
2.0
1.5
1.0
125°C
85°C
25°C
–50°C
0.5
0
75
VS = ±70V
VCOM = 0V
0.5
0.8
1.0
1.3
1.5
OD-COM (V)
1.8
2.0
OD INPUT CURRENT (µA)
3.0
OD Pin Input Current
vs OD Pin Voltage
Output Voltage Swing High (VOH)
vs Load Current and Temperature
50
125°C
85°C
25°C
–50°C
700
600
25
0
500
400
300
200
–25
100
–50
0
1
2
3
4
OD-COM (V)
5
7
6
6090 G35
6090 G34
8
800
125°C
85°C
25°C
–50°C
VS = ±70V
VCOM = 0V
VOH (mV)
Supply Current vs OD Pin Voltage
0
0
2
4
6
ISOURCE (mA)
8
10
6090 G36
6090fe
For more information www.linear.com/LTC6090
LTC6090/LTC6090-5
TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage Swing Low (VOL)
vs Load Current and Temperature
LTC6090 Distortion vs Frequency
–20
125°C
85°C
25°C
–50°C
450
400
–40
DISTORTION (dBc)
VOL (mV)
300
250
200
150
–50
–70
–90
–100
–110
2
4
6
ISOURCE (mA)
8
–120
10
2ND
–80
50
0
2.5
–60
100
0
VS = ±70V
AV = 10
VOUT = 10VP-P
RL = 10k
–30
350
Thermal Shutdown Hysteresis
3.0
SUPPLY CURRENT (mA)
500
3RD
2.0
1.5
1.0
0.5
10
0
162 164 166 168 170 172 174 176 178
JUNCTION TEMPERATURE (°C)
100
FREQUENCY (kHz)
6090 G38
6090 G39
6090 G37
Open Circuit Voltage of COM,
OD, TFLAG
CHANGE IN VOLTAGE OFFSET (µV)
80
PIN VOLTAGE (V)
40
OD
COM
TFLAG
–
V = 0V
60
40
20
0
0
20
40
60
80 100 120
TOTAL SUPPLY VOLTAGE (V)
140
6090 G40
40
VS = ±70V
RLOAD = 10k
TA = 25°C
10 SAMPLES
30
20
CHANGE IN VOLTAGE OFFSET (µV)
100
Open Loop Gain
vs Load Resistance
Open Loop Gain
10
0
–10
–20
–30
–40
–70
–50
–25
0
25
OUTPUT VOLTAGE (V)
50
75
6090 G41
RLOAD = 500k
RLOAD = 10k
RLOAD = 100k
30
20
10
0
–10
–20
–30
–40
–70
–50
–25
0
25
OUTPUT VOLTAGE (V)
50
75
6090 G42
6090fe
For more information www.linear.com/LTC6090
9
LTC6090/LTC6090-5
PIN FUNCTIONS
(S8E/FE)
COM (Pin 1/Pin 1): COM Pin is used to interface OD and
TFLAG pins to voltage control circuits. Tie this pin to the
low voltage ground, or let it float.
–IN (Pin 2/Pin 4): Inverting Input Pin. Input common
mode range is V – + 3V to V + – 3V. Do not exceed absolute
maximum voltage range.
+IN (Pin 3/Pin 5): Noninverting Input Pin. Input common
mode range is V – + 3V to V + – 3V. Do not exceed absolute
maximum voltage range.
V– (Pin 4, Exposed Pad Pin 9/Pin 8, Exposed Pad
Pin 17): Negative Supply Pin. Connect to V– Only. To
achieve low thermal resistance connect this pin to the
V – power plane. The V – power plane connection removes
heat from the device and should be electrically isolated
from all other power planes.
OUT (Pin 6/Pin 12): Output Pin. If this rail-to-rail output
goes below V– , the ESD protection diode will forward
bias. If OUT goes above V+, then output device diodes
will forward bias. Avoid forward biasing the diodes on the
OUT pin. Excessive current can cause damage.
V+ (Pin 7/Pin 14): Positive Supply Pin.
OD (Pin 8/Pin 16): Output Disable Pin. Active low input
disables the output stage. If left open, an internal pull-up
resistor enables the amplifier. Input voltage levels are
referred to the COM pin.
GUARD (NA/Pins 2, 3, 6, 7, 10, 11, 13, 15): Guard pins
increase clearance and creepage between other pins.
Pins 3 and 6 can be used to build guard rings around the
inputs.
TFLAG (Pins 5, 9/Pins 9, 17): Temperature Flag Pin. The
TFLAG pin is an open drain output that sinks current when
the die temperature exceeds 145°C.
10
6090fe
For more information www.linear.com/LTC6090
LTC6090/LTC6090-5
BLOCK DIAGRAM
V+
V+
2M
2M
10k
COM
10k
OD
1.2V
2M
–
ESD
+
ESD
V–
V
–
V+
125Ω
–IN
ESD
V+
ESD
+IN
V–
OUTPUT
ENABLE
DIFFERENTIAL
DRIVE
GENERATOR
125Ω
OUT
ESD
V–
TO COM PIN
6k
500Ω
V–
INPUT STAGE
6k
TJ > 175°C
DIE
TEMPERATURE
TJ > 145°C
SENSOR
TFLAG
ESD
V–
V–
6090 BD
6090fe
For more information www.linear.com/LTC6090
11
LTC6090/LTC6090-5
APPLICATIONS INFORMATION
General
The LTC6090 high voltage operational amplifier is designed
in a Linear Technology proprietary process enabling a railto-rail output stage with a 140V supply while maintaining
precision, low offset, and low noise.
Power Supply
The LTC6090 works off single or split supplies. Split supplies can be balanced or unbalanced. For example, two
±70V supplies can be used, or a 100V and –40V supply
can be used. For single supply applications place a high
quality surface mount ceramic 0.1µF bypass capacitor
between the supply pins close to the part. For dual supply
applications use two high quality surface mount ceramic
capacitors between V+ to ground, and V– to ground located
close to the part. When using split supplies, supply sequencing does not cause problems.
Input Protection
As shown in the block diagram, the LTC6090 has a comprehensive protection network to prevent damage to the
input devices. The current limiting resistors and back to
back diodes are to keep the inputs from being driven apart.
The voltage-current relationship combines exponential
and resistive until the voltage difference between the pins
reach 12V.
At that point the Zeners turn on. Additional current into
the pins will snap back the input differential voltage to 9V.
In the event of an ESD strike between an input and V–, the
voltage clamps and ESD device fire providing a current
path to V– protecting the input devices.
The input pin protection is designed to protect against
momentary ESD events. A repetitive large fast input swing
(>5.5V and <20ns rise time) will cause repeated stress on
the MOSFET input devices. When in such an application,
anti-parallel diodes (1N4148) should be connected between
the inputs to limit the swing.
rise to 50V, causing 10mA to flow through the feedback
resistor. The power dissipated in the output stage will
create thermal feedback to the input stage potentially
causing shifts in offset voltage. A better choice is a 50k
feedback resistor reducing the current in the feedback
resistor to 1mA.
Interfacing to Low Voltage Circuits
The COM pin is provided to set a common signal ground
for communication to a microprocessor or other low voltage logic circuit. The COM pin should be tied to the low
voltage ground as shown in Figure 1. If left floating, the
internal resistive voltage divider will cause the COM pin
to rise 30% above mid-supply. The COM, OD, and TFLAG
pins are protected from overvoltage by internal Zener
diodes and current limiting resistors. Extra care should
be taken to observe the absolute maximum voltage limits
between (OD and COM) and between (TFLAG and COM).
Voltage limits between these pins must remain between
–3V and 7V.
LTC6090
2M
10k
OD
TO LOW
VOLTAGE
CONTROL
V+
2M
10k
COM
TIE TO LOW
VOLTAGE GROUND
2M
LOW VOLTAGE
SUPPLY
V–
6k
500Ω
200k
TO LOW
VOLTAGE
CONTROL
Feedback Resistor Selection
TFLAG
6k
V–
To get the most accuracy, the feedback resistor should be
chosen carefully. Consider an amplifier with AV = –50 and
a 5k feedback resistor. A 1V input will cause the output to
12
V+
6090 F01
Figure 1. Low Voltage Interface
6090fe
For more information www.linear.com/LTC6090
LTC6090/LTC6090-5
APPLICATIONS INFORMATION
When coming out of shutdown the LTC6090 bias circuits
and input stage are already powered up leaving only the
output stage to turn on and drive to the proper output
voltage. Figures 2 and 3 show the part starting up and
coming out of shutdown, respectively.
V+
OUT
10V/DIV
Thermal Shutdown
OD
2V/DIV
The TFLAG pin is an open drain output pin that sinks 200µA
(typical) when the die temperature exceeds 145°C. The
temperature sensor has 5°C of hysteresis requiring the
part to cool to 140°C before disabling the TFLAG pin. Extra
care should be taken to observe the absolute maximum
voltage limits between (OD and COM) and between (TFLAG
and COM). Voltage limits between these pins must remain
between –3V and 7V.
OUT
2V/DIV
Tying the the TFLAG pin to the OD pin will automatically
shut down the output stage as shown in Figure 4. This will
ensure the junction temperature does not exceed 150°C.
1ms/DIV
6090 F02
Figure 2. Starting Up
2.5ms/DIV
6090 F03
Figure 3. LTC6090 Output Disable Function
Output Disable
The OD pin is an active low disable with an internal 2MΩ
resistor that will pull up the OD pin enabling the output
stage if left open. The OD pin voltage is limited by an
internal Zener diode. When the OD pin is brought low to
within 0.65V of the COM pin, the output stage is disabled,
leaving the bias and input circuits enabled. This results in
580μA (typical) standby current through the device. The
OD pin can be directly connected to the low voltage logic
or an open drain NMOS device as shown in Figure 1.
For simplest shutdown operation, float the COM pin, and
tie the OD pin to the TFLAG pin. This will float the low
voltage control pins, and the overtemperature circuit will
safely shutdown the output stage if the die temperature
reaches 145°C.
Extra care should be taken to observe the absolute maximum voltage limits between (OD and COM) and between
(TFLAG and COM). Voltage limits between these pins must
remain between –3V and 7V.
For safety, an independent second overtemperature
threshold shuts down the output stage if the internal die
temperature rises to 175°C. There is hysteresis in the
thermal shutdown circuit requiring the die temperature
to cool 7°C. Once the device has cooled sufficiently, the
output stage will enable. Degradation can occur or reliability may be affected when the junction temperature
of the device exceeds 150°C.
LTC6090
V+
2M
10k
OD
TFLAG
OPTIONAL
(CAN BE LEFT
FLOATING)
6k
COM
V–
6090 F04
Figure 4. Automatic Thermal Output
Disable Using the TFLAG Pin
6090fe
For more information www.linear.com/LTC6090
13
LTC6090/LTC6090-5
APPLICATIONS INFORMATION
Board Layout
GUARD RING
The LTC6090 is a precision low offset high gain amplifier that requires good analog PCB layout techniques to
maintain high performance. Start with a ground plane
that is star connected. Pull back the ground plane from
any high voltage vias. Critical signals such as the inputs
should have short and narrow PCB traces to reduce stray
capacitance which also improves stability. Use high quality
surface mount ceramic capacitors to bypass the supply(s).
In addition to the typical layout issues encountered with
a precision operational amplifier, there are the issues of
high voltage and high power. Important consideration for
high voltage traces are spacing, humidity and dust. High
voltage electric fields between adjacent conductors attract
dust. Moisture is absorbed by the dust and can contribute
to board leakage and electrical breakdown.
C2
R2
–
R1
+
LTC6090
6090 F05a
Figure 5a. Circuit Diagram Showing Guard Ring
OUT
It is important to clean the PCB after soldering down the
part. Solder flux will accumulate dust and become a leakage hazard. It is recommended to clean the PCB with a
solvent, or simply use soap and water to remove residue.
Baking the PCB will remove left over moisture. Depending
on the application, a special low leakage board material
may be considered.
The TSSOP package has guard pins for applications that
require a guard ring. An example schematic diagram and
PCB layout is shown in Figures 5a and 5b, respectively,
of a circuit using a guard ring to protect the –IN pin.
The guard ring completely encloses the high impedance
node –IN. To simplify the PCB layout avoid using vias on
this node. In addition, the solder mask should be pulled
back along the guard ring exposing the metal. To help
the spacing between nodes, one of the extra pins on the
TSSOP package is used to route the guard ring behind
the –IN pin. The PCB should be thoroughly cleaned after
soldering to ensure there is no solder paste between the
exposed pad (Pin 17) and the guard ring.
14
+IN
R2
–IN
R1
C2
6090 F05b
Figure 5b. TSSOP Package PCB Layout with Guard Ring
6090fe
For more information www.linear.com/LTC6090
LTC6090/LTC6090-5
APPLICATIONS INFORMATION
Power Dissipation
With a supply voltage of 140V it doesn’t take much current
to consume a lot of power. Consider that 10mA at 140V
consumes 1.4W of power and needs to be dissipated in a
small plastic SO package. To aid in power dissipation both
LTC6090 packages have exposed pads for low thermal
resistance. The amount of metal connected to the exposed
pad will lower the θJA of a package. An optimal amount
of PCB metal connected to the SO package will lower the
junction to ambient thermal resistance down to 33°C/W.
If minimal metal is used, the θJA could more than double
(see Table 1). If the exposed pad has no metal beneath it,
θJA could be as high 120°C/W.
It’s recommended that the exposed pad have as much PCB
metal connected to it as reasonably available. The more PCB
metal connected to the exposed pad, the lower the thermal
resistance. Use multiple vias from the exposed pad to the
V– supply plane. The exposed pad is electrically connected
to the V– pin. In addition, a heat sink may be necessary
if operating near maximum junction temperature. See
Table 1 for guidance on how thermal resistance changes
as a function of metal area connected to the exposed pad.
The LTC6090 is specified to source and sink 10mA at 140V.
If the total supply voltage is dropped across the device,
1.4W of power will need to be dissipated. If the quiescent
power is included (140V • 2.8mA = 0.4W), the total power
dissipated is 1.8W. The internal die temperature will rise
59° using an optimal layout in a SO package. A sub-optimal
layout could more than double the amount of temperature
increase due to power dissipation.
Table 1. Thermal Resistance as PCB Area of Exposed Pad Varies
EXAMPLE A
TOP LAYER A
EXAMPLE B
TOP LAYER B
EXAMPLE C
TOP LAYER C
EXAMPLE D
TOP LAYER D
BOTTOM LAYER A
BOTTOM LAYER B
BOTTOM LAYER C
BOTTOM LAYER D
θJA = 50°C/W
θJC = 5°C/W
θCA = 45°C/W
θJA = 57°C/W
θJC = 5°C/W
θCA = 52°C/W
MINIMUM BOTTOM LAYER B
MINIMUM BOTTOM LAYER C
θJA = 57°C/W
θJC = 5°C/W
θCA = 52°C/W
θJA = 58°C/W
θJC = 5°C/W
θCA = 53°C/W
θJA = 43°C/W
θJC = 5°C/W
θCA = 38°C/W
MINIMUM BOTTOM LAYER A
θJA = 54°C/W
θJC = 5°C/W
θCA = 49°C/W
θJA = 72°C/W
θJC = 5°C/W
θCA = 67°C/W
6090fe
For more information www.linear.com/LTC6090
15
LTC6090/LTC6090-5
APPLICATIONS INFORMATION
In order to avoid damaging the device, the absolute
maximum junction temperature should not be exceeded
(TJMAX = 150°C). Junction temperature is determined
using the expression:
TJ = PD • θJA + TA
where PD is the power dissipated in the package, θJA is the
package thermal resistance from ambient to junction and
TA is the ambient temperature. For example, if the part has
a 140V supply voltage with 2.8mA of quiescent current
and the output is 20V above the negative rail sourcing
10mA, the total power dissipated in the device is (120V •
10mA) + (140V • 2.8mA) = 1.6W. Under these conditions
the ambient temperature should not exceed:
TA = TJMAX – (PD • θJA) = 150°C – (1.6W • 33°C/W) = 97°C.
and any additional heat sinking. The six SOA curves in
Figure 6 show the direct effect of θJA on SOA.
Stability with Large Resistor Values
A large feedback resistor along with the intrinsic input
capacitance will create an additional pole that affects
stability and causes peaking in the closed loop response.
To mitigate the peaking a small feedback capacitor placed
around the feedback resistor, as shown in Figure 7, will
reduce the peaking and overshoot. Figure 8 shows the
closed loop response with various feedback capacitors.
Additionally stray capacitance on the input pins should
be kept to a minimum. With pA input current, the PCB
traces should be routed as short and narrow as possible.
CF
Safe Operating Area
The safe operating area, or SOA, illustrates the voltage,
current, and temperature conditions where the device can
be reliably operated. Shown below in Figure 6 is the SOA
for the LTC6090. The SOA takes into account ambient
temperature and the power dissipated by the device. This
includes the product of the load current and difference
between the supply and output voltage, and the quiescent
current and supply voltage.
The LTC6090 is safe when operated within the boundaries
shown in Figure 6. Thermal resistance junction to case,
θJC, is rated at a constant 5°C/W. Thermal resistance
junction to ambient, θJA, is dependent on board layout
100
–
10k
PARASITIC INPUT
CAPACITANCE
+
LTC6090
6090 F07
Figure 7. LTC6090 with Feedback Capacitance
to Reduce Peaking
25
CF = 0pF
CF = 2pF
CF = 4pF
20
GAIN (dB)
CURRENT DENSITY LIMITED
TA = 25°C
LOAD CURRENT (mA)
100k
15
JUNCTION
TEMPERATURE
10 LIMITED
1
TA = 90°C
θJA = 33°C/W
θJA = 60°C/W
θJA = 100°C/W
θJA = 33°C/W
θJA = 60°C/W
θJA = 100°C/W
1
10
1
10
100
FREQUENCY (kHz)
1000
6090 F08
10
100
1000
SUPPLY VOLTAGE – LOAD VOLTAGE (V)
Figure 8. Closed Loop Response with
Various Feedback Capacitors
6090 F06
Figure 6. Safe Operating Area
16
6090fe
For more information www.linear.com/LTC6090
LTC6090/LTC6090-5
APPLICATIONS INFORMATION
The LTC6090 includes a slew enhancement circuit which
boosts the slew rate to 21V/μs making the part capable
of slewing rail-to-rail across the 140V output range in
less than 7μs. To optimize the slew rate and minimize
settling, stray capacitance should be kept to a minimum.
A feedback capacitor reduces overshoot and nonlinearities
associated with the slew enhancement circuit. The size of
the feedback capacitor should be tailored to the specific
board, supply voltage and load conditions.
Slewing is a nonlinear behavior and will affect distortion.
The relationship between slew rate and full power bandwidth is given in the relationship below.
SR = VO • ω
Where VO is the peak output voltage and ω is frequency in
radians. The fidelity of a large sine wave output is limited
by the slew rate. The graph in Figure 9 shows distortion
versus frequency for several output levels.
TOTAL HARMONIC DISTORTION + NOISE (%)
Slew Enhancement
10
VS = ±70V
AV = 5
RL = 10k
CF = 30pF
1
0.1
VOUT = 100VP-P
0.01
0.001
VOUT = 50VP-P
VOUT = 10VP-P
10
100
1000
10000
FREQUENCY (Hz)
6090 F09
Figure 9. Distortion vs Frequency for Large Output Swings
SELECT
CH1
10k
+
OD
COM
LTC6090
–
10k
Multiplexer Application
Several LTC6090s may be arranged to act as a high voltage analog multiplexer as shown in Figure 10. When using
this arrangement, it is possible for the output to affect the
source on the disabled amplifier’s noninverting input. The
inverting and noninverting inputs are clamped through
resistors and back to back diodes. There is a path for
current to flow from the multiplexer output through the
disabled amplifier’s feedback resistor, and through the
inputs to the noninverting input’s source. For example, if
the enabled amplifier has a –70V output, and the disabled
amplifier has a 5V input, there is 75V across the two resistors and the input pins. To keep this current below 1mA
the combined resistance of the RIN and feedback resistor
needs to be about 75k.
100000
100k
CH2
10k
MUX
OUT
+
OD
COM
LTC6090
–
10k
100k
6090 F10
Figure 10. Multiplexer Application
The output impedance of the disabled amplifier is greater
than 10MΩ at DC. The AC output impedance is shown in
the Typical Performance Characteristics section.
6090fe
For more information www.linear.com/LTC6090
17
LTC6090/LTC6090-5
TYPICAL APPLICATIONS
Gain of 20 Amplifier with a 40mA Protected Output Driver
Gain of 10 with Protected Output Current Doubler
200k
1%
40.2k
70V
47pF
2
VIN
2k
3
40.2k
–
7
4
2k
–
BAV99
5
8
TF
LTC6090 OD
+
70V
22.1k
1%
CZT5551
9
1k
6
604Ω
1k
1
+
VIN
12.1Ω
±70V
AT ±20mA
VOUT
–70V
BAV99
70V
CZT5401
–70V
100Ω
1%
TF
LTC6090 OD
200k
–
100Ω
1%
TF
LTC6090 OD
6090 TA02
6090 TA03
+
–70V
12V to ±70V Isolated Flyback Converter for Amplifier Supply
750311692 CRM1U-06M
1:1:5
VIN
12V
2.2µF
1M
•
BZX100A
VIN
BAV20W
EN/UVLO
562k
RFB
0.47µF
100V
•
+
100k
LTC6090
RREF
LT3511
•
10k
TC
–
CRM1U-06M
0.47µF
100V
VOUT2–
SW
VC
70V
VOUT1+
GND
BIAS
24.9k
–70V
4.7µF
2.2nF
6090 TA04
9V to ±65V Isolated Flyback Converter for Amplifier Supply
750311692
1:1:5
VIN
9V
100k
1
2
22k
3
LT8300
EN/UVLO
VIN
GND
RFB
SW
130k
5
4
4
3
4.7µF
8
•
65V
CMMR1U-2
6
•
1µF
130V
CMHZ5266B
+
LTC6090
7
•
–
CMMR1U-2
5
1µF
100V
6090 TA05
18
–65V
6090fe
For more information www.linear.com/LTC6090
LTC6090/LTC6090-5
TYPICAL APPLICATIONS
Audio Power Amplifier
50V
1N4148
40.2Ω
1nF
1N4148
100pF
CZT5401
1k
33.2k
IXTH50N20
100pF
VTOP
7
2
1k
3
1nF
5
LTC6090
+
4
9
100pF
8
1
2.49k
6
1N4148
LT1166
VIN
1k
100k
ILIM+
0.1Ω
1µF
1µH
VOUT
1µF
1N4148
0.1Ω
ILIM–
OUT
22nF
10Ω
20k
1k
SENSE–
100k
VBOTTOM
10k*
499Ω
499Ω
33.2k
CZT5551
1nF
1N4148
IXTH24P20
100pF
1N4148
39.2Ω
–50V
6090 TA06a
* USE SEVERAL SERIES RESISTORS TO REDUCE DISTORTION (i.e. 5 × 2kΩ).
Total Harmonic Distortion Plus Noise
Analyzer Passband 10Hz to 80kHz
TOTAL HARMONIC DISTORTION PLUS NOISE (%)
IN
–
SENSE+
0.100
0.010
4Ω AT 100W
0.001
8Ω AT 50W
0
10
100
1000
10000
FREQUENCY (Hz)
100000
6090 TA06b
6090fe
For more information www.linear.com/LTC6090
19
LTC6090/LTC6090-5
TYPICAL APPLICATIONS
High Current Pulse Amplifier
75pF
10k
70V
7
2
499Ω
IN
3
10k
–
+
9
2SK1057
IHSM-3825
1µH
8
LTC6090
4
499Ω
1k
5
6
1
499Ω
100Ω
–70V
OUT
2SJ161
6090 TA07
60V Step Response Into 10Ω
40
30
VOLTS
20
10
0
–10
–20
5µs/DIV
20
6090 TA07b
6090fe
For more information www.linear.com/LTC6090
LTC6090/LTC6090-5
TYPICAL APPLICATIONS
Simple 100W Audio Amplifier
50pF
2k
2k
2k
2k
2k
50V
100k
100Ω
2SK1057
100nF
7
2
499Ω
3
10k
5
4
499Ω
9
6.8k
8
LTC6090
+
6
IHSM-3825
1µH
1k
10k
OUT
BIAS
1
1k
6.8k
2SJ161
100nF
100Ω
2SJ161
100k
–50V
6090 TA08a
SET QUIESCENT SUPPLY CURRENT AT ABOUT 200mA WITH BIAS ADJUSTMENT.
SET QUIESCENT CURRENT TO 100mA IF PARALLEL MOSFETs ARE NOT USED (FOR 8Ω OR HIGHER).
Total Harmonic Distortion Plus
Noise vs Frequency
TOTAL HARMONIC DISTORTION PLUS NOISE (%)
IN
–
2SK1057
1
0.1
4Ω AT 100W
0.01
8Ω AT 50W
0.001
0.0001
100
1k
FREQUENCY (Hz)
10k
6090 TA08b
6090fe
For more information www.linear.com/LTC6090
21
LTC6090/LTC6090-5
TYPICAL APPLICATIONS
Wide Common Mode Range 10x Gain Instrumentation Amplifier
Typically <1mV Input-Referred Error
70V
7
3
+IN
2
+
5
8
LTC6090
–
4
9
6
22pF
10k*
1
100k
22pF
1
LT5400-2
100k
2
7
8
7
3
100k
–70V
205k
70V
7
3
–IN
70V
2
+
4
3
100k
5
9
22pF
8
6
100k
10k*
6
2
5
4
LTC6090
–
24.9k
100k
9
+
5
8
LTC6090
–
4
9
6
1
49.9Ω
OUT
–3dB at 45kHz
22pF
LTC6090 TA09
1
–70V
* THESE RESISTORS CAN BE 0Ω IF INPUT SIGNAL SOURCE IMPEDANCES ARE <20MΩ.
–70V
90
CMRR (dB)
80
70
60
50
40
1
10
CM FREQUENCY (kHz)
100
6090 TA09b
22
6090fe
For more information www.linear.com/LTC6090
LTC6090/LTC6090-5
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC6090#packaging for the most recent package drawings.
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev K)
Exposed Pad Variation BA
4.90 – 5.10*
(.193 – .201)
2.74
(.108)
2.74
(.108)
16 1514 13 12 1110
6.60 ±0.10
4.50 ±0.10
9
2.74
(.108)
2.74 6.40
(.108) (.252)
BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
1.10
(.0433)
MAX
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE16 (BA) TSSOP REV K 0913
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
6090fe
For more information www.linear.com/LTC6090
23
LTC6090/LTC6090-5
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC6090#packaging for the most recent package drawings.
S8E Package
8-Lead Plastic SOIC (Narrow .150 Inch) Exposed Pad
(Reference LTC DWG # 05-08-1857 Rev C)
.050
(1.27)
BSC
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
(1.143 ±0.127)
8
.089
.160 ±.005
(2.26) (4.06 ±0.127)
REF
.245
(6.22)
MIN
.150 – .157
.080 – .099
(2.032 – 2.530) (3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
1
.030 ±.005
(0.76 ±0.127)
TYP
.005 (0.13) MAX
7
5
6
.118
(2.99)
REF
3
2
.118 – .139
(2.997 – 3.550)
4
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
× 45°
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
.053 – .069
(1.346 – 1.752)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
1. DIMENSIONS IN
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010" (0.254mm)
24
4.
STANDARD LEAD STANDOFF IS 4mils TO 10mils (DATE CODE BEFORE 542)
5.
LOWER LEAD STANDOFF IS 0mils TO 5mils (DATE CODE AFTER 542)
4
5
.004 – .010
0.0 – 0.005
(0.101 – 0.254) (0.0 – 0.130)
.050
(1.270)
BSC S8E 1015 REV C
6090fe
For more information www.linear.com/LTC6090
LTC6090/LTC6090-5
REVISION HISTORY
REV
DATE
DESCRIPTION
A
11/12
Added ESD Statement.
PAGE NUMBER
2
B
9/13
Corrected schematics
16, 17, 18
C
6/14
Added LTC6090-5, Improved specs.
D
5/15
Removed ESD statement to reflect improved ESD performance.
Changed internal TFLAG circuit resistor values.
Updated Thermal Shutdown description.
Corrected application circuit resistor value.
E
11/15
Corrected resistor values
All
2
11, 12
13
19, 20, 21
20, 21
6090fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
information
www.linear.com/LTC6090
tion that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
25
LTC6090/LTC6090-5
TYPICAL APPLICATION
Extended Dynamic Range 1MΩ Transimpedance Photodiode Amplifier
0.3pF
10M
1%
IPD
125V
2
3
PHOTODIODE
SFH213
–
+
7
8
LTC6090
1
5
200k
1%
100mW
4
–3V
VOUT
6
22.1k
1%
–3V
VOUT = IPD • 1M
OUTPUT NOISE = 21µVRMS (1kHz – 40kHz)
OUTPUT OFFSET = 150µV MAXIMUM
BANDWIDTH = 40kHz (–3dB)
OUTPUT SWING = 0V TO 12V
6090 TA10
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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±250V Input Range G = 1, 10, Micropower,
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Pin Selectable Gain of 1 or 10
LT1991
Precision, 100µA Gain Selectable Amplifier
Pin Configurable as a Difference Amplifier, Inverting and Noninverting Amplifier
Quad Matched Resistor Network
Excellent Matching Specifications Over the Entire Temperature Range
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Matched Resistors
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Digital to Analog Converters
LTC2641/LTC2642 16-Bit VOUT DACs in 3mm × 3mm DFN
LTC2756
Serial 18-Bit SoftSpan IOUT DAC
Guaranteed Monotonic Over Temperature
18-Bit Settling Time: 2.1µs
Maximum 18-Bit INL Error: ±1 LSB Over Temperature
Flyback Controllers
LT3511
Monolithic High Voltage Isolated Flyback Converter 4.5V to 100V Input Voltage Range, No Opto-Coupler Required
LT8300
100VIN Micropower Isolated Flyback Converter
with 150V/260mA Switch
26 Linear Technology Corporation
6V to 100V Input Voltage Range. VOUT Set with a Single External Resistor
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC6090
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC6090
6090fe
LT 1115 REV E • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2012