Si53102-A1/A2/A3 PCI-E XPRESS G EN 1, G EN 2, G EN 3, AND G EN 4 1:2 F AN - OUT C L O C K B UFFER Features PCI-Express Gen 1, Gen 2, 2.5 V or 3.3 V Power supply Gen 3, and Gen 4 common clock Spread Spectrum Tolerant compliant Extended Temperature: Two low-power PCIe clock –40 to 85 °C outputs Small package 8-pin TDFN Supports Serial-ATA (SATA) at (1.4x1.6 mm) 100 MHz For PCIe Gen 1: Si53102-A1 No termination resistors required For PCIe Gen 2: Si53102-A2 for differential clocks For PCIe Gen 3/4: Si53102-A3 Ordering Information: See page 11 Applications Network Attached Storage Multi-function Printer Wireless Access Point Server/Storage Pin Assignments Description Si53102-A1/A2/A3 is a family of high-performance 1:2 PCIe fan output buffers. This low-additive-jitter clock buffer family is compliant to PCIe Gen 1, Gen 2, Gen 3, and Gen 4 specifications. The ultra-small footprint (1.4x1.6 mm) and industry-leading low power consumption make the Si53102-A1/A2/A3 the ideal clock solution for consumer and embedded applications. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcielearningcenter. DIFFIN 1 8 VDD DIFFIN 2 7 DIFF2 DIFF1 3 6 DIFF2 DIFF1 4 5 VSS Patents pending Functional Block Diagram VDD DIFF1 DIFFIN DIFFIN DIFF2 VSS Rev 1.2 12/15 Copyright © 2015 by Silicon Laboratories Si53102-A1/A2/A3 Si53102-A1/A2/A3 2 Rev 1.2 Si53102-A1/A2/A3 TABLE O F C ONTENTS Table of Contents Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3. Recommended Design Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Rev 1.2 3 Si53102-A1/A2/A3 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Supply Voltage (3.3 V Supply) VDD 3.3 V ± 10% 2.97 3.3 3.63 V Supply Voltage (2.5 V Supply) VDD 2.5 V ± 10% 2.25 2.5 2.75 V Table 2. DC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Operating Voltage (VDD = 3.3 V) VDD 3.3 V ± 10% 2.97 3.30 3.63 V Operating Voltage (VDD = 2.5 V) VDD 2.5 V ± 10% 2.25 2.5 2.75 V Operating Supply Current IDD Full Active — — 12 mA Input Pin Capacitance CIN Input Pin Capacitance — 3 5 pF COUT Output Pin Capacitance — — 5 pF Output Pin Capacitance 4 Rev 1.2 Si53102-A1/A2/A3 Table 3. AC Electrical Specifications Parameter Symbol Condition Min Typ Max Unit 10 100 175 MHz 0.6 — 4 V/ns DIFFIN at 0.7 V Input frequency DIFFIN and DIFFIN Rising/Falling Slew Rate Fin TR / TF Single ended measurement: VOL = 0.175 to VOH = 0.525 V (Averaged) Differential Input High Voltage VIH 150 — — mV Differential Input Low Voltage VIL — — –150 mV Crossing Point Voltage at 0.7 V Swing VOX Single-ended measurement 250 — 550 mV Vcross Variation Over All edges VOX Single-ended measurement — — 140 mV VRB –100 — 100 mV TSTABLE 500 — — ps — 1.15 V –0.3 — — V Differential Ringback Voltage Time before Ringback Allowed Absolute Maximum Input Voltage VMAX Absolute Minimum Input Voltage VMIN DIFFIN and DIFFIN Duty Cycle TDC Measured at crossing point VOX 45 — 55 % Rise/Fall Matching TRFM Determined as a fraction of 2 x (TR – TF)/(TR + TF) — — 20 % TDC Measured at crossing point VOX 45 — 55 % TSKEW Measured at 0 V differential — — 100 ps FACC All output clocks — — 100 ppm tr/f2 Measured differentially from ±150 mV 0.6 — 4.0 V/ns PCIe Gen 1 Pk-Pk Additive Jitter PkPkGEN1 PCIe Gen 1 Si53102-A1 — — 10 ps PCIe Gen 2 Additive Phase Jitter RMSGEN2 10 kHz < F < 1.5 MHz, Si53102-A2 — — 0.50 ps PCIe Gen 2 Additive Phase Jitter RMSGEN2 1.5 MHz < F < Nyquist, Si53102-A2 — — 0.50 ps PCIe Gen 3 Additive Phase Jitter RMSGEN3 Includes PLL BW 2–4 MHz, CDR = 10 MHz, Si53102-A3 — — 0.20 ps PCIe Gen 4 Additive Phase Jitter RMSGEN4 PCIe Gen 4 — — 0.20 ps 300 — 550 mV — — 3.0 ms DIFF Clocks Duty Cycle Output Skew Frequency Accuracy Slew Rate Crossing Point Voltage at 0.7 V Swing VOX Enable/Disable and Setup Clock Stabilization from Powerup TSTABLE Power up to first output Notes: 1. Visit www.pcisig.com for complete PCIe specifications. 2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. Rev 1.2 5 Si53102-A1/A2/A3 Table 4. Thermal Conditions Parameter Symbol Condition Min Temperature, Storage TS Non-functional Temperature, Operating Ambient TA Temperature, Junction Typ Max Unit –65 150 °C Functional –40 85 °C TJ Functional — 150 °C Dissipation, Junction to Case JC JEDEC (JESD 51) — 38.3 °C/W Dissipation, Junction to Ambient JA JEDEC (JESD 51) — 90.4 °C/W Table 5. Absolute Maximum Conditions Parameter Main Supply Voltage Input Voltage ESD Protection (Human Body Model) Flammability Rating Symbol Condition VDD_3.3V Min Typ Max Unit — 4.6 V VIN Relative to VSS –0.5 4.6 VDC ESDHBM JEDEC (JESD 22-A114) 2000 — V UL-94 UL (Class) V–0 Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during powerup. Power supply sequencing is NOT required. 6 Rev 1.2 Si53102-A1/A2/A3 2. Test and Measurement Setup Figures 1 through 3 show the test load configuration for the differential clock signals. M e a s u re m e n t P o in t L1 O UT+ 5 0 2 pF L1 = 5" M e a s u re m e n t P o in t L1 O UT- 5 0 2 pF Figure 1. 0.7 V Differential Load Configuration The outputs from this device can also support LVDS, LVPECL, or CML differential signaling levels using alternative termination. For recommendations on how to achieve this, see “AN781: Alternative Output Termination for Si5213x, Si5214x, Si5121x, and Si5315x PCIe Clock Generator and Buffer Families” at www.silabs.com. Figure 2. Differential Measurement for Differential Output Signals (AC Parameters Measurement) Rev 1.2 7 Si53102-A1/A2/A3 Figure 3. Single-Ended Measurement for Differential Output Signals (AC Parameters Measurement) 8 Rev 1.2 Si53102-A1/A2/A3 3. Recommended Design Guideline 3.3V / 2.5V FB VDD 4.7uF 0.1uF Si53102 Note: FB Specifications: DC resistance 0.1–0.3 Impedance at 100 MHz > 1000 Figure 4. Recommended Application Schematic Rev 1.2 9 Si53102-A1/A2/A3 4. Pin Descriptions DIFFIN 1 8 VDD DIFFIN 2 7 DIFF2 DIFF1 3 6 DIFF2 DIFF1 4 5 VSS Figure 5. 8-Pin TDFN Table 6. Si53102-Ax-GM 8-Pin TDFN Descriptions Pin # Name Type 1 DIFFIN O, DIF 0.7 V, 100 MHz differentials clock input 2 DIFFIN O, DIF 0.7 V, 100 MHz differentials clock input 3 DIFF1 O, DIF 0.7 V, 100 MHz differential clock output 4 DIFF1 O, DIF 0.7 V, 100 MHz differential clock output 5 GND GND 6 DIFF2 O, DIF 0.7 V, 100 MHz differential clock output 7 DIFF2 O, DIF 0.7 V, 100 MHz differential clock output 8 VDD PWR 10 Description Ground 2.5 V or 3.3 V Power supply Rev 1.2 Si53102-A1/A2/A3 5. Ordering Guide Part Number Package Type Temperature Si53102-A1-GM 8-pin TDFN Extended, –40 to 85 C Si53102-A1-GMR 8-pin TDFN—Tape and Reel Extended, –40 to 85 C Si53102-A2-GM 8-pin TDFN Extended, –40 to 85 C Si53102-A2-GMR 8-pin TDFN—Tape and Reel Extended, –40 to 85 C Si53102-A3-GM 8-pin TDFN Extended, –40 to 85 C Si53102-A3-GMR 8-pin TDFN—Tape and Reel Extended, –40 to 85 C Rev 1.2 11 Si53102-A1/A2/A3 6. Package Outlines Figure 6. 8-Pin TDFN Package Drawing Table 7. Package Diagram Dimensions Dimension Min Nom Max A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A3 b 0.20 REF. 0.15 0.20 D D2 0.25 1.60 BSC 1.00 1.05 e 0.40 BSC E 1.40 BSC 1.10 E2 0.20 0.25 0.30 L 0.30 0.35 0.40 aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.07 eee 0.08 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 12 Rev 1.2 Si53102-A1/A2/A3 7. PCB Land Pattern Figure 7. Si53102 8-Pin TDFN Land Pattern Table 8. Si53102 8-Pin Land Pattern Dimensions Dimension mm C 1.40 E 0.40 X1 0.75 Y1 0.20 X2 0.25 Y2 1.10 Notes: General 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1 for all pads. Card Assembly 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev 1.2 13 Si53102-A1/A2/A3 DOCUMENT CHANGE LIST Revision 0.4 to Revision 1.0 Updated Table 3 on page 5. Updated input frequency min and max specs. Updated "2. Test and Measurement Setup" on page 7. Added text and reference to AN781. Revision 1.0 to Revision 1.1 Moved “3. Recommended Design Guideline” to page 9. Corrected Figure 5 title on page 10. Corrected Table 6 title on page 10. Corrected Figure 6 title on page 12. Added "7. PCB Land Pattern" on page 13. Revision 1.1 to Revision 1.2 Updated Features on page 1. Updated Description on page 1. Updated specs in Table 3, “AC Electrical Specifications,” on page 5. 14 Rev 1.2 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. 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