SL28EB742

SL28EB742
EP RO C L O C K ® G E N E R A TO R F O R I NTEL ® C K 5 0 5 C O M P L I A N C E
Features
 Compliant Intel CK505 Clock spec
 25 MHz ouput
 Low power push-pull type differential  Buffered Reference Clock
output buffers
14.318 MHz
 Integrated resistors on differential
 14.318 MHz Crystal Input or Clock
clocks
input
 Wireless friendly 3-bits slew rate
 I2C support with readback
control on single-ended clocks
capabilities
 Differential CPU clocks with pin
 Triangular Spread Spectrum profile
selectable frequency
for maximum electromagnetic
interference (EMI) reduction
Selectable Differential SATA or SRC  Industrial Temperature:
clocks
–40 to 85 °C
96 MHz Differential DOT clock
 3.3 V power supply
48 MHz USB clock
 56-pin QFN package
Selectable 12 or 48 MHz clock
 100 MHz Differential SRC clocks




Ordering Information:
See page 39
Pin Assignments
CPU
SRC
SATA DOT96 48M
x2/x3
x4/x7
x0/x1
x1
x1/2
48M/
12M
33M
25M
14.318M
x1
x2
x1
x1
CKPWRGD/PD#
Selectable Differential SRC or CPU Clock
EProClock® Programmable Technology
 > 4000 bits of configurations
Differential amplitude control
 Can be configured through SMBus
Differential and single-ended
or hard coded
 Custom frequency sets
 Differential skew control on true or
compliment or both
 Differential duty cycle control on true
or compliment or both
slew rate control
Program Internal or External
series resistor on single-ended
clocks
Program different spread
profiles
Program different spread
modulation rate
Selectable Differential SRC or CPU Clock
CPU
SRC
SATA
DOT96
48M
48M/
12M
33M
25M
14.318M
x2/x3
x4/x7
x0/x1
x1
x1/2
x1
x2
x1
x1
* Internal 100K-ohm pull-up resistor
** Internal 100K-ohm pull down resistor
Patents pending
Rev. 1.0 12/13
Copyright © 2013 by Silicon Laboratories
SL28EB742
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
SL28EB742
Description
The SL28EB742 is a high-performance clock generator supporting Intel Cedarview platforms. The SL28EB742 is rated to
support extended grade temperature. Utilizing an inexpensive 14.318 MHz crystal, it is capable of supporting multiple
frequencies from four PLLs. The CPU clock can support a frequency range from 83.33 to 166 MHz by configuration of two strap
pins. With a combination of strap pins and an I2C interface, the device allows maximum configurability.
EProClock® is the world’s first non-volatile programmable clock. The EProClock® technology allows board designer to promptly
achieve optimum compliance and clock signal integrity; historically, attainable typically through device and/or board redesigns.
EProClock® technology can be configured through SMBus or hard coded.
Functional Block Diagram
XIN
XOUT
Crystal/
CLKIN
REF [1:0]
PLL 1
(SSC)
CPU
Divider
SRC
FS [ C:A]
PCI
PLL 4
(non-SSC)
CPU_STP#
Divider
SATA / SRC0
ITP_EN
PCI/SRC_STP#
PLL 3
(non-SSC)
DOT96
Divider
CLKREQ[3:1]
48M
SEL_SATA
PLL 2
(non-SSC)
12 / 48M
Divider
SEL_12_48
25M
OTP
SCLK
SDATA
Logic Core
VR
CLKPWRGD/
PD#
2
Rev. 1.0
SL28EB742
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1. Powerdown (PD#) Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2. Powerdown (PD#) Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3. Powerdown (PD#) Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4. CPU_STP# Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5. CPU_STP# Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6. PCI/SRC_STP# Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7. PCI/SRC_STP# Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1. Single-ended Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.2. Differential Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1. Frequency Select Pin FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2. Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5. Pin Descriptions: 56-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Rev. 1.0
3
SL28EB742
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD = 3.3 V, TA = 25 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD(industrial)
3.3 V ±5%
3.13
3.3
3.46
V
VDD(commercial)
3.3 V ±10%
2.97
3.3
3.63
V
Supply Voltage (extended)
Supply Voltage (commercial)
Table 2. DC Electrical Specifications
Parameter
Symbol
Test Condition
Min
Max
Unit
3.3 V Operating Voltage
VDD core
3.3 ± 5%
3.135
3.465
V
3.3 V Input High Voltage
(SE)
VIH
2.0
VDD +
0.3
V
3.3 V Input Low Voltage (SE)
VIL
VSS –
0.3
0.8
V
Input High Voltage
VIHI2C
SDATA, SCLK
2.2
—
V
Input Low Voltage
VILI2C
SDATA, SCLK
—
1.0
V
FS Input High Voltage
VIH_FS
0.7
VDD+0.
3
V
FS Input Low Voltage
VIL_FS
VSS –
0.3
0.35
V
Input High Leakage Current
IIH
Except internal pull-down resistors,
0 < VIN < VDD
—
5
A
Input Low Leakage Current
IIL
Except internal pull-up resistors,
0 < VIN < VDD
–5
—
A
3.3 V Output High Voltage
(SE)
VOH
IOH = –1 mA
2.4
—
V
3.3 V Output Low Voltage
(SE)
VOL
IOL = 1 mA
—
0.4
V
High-impedance Output
Current
IOZ
–10
10
A
Input Pin Capacitance
CIN
1.5
5
pF
6
pF
Output Pin Capacitance
Pin Inductance
Power Down Current
Dynamic Supply Current
4
COUT
LIN
—
7
nH
IDD_PD
—
1
mA
—
115
mA
IDD_3.3 V
All outputs enabled. SE clocks with 5”
traces. Differential clocks with 5” traces.
Loading per CK505 spec.
Rev. 1.0
SL28EB742
Table 3. AC Electrical Specifications
Parameter
Symbol
Test Condition
Min
Max
Unit
LACC
Measured at VDD/2 differential
—
250
ppm
TDC
Measured at VDD/2
47
53
%
CLKIN Rise and Fall Times
TR/TF
Measured between 0.2 VDD and
0.8 VDD
0.5
4.0
V/ns
CLKIN Cycle to Cycle Jitter
TCCJ
Measured at VDD/2
—
250
ps
CLKIN Long Term Jitter
TLTJ
Measured at VDD/2
350
ps
Input High Voltage
VIH
XIN / CLKIN pin
2
VDD+0.3
V
Input Low Voltage
VIL
XIN / CLKIN pin
—
0.8
V
Input High Current
IIH
XIN / CLKIN pin, VIN = VDD
35
µA
Input Low Current
IIL
XIN / CLKIN pin, 0 < VIN <0.8
–35
—
µA
TDC
Measured at 0 V differential
45
55
%
Long-term Accuracy
Clock Input
CLKIN Duty Cycle
CPU at 0.7 V
CPU Duty Cycle
83.33 MHz CPU Period
TPERIOD
Measured at 0 V differential at 0.1s 11.99880 12.00120
ns
83.33 MHz CPU Period, SSC
TPERIODSS
Measured at 0 V differential at 0.1s 12.02887 12.03128
2
ns
83.33 MHz CPU Absolute Period
TPERIODAbs
83.33 MHz CPU Absolute Period, TPERIODSSAbs
SSC
100 MHz CPU Period
TPERIOD
Measured at 0 V differential at
1clock
11.18969 12.16344
ns
Measured at 0 V differential at 1
clock
11.89687 12.16344
ns
Measured at 0 V differential at 0.1s 9.99900
10.0010
ns
Measured at 0 V differential at 0.1s 10.02406 10.02607
ns
100 MHz CPU Period, SSC
TPERIODSS
100 MHz CPU Absolute Period
TPERIODAbs
Measured at 0 V differential at
1clock
9.87400
10.1260
ns
100 MHz CPU Absolute Period,
SSC
TPERIODSSAbs
Measured at 0 V differential at
1 clock
9.87406
10.1762
ns
TPERIOD
Measured at 0 V differential at 0.1s 7.49925
7.50075
ns
133 MHz CPU Period, SSC
TPERIODSS
Measured at 0 V differential at 0.1s 7.51804
7.51955
ns
133 MHz CPU Absolute Period
TPERIODAbs
Measured at 0 V differential at
1 clock
7.41425
7.58575
ns
133 MHz CPU Absolute period,
SSC
TPERIODSSAbs
Measured at 0 V differential at
1 clock
7.41430
7.62340
ns
133 MHz CPU Period
Rev. 1.0
5
SL28EB742
Table 3. AC Electrical Specifications (Continued)
Parameter
Symbol
Test Condition
Min
Max
Unit
166 MHz CPU Period
TPERIOD
Measured at 0 V differential at 0.1s 5.99940
6.00060
ns
166 MHz CPU Period, SSC
TPERIODSS
Measured at 0 V differential at 0.1s 6.01444
6.01564
ns
166 MHz CPU Absolute period
TPERIODAbs
Measured at 0 V differential at
1 clock
5.91440
6.08560
ns
166 MHz CPU Absolute period,
SSC
TPERIODSSAbs
Measured at 0 V differential at
1 clock
5.91444
6.11572
ns
CPU Cycle to Cycle Jitter
TCCJ
Measured at 0 V differential
—
85
ps
CPU Cycle to Cycle Jitter for
CPU 2
TCCJ (CPU2)
Measured at 0 V differential
—
125
ps
CPU0 to CPU1 skew
Skew
Measured at 0 V differential
—
100
ps
Long-term Accuracy
LACC
Measured at 0 V differential
—
100
ppm
CPU Rising/Falling Slew rate
T R / TF
Measured differentially from
±150 mV
2.5
8
V/ns
Rise/Fall Matching
TRFM
Measured single-endedly from
±75 mV
—
20
%
Voltage High
VHIGH
1.15
V
Voltage Low
VLOW
–0.3
—
V
Crossing Point Voltage at 0.7 V
Swing
VOX
300
550
mV
45
55
%
SRC at 0.7 V
Measured at 0 V differential
SRC Duty Cycle
TDC
100 MHz SRC Period
TPERIOD
Measured at 0 V differential at 0.1s 9.99900
10.0010
ns
100 MHz SRC Period, SSC
TPERIODSS
Measured at 0 V differential at 0.1s 10.02406 10.02607
ns
100 MHz SRC Absolute Period
TPERIODAbs
Measured at 0 V differential at 1
clock
9.87400
10.1260
ns
100 MHz SRC Absolute Period,
SSC
TPERIODSSAbs
Measured at 0 V differential at 1
clock
9.87406
10.1762
ns
Any SRC Clock Skew from the
earliest bank to the latest bank
TSKEW(win-
Measured at 0 V differential
—
3.0
ns
SRC Cycle to Cycle Jitter
TCCJ
Measured at 0 V differential
—
85
ps
SRC Long Term Accuracy
LACC
Measured at 0 V differential
—
100
ppm
SRC Rising/Falling Slew Rate
T R / TF
Measured differentially from
±150 mV
2.5
8
V/ns
6
dow)
Rev. 1.0
SL28EB742
Table 3. AC Electrical Specifications (Continued)
Parameter
Symbol
Test Condition
Min
Max
Unit
Measured single-endedly from
±75 mV
—
20
%
1.15
V
Rise/Fall M-atching
TRFM
Voltage High
VHIGH
Voltage Low
VLOW
–0.3
—
V
Crossing Point Voltage at 0.7 V
Swing
VOX
300
550
mV
45
55
%
DOT96 at 0.7 V
DOT96 Duty Cycle
TDC
DOT96 Period
TPERIOD
Measured at 0 V differential at 0.1s 10.4156
10.4177
ns
DOT96 Absolute Period
TPERIODAbs
Measured at 0 V differential at 0.1s 10.1656
10.6677
ns
DOT96 Cycle to Cycle Jitter
TCCJ
Measured at 0 V differential at
1 clock
—
250
ps
DOT96 Long Term Accuracy
LACC
Measured at 0V differential at
1 clock
—
100
ppm
DOT96 Rising/Falling Slew Rate
T R / TF
Measured differentially from
±150 mV
2.5
8
V/ns
Rise/Fall Matching
TRFM
Measured single-endedly from
±75 mV
—
20
%
Voltage High
VHIGH
1.15
V
Voltage Low
VLOW
–0.3
—
V
Crossing Point Voltage at 0.7 V
Swing
VOX
300
550
mV
Measured at 0 V differential
SATA at 0.7 V
SATAM Duty Cycle
TDC
Measured at 0V differential
45
55
%
SATA Cycle to Cycle Jitter
TCCJ
Measured at 0V differential at
1 clock
—
125
ps
SATA Long Term Accuracy
LACC
Measured at 0V differential at
1 clock
—
100
ppm
SATA Rising/Falling Slew Rate
TR / TF
Measured differentially from
±150 mV
2.5
8
V/ns
Rise/Fall Matching
TRFM
Measured single-endedly from
±75 mV
—
20
%
Voltage High
VHIGH
1.15
V
Voltage Low
VLOW
—
V
–0.3
Rev. 1.0
7
SL28EB742
Table 3. AC Electrical Specifications (Continued)
Parameter
Crossing Point Voltage at 0.7 V
Swing
Symbol
Test Condition
VOX
Min
Max
Unit
300
550
mV
45
55
%
PCI/PCIF at 3.3 V
PCI Duty Cycle
TDC
Measurement at 1.5 V
Spread Disabled PCIF/PCI
Period
TPERIOD
Measurement at 1.5 V
29.99700 30.00300
ns
Spread Enabled PCIF/PCI Period TPERIODSS
Measurement at 1.5 V
30.08421 30.23459
ns
Spread Disabled PCIF/PCI
Period
Measurement at 1.5 V
29.49700 30.50300
ns
Measurement at 1.5 V
29.56617 30.58421
ns
TPERIODAbs
Spread Enabled PCIF/PCI Period TPERIODSSAbs
Spread Enabled PCIF and PCI
High Time
THIGH
Measurement at 2 V
12.27095 16.27995
ns
Spread Enabled PCIF and PCI
Low Time
TLOW
Measurement at 0.8 V
11.87095 16.07995
ns
Spread Disabled PCIF and PCI
High Time
THIGH
Measurement at 2.0 V
12.27365 16.27665
ns
Spread Disabled PCIF and PCI
Low Time
TLOW
Measurement at 0.8 V
11.87365 16.07665
ns
PCIF/PCI Rising/Falling
Slew Rate
TR / TF
Measured between 0.8 V and 2.0 V
1.0
4.0
V/ns
Any PCI clock to Any PCI clock
Skew
TSKEW
Measurement at 1.5 V
—
1000
ps
PCIF and PCI Cycle to
Cycle Jitter
TCCJ
Measurement at 1.5 V
—
300
ps
PCIF/PCI Long Term Accuracy
LACC
Measurement at 1.5 V
—
100
ppm
Duty Cycle
TDC
Measurement at 1.5 V
45
55
%
48 MHz Period
TPERIOD
Measurement at 1.5 V
20.83125 20.83542
ns
48 MHz Absolute Period
TPERIODAbs
Measurement at 1.5 V
20.48125 21.18542
ns
48 MHz High Time
THIGH
Measurement at 2 V
8.216563 11.15198
ns
48 MHz Low Time
TLOW
Measurement at 0.8 V
7.816563 10.95198
ns
Rising and Falling Edge Rate
TR / TF (48M) Measured between 0.8 V and 2.0 V
1.0
2.0
V/ns
Rising and Falling Edge Rate
T R / TF
(12_48M)
Measured between 0.8 V and 2.0 V
1.0
2.0
V/ns
Cycle to Cycle Jitter
TCCJ
Measurement at 1.5 V
—
300
ps
48M, 12_48M at 3.3 V
8
Rev. 1.0
SL28EB742
Table 3. AC Electrical Specifications (Continued)
Parameter
Test Condition
Min
Max
Unit
LACC
Measurement at 1.5 V
—
100
ppm
Duty Cycle
TDC
Measurement at 1.5 V
45
55
%
Period
TPERIOD
Measurement at 1.5 V
39.996
40.004
ns
Absolute Period
TPERIODAbs
Measurement at 1.5 V
Rising and Falling Edge Rate
T R / TF
Cycle to Cycle Jitter
25M Long Term Accuracy
48M Long Term Accuracy
Symbol
25M at 3.3 V
39.32360 40.67640
ns
Measured between 0.8 V and 2.0 V
1.0
4.0
V/ns
TCCJ
Measurement at 1.5 V
—
300
ps
LACC
Measured at 1.5 V
—
100
ppm
Duty Cycle
TDC
Measurement at 1.5 V
45
55
%
Period
TPERIOD
Measurement at 1.5 V
69.82033 69.86224
ns
Absolute Period
TPERIODAbs
Measurement at 1.5 V
68.83429 70.84826
ns
High Time
THIGH
Measurement at 2 V
29.97543 38.46654
ns
Low Time
TLOW
Measurement at 0.8 V
29.57543 38.26654
ns
Rising and Falling Edge Rate
T R / TF
Cycle to Cycle Jitter
Long Term Accuracy
14.318M, at 3.3 V
Measured between 0.8 V and 2.0 V
1.0
4.0
V/ns
TCCJ
Measurement at 1.5 V
—
500
ps
LACC
Measurement at 1.5 V
—
100
ppm
—
1.8
ms
10.0
—
ns
ENABLE/DISABLE and SET-UP
Clock Stabilization from
Powerup
TSTABLE
Stop clock Set-up Time
TSS
Rev. 1.0
9
SL28EB742
Table 4. Thermal Conditions
Parameter
Symbol
Condition
Min
Max
Unit
Temperature, Storage
TS
Non-functional
–65
150
°C
Temperature, Operating Ambient,
Extended
TA
Functional
–40
85
°C
Temperature, Operating Ambient,
Commercial
TA
Functional
0
70
°C
Temperature, Junction
TJ
Functional
—
150
°C
Dissipation, Junction to Case
ØJC
JEDEC (JESD 51)
—
20
°C/W
Dissipation, Junction to Ambient
ØJA
JEDEC (JESD 51)
—
60
°C/W
Note: For multiple supplies, the voltage on any input or I/O pin cannot exceed the power pin during powerup.
Power supply sequencing is not required.
Table 5. Absolute Maximum Conditions
Parameter
Symbol
Test Condition
Min
Max
Unit
Main Supply Voltage
VDD_3.3 V
Functional
—
4.6
V
Input Voltage
VIN
Relative to VSS
–0.5
4.6
VDC
Temperature, Storage
TS
Non-functional
–65
150
°C
Temperature, Operating
Ambient
TA
Functional
–40
85
°C
Temperature, Junction
TJ
Functional
—
150
°C
Dissipation, Junction to
Case
ØJC
JEDEC (JESD 51)
—
20
°C/
W
Dissipation, Junction to
Ambient
ØJA
JEDEC (JESD 51)
—
60
°C/
W
ESD Protection (Human
Body Model)
ESDHBM
JEDEC (JESD 22 - A114)
2000
—
V
Flammability Rating
UL-94
UL (Class)
V–0
Moisture Sensitivity Level
MSL
JEDEC (J-STD-020)
1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
10
Rev. 1.0
SL28EB742
2. Functional Description
2.1. Powerdown (PD#) Clarification
The CKPWRGD/PD# pin is a dual-function pin. During initial powerup, the pin functions as CKPWRGD. Once
CKPWRGD has been sampled high by the clock chip, the pin assumes PD# functionality. The PD# pin is an
asynchronous active low input used to shut off all clocks cleanly before shutting off power to the device. This signal
is synchronized internally to the device before powering down the clock synthesizer. PD# is also an asynchronous
input for powering up the system. When PD# is asserted low, clocks are driven to a low value and held before
turning off the VCOs and the crystal oscillator.
2.2. Powerdown (PD#) Assertion
When PD# is sampled low by two consecutive rising edges of CPUC, all single-ended outputs clocks will be held
low on their next high-to-low transition and differential clocks will be held low. When powerdown mode is desired as
the initial power on state, PD# must be asserted low in less than 10 µs after asserting CKPWRGD.
.
Table 6. Output Driver Status during CPU_STP and PCIS_STP#
Single-ended
Clocks
Differential Clocks
CPU_STP#
Asserted
PCI_STP#
Asserted
CLKREQ#
Asserted
SMBus OE
Disabled
Stoppable
Running
Driven low
Running
Driven low
Non-stoppable
Running
Running
Running
Stoppable
Clock driven high
Clock driven high
Clock driven low Clock driven low
Clock driven low
Clock driven low
Clock driven low
Running
Running
Running
Non-stoppable
Table 7. Output Driver Status
All Single-ended Clocks
PD# = 0 (Powerdown)
All Differential Clocks
w/o Strap
w/ Strap
Clock
Clock#
Low
Hi-z
Low
Low
Rev. 1.0
11
SL28EB742
2.3. Powerdown (PD#) Deassertion
The powerup latency is less than 1.8 ms. This is the time from the deassertion of the PD# pin or the ramping of the
power supply until the time that stable clocks are generated from the clock chip. All differential outputs stopped in a
three-state condition resulting from powerdown are driven high in less than 300 µs of PD# deassertion to a voltage
greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs are enabled within a
few clock cycles. Figure 2 is an example showing the relationship of clocks coming up.
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 1. Powerdown Assertion Timing Waveform
Tstable
<1.8 ms
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33MHz
REF
Tdrive_PWRDN
<300  s, >200 mV
Figure 2. Powerdown Deassertion Timing Waveform
12
Rev. 1.0
SL28EB742
FS_A, FS_B,FS_C
CKPWRGD
PWRGD_VRM
0.2-0.3 ms
Delay
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
State 0
Wait for
VTT_PWRGD#
State 1
State 2
Off
Off
Device is not affected,
VTT_PWRGD is ignored
Sample Sels
State 3
On
On
Figure 3. CKPWRGD Timing Diagram
Rev. 1.0
13
SL28EB742
2.4. CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs
that are set with the I2C configuration to be stoppable are stopped within two to six CPU clock periods after being
sampled by two rising edges of the internal CPUC clock. The final states of the stopped CPU signals are
CPUT = High and CPUC = Low.
2.5. CPU_STP# Deassertion
The deassertion of the CPU_STP# signal causes all stopped CPU outputs to resume normal operation in a
synchronous manner. No short or stretched clock pulses are produced when the clock resumes. The maximum
latency from the deassertion to active outputs is no more than two CPU clock cycles.
CPU_STP
CPUT
CPUC
Figure 4. CPU_STP# Assertion Waveform
CPU_STP
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP, 10 ns>200 mV
Figure 5. CPU_STP# Deassertion Waveform
14
Rev. 1.0
SL28EB742
2.6. PCI/SRC_STP# Assertion
The PCI/SRC_STP# signal is an active low input used for synchronously stopping and starting the PCI outputs
while the rest of the clock generator continues to function. The set-up time for capturing PCI/SRC_STP# going low
is 10 ns (tSU) (refer to Figure 6). The PCIF and SRC clocks are affected by the PCI/SRC pin if their corresponding
control bit in the I2C register is set to allow them to be free running. For SRC clocks assertion description, refer to
the CPU_STP# descriptions in Section 2.4 and Section 2.5.
Figure 6. PCI/SRC_STP# Assertion Waveform
2.7. PCI/SRC_STP# Deassertion
The deassertion of the PCI/SRC_STP# signal causes all PCI and stoppable PCIF to resume running in a
synchronous manner within two PCI clock periods and after PCI/SRC_STP# transitions to a high level. Similarly,
PCI/SRC_STP# deassertion will cause stoppable SRC clocks to resume running. For an SRC clocks deassertion
description, refer to the CPU_STP# description Section 2.4 and Section 2.5.
Figure 7. PCI/SRC_STP# Deassertion Waveform
Rev. 1.0
15
SL28EB742
3. Test and Measurement Setup
3.1. Single-ended Clocks
Figure 8 shows the test load configuration for single-ended clock output signals.
Figure 8. Single-ended Clocks Single Load Configuration
Figure 9. Single-ended Output Signals (for AC Parameters Measurement)
16
Rev. 1.0
SL28EB742
3.2. Differential Clock Signals
Figure 10 shows the test load configuration for differential clock signals.
Figure 10. 0.7 V Differential Load Configuration
Figure 11. Differential Measurement for Differential Output Signals
(for AC Parameters Measurement)
Rev. 1.0
17
SL28EB742
Figure 12. Single-ended Measurement for Differential Output Signals
(for AC Parameters Measurement)
18
Rev. 1.0
SL28EB742
4. Control Registers
4.1. Frequency Select Pin FS
Apply the appropriate logic levels to FS inputs before CKPWRGD assertion to achieve host clock frequency
selection. When the clock chip sampled HIGH on CKPWRGD and indicates that VTT voltage is stable then FS
input values are sampled. This process employs a one-shot functionality and once the CKPWRGD sampled a valid
HIGH, all other FS, and CKPWRGD transitions are ignored except in test mode.
Table 8. Frequency Select Pin (FS)
SEL_SATA
FSC
FSB
FSA
CPU
SRC
SATA
PCI
0
0
0
0
100.00
100.00
100.00
33.33
0
0
0
1
100.00
100.00
100.00
33.33
0
0
1
0
83.33
100.00
100.00
33.33
0
0
1
1
83.33
100.00
100.00
33.33
0
1
0
0
133.33
100.00
100.00
33.33
0
1
0
1
133.33
100.00
100.00
33.33
0
1
1
0
166.67
100.00
100.00
33.33
0
1
1
1
166.67
100.00
100.00
33.33
1
0
0
0
100.00
100.00
100.00
33.33
1
0
0
1
100.00
100.00
100.00
33.33
1
0
1
0
83.33
100.00
100.00
33.33
1
0
1
1
83.33
100.00
100.00
33.33
1
1
0
0
133.33
100.00
100.00
33.33
1
1
0
1
133.33
100.00
100.00
33.33
1
1
1
0
166.67
100.00
100.00
33.33
1
1
1
1
166.67
100.00
100.00
33.33
Rev. 1.0
19
SL28EB742
4.2. Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through
the Serial Data Interface, various device functions, such as individual clock output buffers are individually enabled
or disabled. The registers associated with the Serial Data Interface initialize to their default setting at power-up.
The use of this interface is optional. Clock device register changes are normally made at system initialization, if any
are required. The interface cannot be used during system operation for power management functions.
4.3. Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the
controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most
significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read
operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded
in the command code described in Table 9.
The block write and block read protocol is outlined in Table 10 while Table 11 outlines byte write and byte read
protocol. The slave receiver address is 11010010 (D2h).
Table 9. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation; 1 = Byte read or byte write operation.
Byte offset for byte read or byte write operation. For block read or block write operations, these bits
should be '0000000'.
Table 10. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
Description
Bit
Start
1
Slave address–7 bits
8:2
Description
Start
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
19
27:20
28
36:29
37
45:38
20
Block Read Protocol
Command Code–8 bits
18:11
Command Code–8 bits
Acknowledge from slave
19
Acknowledge from slave
Byte Count–8 bits
20
Repeat start
Acknowledge from slave
27:21
Slave address–7 bits
Data byte 1–8 bits
28
Read = 1
Acknowledge from slave
29
Acknowledge from slave
Data byte 2–8 bits
46
Acknowledge from slave
....
Data Byte /Slave Acknowledges
37:30
38
46:39
Rev. 1.0
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
SL28EB742
Table 10. Block Read and Block Write Protocol (Continued)
Block Write Protocol
Bit
Block Read Protocol
Description
....
Data Byte N–8 bits
....
Acknowledge from slave
....
Stop
Bit
47
55:48
Description
Acknowledge
Data byte 2 from slave–8 bits
56
Acknowledge
....
Data bytes from slave / Acknowledge
....
Data Byte N from slave–8 bits
....
NOT Acknowledge
....
Stop
Table 11. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
Byte Read Protocol
Description
Bit
Start
1
Slave address–7 bits
8:2
Description
Start
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
19
27:20
Command Code–8 bits
18:11
Command Code–8 bits
Acknowledge from slave
19
Acknowledge from slave
Data byte–8 bits
20
Repeated start
28
Acknowledge from slave
29
Stop
27:21
28
Read
29
Acknowledge from slave
37:30
Rev. 1.0
Slave address–7 bits
Data from slave–8 bits
38
NOT Acknowledge
39
Stop
21
SL28EB742
Control Register 0. Byte 0
Bit
D7
D6
Name
Type
R/W
R/W
D5
D4
Spread
Enable
SEL_SATA
R/W
R
D3
R/W
D2
D1
D0
FSC
FSB
FSA
R
R
R
Reset settings = 000x0xxx
22
Bit
Name
7:6
Reserved
5
Spread Enable
4
SEL_SATA
3
Reserved
2
FSC
1
FSB
0
FSA
Function
Enable spread for CPU/SRC/PCI outputs
0 = Disable, 1 = –0.5%
See Table 9 for SATA/SRC selection.
See Table 9 for CPU Frequency Selection Table.
Rev. 1.0
SL28EB742
Register 1. Byte 1
Bit
D7
D6
D5
D4
D3
Name
DOT96_
OE
SATA/
SRC0_OE
CPU2/
SRC6_OE
SRC2
SRC1
Type
R/W
R/W
R/W
R/W
R/W
D2
D1
D0
WOL_EN
R/W
R/W
R/W
Reset settings = 1111110
Bit
Name
7
DOT96_OE
Function
Output enable for DOT96.
0 = Output Disabled, 1 = Output Enabled
6
SATA/SRC0_OE
Output enable for SATA/SRC0.
0 = Output Disabled, 1 = Output Enabled
5
CPU2/SRC6_OE
Output enable for CPU2/SRC6.
0 = Output Disabled, 1 = Output Enabled
4
SRC2
Output enable for SRC2.
0 = Output Disabled, 1 = Output Enabled
3
SRC1
Output enable for SRC1.
0 = Output Disabled, 1 = Output Enabled
2
Reserved
1
WOL_EN
0
Reserved
Wake-On-LAN Enable bit.
25 MHz free running during VDD Suspend (S-states). If this bit is set to 0, the
XTAL OSC will also be powered down in the Suspend States)
Rev. 1.0
23
SL28EB742
Register 2. Byte 2
Bit
D7
D6
Name
48M_OE
Type
R/W
R/W
D5
D4
D3
D2
D1
25M_OE
REF_OE
12_48M_OE
PCI0_OE
PCIF_OE
R/W
R/W
R/W
R/W
R/W
Reset settings = 10111110
Bit
Name
7
48M_OE
Function
Output Enable for 48M.
0: Output disabled.
1: Output enabled.
6
Reserved
5
25M_OE
Output ENABLE for 25M.
0 = Output Disabled, 1 = Output Enabled
4
REF_OE
Output Enable for REF.
0 = Output Disabled, 1 = Output Enabled
3
12_48M_OE
Output Enable for 12_48M.
0 = Output Disabled, 1 = Output Enabled
2
PCI0_OE
Output Enable for PCI0.
0 = Output Disabled, 1 = Output Enabled
1
PCIF_OE
Output Enable for PCIF.
0 = Output Disabled, 1 = Output Enabled
0
24
Reserved
Rev. 1.0
D0
R/W
SL28EB742
Register 3. Byte 3
Bit
D7
D6
Name
CPU1_OE
CPU0_OE
Type
R/W
R/W
D5
D4
D3
D2
D1
D0
CLKREQ#_3 CLKREQ#_3 CLKREQ#_2 CLKREQ#_2 CLKREQ#_1 CLKREQ#_1
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 1100000
Bit
Name
7
CPU1_OE
Function
Output Enable for CPU1.
0 = Output Disabled, 1 = Output Enabled
6
CPU0_OE
Output Enable for CPU0.
0 = Output Disabled, 1 = Output Enabled
5
CLKREQ#_3
Clock Request for SRC2.
0 = Not controlled, 1 = Controlled
4
CLKREQ#_3
Clock Request for SRC6 (does not apply to CPU clock).
0 = Not controlled, 1 = Controlled
3
CLKREQ#_2
Clock Request for SRC2.
0 = Not controlled, 1 = Controlled
2
CLKREQ#_2
Clock Request for SATA75M/SRC0.
0 = Not controlled, 1 = Controlled
1
CLKREQ#_1
Clock Request for SRC1.
0 = Not controlled, 1 = Controlled
0
CLKREQ#_1
Clock Request for SATA75M/SRC0.
0 = Not controlled, 1 = Controlled
Rev. 1.0
25
SL28EB742
Register 4. Byte 4
Bit
D7
Name
Type
D6
D5
D4
D3
CPU1
12_48M
CPU2
ITP_EN
R/W
R
R/W
R
R/W
Reset settings = 00x0x000
Bit
Name
7
Reserved
6
CPU1
Function
CPU1 Free Run Control.
0 = Free Running, 1 = Stoppable
5
12_48M
Selectable 12_48M Status.
0 = 48M, 1 = 12M
4
CPU2
CPU2 Free Run Control.
0 = Free Running, 1 = Stoppable
3
ITP_EN
Selectable CPUe_ITP/ SRC6 Status.
0 = SRC6, 1 = CPU2
2
Reserved
1
CPU0
CPU0 Free Run Control.
0 = Free Running, 1 = Stoppable
0
26
Reserved
Rev. 1.0
D2
D1
D0
CPU0
R/W
R/W
R/W
SL28EB742
Control Register 5. Byte 5
Bit
D7
D6
D5
Name
Type
R/W
R/W
D4
D3
D2
D1
SATA75/SRC0
SRC6
SRC2
SRC1
R/W
R/W
R/W
R/W
R/W
D2
D1
D0
R/W
D0
Reset settings = 00010000
Bit
Name
Function
7:5
Reserved
4
SATA75/SRC0
SATA75/SRC0 Free Run Control.
0 = Free Running, 1 = Stoppable
3
SRC6
SRC6 Free Run Control.
0 = Free Running, 1 = Stoppable
2
SRC2
SRC2 Free Run Control.
0 = Free Running, 1 = Stoppable
1
SRC1
SRC1 Free Run Control.
0 = Free Running, 1 = Stoppable
0
Reserved
Control Register 6. Byte 6
Bit
Name
Type
D7
D6
CPU_AMP
R/W
R/W
D5
D4
D3
SRC_AMP
R/W
R/W
DOT96_AMP
R/W
R/W
SATA_AMP
R/W
R/W
Reset settings = 01010101
Bit
Name
7:6
CPU_AMP
Function
CPU Amplitude Adjustment.
00 = 700 mV, 01 = 800 mV, 10 = 900 mV, 11 = 1000 mV
5:4
SRC_AMP
SRC Amplitude Adjustment.
00 = 700 mV, 01 = 800 mV, 10 = 900 mV, 11 = 1000 mV
3:2
DOT96_AMP
DOT96 Amplitude Adjustment.
00 = 700 mV, 01 = 800 mV, 10 = 900 mV, 11 = 1000 mV
1:0
SATA_AMP
SATA75/SRC0 Amplitude Adjustment.
00 = 700 mV, 01 = 800 mV, 10 = 900 mV, 11 = 1000 mV
Rev. 1.0
27
SL28EB742
Control Register 7. Byte 7
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Rev Code
Bit 3
Rev Code
Bit 2
Rev Code
Bit 1
Rev Code
Bit 0
Vendor ID
Bit 3
Vendor ID
Bit 2
Vendor ID
Bit 1
Vendor ID
Bit 0
Type
R
R
R
R
R
R
R
R
Reset settings = 00011000
28
Bit
Name
Function
7
Rev Code Bit 3
Revision Code Bit 3
6
Rev Code Bit 2
Revision Code Bit 2
5
Rev Code Bit 1
Revision Code Bit 1
4
Rev Code Bit 0
Revision Code Bit 0
3
Vendor ID Bit 3
Vendor ID Bit 3
2
Vendor ID Bit 2
Vendor ID Bit 2
1
Vendor ID Bit 1
Vendor ID Bit 1
0
Vendor ID Bit 0
Vendor ID Bit 0
Rev. 1.0
SL28EB742
Control Register 8. Byte 8
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 00001111
Bit
Name
Function
7
BC7
6
BC6
5
BC5
Byte count register for block read operation.
The default value for Byte count is 15.
In order to read beyond Byte 15, the user should change the byte count limit
to or beyond the byte that is desired to be read.
4
BC4
3
BC3
2
BC2
1
BC1
0
BC0
Rev. 1.0
29
SL28EB742
Control Register 9. Byte 9
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
SRC5
SRC4
SRC3
SRC5
SRC4
SRC3
PCI0
PCIF
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 11100001
Bit
Name
7
SRC5
Function
Output Enable for SRC5.
0 = Output Disabled, 1 = Output Enabled
6
SRC4
Output Enable for SRC4.
0 = Output Disabled, 1 = Output Enabled
5
SRC3
Output Enable for SRC3.
0 = Output Disabled, 1 = Output Enabled
4
SRC5
SRC5 Free Run Control.
0 = Free Running, 1 = Stoppable
3
SRC4
SRC4 Free Run Control.
0 = Free Running, 1 = Stoppable
2
SRC3
SRC3 Free Run Control.
0 = Free Running, 1 = Stoppable
1
PCI0
PCI0 Free Run Control.
0 = Free Running, 1 = Stoppable
0
PCIF
PCIF Free Run Control.
0 = Free Running, 1 = Stoppable
30
Rev. 1.0
SL28EB742
Control Register 10. Byte 10
Bit
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Type
Reset settings = 00000000
Bit
Name
7:0
Reserved
Function
Control Register 11. Byte 11
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
14M_Bit2
14M_Bit1
14M_Bit0
25M_Bit2
25M_Bit1
25M_Bit0
12_48M_
Bit2
12_48M_
Bit0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 10110111
Bit
Name
7
14M_Bit2
6
14M_Bit1
5
14M_Bit0
4
25M_Bit2
3
25M_Bit1
2
25M_Bit0
1
12_48M_Bit2
0
12_48M_Bit0
Function
Drive Strength Control - Bit[2:0] Normal mode default ‘101’
Wireless Friendly Mode default to ‘111’
’
Rev. 1.0
31
SL28EB742
Control Register 12. Byte 12
Bit
D7
D6
D5
D4
D3
D2
Name
48M_Bit2
48M_Bit1
48M_Bit0
PCI0_Bit2
PCI0_Bit1
PCI0_Bit0
Type
R/W
R/W
R/W
R/W
R/W
R/W
D1
12_48M_Bit1
R/W
Reset settings = 10110100
32
Bit
Name
7
48M_Bit2
6
48M_Bit1
5
48M_Bit0
4
PCI0_Bit2
3
PCI0_Bit1
2
PCI0_Bit0
1
Reserved
0
12_48M_Bit1
Function
Drive Strength Control - Bit[2:0] Normal mode default ‘101’
Wireless Friendly Mode default to ‘111’
’
Rev. 1.0
D0
R/W
SL28EB742
Control Register 13. Byte 13
Bit
D7
D6
D5
Name
PCIF_Bit2
PCIF_Bit1
PCIF_Bit0
Type
R/W
R/W
R/W
D4
D3
D2
D1
D0
Wireless Friendly
Mode
R/W
R/W
R/W
R/W
R/W
Reset settings = 10100000
Bit
Name
7
PCIF_Bit2
6
PCIF_Bit1
5
PCIF_Bit0
4:1
Reserved
0
Wireless Friendly
Mode
Function
Drive Strength Control—Bit[2:0] Normal mode default 101
Wireless Friendly Mode default to ‘111’
’
Wireless Friendly Mode.
0 = Disabled, Default all single-ended clocks slew rate config bits to 101
1 = Enabled, Default all single-ended clocks slew rate config bits to 111
Rev. 1.0
33
SL28EB742
Control Register 14. Byte 14
Bit
D7
D6
D5
Name
Type
R/W
R/W
R/W
D4
D3
D2
D1
D0
OTP_4
OTP_3
OTP_2
OTP_1
OTP_0
R/W
R/W
R/W
R/W
R/W
Reset settings = 10101000
34
Bit
Name
7:5
Reserved
4
OTP_4
3
OTP_3
2
OTP_2
1
OTP_1
0
OTP_0
Function
OTP_ID.
Identification for programmed device
Rev. 1.0
SL28EB742
CKPWRGD/PD#
5. Pin Descriptions: 56-Pin QFN
Rev. 1.0
35
SL28EB742
Table 12. 56-QFN Pin Definitions
Pin #
36
Name
Type
Description
1
PCIF/ITP_EN**
I/O, 33 MHz free running clock output/3.3 V LVTTL input to enable SRC6
SE, PD or CPU2_ITP (sampled on the CKPWRGD assertion).
0 = SRC6, 1 = CPU2
2
CLKREQ#3**
3
12_48M / SEL12_48
4
VDD_48
5
48M/FSA**
6
GND_48
GND
Ground.
7
GND_48
GND
Ground.
8
DOT96
O, DIF Fixed true 96 MHz clock output.
9
DOT96#
O, DIF Fixed complement 96 MHz clock output.
10
FSB**
I, PD
3.3 V-tolerant input for CPU frequency selection (internal 100 k pulldown). Refer to Table 2 for Vil_FS and Vih_FS specifications.
11
GND_SATA
GND
Ground.
12
SATA/SRC0
O, DIF 100 MHz True differential serial reference clock.
13
SATA/SRC0#
O, DIF 100 MHz Complement differential serial reference clock.
14
VDD_SATA
PWR
15
SRC1
O, DIF 100 MHz True differential serial reference clock.
16
SRC1#
O, DIF 100 MHz Complement differential serial reference clock.
17
SRC2
O, DIF 100 MHz True differential serial reference clock.
18
SRC2#
O, DIF 100 MHz Complement differential serial reference clock.
19
SRC3
O, DIF 100 MHz True differential serial reference clock.
20
SRC3#
O, DIF 100 MHz Complement differential serial reference clock.
21
GND_SRC
GND
Ground.
22
VDD_SRC
PWR
3.3 V Power supply.
23
SRC4#
O, DIF 100 MHz True differential serial reference clock.
24
SRC4
O, DIF 100 MHz Complement differential serial reference clock.
25
SRC5#
O, DIF 100 MHz True differential serial reference clock.
I, PD
3.3 V clock request input (internal 100 kpull-down)
I/O, SE 12/48 MHz Clock output/3.3 V-tolerance input for 12 MHz or 48 MHz
selection (Sampled at CKPWRGD assertion) (internal 100 k pull-up).
PU
0 = 48M, 1 = 12M
PWR
I/O
PD
3.3 V Power supply
Fixed 48 MHz clock output/3.3 V-tolerant input for CPU frequency
selection (internal 100 k pull-down).
Refer to Table 2 for Vil_FS and Vih_FS specifications.
3.3 V Power supply.
Rev. 1.0
SL28EB742
Table 12. 56-QFN Pin Definitions (Continued)
Pin #
Name
Type
Description
26
SRC5
O, DIF 100 MHz Complement differential serial reference clock.
27
GND_SRC
GND
Ground.
28
VDD_SRC
PWR
3.3 V Power supply.
29
SRC6#/CPU2_ITP#
O, DIF Selectable complementary differential CPU or SRC clock output.
ITP_EN = 0 @ CKPWRGD assertion = SRC6
ITP_EN = 1 @ CKPWRGD assertion = CPU2
30
SRC6/CPU2_ITP
O, DIF Selectable True differential CPU or SRC clock output.
ITP_EN = 0 @ CKPWRGD assertion = SRC6
ITP_EN = 1 @ CKPWRGD assertion = CPU2
31
CPU1#
O, DIF Complement differential CPU clock output.
32
CPU1
O, DIF True differential CPU clock output.
33
VDD_CPU
34
CPU0#
O, DIF Complement differential CPU clock output.
35
CPU0
O, DIF True differential CPU clock output.
36
GND_CPU
37
SCLK
I
38
SDATA
I/O
39
CPU_STP#*
I, PU
3.3 V-tolerant input for stopping CPU outputs (internal 100 k pull-up).
40
PCI/SRC_STP#*
I, PU
3.3 V-tolerant input for stopping PCI and SRC outputs (internal 100 k
pull-up).
41
XOUT
O
14.318 MHz Crystal output. Float XOUT if using only CLKIN (Clock
input).
42
XIN/CLKIN
I
14.318 MHz Crystal input or 3.3 V, 14.318 MHz Clock Input
43
GND_REF
GND
Ground for REF clock and WOL support.
44
GND_REF
GND
Ground for REF clock and WOL support.
45
REF
46
VDD_REF
PWR
3.3 V Power Supply for REF clock and power to support WOL.
47
VDD_REF
PWR
3.3 V Power Supply for REF clock and power to support WOL.
48
CKPWRGD/PD#
49
VDD_25
PWR
GND
O
I
PWR
3.3 V Power supply.
Ground
SMBus compatible SCLOCK.
SMBus compatible SDATA.
14.318 MHz reference output clock.
3.3 V LVTTL input. This pin is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled.
3.3 V Power supply.
Rev. 1.0
37
SL28EB742
Table 12. 56-QFN Pin Definitions (Continued)
Pin #
38
Name
Type
Description
50
25M/FSC**
I/O, PD Fixed 25 MHz clock output/3.3 V-tolerant input for CPU frequency
selection (internal 100 k pull-up). Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
51
GND_25
GND
Ground.
52
CLKREQ#1**
I, PD
3.3 V clock request input (internal 100 k pull-down)
53
CLKREQ#2**
I, PD
3.3 V clock request input (internal 100 k pull-down)
54
PCI0/SEL_SATA**
55
GND_PCI
GND
Ground.
56
VDD_PCI
PWR
3.3 V Power supply.
I/O, SE 33 MHz clock output/3.3 V LVTTL input to enable 100 MHz SATA
(internal 100 k pull-up).
PD
0 = SATA/SRC0 = SRC0 1 = SATA/SRC0 = SATA
Rev. 1.0
SL28EB742
6. Ordering Guide
Part Number
Package Type
Product Flow
SL28EB742ALC
56-pin QFN
Industrial, 0 to 70 C
SL28EB742ALCT
56-pin QFN Tape and Reel
Industrial, 0 to 70 C
SL28EB742ALI
56-pin QFN
Industrial, –40 to 85 C
SL28EB742ALIT
56-pin QFN Tape and Reel
Industrial, –40 to 85 C
Lead-free
Rev. 1.0
39
SL28EB742
7. Package Outline
Figure 13 illustrates the package details for the SL28EB742. Table 13 lists the values for the dimensions shown in
the illustration.
Figure 13. 56-Lead QFN Package
40
Rev. 1.0
SL28EB742
Table 13. Package Diagram Dimensions
Symbol
Millimeters
Min
Nom
Max
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A3
b
0.20 REF
0.18
D
D2
0.25
0.30
8.00 BSC
5.80
e
5.90
6.00
0.50 BSC
E
8.00 BSC
E2
5.80
5.90
6.00
L
0.30
0.40
0.50
aaa
0.10
bbb
0.10
ccc
0.10
ddd
0.10
eee
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
4. This drawing conforms to the JEDEC Solid State Outline MO-220.
Rev. 1.0
41
SL28EB742
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2

Correct

Remove
the pin description.
75 MHz description on pin description.
 Remove WOL function description
 Correct OTP code to 01000
42
Rev. 1.0
SL28EB742
CONTACT INFORMATION
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Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
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and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
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Rev. 1.0
43