Si53320 1:5 L O W J I T T E R LVPECL C LOCK B UFFER W I T H 2:1 I NPUT M UX Features 5 LVPECL outputs Ultra-low additive jitter: 100 fs rms Wide frequency range: 1 to 725 MHz Input compatible with LVPECL, LVDS, CML, HCSL, LVCMOS 2:1 mux Glitchless input clock switching Synchronous output enable 20-TSSOP RoHS compliant, Pb-free Industrial temperature range: –40 to +85 °C Footprint-compatible with MC100LVEP14, SY100EP14U Applications High-speed clock distribution Ethernet switch/router Optical Transport Network (OTN) SONET/SDH PCI Express Gen 1/2/3 Storage Telecom Industrial Servers Backplane clock distribution Description The Si53320 is an ultra low jitter five output LVPECL buffer with synchronous OE. Outputs are enabled/disabled in a low state, ensuring runt pulses are not created when the device is enabled/disabled. The Si53320 features a 2:1 input mux, making it ideal for redundant clocking applications. The Si53320 utilizes Silicon Laboratories’ advanced CMOS technology to fanout clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53320 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Functional Block Diagram Power Supply Filtering VDD Ordering Information: See page 20. Pin Assignments Q0 1 20 VDD Q0 2 19 OE Q1 3 18 VDD Q1 4 17 CLK1 Q2 5 16 CLK1 Q2 6 15 NC Q3 7 14 CLK0 Q3 8 13 CLK0 Q4 9 12 CLK_SEL Q4 10 11 GND Q0 Q0 Q1 CLK0 0 CLK0 Patents pending Q1 Q2 Q2 CLK1 1 CLK1 Q3 Q3 Q4 CLK_SEL GND Rev. 1.0 4/15 Switching Logic Q4 OE Copyright © 2015 by Silicon Laboratories Si53320 Si53320 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3. Glitchless Clock Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4. Synchronous Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.6. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 2.7. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.8. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.9. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.10. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. Pin Description: 20-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1. 20-TSSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 6.1. 20-TSSOP Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1. Si53320 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2 Rev. 1.0 Si53320 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltage Range Symbol Test Condition Min Typ Max Unit TA –40 — 85 °C VDD 2.38 2.5 2.63 V 2.97 3.3 3.63 V Table 2. Input Clock Specifications (2.5 V ± 5%, or 3.3 V ± 10%, TA=–40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Differential Input Common Mode Voltage VCM VDD = 2.5 V± 5%, 3.3 V± 10% 0.05 — — V Differential Input Swing (peak-to-peak) VIN 0.2 — 2.2 V LVCMOS Input High Voltage VIH VDD = 2.5 V± 5%, 3.3 V± 10% VDD x 0.7 — — V LVCMOS Input Low Voltage VIL VDD = 2.5 V± 5%, 3.3 V± 10% — — VDD x 0.3 V Input Capacitance CIN CLK0/CLK0 and CLK1/CLK1 pins with respect to GND — 5 — pF Table 3. DC Common Characteristics (2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Symbol Test Condition Min Typ Max Unit Supply Current IDD Includes pull-down current in resistor Rb (see Figure 7) — 260 — mA Input High Voltage VIH CLK_SEL/OE 0.8 x VDD — — V Input Low Voltage VIL CLK_SEL/OE — — 0.2 x VDD V RDOWN CLK_SEL/OE — 25 — kΩ Parameter Internal Pull-down Resistor Rev. 1.0 3 Si53320 Table 4. Output Characteristics (LVPECL) (VDD = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol Output DC Common Mode Voltage Min Typ Max Unit VCOM VDD – 1.595 — VDD – 1.245 V VSE 0.55 0.80 1.050 V Single-Ended Output Swing* Test Condition *Note: Unused outputs can be left floating. Do not short unused outputs to ground. Table 5. AC Characteristics (VDD = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Symbol Test Condition Min Typ Max Unit F LVPECL 1 — 725 MHz Duty Cycle (50% input duty cycle) DC 20/80% TR/TF<10% of period (Differential) 48 50 52 % Minimum Input Clock Slew Rate SR Required to meet prop delay and additive jitter specifications (20–80%) 0.75 — — V/ns Output Rise/Fall Time TR/TF 20/80% — — 350 ps Minimum Input Pulse Width TW 500 — — ps TPLH, TPHL 700 950 1200 ps F = 1 MHz — 1500 — ns F = 100 MHz — 30 — ns F = 725 MHz — 10 — ns F = 1 MHz — 2000 — ns F = 100 MHz — 30 — ns F = 725 MHz — 10 — ns — 60 90 ps — — 150 ps Parameter Frequency Propagation Delay Output Enable Time Output Disable Time TEN TDIS Output to Output Skew1 TSK Part to Part Skew2 TPS Differential Notes: 1. Output-to-output skew specified for outputs with identical configuration. 2. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 3. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDD (3.3 V = 100 mVPP) and noise spur amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details. 4 Rev. 1.0 Si53320 Table 5. AC Characteristics (Continued) (VDD = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Power Supply Noise Rejection3 Symbol Test Condition Min Typ Max Unit PSRR 10 kHz sinusoidal noise — –67.5 — dBc 100 kHz sinusoidal noise — –62.5 — dBc 500 kHz sinusoidal noise — –60 — dBc 1 MHz sinusoidal noise — –55 — dBc Notes: 1. Output-to-output skew specified for outputs with identical configuration. 2. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 3. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDD (3.3 V = 100 mVPP) and noise spur amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details. Table 6. Additive Jitter, Differential Clock Input VDD Output Input1,2 Freq (MHz) Clock Format Amplitude VIN (Single-Ended, Peak-to-Peak) Differential Clock Format 20%-80% Slew Rate (V/ns) Additive Jitter (fs rms, 12 kHz to 20 MHz)3 Typ Max 3.3 725 Differential 0.15 0.637 LVPECL 45 65 3.3 156.25 Differential 0.5 0.458 LVPECL 160 185 2.5 725 Differential 0.15 0.637 LVPECL 45 65 2.5 156.25 Differential 0.5 0.458 LVPECL 145 185 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. AC-coupled differential inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. Rev. 1.0 5 Si53320 Table 7. Additive Jitter, Single-Ended Clock Input VDD Output Input1,2 Freq (MHz) Clock Format Amplitude VIN (single-ended, peak to peak) Additive Jitter (fs rms, 12 kHz to 20 MHz)3 SE 20%-80% Slew Rate (V/ns) Clock Format Typ Max 3.3 156.25 Single-ended 2.18 1 LVPECL 160 185 2.5 156.25 Single-ended 2.18 1 LVPECL 145 185 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. DC-coupled single-ended inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. PSPL 5310A PSPL 5310A CLKx CLK SYNTH SMA103A AG E5052 Phase Noise Analyzer 50 Si533xx DUT 50ohm 50 Balun /CLKx Balun Figure 1. Differential Measurement Method Using a Balun Table 8. Thermal Conditions Parameter Thermal Resistance, Junction to Ambient 6 Symbol Test Condition Value Unit θJA Still air 93.88 °C/W Rev. 1.0 Si53320 Table 9. Absolute Maximum Ratings Min Typ Max Unit TS –55 — 150 °C Supply Voltage VDD –0.5 — 3.8 V Input Voltage VIN –0.5 — VDD + 0.3 V Output Voltage VOUT — — VDD + 0.3 V ESD Sensitivity HBM 2000 — — V ESD Sensitivity CDM 500 — — V Peak Soldering Reflow Temperature TPEAK — — 260 °C — — 125 °C Parameter Storage Temperature Maximum Junction Temperature Symbol Test Condition HBM, 100 pF, 1.5 kΩ Pb-Free; Solder reflow profile per JEDEC JSTD-020 TJ Note: Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. Rev. 1.0 7 Si53320 2. Functional Description The Si53320 is a low jitter, low skew 1:5 differential buffer with an integrated 2:1 input mux. The device has a universal input that accepts most common differential or LVCMOS input signals. A clock select pin is used to select the active input clock. The selected clock input is routed to five high-performance, low-jitter outputs. 2.1. Universal, Any-Format Input The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, lowpower LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 10 and 11 summarize the various ac- and dc-coupling options supported by the device. For the best high-speed performance, the use of differential formats is recommended. For both single-ended and differential input clocks, the fastest possible slew rate is recommended as low slew rates can increased the noise floor and degrade jitter performance. Though not required, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. Table 10. LVPECL, LVCMOS, and LVDS Input Clock Options LVPECL LVCMOS LVDS AC-Couple DC-Couple AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V N/A N/A No No Yes No 2.5/3.3 V Yes Yes No Yes Yes Yes Table 11. HCSL and CML Input Clock Options HCSL CML AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V No No Yes No 2.5/3.3 V Yes (3.3 V) Yes (3.3 V) Yes No 0.1 µF Si533xx CLKx 100 Ω /CLKx 0.1 µF Figure 2. Differential HCSL, LVPECL, Low-Power LVPECL, LVDS, CML AC-Coupled Input Termination VDD 1 kΩ VDD = 3.3 V or 2.5 V VDD Si533xx CMOS Driver CLKx 50 /CLKx Rs VTERM = VDD/2 1 kΩ VREF Figure 3. LVCMOS DC-Coupled Input Termination 8 Rev. 1.0 Si53320 VDD DC Coupled LVPECL Termination Scheme 1 R1 VDD R1 VDD = 3.3V or 2.5V Si533xx CLKx 50 “Standard” LVPECL Driver /CLKx 50 R2 VTERM = VDD – 2V R1 // R2 = 50 Ohm R2 3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm 2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm DC Coupled LVPECL Termination Scheme 2 VDD VDD = 3.3V or 2.5V Si533xx 50 “Standard” LVPECL Driver CLKx /CLKx 50 50 50 VTERM = VDD – 2V DC Coupled LVDS Termination VDD VDD = 3.3V or 2.5V Si533xx CLKx 50 Standard LVDS Driver /CLKx 50 100 DC Coupled HCSL Source Termination Scheme VDD = 3.3V 33 Si533xx 50 Standard HCSL Driver VDD CLKx /CLKx 33 50 50 50 Note: 33 Ohm series termination is optional depending on the location of the receiver. Figure 4. Differential DC-Coupled Input Terminations Rev. 1.0 9 Si53320 2.2. Input Bias Resistors Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected. The non-inverting input is biased with a 18.75 kΩ pull-down to GND and a 75 kΩ pull-up to VDD. The inverting input is biased with a 75 kΩ pull-up to VDD. VDD RPU RPU + RPD CLK0 or CLK1 – RPU = 75 kΩ RPD = 18.75 kΩ Figure 5. Input Bias Resistors 2.3. Glitchless Clock Input Switching The Si53320 features glitchless switching between two valid input clocks. Figure 6 illustrates that switching between input clocks does not generate runt pulses or glitches at the output. CLK1 CLK0 CLK_SEL Note 2 Note 1 Note 3 Qn Notes: 1. Qn continues with CLK0 for 2-3 falling edges of CLK0. 2. Qn is disabled low for 2-3 falling edges of CLK1 . 3. Qn starts on the first rising edge after 1 + 2. Figure 6. Glitchless Input Clock Switch The Si53320 supports glitchless switching between clocks at the same frequency. In addition, the device supports glitchless switching between 2 input clocks that are up to 10x different in frequency. When a switchover to a new clock is made, the output will disable low after two or three clock cycles of the previously-selected input clock. The outputs will remain low for up to three clock cycles of the newly-selected clock, after which the outputs will start from the newly-selected input. In the case a switchover to an absent clock is made, the output will glitchlessly stop low and wait for edges of the newly selected clock. A switchover from an absent clock to a live clock will also be glitchless. Note that the CLK_SEL input should not be toggled faster than 1/250th the frequency of the slower input clock. 10 Rev. 1.0 Si53320 2.4. Synchronous Output Enable The Si53320 features a synchronous output enable (disable) feature. The output enable pin is sampled and synchronized to the falling edge of the input clock. This feature prevents runt pulses from being generated when the outputs are enabled or disabled. When OE is high, Q is held low and Q is held high. The device features an internal pull-down resistor, so the outputs are enabled when the output enable pin is unconnected. See Table 5, “AC Characteristics,” on page 4 for output enable and output disable times. 2.5. Input Mux and Output Enable Logic The Si53320 provides two clock inputs for applications that need to select between one of two clock sources. The CLK_SEL pin selects the active clock input. The table below summarizes the input and output clock based on the input mux and output enable pin settings. Table 12. Input Mux and Output Enable Logic CLK_SEL CLK0 CLK1 OE1 Q2 L L X L L L H X L H H X L L L H X H L H X X X H L3 Notes: 1. Output enable active low 2. On the next negative transition of CLK0 or CLK1. 3. Q=low, Q=high Rev. 1.0 11 Si53320 2.6. Output Clock Termination Options The recommended output clock termination options are shown below. Unused outputs should be left unconnected. VDDO DC Coupled LVPECL Termination Scheme 1 R1 R1 VDDO = 3.3V or 2.5V Si533xx VDD = VDDO 50 Q LVPECL Receiver Qn 50 R2 VTERM = VDDO – 2V R1 // R2 = 50 Ohm R2 3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm 2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm DC Coupled LVPECL Termination Scheme 2 VDDO = 3.3V or 2.5V Si533xx VDD = VDDO 50 Q LVPECL Receiver Qn 50 50 50 VTERM = VDDO – 2V VDDO AC Coupled LVPECL Termination Scheme 1 R1 VDDO = 3.3V or 2.5V Si533xx R1 0.1 uF VDD = 3.3V or 2.5V 50 Q LVPECL Receiver Qn 50 0.1 uF Rb R2 Rb R2 VBIAS = VDD – 1.3V R1 // R2 = 50 Ohm 3.3V LVPECL: R1 = 82.5 Ohm, R2 = 127 Ohm, Rb = 120 Ohm 2.5V LVPECL: R1 = 62.5 Ohm, R2 = 250 Ohm, Rb = 90 Ohm AC Coupled LVPECL Termination Scheme 2 V DDO = 3.3V or 2.5V Si533xx 0.1 uF V DD = 3.3V or 2.5V 50 Q LVPECL Receiver Qn 50 0.1 uF Rb 50 Rb 50 V BIAS = V DD – 1.3 V 3.3V LVPECL: Rb = 120 Ohm 2.5V LVPECL: Rb = 90 Ohm Figure 7. LVPECL Output Termination 12 Rev. 1.0 Si53320 2.7. AC Timing Waveforms TPHL TSK CLK QN VPP/2 Q VPP/2 QM VPP/2 VPP/2 TPLH TSK Propagation Delay Output-Output Skew TF Q 80% VPP 20% VPP 80% VPP Q 20% VPP TR Rise/Fall Time Figure 8. AC Waveforms Rev. 1.0 13 Si53320 2.8. Typical Phase Noise Performance Each of the following three figures shows three phase noise plots superimposed on the same diagram. Source Jitter: Reference clock phase noise. Total Jitter (SE): Combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. Total Jitter (Diff): Combined source and clock buffer phase noise measured as a differential output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. The differential measurement as shown in each figure is made using a balun. See Figure 1 on page 6. Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS). The total jitter is a measure of the source plus the buffer's additive phase jitter. The additive jitter (rms) of the buffer can then be calculated (via root-sum-square addition). Figure 9. Source Jitter (156.25 MHz) 14 Rev. 1.0 Si53320 Figure 10. Single-Ended Total Jitter (312.5 MHz) Rev. 1.0 15 Si53320 Figure 11. Differential Total Jitter (625 MHz) 16 Rev. 1.0 Si53320 2.9. Input Mux Noise Isolation The input clock mux is designed to minimize crosstalk between the CLK0 and CLK1. This improves phase jitter performance when clocks are present at both the CLK0 and CLK1 inputs. Figure 12 below is a measurement the input mux’s noise isolation. LVPECL [email protected]; Selected clk is active Unselected clk is static Mux Isolation = 61dB LVPECL [email protected]; Selected clk is static Unselected clk is active Figure 12. Input Mux Noise Isolation 2.10. Power Supply Noise Rejection The device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs and SoCs and may reduce board-level filtering requirements. For more information, see “AN491: Power Supply Rejection for Low Jitter Clocks”. Rev. 1.0 17 Si53320 3. Pin Description: 20-Pin TSSOP Q0 1 20 VDD Q0 2 19 OE Q1 3 18 VDD Q1 4 17 CLK1 Q2 5 16 CLK1 Q2 6 15 NC Q3 7 14 CLK0 Q3 8 13 CLK0 Q4 9 12 CLK_SEL Q4 10 11 GND Table 13. Si53320 20-Pin TSSOP Descriptions* Pin # Name Type* 1 Q0 O Output clock 0. 2 Q0 O Output clock 0 (complement). 3 Q1 O Output clock 1. 4 Q1 O Output clock 1 (complement). 5 Q2 O Output clock 2. 6 Q2 O Output clock 2 (complement). 7 Q3 O Output clock 3. 8 Q3 O Output clock 3 (complement). 9 Q4 O Output clock 4. 10 Q4 O Output clock 4 (complement). 11 GND GND 12 CLK_SEL I Mux input select pin (LVCMOS). When CLK_SEL is high, CLK1 is selected. When CLK_SEL is low, CLK0 is selected. CLK_SEL contains an internal pull-down resistor. 13 CLK0 I Input clock 0. 18 Description Ground. Rev. 1.0 Si53320 Table 13. Si53320 20-Pin TSSOP Descriptions* (Continued) Pin # Name Type* Description 14 CLK0 I 15 NC — 16 CLK1 I Input clock 1. 17 CLK1 I Input clock 1 (complement) When CLK1 is driven by a single-ended input, connect CLK1 to an appropriate bias voltage (e.g., for a CMOS input apply VDD/2). 18 VDD P Core voltage supply. Bypass with 1.0 µF capacitor and place as close to the VDD pin as possible. 19 OE I Output enable. When OE = low, the clock outputs are enabled. When OE = high, Q is held low and Q is held high. OE features an internal pull-down resistor and may be left unconnected. 20 VDD P Core voltage supply. Bypass with 1.0 µF capacitor and place as close to the VDD pin as possible. Input clock 0 (complement) When CLK0 is driven by a single-ended input, connect CLK0 to an appropriate bias voltage (e.g., for a CMOS input apply VDD/2). No connect. Leave this pin unconnected. *Note: Pin types are: I = input, O = output, P = power, GND = ground. Rev. 1.0 19 Si53320 4. Ordering Guide 20 Part Number Package Pb-Free, ROHS-6 Temperature Si53320-B-GT 20-TSSOP Yes –40 to 85 °C Rev. 1.0 Si53320 5. Package Outline 5.1. 20-TSSOP Package Diagram Figure 13. Si53320 20-TSSOP Package Diagram Table 14. Package Dimensions Dimension Min Nom Max Dimension A — — 1.20 e A1 0.05 — 0.15 L A2 0.80 1.00 1.05 L2 b 0.19 — 0.30 θ c 0.09 — 0.20 aaa 0.10 D 6.40 6.50 6.60 bbb 0.10 ccc 0.20 6.40 BSC E E1 4.30 4.40 Min Nom Max 0.65 BSC 0.45 0.60 0.75 0.25 BSC 0° — 8° 4.50 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.0 21 Si53320 6. PCB Land Pattern 6.1. 20-TSSOP Package Land Pattern Figure 14. Si53320 20-TSSOP Package Land Pattern Table 15. PCB Land Pattern Dimension Feature (mm) C1 Pad Column Spacing 5.80 E Pad Row Pitch 0.65 X1 Pad Width 0.45 Y1 Pad Length 1.40 Notes: 1. This Land Pattern Design is based on IPC-7351 specifications for Density Level B (Median Land Protrusion) 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. 22 Rev. 1.0 Si53320 7. Top Marking 7.1. Si53320 Top Marking 7.2. Top Marking Explanation Mark Method: Laser Font Size: 2.0 Point (0.71 mm) Right-Justified Line 1 Marking: Customer Part Number Si53320 Line 2 Marking: TTTTTT = Mfg Code Manufacturing Code from Assembly Purchase Order form. Line 3 Marking: Circle = 1.2 mm Diameter “e3” Pb-Free Symbol YY = Year WW = Work Week Assigned by the Assembly House. Corresponds to year and work week of the build date. Rev. 1.0 23 Si53320 DOCUMENT CHANGE LIST Revision 0.4 to 1.0 24 Update operating conditions, including LVCMOS and HCSL voltage support. Updated Table 2, “Input Clock Specifications,” on page 3. Updated Table 3, “DC Common Characteristics,” on page 5. Updated Table 4, “Output Characteristics (LVPECL),” on page 6. Updated Table 10, “AC Characteristics,” on page 7. Updated output voltage specifications Improved data for additive jitter specifications. Improved typical phase noise plots. Updated input/output termination recommendations. Improved performance specifications with more detail. Removed the voltage reference feature. Added pin type description to the pin descriptions table Rev. 1.0 Si53320 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. 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