Si53306 1 : 4 L O W - J ITTER U N I V E R S A L B U F F E R / L E V E L T R A N S L A T O R Features Independent VDD and VDDO : 1.8/2.5/3.3 V 1.2/1.5 V LVCMOS output support Selectable LVCMOS drive strength to tailor jitter and EMI performance Small size: 16-QFN (3 mm x 3 mm) RoHS compliant, Pb-free Industrial temperature range: –40 to +85 °C Applications Storage Telecom Industrial Servers Backplane clock distribution VDD Power Supply Filtering 3 GND 4 Q0 SFOUT0 8 CLK GND PAD SFOUT1 2 7 CLK Q3 VDDO SFOUT[1:0] 1 13 Functional Block Diagram VDD 14 The Si53306 is an ultra low jitter four output differential buffer with pin-selectable output clock signal format. The Si53306 utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53306 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry. 15 Description Q0 Pin Assignments 6 Q3 OE 16 High-speed clock distribution Ethernet switch/router Optical Transport Network (OTN) SONET/SDH PCI Express Gen 1/2/3 Ordering Information: See page 24. 5 VDDO 4 differential or 8 LVCMOS outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: 1 to 725 MHz Any-format input with pin selectable output formats: LVPECL, low power LVPECL, LVDS, CML, HCSL, LVCMOS Synchronous output enable OE Q0 12 Q1 11 Q1 10 Q2 9 Q2 Patents pending Q0 Q1 CLK Q1 CLK Q2 Q2 Q3 Q3 Rev. 1.0 2/15 Copyright © 2015 by Silicon Laboratories Si53306 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA). Si53306 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4. Synchronous Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5. Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6. Power Supply (VDD and VDDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.7. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.8. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.9. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.10. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3. Pin Description: 16-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1. Si53306 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2 Rev. 1.0 Si53306 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltage Range* Output Buffer Supply Voltage* Symbol Test Condition Min Typ Max Unit –40 — 85 °C 1.71 1.8 1.89 V 2.38 2.5 2.63 V 2.97 3.3 3.63 V LVPECL, low power LVPECL, LVCMOS 2.38 2.5 2.63 V 2.97 3.3 3.63 V HCSL 2.97 3.3 3.63 V LVDS, CML, LVCMOS 1.71 1.8 1.89 V 2.38 2.5 2.63 V 2.97 3.3 3.63 V 2.38 2.5 2.63 V 2.97 3.3 3.63 V 2.97 3.3 3.63 V TA VDD VDDOX LVDS, CML LVPECL, low power LVPECL HCSL *Note: Core supply VDD and output buffer supplies VDDO are independent. LVCMOS clock input is not supported for VDD = 1.8V but is supported for LVCMOS clock output for VDDOX = 1.8V. LVCMOS outputs at 1.5V and 1.2V can be supported via a simple resistor divider network. See “2.7.1. LVCMOS Output Termination To Support 1.5V and 1.2V” Table 2. Input Clock Specifications (VDD=1.8 V 5%, 2.5 V 5%, or 3.3 V 10%, TA=–40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Differential Input Common Mode Voltage VCM VDD = 2.5 V 5%, 3.3 V 10% 0.05 — — V Differential Input Swing (peak-to-peak) VIN 0.2 — 2.2 V LVCMOS Input High Voltage VIH VDD = 2.5 V 5%, 3.3 V 10% VDD x 0.7 — — V LVCMOS Input Low Voltage VIL VDD = 2.5 V 5%, 3.3 V 10% — — VDD x 0.3 V Input Capacitance CIN CLK pins with respect to GND — 5 — pF Rev. 1.0 3 Si53306 Table 3. DC Common Characteristics (VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Supply Current Output Buffer Supply Current (Per Clock Output) @100 MHz (diff) @200 MHz (CMOS) Symbol Test Condition Min Typ Max Unit — 55 100 mA LVPECL (3.3 V) — 35 — mA Low Power LVPECL (3.3 V)* — 35 — mA LVDS (3.3 V) — 20 — mA CML (3.3 V) — 40 — mA HCSL, 100 MHz, 2 pF load (3.3 V) — 35 — mA CMOS (1.8 V, SFOUT = Open/0), per output, CL = 5 pF, 200 MHz — 5 — mA CMOS (2.5 V, SFOUT = Open/0), per output, CL = 5 pF, 200 MHz — 10 — mA CMOS (3.3 V, SFOUT = 0/1), per output, CL = 5 pF, 200 MHz — 20 — mA IDD IDDOX Input Clock Voltage Reference VREF VREF pin IREF = +/-500 A — VDD/2 — V Input High Voltage VIH SFOUTx, OE 0.8 x VDD — — V Input Mid Voltage VIM SFOUTx 3-level input pins 0.45 x VDD 0.5 x VDD 0.55 x VDD V Input Low Voltage VIL SFOUTx, OE — — 0.2 x VDD V Internal Pull-down Resistor RDOWN SFOUTx — 25 — k RUP SFOUTx, OE — 25 — k Internal Pull-up Resistor *Note: Low-power LVPECL mode supports an output termination scheme that will reduce overall system power. 4 Rev. 1.0 Si53306 Table 4. Output Characteristics (LVPECL) (VDDOX = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol Output DC Common Mode Voltage Min Typ Max Unit VCOM VDDOX – 1.595 — VDDOX – 1.245 V VSE 0.55 0.80 1.050 V Single-Ended Output Swing* Test Condition *Note: Unused outputs can be left floating. Do not short unused outputs to ground. Table 5. Output Characteristics (Low Power LVPECL) (VDDOX = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Output DC Common Mode Voltage VCOM RL = 100 across Qn and Qn VDDOX – 1.895 VSE RL = 100 across Qn and Qn 0.25 Single-Ended Output Swing Typ 0.60 Max Unit VDDOX – 1.275 V 0.85 V Table 6. Output Characteristics—CML (VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Single-Ended Output Swing VSE Terminated as shown in Figure 7 (CML termination). 300 400 550 mV Table 7. Output Characteristics—LVDS (VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Single-Ended Output Swing VSE RL = 100 Ω across QN and QN 247 — 490 mV Output Common Mode Voltage (VDDO = 2.5 V or 3.3V) VCOM1 VDDOX = 2.38 to 2.63 V, 2.97 to 3.63 V, RL = 100 Ω across QN and QN 1.10 1.25 1.35 V Output Common Mode Voltage (VDDO = 1.8 V) VCOM2 VDDOX = 1.71 to 1.89 V, RL = 100 Ω across QN and QN 0.85 0.97 1.25 V Rev. 1.0 5 Si53306 Table 8. Output Characteristics—LVCMOS (VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Symbol Output Voltage High* Output Voltage Low* Test Condition Min Typ Max Unit VOH 0.75 x VDDOX — — V VOL — — 0.25 x VDDOX V *Note: IOH and IOL per the Output Signal Format Table for specific VDDOX and SFOUTX settings. Table 9. Output Characteristics—HCSL (VDDOX = 3.3 V ± 10%, TA = –40 to 85 °C)) Parameter Symbol Test Condition Min Typ Max Unit Output Voltage High VOH RL = 50 Ω to GND 550 700 900 mV Output Voltage Low VOL RL = 50 Ω to GND –150 0 150 mV Single-Ended Output Swing VSE RL = 50 Ω to GND 550 700 850 mV Crossing Voltage VC RL = 50 Ω to GND 250 350 550 mV Table 10. AC Characteristics (VDD = VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Frequency Duty Cycle Symbol Test Condition Min Typ Max Unit F LVPECL, low power LVPECL, LVDS, CML, HCSL 1 — 725 MHz LVCMOS 1 — 200 MHz 200 MHz, 20/80%TR/TF<10% of period (LVCMOS) (12 mA drive) 40 50 60 % 20/80% TR/TF<10% of period (Differential) 48 50 52 % Required to meet prop delay and additive jitter specifications (20–80%) 0.75 — — V/ns DC Note: 50% input duty cycle. Minimum Input Clock Slew Rate SR Notes: 1. HCSL measurements were made with receiver termination. See Figure 7 on page 16. 2. Output to Output skew specified for outputs with an identical configuration. 3. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 4. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDDOX (3.3 V = 100 mVPP) and noise spur amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details. 6 Rev. 1.0 Si53306 Table 10. AC Characteristics (Continued) (VDD = VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Output Rise/Fall Time Symbol Test Condition Min Typ Max Unit TR/TF LVDS, 20/80% — — 350 ps LVPECL, 20/80% — — 350 ps HCSL , 20/80% — — 280 ps CML, 20/80% — — 350 ps Low-Power LVPECL, 20/80% — — 350 ps LVCMOS 200 MHz, 20/80%, 2 pF load — — 750 ps 500 — — ps LVCMOS (12mA drive with no load) 1250 2000 2750 ps LVPECL 675 875 1075 ps LVDS 675 875 1075 ps F = 1 MHz — 1570 — ns F = 100 MHz — 20 — ns F = 725 MHz — 5 — ns F = 1 MHz — 2000 — ns F = 100 MHz — 35 — ns F = 725 MHz — 5 — ns LVCMOS (12 mA drive to no load) — 50 120 ps LVPECL — 30 75 ps LVDS — 40 85 ps TPS Differential — — 150 ps PSRR 10 kHz sinusoidal noise — –72.5 — dBc 100 kHz sinusoidal noise — –70 — dBc 500 kHz sinusoidal noise — –67.5 — dBc 1 MHz sinusoidal noise — –62.5 — dBc 1 Minimum Input Pulse Width Propagation Delay Output Enable Time Output Disable Time Output to Output Skew2 Part to Part Skew3 Power Supply Noise Rejection4 TW TPLH, TPHL TEN TDIS TSK Notes: 1. HCSL measurements were made with receiver termination. See Figure 7 on page 16. 2. Output to Output skew specified for outputs with an identical configuration. 3. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 4. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDDOX (3.3 V = 100 mVPP) and noise spur amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details. Rev. 1.0 7 Si53306 Table 11. Additive Jitter, Differential Clock Input VDD Output Input1,2 Freq (MHz) Clock Format Amplitude VIN (Single-Ended, Peak-to-Peak) Differential Clock Format 20%-80% Slew Rate (V/ns) Additive Jitter (fs rms, 12 kHz to 20 MHz)3 Typ Max 3.3 725 Differential 0.15 0.637 LVPECL 45 65 3.3 725 Differential 0.15 0.637 LVDS 50 65 3.3 156.25 Differential 0.5 0.458 LVPECL 160 185 3.3 156.25 Differential 0.5 0.458 LVDS 150 200 2.5 725 Differential 0.15 0.637 LVPECL 45 65 2.5 725 Differential 0.15 0.637 LVDS 50 65 2.5 156.25 Differential 0.5 0.458 LVPECL 145 185 2.5 156.25 Differential 0.5 0.458 LVDS 145 195 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. AC-coupled differential inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. 8 Rev. 1.0 Si53306 Table 12. Additive Jitter, Single-Ended Clock Input VDD Output Input1,2 Freq (MHz) Clock Format Amplitude VIN (single-ended, peak to peak) Additive Jitter (fs rms, 12 kHz to 20 MHz)3 SE 20%-80% Slew Rate (V/ns) Clock Format Typ Max 3.3 200 Single-ended 1.70 1 LVCMOS4 120 160 3.3 156.25 Single-ended 2.18 1 LVPECL 160 185 3.3 156.25 Single-ended 2.18 1 LVDS 150 200 3.3 156.25 Single-ended 2.18 1 LVCMOS4 130 180 2.5 200 Single-ended 1.70 1 LVCMOS5 120 160 2.5 156.25 Single-ended 2.18 1 LVPECL 145 185 2.5 156.25 Single-ended 2.18 1 LVDS 145 195 2.5 156.25 Single-ended 2.18 1 LVCMOS5 140 180 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. DC-coupled single-ended inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. 4. Drive Strength: 12 mA, 3.3 V (SFOUT = 11). LVCMOS jitter is measured single-ended. 5. Drive Strength: 9 mA, 2.5 V (SFOUT = 11). LVCMOS jitter is measured single-ended. PSPL 5310A CLK SYNTH SMA103A 50 Si533xx DUT Balun PSPL 5310A CLKx AG E5052 Phase Noise Analyzer 50ohm /CLKx 50 Balun Figure 1. Differential Measurement Method Using a Balun Rev. 1.0 9 Si53306 Table 13. Thermal Conditions Parameter Symbol Test Condition Value Unit Thermal Resistance, Junction to Ambient JA Still air 49.6 °C/W Thermal Resistance, Junction to Case JC Still air 32.3 °C/W Table 14. Absolute Maximum Ratings Parameter Symbol Storage Temperature Min Typ Max Unit TS –55 — 150 C Supply Voltage VDD –0.5 — 3.8 V Input Voltage VIN –0.5 — VDD+ 0.3 V Output Voltage VOUT — — VDD+ 0.3 V ESD Sensitivity HBM — — 2000 V ESD Sensitivity CDM — — 500 V Peak Soldering Reflow Temperature TPEAK — — 260 C — — 125 C Maximum Junction Temperature Test Condition HBM, 100 pF, 1.5 k Pb-Free; Solder reflow profile per JEDEC J-STD-020 TJ Note: Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 10 Rev. 1.0 Si53306 2. Functional Description The Si53306 is a low jitter, low skew 1:4 differential buffer. The device has a universal input that accepts most common differential or LVCMOS input signals. The Si53306 features control pins for output enable, output signal format selection and LVCMOS drive strength. 2.1. Universal, Any-Format Input The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, lowpower LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 15 and 16 summarize the various ac- and dc-coupling options supported by the device. For the best high-speed performance, the use of differential formats is recommended. For both single-ended and differential input clocks, the fastest possible slew rate is recommended as low slew rates can increase the noise floor and degrade jitter performance. Though not required, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. Table 15. LVPECL, LVCMOS, and LVDS Input Clock Options LVPECL LVCMOS LVDS AC-Couple DC-Couple AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V N/A N/A No No Yes No 2.5/3.3 V Yes Yes No Yes Yes Yes Table 16. HCSL and CML Input Clock Options HCSL CML AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V No No Yes No 2.5/3.3 V Yes (3.3 V) Yes (3.3 V) Yes No 0.1 µF Si533xx CLKx 100 /CLKx 0.1 µF Figure 2. Differential HCSL, LVPECL, Low-Power LVPECL, LVDS, CML AC-Coupled Input Termination VDD 1 k VDDO= 3.3 V or 2.5 V VDD Si533xx CMOS Driver CLKx 50 /CLKx Rs VTERM = VDD/2 1 k VREF Figure 3. LVCMOS DC-Coupled Input Termination Rev. 1.0 11 Si53306 VDDO DC Coupled LVPECL Termination Scheme 1 R1 VDD R1 VDDO = 3.3V or 2.5V Si533xx CLKx 50 “Standard” LVPECL Driver /CLKx 50 R2 VTERM = VDDO – 2V R1 // R2 = 50 Ohm R2 3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm 2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm DC Coupled LVPECL Termination Scheme 2 VDD VDDO = 3.3V or 2.5V Si533xx 50 “Standard” LVPECL Driver CLKx /CLKx 50 50 50 VTERM = VDDO – 2V DC Coupled LVDS Termination VDD VDDO = 3.3V or 2.5V Si533xx CLKx 50 Standard LVDS Driver /CLKx 50 100 DC Coupled HCSL Source Termination Scheme VDDO = 3.3V 33 Si533xx 50 Standard HCSL Driver VDD CLKx /CLKx 33 50 50 50 Note: 33 Ohm series termination is optional depending on the location of the receiver. Figure 4. Differential DC-Coupled Input Terminations 12 Rev. 1.0 Si53306 2.2. Input Bias Resistors Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected. The non-inverting input is biased with a 18.75 k pull-down to GND and a 75 k pull-up to VDD. The inverting input is biased with a 75 k pull-up to VDD. VDD RPU RPU + RPD CLK0 or CLK1 – RPU = 75 k RPD = 18.75 k Figure 5. Input Bias Resistors 2.3. Universal, Any-Format Output Buffer The Si53306 has highly flexible output drivers that support a wide range of clock signal formats, including LVPECL, low power LVPECL, LVDS, CML, HCSL, and LVCMOS. SFOUT1 and SFOUT0 are 3-level inputs that can be pinstrapped to select the output clock signal formats. This feature enables the device to be used for format translation in addition to clock distribution, minimizing the number of unique buffer part numbers required in a typical application and simplifying design reuse. For EMI reduction applications, four LVCMOS drive strength options are available for each VDDO setting. Table 17. Output Signal Format Selection SFOUT1 SFOUT0 VDDOX = 3.3 V VDDOX = 2.5 V VDDOX = 1.8 V Open* Open* LVPECL LVPECL N/A 0 0 LVDS LVDS LVDS 0 1 LVCMOS, 24 mA drive LVCMOS, 18 mA drive LVCMOS, 12 mA drive 1 0 LVCMOS, 18 mA drive LVCMOS, 12 mA drive LVCMOS, 9 mA drive 1 1 LVCMOS, 12 mA drive LVCMOS, 9 mA drive LVCMOS, 6 mA drive Open* 0 LVCMOS, 6 mA drive LVCMOS, 4 mA drive LVCMOS, 2 mA drive Open* 1 LVPECL low power LVPECL low power N/A 0 Open* CML CML CML 1 Open* HCSL N/A N/A *Note: SFOUTx are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin floats to VDD/2. Rev. 1.0 13 Si53306 2.4. Synchronous Output Enable This buffer features a synchronous output enable (disable) feature. Output enable is sampled and synchronized on the falling edge of the input clock. This feature prevents runt pulses from being generated when the outputs are enabled or disabled. When OE is low, Q is held low and Q is held high for differential output formats. For LVCMOS output format options, both Q and Q are held low when OE is set low. The device outputs are enabled when the output enable pin is unconnected. See Table 10, “AC Characteristics,” on page 6 for output enable and output disable times. 2.5. Output Enable Logic All four outputs are controlled with a single output enable (OE) pin. Table 18 summarizes the input and output clock based upon the state of the input clock and the OE pin. Table 18. Output Enable Logic CLK OE1 Q2 L H L H H H X L L3 Notes: 1. Output enable active high 2. On the next negative transition of CLK. 3. Single-end: Q = low, Q = low Differential: Q = low, Q = high 2.6. Power Supply (VDD and VDDO) The buffer includes separate core (VDD) and output driver supplies (VDDOX). This feature allows the core to operate at a lower voltage than VDDO, reducing current consumption in mixed supply applications. The core VDD supports 3.3 V, 2.5 V, or 1.8 V. Each output bank has its own VDDOX supply, supporting 3.3 V, 2.5 V, or 1.8 V. 14 Rev. 1.0 Si53306 2.7. Output Clock Termination Options The recommended output clock termination options are shown below. VDDO DC Coupled LVPECL Termination Scheme 1 R1 R1 VDDO = 3.3V or 2.5V Si533xx VDD = VDDO 50 Q LVPECL Receiver Qn 50 R2 VTERM = VDDO – 2V R1 // R2 = 50 Ohm R2 3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm 2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm DC Coupled LVPECL Termination Scheme 2 VDDO = 3.3V or 2.5V Si533xx VDD = VDDO 50 Q LVPECL Receiver Qn 50 50 50 VTERM = VDDO – 2V VDDO AC Coupled LVPECL Termination Scheme 1 R1 VDDO = 3.3V or 2.5V Si533xx R1 0.1 uF VDD = 3.3V or 2.5V 50 Q LVPECL Receiver Qn 50 0.1 uF Rb R2 Rb R2 VBIAS = VDD – 1.3V R1 // R2 = 50 Ohm 3.3V LVPECL: R1 = 82.5 Ohm, R2 = 127 Ohm, Rb = 120 Ohm 2.5V LVPECL: R1 = 62.5 Ohm, R2 = 250 Ohm, Rb = 90 Ohm AC Coupled LVPECL Termination Scheme 2 V DDO = 3.3V or 2.5V Si533xx 0.1 uF V DD = 3.3V or 2.5V 50 Q LVPECL Receiver Qn 50 0.1 uF Rb Rb 50 50 V BIAS = V DD – 1.3 V 3.3V LVPECL: Rb = 120 Ohm 2.5V LVPECL: Rb = 90 Ohm Figure 6. LVPECL Output Termination Rev. 1.0 15 Si53306 DC Coupled LVDS and Low-Power LVPECL Termination VDDO = 3.3 V or 2.5 V, or 1.8 V (LVDS only) Si533xx VDD 50 Q Standard LVDS Receiver Qn 50 100 AC Coupled LVDS and Low-Power LVPECL Termination VDDO = 3.3 V or 2.5 V or 1.8 V (LVDS only) Si533xx 0.1 uF VDD 50 Q Standard LVDS Receiver Qn 50 0.1 uF 100 AC Coupled CML Termination VDDO = 3.3V or 2.5V or 1.8V Si533xx 0.1 uF VDD 50 Q Standard CML Receiver 100 Qn 50 0.1 uF DC Coupled HCSL Receiver Termination VDDO = 3.3V Si533xx VDD 50 Q Standard HCSL Receiver Qn 50 50 50 DC Coupled HCSL Source Termination VDDO = 3.3V Si533xx VDD 42.2 50 Q Qn 42.2 50 86.6 Standard HCSL Receiver 86.6 Figure 7. LVDS, CML, HCSL, and Low-Power LVPECL Output Termination 16 Rev. 1.0 Si53306 CMOS Receivers Si533xx CMOS Driver Zout Zo Rs 50 Figure 8. LVCMOS Output Termination Table 19. Recommended LVCMOS RS Series Termination SFOUT1 SFOUT0 RS (ohms) 3.3 V 2.5 V 1.8 V 0 1 33 33 33 1 0 33 33 33 1 1 33 33 0 Open 0 0 0 0 2.7.1. LVCMOS Output Termination To Support 1.5V and 1.2V LVCMOS clock outputs are natively supported at 1.8, 2.5, and 3.3V. However, 1.2V and 1.5V LVCMOS clock outputs can be supported via a simple resistor divider network that will translate the buffer’s 1.8V output to a lower voltage as shown in Figure 9 below. VDDOx= 1.8V R1 50 R2 LVCMOS 1.5V LVCMOS: R1 = 43 ohms, R2 = 300 ohms, IOUT = 12mA 1.2V LVCMOS: R1 = 58 ohms, R2 = 150 ohms, IOUT = 12mA R1 50 R2 Figure 9. 1.5V and 1.2V LVCMOS Low-Voltage Output Termination Rev. 1.0 17 Si53306 2.8. AC Timing Waveforms TPHL TSK VPP/2 CLK Q VPP/2 QN QM VPP/2 VPP/2 TPLH TSK Propagation Delay Output-Output Skew TF Q 80% VPP 20% VPP Rise/Fall Time Figure 10. AC Waveforms 18 80% VPP 20% VPP Q Rev. 1.0 TR Si53306 2.9. Typical Phase Noise Performance Each of the following three figures shows three phase noise plots superimposed on the same diagram. Source Jitter: Reference clock phase noise. Total Jitter (SE): Combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. Total Jitter (Diff): Combined source and clock buffer phase noise measured as a differential output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. The differential measurement as shown in each figure is made using a balun. See Figure 1 on page 9. Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS). The total jitter is a measure of the source plus the buffer's additive phase jitter. The additive jitter (rms) of the buffer can then be calculated (via root-sum-square addition). Figure 11. Source Jitter (156.25 MHz) Rev. 1.0 19 Si53306 Figure 12. Single-Ended Total Jitter (312.5 MHz) 20 Rev. 1.0 Si53306 Figure 13. Differential Total Jitter (625 MHz) 2.10. Power Supply Noise Rejection The device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs and SoCs and may reduce board-level filtering requirements. For more information, see “AN491: Power Supply Rejection for Low Jitter Clocks”. Rev. 1.0 21 Si53306 Q0 Q0 SFOUT0 6 7 8 Q3 SFOUT1 4 Q3 GND 5 3 GND PAD VDDO CLK 13 2 14 CLK 15 1 16 VDD OE 3. Pin Description: 16-Pin QFN 12 Q1 11 Q1 10 Q2 9 Q2 Table 20. Pin Description 22 Pin Name Type* Description 1 VDD P Core voltage supply. Bypass with 1.0 μF capacitor and place as close to the VDD pin as possible. 2 CLK I Input clock. 3 CLK I Input clock (complement). When the CLK is driven by a single-ended input, connect CLK to VDD/2. See Figure 1, “Differential Measurement Method Using a Balun,” on page 9. 4 GND GND 5 VDDO P Output voltage supply— All outputs (Q0 to Q3). Bypass with 1.0 μF capacitor and place as close to the VDDO pin as possible. 6 Q3 O Output clock 3 (complement). 7 Q3 O Output clock 3. 8 SFOUT1 I Output signal format control pin 1. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. Ground. Rev. 1.0 Si53306 Table 20. Pin Description (Continued) Pin Name Type* Description 9 Q2 O Output clock 2 (complement). 10 Q2 O Output clock 2. 11 Q1 O Output clock 1 (complement). 12 Q1 O Output clock 1. 13 SFOUT0 I Output signal format control pin 0. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 14 Q0 O Output clock 0 (complement). 15 Q0 O Output clock 0. 16 OE I Output enable. When OE = high, all outputs are enabled. When OE = low, Q is held low, and Q is held high for differential formats. For LVCMOS, both Q and Q are held low when OE is set low. OE contains an internal pull-up resistor. GND Pad GND GND Ground. *Pin types are: I = input, O = output, P = power, GND = ground. Rev. 1.0 23 Si53306 4. Ordering Guide Part Number Package Pb-Free, ROHS-6 Temperature Si53306-B-GM 16-QFN Yes –40 to 85 C Si53301/4-EVB Evaluation Board Yes — Notes: 1. To buy, go to http://www.supplier-direct.com/silabs/Cart.aspx?supplierUVID=63410000&partnumber=Si53306-BGM&quantity=1&issample=0. 2. To sample, go to http://www.supplier-direct.com/silabs/Cart.aspx?supplierUVID=63410000&partnumber=Si53306-BGM&quantity=1&issample=1. 24 Rev. 1.0 Si53306 5. Package Outline Figure 14 shows the package dimensions for the 3x3 mm 16-pin QFN package. Table 21 lists the values for the dimensions shown in the illustration. Figure 14. Si53306 3x3 mm 16-QFN Package Diagram Table 21. Package Diagram Dimensions Dimension Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 3.00 BSC. 1.65 1.70 e 0.50 BSC. E 3.00 BSC. 1.75 E2 1.65 1.70 1.75 L 0.30 0.40 0.50 aaa — — 0.10 bbb — — 0.10 ccc — — 0.08 ddd — — 0.10 eee — — 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. Rev. 1.0 25 Si53306 6. PCB Land Pattern Figure 15 shows the PCB land pattern dimensions for the 3x3 mm 16-pin QFN package. Table 22 lists the values for the dimensions shown in the illustration. Figure 15. Si53306 3x3 mm 16-QFN Package Land Pattern Table 22. PCB Land Pattern Dimensions Dimension mm C1 3.00 C2 3.00 E 0.50 X1 0.30 Y1 0.80 X2 1.75 Y2 1.75 Notes: General 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 8. A 2x2 array of 0.65 mm square openings on a 0.90 mm pitch should be used for the center ground pad. Card Assembly 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 26 Rev. 1.0 Si53306 7. Top Marking 7.1. Si53306 Top Marking 7.2. Top Marking Explanation Mark Method: Laser Font Size: 0.635 mm (25 mils) Right-Justified Line 1 Marking: Product ID 3306 Line 2 Marking: TTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form. Line 3 Marking Circle = 0.5 mm Diameter (Bottom-Left Justified) Pin 1 Identifier YWW = Date Code Corresponds to the last digit of the current year (Y) and the workweek (WW) of the mold date. Rev. 1.0 27 Si53306 DOCUMENT CHANGE LIST Revision 0.9 to Revision 1.0 Corrected Improved front-page block diagram. performance specifications with more detail. Added additional information to clarify the use of the voltage reference feature. Added pin type description to Table 20, “Pin Description,” on page 22. Added low-voltage termination options for 1.2 V and 1.5 V LVCMOS support. 28 Rev. 1.0 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. 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