Si4736/37/38/39-B20 B ROADCAST W EATHER BAND R ADIO R ECEIVER Features NOAA weather band support (162.4– No manual alignment necessary 162.55 MHz) Programmable reference clock only) Optional digital audio output (Si47/39 only) Optional digital audio output (Si4737/39 only) 2-wire and 3-wire control interface 2.7 to 5.5 V supply voltage Firmware upgradeable 3 x 3 x 0.55 mm 20-pin QFN package Pb-free/RoHS compliant Ordering Information: See page 30. Pin Assignments Si4736/37/38/39-GM (Top View) DFS RDS/RBDS processor (Si4737/39 GPO3/DCLK Programmable de-emphasis GPO2/INT Programmable soft mute control GPO1 (76–108 MHz) Worldwide AM band support (520–1710 kHz) (Si4736/37 only) 1050 Hz alert tone detection Excellent real-world performance Freq synthesizer with integrated VCO Advanced AM/FM seek tuning Automatic frequency control (AFC) Automatic gain control (AGC) Integrated LDO regulator Digital FM stereo decoder Adaptive noise suppression AM/FM/WB digital tuning NC Volume control N ot Pl Re ea c se om us me e nd Si e 47 d 36 for /3 N 7/ ew 38 D /3 e 9- sig C n 40 s Worldwide FM band support 20 19 18 17 16 Applications Emergency radios Table and portable radios Stereos Mini/micro systems Portable media players Boom boxes Cellular handsets Modules Clock radios Mini HiFi NC FMI 2 RFGND 3 Si473x AMI LNA AGC LOW-IF ADC 2.7– 5.5 V VDD LDO AFC RCLK GND Rev. 1.0 4/08 DOUT DFS GPO/DCLK DAC ROUT DAC LOUT CONTROL INTERFACE SEN AGC 9 10 VIO 14 LOUT 13 ROUT 12 GND 11 VDD Patents pending DSP ADC 8 15 DOUT VIO 1.5–3.6 V Notes: 1. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Universal Antenna Selection and Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 2. Place Si4736/37/38/39 as close as possible to antenna jack and keep the FMI and AMI traces as short as possible. RST LNA SCLK FMI DIGITAL AUDIO (Si4737/ 39) SDIO RFGND RDS (Si4737/ 39) 7 RCLK Functional Block Diagram 6 SDIO RST 5 The Si4736/37/38/39 is the first digital CMOS AM/FM/WB radio receiver IC that integrates the complete tuner function from antenna input to audio output. FM/ WB ANT GND PAD AMI 4 Description AM ANT 1 SCLK SEN Copyright © 2008 by Silicon Laboratories Si4736/37/38/39-B20 Si4736/37/38/39-B20 2 Rev. 1.0 Si4736/37/38/39-B20 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.4. AM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.5. SW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6. LW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.7. Digital Audio Interface (Si4735 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.8. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.9. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.10. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.11. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.12. RDS/RBDS Processor (Si4735 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.13. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.14. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.15. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.16. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.17. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.18. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.19. Reset, Power Up, and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.20. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6. Pin Descriptions: Si4734/35-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.1. Si4734/35 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9. Package Outline: Si4734/35 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10. PCB Land Pattern: Si4734/35 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Rev. 1.0 3 Si4736/37/38/39-B20 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Supply Voltage VDD 2.7 — 5.5 V Interface Supply Voltage VIO 1.5 — 3.6 V Power Supply Power-Up Rise Time VDDRISE 10 — — µs Interface Power Supply Power-Up Rise Time VIORISE 10 — — µs TA –20 25 85 C Ambient Temperature Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at VDD = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless otherwise stated. Table 2. Absolute Maximum Ratings1,2 Parameter Symbol Value Unit Supply Voltage VDD –0.5 to 5.8 V Interface Supply Voltage VIO –0.5 to 3.9 V 3 Input Current IIN 10 mA Input Voltage3 VIN –0.3 to (VIO + 0.3) V Operating Temperature TOP –40 to 95 C Storage Temperature TSTG –55 to 150 C 0.4 VpK RF Input Level 4 Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. The Si4736/37/38/39 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV HBM. Handling and assembly of these devices should only be done at ESD-protected workstations. 3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3. 4. At RF input pins, FMI and AMI. 4 Rev. 1.0 Si4736/37/38/39-B20 Table 3. DC Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit — 19.2 22 mA — 19.8 23 mA — 19.9 23 mA — 18.0 20.5 mA — 19.2 22 mA — 19.8 23 mA — 17.2 20.5 mA FM Mode Supply Current Supply Current IFM 1 IFM RDS Supply Current2 Supply Current 2 Low SNR level IFM IFMD Digital Output Mode WB Mode Supply Current IFM Supply Current IFM Supply Current IFMD Low SNR level AM Mode Supply Current Supply Current 2 IAM Analog Output Mode — 17.3 20.5 mA IAMD Digital Output Mode — 15.5 20.5 mA Supplies and Interface Interface Supply Current IIO — 320 600 µA VDD Powerdown Current IDDPD — 10 20 µA VIO Powerdown Current IIOPD — 1 10 µA SCLK, RCLK inactive High Level Input Voltage3 VIH 0.7 x VIO — VIO + 0.3 V Voltage3 VIL –0.3 — 0.3 x VIO V High Level Input Current3 IIH VIN = VIO = 3.6 V –10 — 10 µA Current3 IIL VIN = 0 V, VIO = 3.6 V –10 — 10 µA High Level Output Voltage4 VOH IOUT = 500 µA 0.8 x VIO — — V Voltage4 VOL IOUT = –500 µA — — 0.2 x VIO V Low Level Input Low Level Input Low Level Output Notes: 1. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions. 2. Specifications are guaranteed by characterization. 3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, and DFS. 4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3. Rev. 1.0 5 Si4736/37/38/39-B20 Table 4. Reset Timing Characteristics1,2,3 (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Min Typ Max Unit RST Pulse Width and GPO1, GPO2/INT Setup to RST tSRST 100 — — µs GPO1, GPO2/INT Hold from RST tHRST 30 — — ns Important Notes: 1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST. 2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. 4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then minimum tSRST is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and GPO2 low. tSRST RST tHRST 70% 30% GPO1 70% GPO2/ INT 70% 30% 30% Figure 1. Reset Timing Parameters for Busmode Select 6 Rev. 1.0 Si4736/37/38/39-B20 Table 5. 2-Wire Control Interface Characteristics1,2,3 (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fSCL 0 — 400 kHz SCLK Low Time tLOW 1.3 — — µs SCLK High Time tHIGH 0.6 — — µs SCLK Input to SDIO Setup (START) tSU:STA 0.6 — — µs SCLK Input to SDIO Hold (START) tHD:STA 0.6 — — µs SDIO Input to SCLK Setup tSU:DAT 100 — — ns SDIO Input to SCLK Hold4,5 tHD:DAT 0 — 900 ns SCLK input to SDIO Setup (STOP) tSU:STO 0.6 — — µs STOP to START Time tBUF 1.3 — — µs SDIO Output Fall Time tf:OUT — 250 ns — 300 ns Cb 20 + 0.1 ----------1pF SDIO Input, SCLK Rise/Fall Time tf:IN tr:IN Cb 20 + 0.1 ----------1pF SCLK, SDIO Capacitive Loading Cb — — 50 pF Input Filter Pulse Suppression tSP — — 50 ns Notes: 1. When VIO = 0 V, SCLK and SDIO are low impedance. 2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST. 3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 4. The Si4736/37/38/39 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum tHD:DAT specification. 5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 kHz, tHD:DAT may be violated as long as all other timing parameters are met. Rev. 1.0 7 Si4736/37/38/39-B20 SCLK SDIO tSU:STA tHD:STA tLOW START tr:IN tHIGH tr:IN tf:IN tSP tSU:STO tBUF 70% 30% 70% 30% tf:IN, tf:OUT tHD:DAT tSU:DAT STOP START Figure 2. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, R/W SDIO START ADDRESS + R/W D7-D0 ACK DATA D7-D0 ACK DATA ACK Figure 3. 2-Wire Control Interface Read and Write Timing Diagram 8 Rev. 1.0 STOP Si4736/37/38/39-B20 Table 6. 3-Wire Control Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fCLK 0 — 2.5 MHz SCLK High Time tHIGH 25 — — ns SCLK Low Time tLOW 25 — — ns tS 20 — — ns SDIO Input to SCLKHold tHSDIO 10 — — ns SEN Input to SCLKHold tHSEN 10 — — ns SCLKto SDIO Output Valid tCDV Read 2 — 25 ns SCLKto SDIO Output High Z tCDZ Read 2 — 25 ns SCLK, SEN, SDIO, Rise/Fall time tR, tF — — 10 ns SDIO Input, SEN to SCLKSetup Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. SCLK 70% 30% tS SEN SDIO tR tF 70% tHSDIO tHIGH tLOW tHSEN tS 30% 70% 30% A7 A6-A5, R/W, A4-A1 A0 D15 D14-D1 Address In D0 Data In Figure 4. 3-Wire Control Interface Write Timing Parameters SCLK 70% 30% tHSDIO tS SEN 70% tCDV tHSEN tCDZ tS 30% 70% SDIO A7 30% A6-A5, R/W, A4-A1 Address In A0 D15 ½ Cycle Bus Turnaround D14-D1 D0 Data Out Figure 5. 3-Wire Control Interface Read Timing Parameters Rev. 1.0 9 Si4736/37/38/39-B20 Table 7. SPI Control Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fCLK 0 — 2.5 MHz SCLK High Time tHIGH 25 — — ns SCLK Low Time tLOW 25 — — ns tS 15 — — ns SDIO Input to SCLKHold tHSDIO 10 — — ns SEN Input to SCLKHold tHSEN 5 — — ns SCLKto SDIO Output Valid tCDV Read 2 — 25 ns SCLKto SDIO Output High Z tCDZ Read 2 — 25 ns SCLK, SEN, SDIO, Rise/Fall time tR, tF — — 10 ns SDIO Input, SEN to SCLKSetup Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. SCLK 70% 30% tHIGH SEN SDIO tLOW tHSDIO tR tF tHSEN 70% 30% 70% 30% tS tS C7 C6–C1 C0 D7 Control Byte In D6–D1 D0 8 Data Bytes In Figure 6. SPI Control Interface Write Timing Parameters SCLK 70% 30% tCDV tS SEN 70% tHSEN tHSDIO tS 30% tCDZ SDIO 70% C7 C6–C1 C0 D7 D6–D1 D0 30% Control Byte In Bus Turnaround 16 Data Bytes Out (SDIO or GPO1) Figure 7. SPI Control Interface Read Timing Parameters 10 Rev. 1.0 Si4736/37/38/39-B20 Table 8. Digital Audio Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit DCLK Cycle Time tDCT 26 — 1000 ns DCLK Pulse Width High tDCH 10 — — ns DCLK Pulse Width Low tDCL 10 — — ns DFS Set-up Time to DCLK Rising Edge tSU:DFS 5 — — ns DFS Hold Time from DCLK Rising Edge tHD:DFS 5 — — ns tPD:DOUT 0 — 12 ns DOUT Propagation Delay from DCLK Falling Edge tDCH tDCL DCLK tDCT DFS tHD:DFS tSU:DFS DOUT tPD:OUT Figure 8. Digital Audio Interface Timing Parameters, I2S Mode Rev. 1.0 11 Si4736/37/38/39-B20 Table 9. FM Receiver Characteristics1,2 (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Input Frequency Test Condition fRF Min Typ Max Unit 76 — 108 MHz Sensitivity with Headphone Network3,4,5 (S+N)/N = 26 dB — 2.2 3.5 µV EMF Sensitivity with 50 Network3,4,5,6 (S+N)/N = 26 dB — 1.1 — µV EMF RDS Sensitivity6 f = 2 kHz, RDS BLER < 5% — 15 — µV EMF 3 4 5 k 4 5 6 pF 100 105 — dBµV EMF m = 0.3 40 50 — dB Adjacent Channel Selectivity ±200 kHz 35 50 — dB Alternate Channel Selectivity ±400 kHz 60 70 — dB In-band 35 — — dB 72 80 90 mVRMS — — 1 dB LNA Input Resistance6,7 6,7 LNA Input Capacitance Input IP36,8 AM Suppression3,4,6,7 Spurious Response Rejection6 Audio Output Voltage3,4,7 3,7,9 Audio Output L/R Imbalance Low6 –3 dB — — 30 Hz Audio Frequency Response High6 –3 dB 15 — — kHz 25 — — dB 55 63 — dB — 58 — dB — 0.1 0.5 % FM_DEEMPHASIS = 2 70 75 80 µs FM_DEEMPHASIS = 1 45 50 54 µs RL Single-ended 10 — — k CL Single-ended — — 50 pF Audio Frequency Response Audio Stereo Separation7,9 Audio Mono S/N 3,4,5,7,10 Audio Stereo S/N 4,5,7,10,11 Audio THD3,7,9 De-emphasis Time Constant6 Audio Output Load Resistance6,10 Audio Output Load Capacitance6,10 Notes: 1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests. Tested at RF = 98.1 MHz. 2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and Universal Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise. 4. f = 22.5 kHz. 5. BAF = 300 Hz to 15 kHz, A-weighted. 6. Guaranteed by characterization. 7. VEMF = 1 mV. 8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. Refer to "6. Pin Descriptions: Si4736/37/38/39-GM" on page 29. 9. f = 75 kHz. 10. At LOUT and ROUT pins. 11. Analog audio output mode. 12. At temperature (25 °C). 12 Rev. 1.0 Si4736/37/38/39-B20 Table 9. FM Receiver Characteristics1,2 (Continued) (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Seek/Tune Time6 Powerup Time6 12 RSSI Offset Test Condition Min Typ Max Unit RCLK tolerance = 100 ppm — — 80 ms/channel From powerdown — — 110 ms Input levels of 8 and 60 dBµV at RF Input –3 — 3 dB Notes: 1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests. Tested at RF = 98.1 MHz. 2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and Universal Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise. 4. f = 22.5 kHz. 5. BAF = 300 Hz to 15 kHz, A-weighted. 6. Guaranteed by characterization. 7. VEMF = 1 mV. 8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. Refer to "6. Pin Descriptions: Si4736/37/38/39-GM" on page 29. 9. f = 75 kHz. 10. At LOUT and ROUT pins. 11. Analog audio output mode. 12. At temperature (25 °C). Table 10. WB Receiver Characteristics1 (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6V, TA = 25 °C) Parameter Min Typ Max Unit 162.4 — 162.55 MHz SINAD = 12 dB — 0.9 — µV EMF +/-25 kHz — 52 — dB Audio S/N2,3,4,5 Mono — 45 — dB Audio Frequency Response Low6 –3 dB — — 300 Hz Audio Frequency Response High6 –3 dB 3 — — kHz Input Frequency Sensitivity2,3 Adjacent Channel Selectivity Symbol Test Condition fR Notes: 1. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Universal Antenna Selection and Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 2. FMOD = 1 kHz. 3. f = 3 kHz. 4. VEMF = 1 mV. 5. A-weighted. 6. Guaranteed by characterization Rev. 1.0 13 Si4736/37/38/39-B20 Table 11. AM Receiver Characteristics1 (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Input Frequency Sensitivity Symbol Test Condition Min Typ Max Unit 520 — 1710 kHz (S+N)/N = 26 dB — 25 35 µV EMF THD < 8% — 300 — mVRMS ∆VDD = 100 mVRMS, 100 Hz — 40 — dB 54 60 67 mVRMS 50 56 — dB — 0.1 0.5 % 180 — 450 µH — — 110 ms fRF 2,3,4,5, 6 Large Signal Voltage Handling5,7 Power Supply Rejection Ratio Audio Output Voltage2,8 Audio S/N 2,3,4,6,8 Audio THD2,4,8 5,9 Antenna Inductance Powerup Time From powerdown Notes: 1. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and Universal Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 2. FMOD = 1 kHz, 30% modulation, A-weighted, 2 kHz channel filter. 3. BAF = 300 Hz to 15 kHz, A-weighted. 4. fRF = 1000 kHz, f = 10 kHz. 5. Guaranteed by characterization. 6. Analog audio output mode. 7. See “AN388: Evaluation Board Test Procedure” for evaluation method. 8. VIN = 5 mVrms. 9. Stray capacitance on antenna and board must be < 10 pF to achieve full tuning range at higher inductance levels. 14 Rev. 1.0 Si4736/37/38/39-B20 Table 12. Reference Clock and Crystal Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit 31.130 32.768 40000.0 kHz –50 — 50 ppm 1 — 4095 31.130 32.768 34.406 kHz Crystal Oscillator Frequency — 32.768 — kHz Crystal Frequency Tolerance* –100 — 100 ppm — — 3.5 pF Reference Clock RCLK Supported Frequencies* RCLK Frequency Tolerance REFCLK_PRESCALE REFCLK Crystal Oscillator Board Capacitance *Note: The Si4736/37/38/39 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies between 31.130 kHz and 40 MHz that are not supported. See AN332, Table 6 for more details. 15 Rev. 1.0 Si4736/37/38/39-B20 2. Typical Application Schematic GPO1 GPO2/INT R1 R2 GPO3/DCLK 2 FMI 3 RFGND FMIP L1 AM antenna C5 4 AMI 5 GPO3/DCLK DFS NC GPO2/INT 1 GPO1 NC 20 19 18 17 16 DFS U1 Si473x DOUT 15 R3 DOUT Optional: Digital Audio Output 14 13 ROUT/DOUT 12 LOUT/DFS GND VDD RST LOUT ROUT 11 VBATTERY 2.7 to 5.5 V C1 RST 6 7 8 9 10 SEN SCLK SDIO RCLK VIO Si4736/37 only X1 GPO3 SEN SCLK SDIO RCLK VIO 1.5 to 3.6 V C2 RCLK C3 Optional: for crystal oscillator option L2 RFGND AMI T1 C5 Optional: AM air loop antenna Notes: 1. Place C1 close to VDD pin. 2. All grounds connect directly to GND plane on PCB. 3. Pins 1 and 20 are no connects, leave floating. 4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Universal Antenna Selection and Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface. 6. RFGND should be locally isolated from GND. 7. Place Si4736/37/38/39 as close as possible to antenna jack and keep the FMI and AMI traces as short as possible. 16 Rev. 1.0 Si4736/37/38/39-B20 3. Bill of Materials Component(s) Value/Description Supplier C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R Murata C5 Coupling capacitor, 0.47 µF, ±20%, Z5U/X7R Murata L1 Ferrite loop stick, 180–450 µH Jiaxin U1 Si4736/37/38/39 AM/FM/WB Radio Tuner Silicon Laboratories Optional Components T1 Transformer, 1–5 turns ratio Jiaxin, UMEC L2 Air loop antenna, 10–20 µH Various Crystal load capacitors, 22 pF, ±5%, COG (Optional: for crystal oscillator option) Venkel X1 32.768 kHz crystal (Optional: for crystal oscillator option) Epson R1 Resistor, 2 k(Optional: for digital audio) Venkel R2 Resistor, 2 k(Optional: for digital audio) Venkel R3 Resistor, 600 (Optional: for digital audio) Venkel C2, C3 Rev. 1.0 17 Si4736/37/38/39-B20 4. Functional Description 4.1. Overview Si473x AMI RDS (Si4737/ 39) AGC LOW-IF GPO/DCLK ROUT DAC LOUT DSP ADC VDD LDO AFC RCLK GND DFS CONTROL INTERFACE VIO 1.5–3.6 V RST LNA DOUT DAC SDIO FMI AGC 2.7– 5.5 V DIGITAL AUDIO (Si4737/ 39) ADC SCLK FM/ WB ANT RFGND LNA SEN AM ANT Figure 9. Functional Block Diagram The Si4736/37 and Si4738/39 are the industry's first fully integrated, 100% CMOS AM/FM/WB and FM/WB radio receiver ICs. Offering unmatched integration and PCB space savings, the Si4736/37/38/39 requires only two external components and less than 15 mm2 of board area, excluding the antenna inputs. The Si4736/37/38/39 AM/FM/WB radio provides the space savings and low power consumption necessary for portable devices while delivering the high performance and design simplicity desired for all AM/FM/WB solutions. Leveraging Silicon Laboratories' proven and patented Si4700/01 FM tuner's digital low intermediate frequency (low-IF) receiver architecture, the Si4736/37/38/39 delivers superior RF performance and interference rejection in both AM and FM bands. The high integration and complete system production test simplifies designin, increases system quality, and improves manufacturability. wire control interface, SPI, and a Si4700/01 backwardscompatible, 3-wire control interface. The Si4736/37/38/39 utilizes digital processing to achieve high fidelity, optimal performance, and design flexibility. The chip provides excellent pilot rejection, selectivity, and unmatched audio performance, and offers both the manufacturer and the end-user extensive programmability and flexibility in listening experience. The Si4737/39 incorporates a digital processor for the European Radio Data System (RDS) and the North American Radio Broadcast Data System (RBDS), and includes all required symbol decoding, block synchronization, error detection, and error correction functions. Using this feature, the Si4737/39 enables broadcast data such as station identification and song name to be displayed to the user. The Si4736/37/38/39 is a feature-rich solution including 1050 Hz tone detection, advanced seek algorithms, soft mute, auto-calibrated digital tuning, and FM stereo processing. In addition, the Si4736/37/38/39 provides analog and digital audio outputs and a programmable reference clock. The device supports I2C-compatible, 2- 18 Rev. 1.0 Si4736/37/38/39-B20 4.2. Operating Modes 4.4. AM Receiver (Si4736/37) The Si4736/37/38/39 operates in an FM receive, an AM receive, or a weather band receive mode. In FM mode and WB mode, radio signals are received on FMI (pin 2) and processed by the FM front-end circuitry. In AM mode, radio signals are received on AMI (pin 4) and processed by the AM front-end circuitry. In addition to the receiver mode, there is a clocking mode to choose to clock the Si473x from a reference clock or crystal. On the Si4737/39, there is an audio output mode to choose between an analog and/or digital audio output. In the analog audio output mode, pin 13 is ROUT, pin 14 is LOUT, and pin 17 is GPO3. In the digital audio mode, pin 15 is DOUT, pin 16 is DFS, and pin 17 is DCLK. Concurrent analog/digital audio output mode requires pins 13, 14, 15, 16, and 17. The receiver mode and the audio output mode are set by the POWER_UP command listed in Table 12. Si473x Command Summary. The highly integrated Si4736/37 supports worldwide AM band reception from 520 to 1710 kHz using a digital low-IF architecture with a minimum number of external components and no manual alignment required. This digital low-IF architecture allows for high-precision filtering and offers excellent selectivity and noise suppression. The DSP also provides 9 or 10 kHz channel selection, AM demodulation, soft mute, and additional features such as adjustable channel bandwidth settings. Similar to the FM receiver, the integrated LNA and AGC optimize sensitivity and rejection of strong interferers allowing better reception of weak stations. 4.3. FM Receiver The Si4736/37/38/39 FM receiver is based on the proven Si4700/01 FM tuner. The receiver uses a digital low-IF architecture, allowing the elimination of external components and factory adjustments. The Si4736/37/38/39 integrates a low noise amplifier (LNA) supporting the worldwide FM broadcast band (76 to 108 MHz). An AGC circuit controls the gain of the LNA to optimize sensitivity and rejection of strong interferers. For testing purposes, the AGC can be disabled. Refer to Section "5. Commands and Properties" on page 25 for additional programming and configuration information. An image-reject mixer downconverts the RF signal to low-IF. The quadrature mixer output is amplified, filtered, and digitized with high resolution analog-todigital converters (ADCs). This advanced architecture allows the Si4736/37/38/39 to perform channel selection, FM demodulation, and stereo audio processing to achieve superior performance compared to traditional analog architectures. 19 The Si4736/37 provides highly accurate digital AM tuning without factory adjustments. To offer maximum flexibility, the receiver supports a wide range of ferrite loop sticks from 180–450 µH. An air loop antenna is supported by using a transformer to increase the effective inductance from the air loop. Using a 1:5 turn ratio inductor, the inductance is increased by 25 times and easily supports all typical AM air loop antennas, which generally vary between 10 and 20 µH. 4.5. Weather Band Receiver The Si4736/37/38/39 supports weather band reception from 162.4 to 162.55 MHz. The highly integrated Si4736/37/38/39 meets NOAA specification, receives all seven NOAA specified frequencies, implements narrowband FM de-emphasis, and supports 1050 Hz alert tone detection. In addition, the Si4736/37/38/39 provides advanced features not available on conventional radios, such as an AFC and a dynamic channel bandwidth filter. The AFC locks on to the strongest signal within a narrow, adjustable frequency range to compensate for any potential frequency errors such as crystal tolerance or transmit frequency errors. The AFC ensures the channel filter is always centered on the desired channel providing optimal reception. The dynamic channel bandwidth feature utilizes a wide filter in strong signal conditions to provide best sound quality and a narrower filter in weak conditions to provide best sensitivity. Rev. 1.0 Si4736/37/38/39-B20 4.6. Digital Audio Interface (Si4737/39 Only) The digital audio interface operates in slave mode and supports three different audio data formats: I2S Left-Justified DSP Mode 4.6.1. Audio Data Formats In I2S mode, by default the MSB is captured on the second rising edge of DCLK following each DFS transition. The remaining bits of the word are sent in order, down to the LSB. The left channel is transferred first when the DFS is low, and the right channel is transferred when the DFS is high. In Left-Justified mode, by default the MSB is captured on the first rising edge of DCLK following each DFS transition. The remaining bits of the word are sent in order, down to the LSB. The left channel is transferred first when the DFS is high, and the right channel is transferred when the DFS is low. (OFALL = 1) INVERTED DCLK (OFALL = 0) DCLK I2S (OMODE = 0000) In DSP mode, the DFS becomes a pulse with a width of 1DCLK period. The left channel is transferred first, followed right away by the right channel. There are two options in transferring the digital audio data in DSP mode: the MSB of the left channel can be transferred on the first rising edge of DCLK following the DFS pulse or on the second rising edge. In all audio formats, depending on the word size, DCLK frequency and sample rates, there may be unused DCLK cycles after the LSB of each word before the next DFS transition and MSB of the next word. In addition, if preferred, the user can configure the MSB to be captured on the falling edge of DCLK via properties. The number of audio bits can be configured for 8, 16, 20, or 24 bits. 4.6.2. Audio Sample Rates The device supports a number of industry-standard sampling rates including 32, 40, 44.1, and 48 kHz. The digital audio interface enables low-power operation by eliminating the need for redundant DACs on the audio baseband processor. LEFT CHANNEL DFS RIGHT CHANNEL 1 DCLK 1 DCLK 1 DOUT 2 n-2 3 n-1 MSB n 1 LSB MSB 2 n-2 3 n-1 n LSB Figure 10. I2S Digital Audio Format (OFALL = 1) INVERTED DCLK (OFALL = 0) DCLK DFS LEFT CHANNEL RIGHT CHANNEL Left-Justified (OMODE = 0110) 1 DOUT 2 3 n-2 n-1 MSB n 1 LSB MSB 2 n-2 3 n-1 n LSB Figure 11. Left-Justified Digital Audio Format DCLK (OFALL = 0) DFS RIGHT CHANNEL LEFT CHANNEL (OMODE = 1100) DOUT (MSB at 1 rising edge) 1 st 2 3 n-2 n-1 MSB (OMODE = 1000) 1 LSB MSB n-1 n 1 LSB MSB 2 3 1 2 3 n-2 n-1 n LSB RIGHT CHANNEL MSB 2 Figure 12. DSP Digital Audio Format 20 n-2 LEFT CHANNEL 1 DCLK DOUT (MSB at 2 rising edge) nd n Rev. 1.0 3 n-2 n-1 n LSB Si4736/37/38/39-B20 4.8. De-emphasis The output of the FM demodulator is a stereo multiplexed (MPX) signal. The MPX standard was developed in 1961, and is used worldwide. Today's MPX signal format consists of left + right (L+R) audio, left – right (L–R) audio, a 19 kHz pilot tone, and RDS/RBDS data as shown in Figure 13 below. Pre-emphasis and de-emphasis is a technique used by FM broadcasters to improve the signal-to-noise ratio of FM receivers by reducing the effects of high-frequency interference and noise. When the FM signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. The Si4736/37/38/39 incorporates a de-emphasis filter which attenuates high frequencies to restore a flat frequency response. Two time constants are used in various regions. The de-emphasis time constant is programmable to 50 or 75 µs and is set by the FM_DEEMPHASIS property. Modulation Level 4.7. Stereo Audio Processing Mono Audio Left + Right Stereo Pilot Stereo Audio Left - Right RDS/ RBDS 4.9. Stereo DAC 0 15 19 23 38 53 57 Frequency (kHz) Figure 13. MPX Signal Spectrum High-fidelity stereo digital-to-analog converters (DACs) drive analog audio signals onto the LOUT and ROUT pins. The audio output may be muted. Volume is adjusted digitally with the RX_VOLUME property. 4.7.1. Stereo Decoder 4.10. Soft Mute The Si4736/37/38/39's integrated stereo decoder automatically decodes the MPX signal using DSP techniques. The 0 to 15 kHz (L+R) signal is the mono output of the FM tuner. Stereo is generated from the (L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is used as a reference to recover the (L–R) signal. Output left and right channels are obtained by adding and subtracting the (L+R) and (L–R) signals respectively. The Si4737/39 uses frequency information from the 19 kHz stereo pilot to recover the 57 kHz RDS/RBDS signal. The soft mute feature is available to attenuate the audio outputs and minimize audible noise in very weak signal conditions. The softmute attenuation level is adjustable using the FM_SOFT_MUTE_MAX_ATTENUATION and AM_SOFT_MUTE_MAX_ATTENUATION properties. 4.7.2. Stereo-Mono Blending Adaptive noise suppression is employed to gradually combine the stereo left and right audio channels to a mono (L+R) audio signal as the signal quality degrades to maintain optimum sound fidelity under varying reception conditions. Stereo/mono status can be monitored with the FM_RSQ_STATUS command. Mono operation can be forced with the FM_BLEND_MONO_THRESHOLD property. 4.11. RDS/RBDS Processor (Si4737/39 Only) The Si4737/39 implements an RDS/RBDS* processor for symbol decoding, block synchronization, error detection, and error correction. The Si4737/39 device is user configurable and provides an optional interrupt when RDS is synchronized, loses synchronization, and/or the user configurable RDS FIFO threshold has been met. The Si4737/39 reports RDS decoder synchronization status, and detailed bit errors in the information word for each RDS block with the FM_RDS_STATUS command. The range of reportable block errors is 0, 1–2, 3–5, or 6+. More than six errors indicates that the corresponding block information word contains six or more non-correctable errors, or that the block checkword contains errors. *Note: RDS/RBDS is referred to only as RDS throughout the remainder of this document. 21 Rev. 1.0 Si4736/37/38/39-B20 4.12. Tuning The frequency synthesizer uses Silicon Laboratories’ proven technology, including a completely integrated VCO. The frequency synthesizer generates the quadrature local oscillator signal used to downconvert the RF input to a low intermediate frequency. The VCO frequency is locked to the reference clock and adjusted with an AFC servo loop during reception. The tuning frequency can be directly programmed using the WB_TUNE_FREQ, FM_TUNE_FREQ, and AM_TUNE_FREQ commands. The Si4736/37/38/39 supports channel spacing of 25 kHz in WB mode; 50, 100, or 200 kHz in FM mode; and 9 or 10 kHz in AM mode. 4.13. Seek Seek tuning will search up or down for a valid channel. Valid channels are found when the receive signal strength indicator (RSSI) and the signal-to-noise ratio (SNR) values exceed the set threshold. Using the SNR qualifier rather than solely relying on the more traditional RSSI qualifier can reduce false stops and increase the number of valid stations detected. Seek is initiated using the FM_SEEK_START and AM_SEEK_START commands. The RSSI and SNR threshold settings are adjustable using properties (see Table 15). Two seek options are available. The device will either wrap or stop at the band limits. If the seek operation is unable to find a channel, the device will indicate failure and return to the channel selected before the seek operation began. which may result in mistunes, false stops, and/or lower SNR. For best seek/tune results, Silicon Laboratories recommends that all SDIO data traffic be suspended during Si4736/37/38/39 seek and tune operations. This is achieved by keeping the bus quiet for all other devices on the bus, and delaying tuner polling until the tune or seek operation is complete. The STC (seek/tune complete) interrupt should be used instead of polling to determine when a seek/tune operation is complete. 4.15. Control Interface A serial port slave interface is provided, which allows an external controller to send commands to the Si4736/37/38/39 and receive responses from the device. The serial port can operate in three bus modes: 2-wire mode, 3-wire mode, or SPI mode. The Si4736/37/38/39 selects the bus mode by sampling the state of the GPO1 and GPO2 pins on the rising edge of RST. The GPO1 pin includes an internal pull-up resistor, which is connected while RST is low, and the GPO2 pin includes an internal pull-down resistor, which is connected while RST is low. Therefore, it is only necessary for the user to actively drive pins which differ from these states. See Table 13. Table 13. Bus Mode Select on Rising Edge of RST Seek is not available for weather band. 4.14. Reference Clock The Si4736/37/38/39 reference clock is programmable, supporting RCLK frequencies in Table 12. Refer to Table 3, “DC Characteristics,” on page 5 for switching voltage levels and Table 9, “FM Receiver Characteristics” on page 12 for frequency tolerance information. An onboard crystal oscillator is available to generate the 32.768 kHz reference when an external crystal and load capacitors are provided. Refer to "2. Typical Application Schematic" on page 16. This mode is enabled using the POWER_UP command, see Table 14, “Si473x Command Summary,” on page 25. The Si4736/37/38/39 performance may be affected by data activity on the SDIO bus when using the integrated internal oscillator. SDIO activity results from polling the tuner for status or communicating with other devices that share the SDIO bus. If there is SDIO bus activity while the Si4736/37/38/39 is performing the seek/tune function, the crystal oscillator may experience jitter, 22 Bus Mode GPO1 GPO2 2-Wire 1 0 SPI 1 1 (must drive) 3-Wire 0 (must drive) 0 After the rising edge of RST, the pins GPO1 and GPO2 are used as general purpose output (O) pins, as described in Section “4.16. GPO Outputs”. In any bus mode, commands may only be sent after VIO and VDD supplies are applied. In any bus mode, before sending a command or reading a response, the user must first read the status byte to ensure that the device is ready (CTS bit is high). 4.15.1. 2-Wire Control Interface Mode When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. Also, a start condition must not occur within 300 ns before the rising edge of RST. The 2-wire bus mode uses only the SCLK and SDIO pins for signaling. A transaction begins with the START condition, which occurs when SDIO falls while SCLK is high. Next, the user drives an 8-bit control word serially Rev. 1.0 Si4736/37/38/39-B20 on SDIO, which is captured by the device on rising edges of SCLK. The control word consists of a 7-bit device address, followed by a read/write bit (read = 1, write = 0). The Si4736/37/38/39 acknowledges the control word by driving SDIO low on the next falling edge of SCLK. the Si4736/37/38/39 will drive the 16-bit read data word serially on SDIO, changing the state of SDIO on each rising edge of SCLK. Although the Si4736/37/38/39 will respond to only a single device address, this address can be changed with the SEN pin (note that the SEN pin is not used for signaling in 2-wire mode). When SEN = 0, the 7-bit device address is 0010001b. When SEN = 1, the address is 1100011b. In 3-wire mode, commands are sent by first writing each argument to register(s) 0xA1–0xA3, then writing the command word to register 0xA0. A response is retrieved by reading registers 0xA8–0xAF. For write operations, the user then sends an 8-bit data byte on SDIO, which is captured by the device on rising edges of SCLK. The Si4736/37/38/39 acknowledges each data byte by driving SDIO low for one cycle, on the next falling edge of SCLK. The user may write up to 8 data bytes in a single 2-wire transaction. The first byte is a command, and the next seven bytes are arguments. For read operations, after the Si4736/37/38/39 has acknowledged the control byte, it will drive an 8-bit data byte on SDIO, changing the state of SDIO on the falling edge of SCLK. The user acknowledges each data byte by driving SDIO low for one cycle, on the next falling edge of SCLK. If a data byte is not acknowledged, the transaction will end. The user may read up to 16 data bytes in a single 2-wire transaction. These bytes contain the response data from the Si4736/37/38/39. A 2-wire transaction ends with the STOP condition, which occurs when SDIO rises while SCLK is high. For details on timing specifications and diagrams, refer to Table 5, “2-Wire Control Interface Characteristics” on page 7; Figure 2, “2-Wire Control Interface Read and Write Timing Parameters,” on page 8, and Figure 3, “2Wire Control Interface Read and Write Timing Diagram,” on page 8. 4.15.2. 3-Wire Control Interface Mode When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. The 3-wire bus mode uses the SCLK, SDIO, and SEN_ pins. A transaction begins when the user drives SEN low. Next, the user drives a 9-bit control word on SDIO, which is captured by the device on rising edges of SCLK. The control word consists of a 9-bit device address (A7:A5 = 101b), a read/write bit (read = 1, write = 0), and a 5-bit register address (A4:A0). For write operations, the control word is followed by a 16-bit data word, which is captured by the device on rising edges of SCLK. For read operations, the control word is followed by a delay of one-half SCLK cycle for bus turn-around. Next, 23 A transaction ends when the user sets SEN high, then pulses SCLK high and low one final time. SCLK may either stop or continue to toggle while SEN is high. For details on timing specifications and diagrams, refer to Table 6, “3-Wire Control Interface Characteristics,” on page 9; Figure 4, “3-Wire Control Interface Write Timing Parameters,” on page 9, and Figure 5, “3-Wire Control Interface Read Timing Parameters,” on page 9. 4.15.3. SPI Control Interface Mode When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. SPI bus mode uses the SCLK, SDIO, and SEN pins for read/write operations. The system controller can choose to receive read data from the device on either SDIO or GPO1. A transaction begins when the system controller drives SEN = 0. The system controller then pulses SCLK eight times, while driving an 8-bit control byte serially on SDIO. The device captures the data on rising edges of SCLK. The control byte must have one of five values: 0x48 = write a command (controller drives 8 additional bytes on SDIO). 0x80 = read a response (device drives 1additional byte on SDIO). 0xC0 = read a response (device drives 16 additional bytes on SDIO). 0xA0 = read a response (device drives 1 additional byte on GPO1). 0xE0 = read a response (device drives 16 additional bytes on GPO1). For write operations, the system controller must drive exactly 8 data bytes (a command and seven arguments) on SDIO after the control byte. The data is captured by the device on the rising edge of SCLK. For read operations, the controller must read exactly 1 byte (STATUS) after the control byte or exactly 16 data bytes (STATUS and RESP1–RESP15) after the control byte. The device changes the state of SDIO (or GPO1, if specified) on the falling edge of SCLK. Data must be captured by the system controller on the rising edge of SCLK. Keep SEN low until all bytes have transferred. A transaction may be aborted at any time by setting SEN Rev. 1.0 Si4736/37/38/39-B20 high and toggling SCLK high and then low. Commands will be ignored by the device if the transaction is aborted. For details on timing specifications and diagrams, refer to Figure 6 and Figure 7 on page 10. 4.16. GPO Outputs The Si4736/37/38/39 provides three general-purpose output pins. The GPO pins can be configured to output a constant low, constant high, or high-impedance. The GPO pins can be reconfigured as specialized functions. GPO2/INT can be configured to provide interrupts and GPO3 can be configured to provide external crystal support or as DCLK in digital audio output mode. In digital output mode (Si4737/39 only), pin 16 and pin 17 can be configured as DFS and DOUT, respectively. 4.17. Firmware Upgrades The Si4736/37/38/39 contains on-chip program RAM to accommodate minor changes to the firmware. This allows Silicon Laboratories to provide future firmware updates to optimize the characteristics of new radio designs and those already deployed in the field. 4.18. Reset, Power Up, and Power Down Setting the RST pin low will disable analog and digital circuitry, reset the registers to their default settings, and disable the bus. Setting the RST pin high will bring the device out of reset. 4.19. Programming with Commands To ease development time and offer maximum customization, the Si4736/37/38/39 provides a simple yet powerful software interface to program the receiver. The device is programmed using commands, arguments, properties and responses. To perform an action, the user writes a command byte and associated arguments causing the chip to execute the given command. Commands control an action such as power up the device, shut down the device, or tune to a station. Arguments are specific to a given command and are used to modify the command. A complete list of commands is available in Table 14, “Si473x Command Summary,” on page 25. Properties are a special command argument used to modify the default chip operation and are generally configured immediately after power up. Examples of properties are de-emphasis level, RSSI seek threshold, and soft mute attenuation threshold. A complete list of properties is available in Table 15, “Si473x Property Summary,” on page 26. Responses provide the user information and are echoed after a command and associated arguments are issued. All commands provide a one-byte status update indicating interrupt and clear-to-send status information. For a detailed description of the commands and properties for the Si4736/37/38/39, see “AN332: Universal Programming Guide.” A power down mode is available to reduce power consumption when the part is idle. Putting the device in power down mode will disable analog and digital circuitry while keeping the bus active. 24 Rev. 1.0 Si4736/37/38/39-B20 5. Commands and Properties Table 14. Si473x Command Summary Cmd Name Description 0x01 POWER_UP 0x10 GET_REV 0x11 POWER_DOWN Power down device. 0x12 SET_PROPERTY Sets the value of a property. 0x13 GET_PROPERTY Retrieves a property’s value. 0x14 GET_INT_STATUS Read interrupt status bits. 0x15 PATCH_ARGS Reserved command used for firmware file downloads. 0x16 PATCH_DATA Reserved command used for firmware file downloads. 0x20 FM_TUNE_FREQ Selects the FM tuning frequency. 0x21 FM_SEEK_START Begins searching for a valid frequency. 0x22 FM_TUNE_STATUS Queries the status of previous FM_TUNE_FREQ or FM_SEEK_START command. 0x23 FM_RSQ_STATUS Queries the status of the Received Signal Quality (RSQ) of the current channel. 0x24 FM_RDS_STATUS Returns RDS information for current channel and reads an entry from the RDS FIFO (Si4737/39 only). 0x40 AM_TUNE_FREQ Tunes to a given AM frequency. 0x41 AM_SEEK_START Begins searching for a valid frequency. 0x42 AM_TUNE_STATUS Queries the status of the already issued AM_TUNE_FREQ or AM_SEEK_START command. 0x43 AM_RSQ_STATUS Queries the status of the RSQ for the current channel. 0x50 WB_TUNE_FREQ Selects the WB tuning frequency. 0x52 WB_TUNE_STATUS Queries the status of the previous WB_TUNE_FREQ command. 0x53 WB_RSQ_STATUS Queries the status of the Received Signal Quality (RSQ) of the current channel. 0x55 WB_ASQ_STATUS Queries the status of the 1050 Hz alert tone. 0x57 WB_AGC_STATUS Queries the status of the AGC. 0x58 WB_AGC_OVERRIDE Enable or disable the WB AGC. 0x80 GPO_CTL Configures GPO3 as output or Hi-Z. 0x81 GPO_SET Sets GPO3 output level (low or high). Power up device and mode selection. Modes include AM or FM receive, analog or digital output, and reference clock or crystal support. Returns revision information on the device. Rev. 1.0 25 Si4736/37/38/39-B20 Table 15. Si473x Property Summary Prop Name 0x0001 GPO_IEN Description Enables interrupt sources. 0x0102 DIGITAL_OUTPUT_FORMAT Configures the digital output format (Si4737/39 only). Default 0x0000 0x0000 0x0104 DIGITAL_OUTPUT_ SAMPLE_RATE Configures the digital output sample rate in 100 Hz steps. The digital output sample rate is disabled by default (Si4737/39 only). 0x0000 0x0201 REFCLK_FREQ Sets frequency of reference clock in Hz. The range is 31130 to 34406 Hz, or 0 to disable the AFC. Default is 32768 Hz. 0x8000 0x0202 REFCLK_PRESCALE Sets the prescaler value for RCLK input. 0x0001 0x1100 FM_DEEMPHASIS Sets de-emphasis time constant. Default is 75 us. 0x0002 0x1105 FM_BLEND_STEREO_ THRESHOLD Sets RSSI threshold for stereo blend (Full stereo above threshold, blend below threshold). To force stereo set this to 0. To force mono set this to 127. Default value is 49 dBuV. 0x0031 0x1106 FM_BLEND_MONO_ THRESHOLD Sets RSSI threshold for mono blend (full mono below threshold, blend above threshold). To force stereo set this to 0. To force 0x001E mono set this to 127. Default value is 30 dBuV. 0x1108 FM_MAX_TUNE_ ERROR Sets the maximum freq error allowed before setting the AFC rail 0x001E (AFCRL) indicator. Default value is 30 kHz. 0x1200 FM_RSQ_INT_ SOURCE 0x1201 Configures interrupt related to RSQ metrics. 0x0000 FM_RSQ_SNR_HI_ THRESHOLD Sets high threshold for SNR interrupt. 0x007F 0x1202 FM_RSQ_SNR_LO_ THRESHOLD Sets low threshold for SNR interrupt. 0x0000 0x1203 FM_RSQ_RSSI_HI_ THRESHOLD Sets high threshold for RSSI interrupt. 0x007F 0x1204 FM_RSQ_RSSI_LO_ THRESHOLD Sets low threshold for RSSI interrupt. 0x0000 0x1207 FM_RSQ_BLEND_ THRESHOLD Sets the blend threshold for blend interrupt when boundary is crossed. 0x0081 0x1300 FM_SOFT_MUTE_RATE Sets the attack and decay rates when entering and leaving soft mute. 0x0040 0x1302 FM_SOFT_MUTE_ MAX_ATTENUATION 0x1303 FM_SOFT_MUTE_ SNR_THRESHOLD Sets SNR threshold to engage soft mute. Default is 4 dB. 0x0004 0x1400 FM_SEEK_BAND_ BOTTOM Sets the bottom of the FM band for seek. Default is 8750. 0x222E 0x1401 FM_SEEK_BAND_TOP Sets the top of the FM band for seek. Default is 10790. 0x2A26 0x1402 FM_SEEK_FREQ_ SPACING Selects frequency spacing for FM seek. 0x000A 0x1403 FM_SEEK_TUNE_ SNR_THRESHOLD Sets the SNR threshold for a valid FM Seek/Tune. Default value is 3 dB. 0x0003 0x1404 FM_SEEK_TUNE_ RSSI_TRESHOLD Sets the RSSI threshold for a valid FM Seek/Tune. Default value is 20 dBuV. 0x0014 26 Sets maximum attenuation during soft mute (dB). Set to 0 to dis0x0010 able soft mute. Default is 16 dB. Rev. 1.0 Si4736/37/38/39-B20 Table 15. Si473x Property Summary (Continued) Prop Name 0x1500 RDS_INT_SOURCE Description Default Configures RDS interrupt behavior. 0x0000 Sets the minimum number of RDS groups stored in the receive RDS FIFO required before RDS RECV is set. 0x0000 Configures RDS setting. 0x0000 Sets de-emphasis time constant. Can be set to 50 us. Deemphasis is disabled by default. 0x0000 0x1501 RDS_INT_FIFO_COUNT 0x1502 RDS_CONFIG 0x3100 AM_DEEMPHASIS 0x3102 AM_CHANNEL_FILTER Selects the bandwidth of the channel filter for AM reception. The 0x0003 choices are 6, 4, 3, or 2 (kHz). The default bandwidth is 2 kHz. 0x3200 AM_RSQ_INTERRUPTS Configures interrupt related to RSQ metrics. All interrupts are disabled by default. 0x0000 0x3201 AM_RSQ_SNR_HIGH_ THRESHOLD Sets high threshold for SNR interrupt. The default is 0 dB. 0x0000 0x3202 AM_RSQ_SNR_LOW_ THRESHOLD Sets low threshold for SNR interrupt. The default is 0 dB. 0x0000 0x3203 AM_RSQ_RSSI_HIGH_ THRESHOLD Sets high threshold for RSSI interrupt. The default is 0 dB. 0x0000 0x3204 AM_RSQ_RSSI_LOW_ THRESHOLD Sets low threshold for RSSI interrupt. The default is 0 dB. 0x0000 0x3300 AM_SOFT_MUTE_RATE Sets the rate of attack when entering or leaving soft mute. The default is 278 dB/s. 0x0040 0x3301 AM_SOFT_MUTE_SLOPE Sets the AM soft mute slope. The bigger the number, the higher the max attenuation level. Default value is a slope of 2. 0x0002 0x3302 AM_SOFT_MUTE_MAX_ ATTENUATION Sets maximum attenuation during soft mute (dB). Set to 0 to dis0x0010 able soft mute. Default is 16 dB. 0x3303 AM_SOFT_MUTE_SNR_ THRESHOLD Sets SNR threshold to engage soft mute. Default is 10 dB. 0x000A 0x3400 AM_SEEK_BAND_ BOTTOM Sets the bottom of the AM band for seek. Default is 520. 0x0208 0x3401 AM_SEEK_BAND_TOP Sets the top of the AM band for seek. Firmware 1.0 incorrectly defaults to 1721 kHz instead of 1710. 0x06AE 0x3402 AM_SEEK_FREQ_ SPACING 0x3403 AM_SEEK_SNR_ THRESHOLD Sets the SNR threshold for a valid AM Seek/Tune. If the value is zero then SNR threshold is not considered when doing a seek. Default value is 5 dB. 0x0005 0x3404 AM_SEEK_RSSI_ THRESHOLD Sets the RSSI threshold for a valid AM Seek/Tune. If the value is zero then RSSI threshold is not considered when doing a seek. Default value is 25 dBuV. 0x0019 0x4000 RX_VOLUME Sets the output volume. 0x003F 0x4001 RX_HARD_MUTE Mutes the audio output. L and R audio outputs may be muted independently in FM mode. 0x0000 0x5108 WB_MAX_TUNE_ERROR Maximum change in frequencies from the WB_TUNE_FREQ to which the AFC will lock. 0x000F Selects frequency spacing for AM seek. Default is 10 kHz spac0x000A ing. Rev. 1.0 27 Si4736/37/38/39-B20 Table 15. Si473x Property Summary (Continued) Prop Name 0x5200 WB_RSQ_INTERRUPT_ SOURCE Configures interrupts related to RSQ metrics. All interrupts are disabled by default. 0x0000 0x5201 WB_RSQ_SNR_HIGH_ THRESHOLD Sets high threshold for SNR interrupt. The default is 0 dB. 0x007F 0x5202 WB_RSQ_SNR_LOW_ THRESHOLD Sets low threshold for SNR interrupt. The default is 0 dB. 0x0000 0x5203 WB_RSQ_RSSI_HIGH_ THRESHOLD Sets high threshold for RSSI interrupt. The default is 0 dB. 0x007F 0x5204 WB_RSQ_RSSI_LOW_ THRESHOLD Sets low threshold for RSSI interrupt. The default is 0 dB. 0x0000 0x5600 WB_ASQ_INTERRUPT_ SOURCE Configures 1050 Hz alert tone interrupts. All interrupts are disabled by default. 0x0000 28 Description Rev. 1.0 Default Si4736/37/38/39-B20 GPO2/INT GPO3/DCLK DFS 1 GPO1 NC NC 6. Pin Descriptions: Si4736/37/38/39-GM 20 19 18 17 16 FMI 2 15 DOUT RFGND 3 14 LOUT GND PAD AMI 4 13 ROUT 6 7 8 9 10 SCLK SDIO RCLK VIO 12 GND SEN RST 5 11 VDD Pin Number(s) Name Description 1, 20 NC No connect. Leave floating. 2 FMI FM/WB RF inputs. FMI should be connected to the antenna trace. 3 RFGND 4 AMI AM RF input. AMI should be connected to the AM antenna. 5 RST Device reset (active low) input. 6 SEN Serial enable input (active low). 7 SCLK Serial clock input. 8 SDIO Serial data input/output. 9 RCLK External reference oscillator input. 10 VIO I/O supply voltage. 11 VDD Supply voltage. May be connected directly to battery. 12, GND PAD GND Ground. Connect to ground plane on PCB. 13 ROUT Right audio line output in analog output mode. 14 LOUT Left audio line output in analog output mode. 15 DOUT Digital output data in digital output mode. 16 DFS 17 GPO3/DCLK 18 GPO2/INT 19 GPO1 RF ground. Connect to ground plane on PCB. Digital frame synchronization input in digital output mode. General purpose output, crystal oscillator, or digital bit synchronous clock input in digital output mode. General purpose output or interrupt pin. General purpose output. Rev. 1.0 29 Si4736/37/38/39-B20 7. Ordering Guide Part Number* Description Package Type Operating Temperature Si4736-B20-GM AM/FM/WB Broadcast Radio Receiver QFN Pb-free –20 to 85 °C Si4737-B20-GM AM/FM/WB Broadcast Radio Receiver with RDS/RBDS QFN Pb-free –20 to 85 °C Si4738-B20-GM FM/WB Broadcast Radio Receiver QFN Pb-free –20 to 85 °C Si4739-B20-GM FM/WB Broadcast Radio Receiver with RDS/RBDS QFN Pb-free –20 to 85 °C *Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. 30 Rev. 1.0 Si4736/37/38/39-B20 8. Package Markings (Top Marks) 8.1. Top Mark 3620 BTTT YWW 3820 BTTT YWW 3720 BTTT YWW 3920 BTTT YWW 8.2. Top Mark Explanation Mark Method: YAG Laser Line 1 Marking: Part Number 36 = Si4736, 37 = Si4737, 38 = Si4738, 39 = Si4739 Firmware Revision 20 = Firmware Revision 2.0 Die Revision B = Revision B Die TTT = Internal Code Internal tracking code Line 2 Marking: Line 3 Marking: Circle = 0.5 mm Diameter Pin 1 Identifier (Bottom-Left Justified) Y = Year WW = Workweek Assigned by the Assembly House. Corresponds to the last significant digit of the year and workweek of the mold date. Rev. 1.0 31 Si4736/37/38/39-B20 9. Package Outline: Si4736/37/38/39 QFN Figure 14 illustrates the package details for the Si4736/37/38/39. Table 16 lists the values for the dimensions shown in the illustration. Figure 14. 20-Pin Quad Flat No-Lead (QFN) Table 16. Package Dimensions Symbol Millimeters Symbol Min Nom Max A 0.50 0.55 0.60 f A1 0.00 0.02 0.05 L 0.35 0.40 0.45 b 0.20 0.25 0.30 L1 0.00 — 0.10 c 0.27 0.32 0.37 aaa — — 0.05 bbb — — 0.05 ccc — — 0.08 ddd — — 0.10 eee — — 0.10 D D2 1.65 1.70 1.75 0.50 BSC E E2 Min 3.00 BSC e 3.00 BSC 1.65 1.70 1.75 Notes: 1. All dimensions are shown in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 32 Millimeters Rev. 1.0 Nom Max 2.53 BSC Si4736/37/38/39-B20 10. PCB Land Pattern: Si4736/37/38/39 QFN Figure 15 illustrates the PCB land pattern details for the Si4736/37/38/39-GM. Table 17 lists the values for the dimensions shown in the illustration. Figure 15. PCB Land Pattern Rev. 1.0 33 Si4736/37/38/39-B20 Table 17. PCB Land Pattern Dimensions Symbol Millimeters Min D D2 Symbol Max 2.71 REF 1.60 1.80 Min Max GE 2.10 — W — 0.34 — e 0.50 BSC X E 2.71 REF Y E2 f GD 1.60 1.80 2.53 BSC 2.10 Millimeters 0.28 0.61 REF ZE — 3.31 ZD — 3.31 — Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Notes: Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Notes: Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. Notes: Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 34 Rev. 1.0 Si4736/37/38/39-B20 11. Additional Reference Resources EN55020 Compliance Test Certificate AN231: Si4700/01 Headphone and Antenna Interface AN332: Universal Programming Guide AN383: Universal Antenna Selection and Layout Guidelines AN386: Si473x Ferrite Loop Stick Antenna Interface AN388: Si473x AM/FM Tuner Evaluation Board Test Procedure AN389: Si473x EVB Quick-Start Guide Si47xx Customer Support Site: http://www.mysilabs.com This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA is required for access. To request access, register at http://www.mysilabs.com and send user’s first and last name, company, NDA reference number, and mysilabs user name to [email protected]. Silicon Labs recommends an all lower case user name. Rev. 1.0 35 Si4736/37/38/39-B20 DOCUMENT CHANGE LIST Revision 0.4 to Revision 0.5 Updated Table 3, “DC Characteristics,” on page 5. Updated Table 5, “2-Wire Control Interface Characteristics1,2,3,” on page 7. Updated Table 8, “Digital Audio Interface Characteristics,” on page 11. 36 Updated Table 9, “FM Receiver Characteristics1,2,” on page 12. Updated Table 10, “WB Receiver Characteristics1,” on page 13. Updated Table 11, “AM Receiver Characteristics1,” on page 14. Updated Table 12, “Reference Clock and Crystal Characteristics,” on page 15. Updated "3. Bill of Materials" on page 17. Added GPO_CTL and GPO_SET commands to Table 13, “Bus Mode Select on Rising Edge of RST,” on page 22. Updated "11. Additional Reference Resources" on page 35.. Rev. 1.0 Si4736/37/38/39-B20 NOTES: Rev. 1.0 37 Si4736/37/38/39-B20 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: [email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 38 Rev. 1.0