Si4704/05-C40 B ROADCAST F M R ADIO R ECEIVER FOR C ON SUMER E LECTRONICS Features Applications s es ig n NC 1 FMI 2 The Si4704/05 integrates all functions required for an advanced broadcast FM radio receiver, from antenna input to stereo audio output. om Functional Block Diagram R ec ADC ADC DAC ROUT RSSI AFC 14 LOUT GND PAD LPI 4 13 ROUT RST 5 12 GND 6 7 8 9 10 11 VDD GPO DCLK This product, its features, and/or its architecture is covered by one or more of the following patents, as well as other patents, pending and issued, both foreign and domestic: 7,127,217; 7,272,373; 7,272,375; 7,321,324; 7,355,476; 7,426,376; 7,471,940; 7,339,503; 7,339,504. DOUT DFS VIO 1.85-3.6 V RST CONTROL INTERFACE XTAL OSC SEN REG RDS (Si4705) DIGITAL INTERFACE (Si4705) 0/90 VDD Rev. 1.0 12/09 LOUT DSP SDIO N 2.7–5.5 V DAC AGC 32.768 kHz RCLK PGA SCLK ot LPI LNA 15 DOUT Si4704/05 FMI RFGND 20 19 18 17 16 RFGND 3 m en Description FM Antenna Si4704/05-GM (Top View) fo Modules Clock radios Mini HiFi Entertainment systems d Table and portable radios Stereos Mini/micro systems CD/DVD players Boom boxes de Pin Assignments DFS RoHS compliant GPO3/DCLK VIO 3x3 mm 20-pin QFN package Ordering Information: See page 28. GPO2/INT 2.7 to 5.5 V supply voltage RCLK Signal quality measurements GPO1 Integrated LDO regulator SDIO 2-wire and 3-wire control interface NC Optional digital audio out (Si4705) SCLK RDS/RBDS processor (Si4705) D Adjustable soft mute control SEN Volume control ew Programmable reference clock (64–108 MHz) Integrated antenna support EN55020 compliant Excellent real-world performance Freq synthesizer with integrated VCO Advanced FM seek tuning Automatic frequency control (AFC) Automatic gain control (AGC) Digital FM stereo decoder Minimal BOM Programmable de-emphasis rN Worldwide FM band support Copyright © 2009 by Silicon Laboratories Si4704/05-C40 Si4704/05-C40 2 Rev. 1.0 Si4704/05-C40 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2. Application Schematics and Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.4. Digital Audio Interface (Si4705 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.7. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.8. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.9. RDS/RBDS Processor (Si4705 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.10. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.11. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.12. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.13. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.14. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.15. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.16. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. Pin Descriptions: Si4704/05-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1. Si4704 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2. Si4705 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9. Package Outline: Si4704/05-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10. PCB Land Pattern: Si4704/05-C40-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Rev. 1.0 3 Si4704/05-C40 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Supply Voltage VDD 2.7 — 5.5 V Interface Supply Voltage VIO 1.85 — 3.6 V Digital Power Supply Powerup Rise Time VDRISE 10 — — µs Interface Power Supply Powerup Rise Time VIORISE 10 — — µs TA –20 25 85 C Ambient Temperature Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at VDD= 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless otherwise stated. Table 2. Absolute Maximum Ratings1,2 Parameter Symbol Value Unit Supply Voltage VDD –0.5 to 5.8 V Interface Supply Voltage VIO –0.5 to 3.9 V Input Current3 IIN 10 mA 3 VIN –0.3 to (VIO + 0.3) V Operating Temperature TOP –40 to 95 C Storage Temperature TSTG –55 to 150 C 0.4 VPK Input Voltage RF Input Level4 Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. The Si4704/05 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV HBM. Handling and assembly of these devices should be done only at ESD-protected workstations. 3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3. 4. At RF input pin, FMI. 4 Rev. 1.0 Si4704/05-C40 Table 3. DC Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit — 19.2 22 mA — 19.9 23 mA IFM — 19.2 23 mA Interface Supply Current IIO — 320 600 µA VDD Powerdown Current IDDPD — 10 20 µA VIO Powerdown Current IIOPD — 1 10 µA FM Receiver to Line Output Supply Current1 IFM Supply Current2 IFM RDS Supply Current1 Low SNR level Supplies and Interface SCLK, RCLK inactive High Level Input Voltage3 VIH 0.7 x VIO — VIO + 0.3 V Voltage3 VIL –0.3 — 0.3 x VIO V High Level Input Current3 IIH VIN = VIO = 3.6 V –10 — 10 µA Current3 IIL VIN = 0 V, VIO = 3.6 V –10 — 10 µA High Level Output Voltage4 VOH IOUT = 500 µA 0.8 x VIO — — V Voltage4 VOL IOUT = –500 µA — — 0.2 x VIO V Low Level Input Low Level Input Low Level Output Notes: 1. Guaranteed by characterization. 2. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions. 3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3. 4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3. Rev. 1.0 5 Si4704/05-C40 Table 4. Reset Timing Characteristics1,2,3 (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Min Typ Max Unit RST Pulse Width and GPO1, GPO2/INT Setup to RST tSRST 100 — — µs GPO1, GPO2/INT Hold from RST tHRST 30 — — ns Important Notes: 1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST. 2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. 4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is high impedance, then minimum tSRST is 100 µs to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and GPO2 low. tSRST RST 70% GPO1 70% GPO2/ INT tHRST 30% 30% 70% 30% Figure 1. Reset Timing Parameters for Busmode Select 6 Rev. 1.0 Si4704/05-C40 Table 5. 2-Wire Control Interface Characteristics1,2,3 (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fSCL 0 — 400 kHz SCLK Low Time tLOW 1.3 — — µs SCLK High Time tHIGH 0.6 — — µs SCLK Input to SDIO Setup (START) tSU:STA 0.6 — — µs SCLK Input to SDIO Hold (START) tHD:STA 0.6 — — µs SDIO Input to SCLK Setup tSU:DAT 100 — — ns SDIO Input to SCLK Hold 4, 5 tHD:DAT 0 — 900 ns SCLK Input to SDIO Setup (STOP) tSU:STO 0.6 — — µs STOP to START Time tBUF 1.3 — — µs SDIO Output Fall Time tf:OUT — 250 ns — 300 ns Cb 20 + 0.1 ----------1pF SDIO Input, SCLK Rise/Fall Time tf:IN tr:IN Cb 20 + 0.1 ----------1pF SCLK, SDIO Capacitive Loading Cb — — 50 pF Input Filter Pulse Suppression tSP — — 50 ns Notes: 1. When VIO = 0 V, SCLK and SDIO are low impedance. 2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST. 3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 4. The Si4704/05 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum tHD:DAT specification. 5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be violated as long as all other timing parameters are met. Rev. 1.0 7 Si4704/05-C40 SCLK 70% SDIO 70% tSU:STA tHD:STA tLOW START tr:IN tHIGH tr:IN tf:IN tSP tSU:STO tBUF 30% 30% tf:IN, tf:OUT tHD:DAT tSU:DAT STOP START Figure 2. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, R/W SDIO START ADDRESS + R/W D7-D0 ACK DATA D7-D0 ACK DATA ACK Figure 3. 2-Wire Control Interface Read and Write Timing Diagram 8 Rev. 1.0 STOP Si4704/05-C40 Table 6. 3-Wire Control Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fCLK 0 — 2.5 MHz SCLK High Time tHIGH 25 — — ns SCLK Low Time tLOW 25 — — ns tS 20 — — ns SDIO Input to SCLK Hold tHSDIO 10 — — ns SEN Input to SCLK Hold tHSEN 10 — — ns SCLK to SDIO Output Valid tCDV Read 2 — 25 ns SCLK to SDIO Output High Z tCDZ Read 2 — 25 ns SCLK, SEN, SDIO, Rise/Fall Time tR, tF — — 10 ns SDIO Input, SEN to SCLK Setup SCLK 70% 30% tR tF tHSDIO tS SEN 70% SDIO 70% tHIGH tLOW tHSEN tS 30% A7 30% A6-A5, R/W, A4-A1 A0 D15 D14-D1 Address In D0 Data In Figure 4. 3-Wire Control Interface Write Timing Parameters SCLK 70% SEN 70% 30% tHSDIO tS tCDV tHSEN tCDZ tS 30% 70% SDIO A7 30% A6-A5, R/W, A4-A1 Address In A0 D15 ½ Cycle Bus Turnaround D14-D1 D0 Data Out Figure 5. 3-Wire Control Interface Read Timing Parameters Rev. 1.0 9 Si4704/05-C40 Table 7. SPI Control Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fCLK 0 — 2.5 MHz SCLK High Time tHIGH 25 — — ns SCLK Low Time tLOW 25 — — ns tS 15 — — ns SDIO Input to SCLKHold tHSDIO 10 — — ns SEN Input to SCLKHold tHSEN 5 — — ns SCLKto SDIO Output Valid tCDV Read 2 — 25 ns SCLKto SDIO Output High Z tCDZ Read 2 — 25 ns — — 10 ns SDIO Input, SEN to SCLKSetup tR tF SCLK, SEN, SDIO, Rise/Fall time Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. SCLK 70% 30% tR tHIGH SEN 70% SDIO 70% tS tLOW tF tHSDIO tHSEN tS 30% C7 C6–C1 C0 D7 D6–D1 D0 30% Control Byte In 8 Data Bytes In Figure 6. SPI Control Interface Write Timing Parameters SCLK 70% 30% tCDV tS SEN 70% tHSEN tHSDIO tS 30% tCDZ SDIO 70% C7 C6 –C1 C0 D7 D6 –D1 D0 30% Control Byte In Bus Turnaround 16 Data Bytes Out (SDIO or GPO1) Figure 7. SPI Control Interface Read Timing Parameters 10 Rev. 1.0 Si4704/05-C40 Table 8. Digital Audio Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit DCLK Cycle Time tDCT 26 — 1000 ns DCLK Pulse Width High tDCH 10 — — ns DCLK Pulse Width Low tDCL 10 — — ns DFS Set-up Time to DCLK Rising Edge tSU:DFS 5 — — ns DFS Hold Time from DCLK Rising Edge tHD:DFS 5 — — ns tPD:DOUT 0 — 12 ns DOUT Propagation Delay from DCLK Falling Edge tDCH tDCL DCLK tDCT DFS tHD:DFS tSU:DFS DOUT tPD:OUT Figure 8. Digital Audio Interface Timing Parameters, I2S Mode Rev. 1.0 11 Si4704/05-C40 Table 9. FM Receiver Characteristics1,2 (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Input Frequency Test Condition fRF Min Typ Max Unit 76 — 108 MHz Sensitivity with Headphone Network3,4,5 (S+N)/N = 26 dB — 2.2 3.5 µV EMF Sensitivity with 50 Network3,4,5,6 (S+N)/N = 26 dB — 1.1 — µV EMF RDS Sensitivity6 f = 2 kHz, RDS BLER < 5% — 15 — µV EMF — 3.5 — µV EMF 3 4 5 k 4 5 6 pF 100 105 — dBµV EMF m = 0.3 40 50 — dB Adjacent Channel Selectivity ±200 kHz 35 50 — dB Alternate Channel Selectivity ±400 kHz 60 70 — dB In-band 35 — — dB 72 80 90 mVRMS — — 1 dB LPI Sensitivity6 LNA Input Resistance LNA Input 6,7 Capacitance6,7 Input IP36,8 AM Suppression 3,4,6,7 Spurious Response Rejection6 3,4,7 Audio Output Voltage Audio Output L/R Imbalance3,7,9 Audio Frequency Response Low6 –3 dB — — 30 Hz Audio Frequency Response High6 –3 dB 15 — — kHz 32 42 — dB 55 63 — dB — 58 — dB f = ±400 kHz — 32 — dBµV f = ±4 MHz — 38 — dBµV Audio Stereo Separation Audio Mono S/N 7,9 3,4,5,7,10 Audio Stereo S/N4,5,6,7,10,11 Blocking Sensitivity3,6,12,13 Notes: 1. Additional testing information is available in application note, “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.” Volume = maximum for all tests. Tested at RF = 98.1 MHz. 2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise. 4. f = 22.5 kHz. 5. BAF = 300 Hz to 15 kHz, A-weighted. 6. Guaranteed by characterization. 7. VEMF = 1 mV. 8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. 9. f = 75 kHz. 10. At LOUT and ROUT pins. 11. Analog audio output mode. 12. Blocker Amplitude = 100 dBµV 13. Sensitivity measured at (S+N)/N = 26 dB. 14. At temperature 25°C. 12 Rev. 1.0 Si4704/05-C40 Table 9. FM Receiver Characteristics1,2 (Continued) (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit f = ±400 kHz, ±800 kHz — 40 — dBµV f = ±4 MHz, ±8 MHz — 35 — dBµV — 0.1 0.5 % FM_DEEMPHASIS = 2 70 75 80 µs FM_DEEMPHASIS = 1 45 50 54 µs RL Single-ended 10 — — k CL Single-ended — — 50 pF RCLK tolerance = 100 ppm — — 60 ms/channel From powerdown — — 110 ms Input levels of 8 and 60 dBµV at RF Input –3 — 3 dB Intermod Sensitivity3,6,12,13 Audio THD3,7,9 6 De-emphasis Time Constant Audio Output Load Resistance6,10 Audio Output Load Capacitance Seek/Tune Time6 Powerup Time6 14 RSSI Offset 6,10 Notes: 1. Additional testing information is available in application note, “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.” Volume = maximum for all tests. Tested at RF = 98.1 MHz. 2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise. 4. f = 22.5 kHz. 5. BAF = 300 Hz to 15 kHz, A-weighted. 6. Guaranteed by characterization. 7. VEMF = 1 mV. 8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. 9. f = 75 kHz. 10. At LOUT and ROUT pins. 11. Analog audio output mode. 12. Blocker Amplitude = 100 dBµV 13. Sensitivity measured at (S+N)/N = 26 dB. 14. At temperature 25°C. Rev. 1.0 13 Si4704/05-C40 Table 10. 64–75.9 MHz Input Frequency FM Receiver Characteristics1,2,6 (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Min Typ Max Unit 64 — 75.9 MHz — 4.0 — µV EMF LNA Input Resistance7 3 4 5 k LNA Input Capacitance7 4 5 6 pF 100 105 — dBµV EMF m = 0.3 40 50 — dB Adjacent Channel Selectivity ±200 kHz — 50 — dB Alternate Channel Selectivity ±400 kHz — 70 — dB 72 80 90 mVRMS — — 1 dB Input Frequency fRF Sensitivity with Headphone Network3,4,5 Input IP3 Test Condition (S+N)/N = 26 dB 8 AM Suppression 3,4,7 3,4,7 Audio Output Voltage 3,7,9 Audio Output L/R Imbalance Audio Frequency Response Low –3 dB — — 30 Hz Audio Frequency Response High –3 dB 15 — — kHz 55 63 — dB — 0.1 0.5 % FM_DEEMPHASIS = 2 70 75 80 µs FM_DEEMPHASIS = 1 45 50 54 µs RL Single-ended 10 — — k CL Single-ended — — 50 pF RCLK tolerance = 100 ppm — — 60 ms/channel From powerdown — — 110 ms Input levels of 8 and 60 dBµV EMF –3 — 3 dB Audio Mono S/N Audio 3,4,5,7,10 THD3,7,9 De-emphasis Time Constant 10 Audio Output Load Resistance Audio Output Load Capacitance Seek/Tune Time Powerup Time RSSI Offset11 10 Notes: 1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.” Volume = maximum for all tests. Tested at RF = 98.1 MHz. 2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise. 4. f = 22.5 kHz. 5. BAF = 300 Hz to 15 kHz, A-weighted. 6. Guaranteed by characterization. 7. VEMF = 1 mV. 8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. 9. f = 75 kHz. 10. At LOUT and ROUT pins. 11. At temperature (25 °C). 14 Rev. 1.0 Si4704/05-C40 Table 11. Reference Clock and Crystal Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit 31.130 32.768 40,000 kHz –100 — 100 ppm 1 — 4095 31.130 32.768 34.406 kHz — 32.768 — kHz –100 — 100 ppm — — 3.5 pF Reference Clock RCLK Supported Frequencies1 RCLK Frequency Tolerance 2 REFCLK_PRESCALE REFCLK Crystal Oscillator Crystal Oscillator Frequency Crystal Frequency Tolerance2 Board Capacitance Notes: 1. The Si4704/05 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies between 31.130 kHz and 40 MHz that are not supported. See “AN332: Si47xx Programming Guide,” Table 6 for more details. 2. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing. Rev. 1.0 15 Si4704/05-C40 2. Typical Application Schematic GPO1 GPO2/INT R1 R2 GPO3/DCLK FMI LPI 2 FMI 3 RFGND 4 LPI 5 GPO3/DCLK DFS NC GPO2/INT 1 GPO1 NC 20 19 18 17 16 DFS U1 Si4704/05 DOUT R3 DOUT Optional: Digital Audio Output 14 13 ROUT 12 LOUT GND VDD RST 15 LOUT ROUT 11 VBATTERY 2.7 to 5.5 V RST 6 7 8 9 10 SEN SCLK SDIO RCLK VIO C1 X1 GPO3 SEN SCLK SDIO RCLK VIO 1.85 to 3.6 V C2 RCLK C3 Optional: for crystal oscillator option Notes: 1. Place C1 close to VDD pin. 2. All grounds connect directly to GND plane on PCB. 3. Pins 1 and 20 are no connects, leave floating. 4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 5. Pin 2 or Pin 4 connects to the FM antenna interface. Pin 2 is for a headphone antenna. Pin 4 is for an integrated antenna. 6. Place Si4704/05 as close as possible to antenna and keep the FMI and LPI traces as short as possible. 16 Rev. 1.0 Si4704/05-C40 3. Bill of Materials Component(s) Value/Description C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R U1 Si4704/05 FM Radio Receiver Supplier Murata Silicon Laboratories Optional Components C2, C3 Crystal load capacitors, 22 pF, ±5%, COG (Optional: for crystal oscillator option) Venkel X1 32.768 kHz crystal (Optional: for crystal oscillator option) Epson R1 Resistor, 2 k(Optional: for digital audio) Venkel R2 Resistor, 2 k(Optional: for digital audio) Venkel R3 Resistor, 600 (Optional: for digital audio) Venkel Rev. 1.0 17 Si4704/05-C40 4. Functional Description 4.1. Overview Si4704/05 FM Antenna ADC FMI RFGND LNA PGA ROUT RSSI AFC GPO DCLK DOUT DFS VIO 1.85-3.6 V RST SEN REG CONTROL INTERFACE XTAL OSC SDIO VDD RDS (Si4705) DIGITAL INTERFACE (Si4705) 0/90 SCLK 2.7–5.5 V DAC AGC 32.768 kHz RCLK LOUT DSP ADC LPI DAC Figure 9. Functional Block Diagram The Si4704/05 device leverages Silicon Laboratories’ highly successful and proven Si4700/01/02/03 FM receiver, and offers unmatched integration and performance. The Si4704/05 offers additional features, such as EN55020 compliance, embedded antenna support, and a digital audio interface. The Si4704/05 is layout compatible with Silicon Laboratories’ Si4710/11 FM Transmitter, Si4720/21 FM Transceiver, and Si4730/31 AM/FM Receiver. The Si4704/05 is the first FM radio receiver integrated circuit to support a short PCB trace or wire antenna, which can be integrated into the enclosure or PCB. The Si4704/05’s digital integration reduces the required external components of traditional offerings, resulting in a solution requiring only an external inductor and bypass capacitor, and occupying board space of approximately 15 mm2. Other advantages of the Si4704/05 include highly reliable device manufacturing, excellent quality, and ease of use to design-in and program. The Si4704/05 includes line outputs from the on-chip digital-to-analog converters (DAC), digital audio mixers, a programmable reference clock input, and a configurable digital audio interface with the Si4705. The chip supports an I2C-compliant 2-wire interface, an Si4700/01/02/03 backwards compatible 3-wire control interface, and an SPI control interface. 18 The Si4704/05 performs much of the FM demodulation digitally to achieve high fidelity, optimal performance versus power consumption, and flexibility of design. The on-board DSP provides unmatched pilot rejection, selectivity, and optimum sound quality. The Si4704/05 offers both the manufacturer and the end-user unmatched programmability and flexibility in the listening experience. The Si4705 incorporates on-board processing capability for the European Radio Data System (RDS) and the US Radio Broadcast Data System (RBDS) including all the symbol encoding/decoding, block synchronization, error detection, and error correction functions. RDS allows digital information sent from the broadcaster to be displayed, such as station ID, song name, and music category. In Europe, alternate frequency (AF) information is also provided to automatically change stations in areas where broadcasters use multiple frequencies. The Si4704/05 has two separate RF inputs. FMI is the input for use with a traditional FM antenna. The LPI input is for use with a short PCB trace or wire antenna that may be integrated into the system enclosure. There is a clocking mode to choose to clock the Si4704/05 from a reference clock or crystal. On the Si4705, there is an audio output mode to choose between an analog and/or digital audio output. Rev. 1.0 Si4704/05-C40 In the analog audio output mode, pin 13 is ROUT, pin 14 is LOUT, and pin 17 is GPO3. In the digital audio mode, pin 15 is DOUT, pin 16 is DFS, and pin 17 is DCLK. Concurrent analog/digital audio output mode requires pins 13, 14, 15, 16, and 17. The digital audio interface operates in slave mode and supports a variety of MSB-first audio data formats including I2S and left-justified modes. The interface has three pins: digital data input (DIN), digital frame synchronization input (DFS), and a digital bit synchronization input clock (DCLK). The Si4704/05 supports a number of industry-standard sampling rates including 32, 40, 44.1, and 48 kHz. The digital audio interface enables low-power operation by eliminating the need for redundant DACs and ADCs on the audio baseband processor. The Si4704/05 is reset by applying a logic low on RST signal. This causes all register values to be reset to their default values. The digital output interface supply (VIO) provides voltage to the RST, SEN, SDIO, RCLK, DOUT, DFS, and DCLK pins and can be connected to the audio baseband processor's supply voltage to save power and remove the need for voltage level translators. RCLK is not required for register operation. The Si4704/05 reference clock is programmable, supporting many RCLK inputs as shown in Table 11. 4.2. Application Schematics and Operating Modes The application schematic for the Si4704/05 is shown in Section "2. Typical Application Schematic" on page 16. The Si4704/05 supports selectable analog, digital, or concurrent analog and digital audio output modes. In the analog output mode, pin 13 is ROUT, pin 14 is LOUT, and pin 17 is GPO3. In the digital output mode, pin 15 is DOUT, pin 16 is DFS, and pin 17 is DCLK. Concurrent analog and digital audio output mode requires pins 13, 14, 15, 16, and 17. In addition to output mode, there is a clocking mode to clock the Si4704/05 from a reference clock or crystal oscillator. The user sets the operating modes with commands as described in Section "5. Commands and Properties" on page 25. The quadrature mixer output is amplified, filtered, and digitized with high resolution analog-to-digital converters (ADCs). This advanced architecture allows the Si4704/05 to perform channel selection, FM demodulation, and stereo audio processing to achieve superior performance compared to traditional analog architectures. 4.4. Digital Audio Interface (Si4705 Only) The digital audio interface operates in slave mode and supports three different audio data formats: I2S Left-Justified DSP Mode 4.4.1. Audio Data Formats In I2S mode, by default the MSB is captured on the second rising edge of DCLK following each DFS transition. The remaining bits of the word are sent in order, down to the LSB. The left channel is transferred first when the DFS is low, and the right channel is transferred when the DFS is high. In Left-Justified mode, by default the MSB is captured on the first rising edge of DCLK following each DFS transition. The remaining bits of the word are sent in order, down to the LSB. The left channel is transferred first when the DFS is high, and the right channel is transferred when the DFS is low. In DSP mode, the DFS becomes a pulse with a width of 1DCLK period. The left channel is transferred first, followed right away by the right channel. There are two options in transferring the digital audio data in DSP mode: the MSB of the left channel can be transferred on the first rising edge of DCLK following the DFS pulse or on the second rising edge. In all audio formats, depending on the word size, DCLK frequency, and sample rates, there may be unused DCLK cycles after the LSB of each word before the next DFS transition and MSB of the next word. In addition, if preferred, the user can configure the MSB to be captured on the falling edge of DCLK via properties. The number of audio bits can be configured for 8, 16, 20, or 24 bits. 4.3. FM Receiver 4.4.2. Audio Sample Rates The Si4704/05 FM receiver is based on the proven Si4700/01 FM tuner. The receiver uses a digital low-IF architecture allowing the elimination of external components and factory adjustments. The Si4704/05 integrates a low noise amplifier (LNA) supporting the worldwide FM broadcast band (64 to 108 MHz). An AGC circuit controls the gain of the LNA to optimize sensitivity and rejection of strong interferers. An imagereject mixer downconverts the RF signal to low-IF. The device supports a number of industry-standard sampling rates including 32, 40, 44.1, and 48 kHz. The digital audio interface enables low-power operation by eliminating the need for redundant DACs on the audio baseband processor. Rev. 1.0 19 Si4704/05-C40 (OFALL = 1) INVERTED DCLK (OFALL = 0) DCLK LEFT CHANNEL DFS I2S (OMODE = 0000) RIGHT CHANNEL 1 DCLK 1 DCLK 1 DOUT 2 n-2 3 n-1 MSB n 1 LSB MSB 2 n-2 3 n-1 n LSB Figure 10. I2S Digital Audio Format (OFALL = 1) INVERTED DCLK (OFALL = 0) DCLK DFS LEFT CHANNEL RIGHT CHANNEL Left-Justified (OMODE = 0110) 1 DOUT 2 3 n-2 n-1 MSB n 1 LSB MSB 2 n-2 3 n-1 n LSB Figure 11. Left-Justified Digital Audio Format (OFALL = 0) DCLK DFS RIGHT CHANNEL LEFT CHANNEL (OMODE = 1100) DOUT (MSB at 1st rising edge) 1 2 3 n-2 n-1 MSB DOUT (MSB at 2nd rising edge) 1 LSB MSB n-1 n 1 LSB MSB 2 1 2 3 n-2 MSB Rev. 1.0 n-1 n LSB RIGHT CHANNEL 2 Figure 12. DSP Digital Audio Format 20 n-2 3 LEFT CHANNEL 1 DCLK (OMODE = 1000) n 3 n-2 n-1 n LSB Si4704/05-C40 4.6. De-emphasis The output of the FM demodulator is a stereo multiplexed (MPX) signal. The MPX standard was developed in 1961, and is used worldwide. Today's MPX signal format consists of left + right (L+R) audio, left – right (L–R) audio, a 19 kHz pilot tone, and RDS/RBDS data as shown in Figure 13 below. Pre-emphasis and de-emphasis is a technique used by FM broadcasters to improve the signal-to-noise ratio of FM receivers by reducing the effects of high-frequency interference and noise. When the FM signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. The Si4704/05 incorporates a de-emphasis filter which attenuates high frequencies to restore a flat frequency response. Two time constants are used in various regions. The deemphasis time constant is programmable to 50 or 75 µs and is set by the FM_DEEMPHASIS property. Modulation Level 4.5. Stereo Audio Processing Mono Audio Left + Right 0 Stereo Pilot 15 19 23 Stereo Audio Left - Right 38 RDS/ RBDS 53 57 Frequency (kHz) 4.7. Stereo DAC High-fidelity stereo digital-to-analog converters (DACs) drive analog audio signals onto the LOUT and ROUT pins. The audio output may be muted. Volume is adjusted digitally with the RX_VOLUME property. 4.8. Soft Mute Figure 13. MPX Signal Spectrum 4.5.1. Stereo Decoder The Si4704/05's integrated stereo decoder automatically decodes the MPX signal using DSP techniques. The 0 to 15 kHz (L+R) signal is the mono output of the FM tuner. Stereo is generated from the (L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is used as a reference to recover the (L–R) signal. Output left and right channels are obtained by adding and subtracting the (L+R) and (L–R) signals respectively. The Si4705 uses frequency information from the 19 kHz stereo pilot to recover the 57 kHz RDS/RBDS signal. 4.5.2. Stereo-Mono Blending Adaptive noise suppression is employed to gradually combine the stereo left and right audio channels to a mono (L+R) audio signal as the signal quality degrades to maintain optimum sound fidelity under varying reception conditions. Stereo/mono status can be monitored with the FM_RSQ_STATUS command. Mono operation can be forced with the FM_BLEND_MONO_THRESHOLD property. The soft mute feature is available to attenuate the audio outputs and minimize audible noise in very weak signal conditions. The softmute attenuation level is adjustable using the FM_SOFT_MUTE_MAX_ATTENUATION property. 4.9. RDS/RBDS Processor (Si4705 Only) The Si4705 implements an RDS/RBDS* processor for symbol decoding, block synchronization, error detection, and error correction. The Si4705 device is user configurable and provides an optional interrupt when RDS is synchronized, loses synchronization, and/or the user configurable RDS FIFO threshold has been met. The Si4705 reports RDS decoder synchronization status and detailed bit errors in the information word for each RDS block with the FM_RDS_STATUS command. The range of reportable block errors is 0, 1–2, 3–5, or 6+. More than six errors indicates that the corresponding block information word contains six or more non-correctable errors or that the block checkword contains errors. *Note: RDS/RBDS is referred to only as RDS throughout the remainder of this document. Rev. 1.0 21 Si4704/05-C40 4.10. Tuning 4.13. Control Interface The tuning frequency can be directly programmed using the FM_TUNE_FREQ command. The Si4704/05 supports channel spacing steps of 10 kHz in FM mode. A serial port slave interface is provided, which allows an external controller to send commands to the Si4704/05 and receive responses from the device. The serial port can operate in three bus modes: 2-wire mode, 3-wire mode, or SPI mode. The Si4704/05 selects the bus mode by sampling the state of the GPO1 and GPO2 pins on the rising edge of RST. The GPO1 pin includes an internal pull-up resistor, which is connected while RST is low, and the GPO2 pin includes an internal pulldown resistor, which is connected while RST is low. Therefore, it is only necessary for the user to actively drive pins which differ from these states. See Table 12. 4.11. Seek Seek tuning will search up or down for a valid channel. Valid channels are found when the receive signal strength indicator (RSSI) and the signal-to-noise ratio (SNR) values exceed the set threshold. Using the SNR qualifier rather than solely relying on the more traditional RSSI qualifier can reduce false stops and increase the number of valid stations detected. Seek is initiated using the FM_SEEK_START command. The RSSI and SNR threshold settings are adjustable using properties (see Table 14). Table 12. Bus Mode Select on Rising Edge of RST 4.12. Reference Clock The Si4704/05 reference clock is programmable, supporting RCLK frequencies in Table 11. Refer to Table 3, “DC Characteristics,” on page 5 for switching voltage levels and Table 9, “FM Receiver Characteristics,” on page 12 for frequency tolerance information. An onboard crystal oscillator is available to generate the 32.768 kHz reference when an external crystal and load capacitors are provided. Refer to "2. Typical Application Schematic" on page 16. This mode is enabled using the POWER_UP command. Refer to Table 13, “Selected Si4704/05 Commands,” on page 25. The Si4704/05 performance may be affected by data activity on the SDIO bus when using the integrated internal oscillator. SDIO activity results from polling the tuner for status or communicating with other devices that share the SDIO bus. If there is SDIO bus activity while the Si4704/05 is performing the seek/tune function, the crystal oscillator may experience jitter, which may result in mistunes, false stops, and/or lower SNR. For best seek/tune results, Silicon Laboratories recommends that all SDIO data traffic be suspended during Si4704/05 seek and tune operations. This is achieved by keeping the bus quiet for all other devices on the bus, and delaying tuner polling until the tune or seek operation is complete. The seek/tune complete (STC) interrupt should be used instead of polling to determine when a seek/tune operation is complete. 22 Bus Mode GPO1 GPO2 2-Wire 1 0 SPI 1 1 (must drive) 3-Wire 0 (must drive) 0 After the rising edge of RST, the pins GPO1 and GPO2 are used as general purpose output (O) pins as described in Section “4.14. GPO Outputs”. In any bus mode, commands may only be sent after VIO and VDD supplies are applied. In any bus mode, before sending a command or reading a response, the user must first read the status byte to ensure that the device is ready (CTS bit is high). 4.13.1. 2-Wire Control Interface Mode When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. Also, a start condition must not occur within 300 ns before the rising edge of RST. The 2-wire bus mode uses only the SCLK and SDIO pins for signaling. A transaction begins with the START condition, which occurs when SDIO falls while SCLK is high. Next, the user drives an 8-bit control word serially on SDIO, which is captured by the device on rising edges of SCLK. The control word consists of a 7-bit device address, followed by a read/write bit (read = 1, write = 0). The Si4704/05 acknowledges the control word by driving SDIO low on the next falling edge of SCLK. Rev. 1.0 Si4704/05-C40 Although the Si4704/05 will respond to only a single device address, this address can be changed with the SEN pin (note that the SEN pin is not used for signaling in 2-wire mode). When SEN = 0, the 7-bit device address is 0010001b. When SEN = 1, the address is 1100011b. For write operations, the user then sends an 8-bit data byte on SDIO, which is captured by the device on rising edges of SCLK. The Si4704/05 acknowledges each data byte by driving SDIO low for one cycle, on the next falling edge of SCLK. The user may write up to 8 data bytes in a single 2-wire transaction. The first byte is a command, and the next seven bytes are arguments. For read operations, after the Si4704/05 has acknowledged the control byte, it will drive an 8-bit data byte on SDIO, changing the state of SDIO on the falling edge of SCLK. The user acknowledges each data byte by driving SDIO low for one cycle, on the next falling edge of SCLK. If a data byte is not acknowledged, the transaction will end. The user may read up to 16 data bytes in a single 2-wire transaction. These bytes contain the response data from the Si4704/05. A 2-wire transaction ends with the STOP condition, which occurs when SDIO rises while SCLK is high. For details on timing specifications and diagrams, refer to Table 5, “2-Wire Control Interface Characteristics” on page 7; Figure 2, “2-Wire Control Interface Read and Write Timing Parameters,” on page 8, and Figure 3, “2Wire Control Interface Read and Write Timing Diagram,” on page 8. 4.13.2. 3-Wire Control Interface Mode When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. The 3-wire bus mode uses the SCLK, SDIO, and SEN_ pins. A transaction begins when the user drives SEN low. Next, the user drives a 9-bit control word on SDIO, which is captured by the device on rising edges of SCLK. The control word consists of a 3-bit device address (A7:A5 = 101b), a read/write bit (read = 1, write = 0), and a 5-bit register address (A4:A0). For write operations, the control word is followed by a 16-bit data word, which is captured by the device on rising edges of SCLK. For read operations, the control word is followed by a delay of one-half SCLK cycle for bus turn-around. Next, the Si4704/05 will drive the 16-bit read data word serially on SDIO, changing the state of SDIO on each rising edge of SCLK. A transaction ends when the user sets SEN high, then pulses SCLK high and low one final time. SCLK may either stop or continue to toggle while SEN is high. In 3-wire mode, commands are sent by first writing each argument to register(s) 0xA1–0xA3, then writing the command word to register 0xA0. A response is retrieved by reading registers 0xA8–0xAF. For details on timing specifications and diagrams, refer to Table 6, “3-Wire Control Interface Characteristics,” on page 9; Figure 4, “3-Wire Control Interface Write Timing Parameters,” on page 9, and Figure 5, “3-Wire Control Interface Read Timing Parameters,” on page 9. 4.13.3. SPI Control Interface Mode When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. SPI bus mode uses the SCLK, SDIO, and SEN pins for read/write operations. The system controller can choose to receive read data from the device on either SDIO or GPO1. A transaction begins when the system controller drives SEN = 0. The system controller then pulses SCLK eight times, while driving an 8-bit control byte serially on SDIO. The device captures the data on rising edges of SCLK. The control byte must have one of five values: 0x48 = write a command (controller drives 8 additional bytes on SDIO). 0x80 = read a response (device drives one additional byte on SDIO). 0xC0 = read a response (device drives 16 additional bytes on SDIO). 0xA0 = read a response (device drives one additional byte on GPO1). 0xE0 = read a response (device drives 16 additional bytes on GPO1). For write operations, the system controller must drive exactly eight data bytes (a command and seven arguments) on SDIO after the control byte. The data is captured by the device on the rising edge of SCLK. For read operations, the controller must read exactly 1 byte (STATUS) after the control byte or exactly 16 data bytes (STATUS and RESP1–RESP15) after the control byte. The device changes the state of SDIO (or GPO1, if specified) on the falling edge of SCLK. Data must be captured by the system controller on the rising edge of SCLK. Rev. 1.0 23 Si4704/05-C40 Keep SEN low until all bytes have transferred. A transaction may be aborted at any time by setting SEN high and toggling SCLK high and then low. Commands will be ignored by the device if the transaction is aborted. For details on timing specifications and diagrams, refer to Figure 6 and Figure 7 on page 10. 4.14. GPO Outputs The Si4704/05 provides three general-purpose output pins. The GPO pins can be configured to output a constant low, constant high, or high-impedance. The GPO pins can be reconfigured as specialized functions. GPO2/INT can be configured to provide interrupts and GPO3 can be configured to provide external crystal support or as DCLK in digital audio output mode. 4.15. Reset, Powerup, and Powerdown Setting the RST pin low will disable analog and digital circuitry, reset the registers to their default settings, and disable the bus. Setting the RST pin high will bring the device out of reset. A powerdown mode is available to reduce power consumption when the part is idle. Putting the device in powerdown mode will disable analog and digital circuitry while keeping the bus active. 24 4.16. Programming with Commands To ease development time and offer maximum customization, the Si4704/05 provides a simple yet powerful software interface to program the receiver. The device is programmed using commands, arguments, properties, and responses. To perform an action, the user writes a command byte and associated arguments, causing the chip to execute the given command. Commands control an action such as powerup the device, shut down the device, or tune to a station. Arguments are specific to a given command and are used to modify the command. A partial list of commands is available in Table 13, “Selected Si4704/05 Commands,” on page 25. Properties are a special command argument used to modify the default chip operation and are generally configured immediately after powerup. Examples of properties are de-emphasis level, RSSI seek threshold, and soft mute attenuation threshold. A partial list of properties is available in Table 14, “Selected Si4704/05 Properties,” on page 26. Responses provide the user information and are echoed after a command and associated arguments are issued. All commands provide a one-byte status update indicating interrupt and clear-to-send status information. For a detailed description of the commands and properties for the Si4704/05, see “AN332: Universal Programming Guide.” Rev. 1.0 Si4704/05-C40 5. Commands and Properties Table 13. Selected Si4704/05 Commands Cmd Name Description 0x01 POWER_UP Powerup device and mode selection. Modes include analog or digital output and reference clock or crystal support. 0x10 GET_REV 0x11 POWER_DOWN Powerdown device. 0x12 SET_PROPERTY Sets the value of a property. 0x13 GET_PROPERTY Retrieves a property’s value. 0x20 FM_TUNE_FREQ Selects the FM tuning frequency. 0x21 FM_SEEK_START Begins searching for a valid frequency. 0x22 FM_TUNE_STATUS Queries the status of previous FM_TUNE_FREQ or FM_SEEK_START command. 0x23 FM_RSQ_STATUS Queries the status of the Received Signal Quality (RSQ) of the current channel (Si4705 only). 0x24 FM_RDS_STATUS Returns RDS information for current channel and reads an entry from the RDS FIFO (Si4705 only). Returns revision information on the device. Rev. 1.0 25 Si4704/05-C40 Table 14. Selected Si4704/05 Properties Prop Name 0x1100 FM_DEEMPHASIS 0x1105 Description Default Sets deemphasis time constant. Default is 75 us. 0x0002 FM_BLEND_STEREO_ THRESHOLD Sets RSSI threshold for stereo blend (Full stereo above threshold, blend below threshold). To force stereo set this to 0. To force mono set this to 127. Default value is 49 dBuV. 0x0031 0x1106 FM_BLEND_MONO_ THRESHOLD Sets RSSI threshold for mono blend (Full mono below threshold, blend above threshold). To force stereo set this to 0. To force mono set this to 127. Default value is 30 dBuV. 0x001E 0x1200 FM_RSQ_INT_ SOURCE Configures interrupt related to Received Signal Quality metrics. 0x0000 0x1302 FM_SOFT_MUTE_ MAX_ATTENUATION Sets maximum attenuation during soft mute (dB). Set to 0 to disable soft mute. Default is 16 dB. 0x0010 0x1400 FM_SEEK_BAND_ BOTTOM Sets the bottom of the FM band for seek. Default is 8750. 0x222E 0x1401 FM_SEEK_BAND_TOP Sets the top of the FM band for seek. Default is 10790. 0x2A26 0x1402 FM_SEEK_FREQ_ SPACING Selects frequency spacing for FM seek. 0x000A 0x1403 FM_SEEK_TUNE_ SNR_THRESHOLD Sets the SNR threshold for a valid FM Seek/Tune. Default value is 3 dB. 0x0003 0x1404 FM_SEEK_TUNE_ RSSI_TRESHOLD Sets the RSSI threshold for a valid FM Seek/Tune. Default value is 20 dBuV. 0x0014 0x1500 RDS_INT_SOURCE Configures RDS interrupt behavior. 0x0000 0x1501 RDS_INT_FIFO_COUNT Sets the minimum number of RDS groups stored in the receive RDS FIFO required before RDS RECV is set. 0x0000 0x1502 RDS_CONFIG Configures RDS setting. 0x0000 0x4000 RX_VOLUME Sets the output volume. 0x003F 0x4001 RX_HARD_MUTE Mutes the audio output. L and R audio outputs may be muted independently in FM mode. 0x0000 26 Rev. 1.0 Si4704/05-C40 NC 1 DFS GPO3/DCLK GPO2/INT GPO1 NC 6. Pin Descriptions: Si4704/05-GM 20 19 18 17 16 FMI 2 15 DOUT RFGND 3 14 LOUT GND PAD LPI 4 13 ROUT 7 8 9 SDIO RCLK 10 11 VDD VIO 6 SCLK 12 GND SEN RST 5 Pin Number(s) Name Description 1, 20 NC No connect. Leave floating. 2 FMI FM RF input. 3 RFGND 4 LPI Loop antenna RF input. 5 RST Device reset input (active low). 6 SEN Serial enable input (active low). 7 SCLK Serial clock input. 8 SDIO Serial data input/output. 9 RCLK External reference or crystal oscillator input. 10 VIO I/O supply voltage. 11 VDD Supply voltage. May be connected directly to battery. 12, GND PAD GND Ground. Connect to ground plane on PCB. 13 ROUT Right audio analog line output. 14 LOUT Left audio analog line output. 15 DOUT Digital audio output data. 16 DFS 17 GPO3/DCLK 18 GPO2/INT 19 GPO1 RF ground. Connect to ground plane on PCB. Digital frame synchronization. General purpose output/digital bit synchronous clock or crystal oscillator input. General purpose output/interrupt. General purpose output. Rev. 1.0 27 Si4704/05-C40 7. Ordering Guide Part Number* Description Package Type Operating Temperature Si4704-C40-GM FM Broadcast Radio Receiver QFN Pb-free –20 to 85 °C Si4705-C40-GM FM Broadcast Radio Receiver with RDS/RBDS QFN Pb-free –20 to 85 °C *Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. 28 Rev. 1.0 Si4704/05-C40 8. Package Markings (Top Marks) 8.1. Si4704 Top Mark 0440 CTTT YWW Figure 14. Si4704 Top Mark 8.2. Si4705 Top Mark 0540 CTTT YWW Figure 15. Si4705 Top Mark 8.3. Top Mark Explanation Mark Method: YAG Laser Line 1 Marking: Part Number 04 = Si4704 05 = Si4705 Firmware Revision 40 = Firmware Revision 4.0 R = Die Revision C = Revision C Die. TTT = Internal Code Internal tracking code. Line 2 Marking: Line 3 Marking: Circle = 0.5 mm Diameter Pin 1 Identifier. (Bottom-Left Justified) Y = Year WW = Workweek Assigned by the Assembly House. Corresponds to the last significant digit of the year and workweek of the mold date. Rev. 1.0 29 Si4704/05-C40 9. Package Outline: Si4704/05-GM Figure 16 illustrates the package details for the Si4704/05. Table 15 lists the values for the dimensions shown in the illustration. Figure 16. 20-Pin Quad Flat No-Lead (QFN) Table 15. Package Dimensions Symbol Millimeters Symbol Min Nom Max A 0.50 0.55 0.60 f A1 0.00 0.02 0.05 L 0.35 0.40 0.45 b 0.20 0.25 0.30 L1 0.00 — 0.10 c 0.27 0.32 0.37 aaa — — 0.05 bbb — — 0.05 ccc — — 0.08 ddd — — 0.10 eee — — 0.10 D D2 1.65 1.70 1.75 0.50 BSC E E2 Min 3.00 BSC e 3.00 BSC 1.65 1.70 1.75 Notes: 1. All dimensions are shown in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 30 Millimeters Rev. 1.0 Nom Max 2.53 BSC Si4704/05-C40 10. PCB Land Pattern: Si4704/05-C40-GM Figure 17 illustrates the PCB land pattern details for the Si4704/05-GM. Table 16 lists the values for the dimensions shown in the illustration. Figure 17. PCB Land Pattern Rev. 1.0 31 Si4704/05-C40 Table 16. PCB Land Pattern Dimensions Symbol Millimeters Min D D2 Symbol Max 2.71 REF 1.60 1.80 Min Max GE 2.10 — W — 0.34 — e 0.50 BSC X E 2.71 REF Y E2 f GD 1.60 1.80 2.53 BSC 2.10 Millimeters 0.28 0.61 REF ZE — 3.31 ZD — 3.31 — Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Notes: Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Notes: Stencil Design 1. A stainless steel, laser-cut, and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. Notes: Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 32 Rev. 1.0 Si4704/05-C40 11. Additional Reference Resources Contact your local sales representatives for more information or to obtain copies of the following references: EN55020 Compliance Test Certificate AN332: Si47xx Programming Guide AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure Rev. 1.0 33 Si4704/05-C40 DOCUMENT CHANGE LIST Revision 0.7 to Revision 0.71 VIO minimum changed from 1.5 V to 1.85 V. Revision 0.71 to Revision 1.0 Updated patent information on page 1. Updated Table 3 on page 5. 34 Rev. 1.0 Si4704/05-C40 NOTES: Rev. 1.0 35 Si4704/05-C40 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: [email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 36 Rev. 1.0