Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 LP3907-Q1 Dual High-Current Step-Down DC-DC And Dual Linear Regulator With I2C Interface 1 Features 2 Applications • • • • • 1 • • • • • • • • • • Input Voltage Range: 2.8 V to 5.5 V Compatible with Advanced Applications Processors and FPGAs 2 LDOs for Powering Internal Processor Functions and I/Os High-Speed Serial Interface for Independent Control of Device Functions and Settings Precision Internal Reference Thermal Overload Protection Current Overload Protection Software Programmable Regulators External Power-On-Reset Function for Buck1 and Buck2 (Power Good with Delay Function) Undervoltage Lockout Detector to Monitor Input Supply Voltage Step-Down DC-DC Converter (Buck) – Programmable VOUT from: – Buck1 : 0.8 V - 2 V at 1 A – Buck2 : 1 V - 3.5 V at 600 mA – Up to 96% Efficiency – 2.1-MHz PWM Switching Frequency – PWM-to-PFM Automatic Mode Change Under Low Loads – ±3% Output Voltage Accuracy – Automatic Soft Start Linear Regulators (LDO) – Programmable VOUT of 1 V to 3.5 V – ±3% Output Voltage Accuracy – 300-mA Output Current – 30-mV (typical) Dropout FPGA, DSP Core Power Applications Processors Peripheral I/O Power 3 Description The LP3907-Q1 is a multi-function, programmable Power Management Unit, optimized for low power FPGAs, microprocessors, and DSPs. This device integrates two highly efficient 1-A/600-mA step-down DC-DC converters with dynamic voltage management (DVM), two 300-mA linear regulators, and a 400-kHz I2C interface to allow a host controller access to the internal control registers of the device. The LP3907Q1 additionally features programmable power-on sequencing. This device is an Automotive-Grade Product that is AECQ-100 Grade 1 Qualified. Device Information(1) PART NUMBER LP3907-Q1 PACKAGE BODY SIZE (NOM) WQFN (24) 4.00 mm x 4.00 mm DSBGA (25) 2.49 mm x 2.49 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Application Circuit VINLDO12 EN_T VDD ENLDO1 1 PF 100k ENLDO2 nPOR ENSW1 VIN1 10 PF ENSW2 2.2 PH LDO1 SW1 0.47 PF 10 PF FB1 VINLDO1 GND_SW1 LP3907-Q1 1 PF VINLDO2 VIN2 1 PF 10 PF LDO2 2.2 PH 0.47 PF SW2 SDA 10 PF FB2 SCL GND_SW2 GND_L GND_C AVDD DAP 1 PF 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Tables................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 1 1 1 2 3 4 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions (Bucks).......... 6 Thermal Information .................................................. 7 General Electrical Characteristics............................ 7 Low Dropout Regulators, LDO1 And LDO2............. 7 Buck Converters SW1, SW2.................................... 8 I/O Electrical Characteristics.................................... 9 Power-On Reset Threshold/Function (POR) ........... 9 I2C Interface Timing Requirements ....................... 9 Typical Characteristics — LDO............................... 9 Typical Characteristics — Bucks .......................... 11 Typical Characteristics — Buck1 .......................... 12 Typical Characteristics — Buck2 .......................... 12 Typical Characteristics — Bucks .......................... 13 8 Detailed Description ............................................ 15 8.1 8.2 8.3 8.4 8.5 8.6 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming .......................................................... Register Maps ........................................................ 15 15 16 25 25 28 Application and Implementation ........................ 38 9.1 Application Information............................................ 38 9.2 Typical Application ................................................. 38 10 Power Supply Recommendations ..................... 43 10.1 Analog Power Signal Routing ............................... 43 11 Layout................................................................... 44 11.1 DSBGA Layout Guidelines.................................... 44 11.2 Layout Example .................................................... 45 11.3 Thermal Considerations of WQFN Package......... 45 12 Device and Documentation Support ................. 46 12.1 12.2 12.3 12.4 Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 46 46 46 46 13 Mechanical, Packaging, and Orderable Information ........................................................... 46 4 Revision History Changes from Original (December 2014) to Revision A • 2 Page Added last sentence to "NOTE" .......................................................................................................................................... 19 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 5 Device Comparison Tables Table 1. Default I2C Addresses PACKAGE TYPE DEFAULT I2C ADDRESS 24-lead WQFN 60 25-bump DSBGA 61 Table 2. Power Block POWER BLOCK OPERATION POWER BLOCK INPUT ENABLED VINLDO12 (1) VIN+ NOTE DISABLED (1) VIN+ Always powered AVDD VIN+ VIN+ Always powered VIN1 VIN+ VIN+ VIN2 VIN+ VIN+ LDO1 ≤ VIN+ ≤ VIN+ If enabled, minimum VIN is 1.74 V LDO2 ≤ VIN+ ≤ VIN+ If enabled, minimum VIN is 1.74 V VIN+ is the largest potential voltage on the device. Table 3. Default Device Options (1) (2) PART NUMBER BUCK1 BUCK2 LDO1 LDO2 BUCK MODES DEFAULT EN_T DELAY DEFAULT UVLO LP3907QSQ-JXIP/NOPB 1.2V 3.3V 1.8V 2.5V Forced PWM 001 Enabled LP3907QSQX-JXIP/NOPB 1.2V 3.3V 1.8V 2.5V Forced PWM 001 Enabled LP3907QSQ-JXI7/NOPB 1.2V 3.3V 1.8V 2.5V Forced PWM 001 Disabled LP3907QSQX-JXI7/NOPB 1.2V 3.3V 1.8V 2.5V Forced PWM 001 Disabled LP3907QSQ-JJXP/NOPB 1.2V 1.8V 3.3V 2.5V Forced PWM 010 Disabled LP3907QSQX-JJXP/NOPB 1.2V 1.8V 3.3V 2.5V Forced PWM 010 Disabled LP3907QTL-VXSS/NOPB 1.8V 3.3V 2.8V 2.8V Forced PWM 010 Enabled LP3907QTLX-VXSS/NOPB 1.8V 3.3V 2.8V 2.8V Forced PWM 010 Enabled (1) (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 3 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com 6 Pin Configuration and Functions WQFN (RTW) 24 Leads Top View 17 16 15 14 13 1 2 3 4 5 6 21 10 20 11 19 12 18 9 22 8 23 7 24 DSBGA (YZR) 25 Pins Top View 4 5 VIN LDO2 VIN LDO12 GND_S W1 SW1 VIN1 4 LDO2 VIN LDO12 EN_T EN_S W1 FB1 3 EN_ LDO2 EN_ LDO1 nPOR GND_C AVDD 2 LDO1 SCL SDA EN_ SW2 FB2 1 VIN LDO1 GND_ L GND_ SW2 SW2 VIN2 A B C D E Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 Pin Functions PIN I/O TYPE (1) VINLDO12 I PWR C4 EN_T I D Enable for preset power on sequence. (See .) 3 C3 nPOR O D nPOR Power on reset pin for both Buck1 and Buck 2. Open drain logic output 100-kΩ pull-up resistor. nPOR is pulled to ground when the voltages on these supplies are not good. See Flexible Power-On Reset (Power Good with Delay) section for more info. 4 C5 GND_SW1 G G Buck1 NMOS Power Ground 5 D5 SW1 O PWR Buck1 switcher output pin 6 E5 VIN1 I PWR Power in from either DC source or Battery to Buck1 7 D4 ENSW1 I D Enable Pin for Buck1 switcher, a logic HIGH enables Buck1 8 E4 FB1 I A Buck1 input feedback terminal 9 D3 GND_C G G Non switching core ground pin 10 E3 AVDD I PWR 11 E2 FB2 I A Buck2 input feedback terminal 12 D2 ENSW2 I D Enable Pin for Buck2 switcher, a logic HIGH enables Buck2 13 E1 VIN2 I PWR Power in from either DC source or Battery to Buck2 14 D1 SW2 O PWR Buck2 switcher output pin 15 C1 GND_SW2 G G Buck2 NMOS Power ground 16 C2 SDA I/O D I2C Data (bidirectional) 17 B2 SCL I D I2C Clock 18 B1 GND_L G G LDO ground 19 A1 VINLDO1 I PWR Power in from either DC source or battery to input terminal to LDO1 20 A2 LDO1 O PWR LDO1 Output 21 B3 ENLDO1 I D LDO1 enable pin, a logic HIGH enables the LDO1 22 A3 ENLDO2 I D LDO2 enable pin, a logic HIGH enables the LDO2 23 A4 LDO2 O PWR LDO2 Output 24 A5 VINLDO2 I PWR Power in from either DC source or battery to input terminal to LDO2. DAP GND GND Connection isn't necessary for electrical performance, but it is recommended for better thermal dissipation. WQFN NUMBER DSBGA NUMBER NAME 1 B4, B5 2 DAP (1) A: Analog Pin D: Digital Pin G: Ground Pin DESCRIPTION Analog Power for Internal Functions (VREF, BIAS, I2C, Logic) Analog Power for Buck converters PWR: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 5 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) VIN, SDA, SCL MIN MAX –0.3 6 GND to GND SLUG Power dissipation (DSBGA (YZR)) (3) 1.43 (4) 150 Maximum lead temperature (soldering) 260 −65 Storage temperature, Tstg (4) W 0.78 Junction temperature (TJ-MAX) (2) (3) V ±0.3 Power dissipation (WQFN (RTW)) (3) (1) UNIT °C 150 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pin. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP − (RθJA × PD-MAX). For TA = 85°C, TJ-MAX = 125°C. 7.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) UNIT ±2000 Charged-device model (CDM), per AEC Q100-011 V ±750 AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.3 Recommended Operating Conditions (Bucks) over operating free-air temperature range (unless otherwise noted) (1) (2) (3) (4) MIN NOM MAX VIN 2.8 5.5 VEN 0 (VIN + 0.3 V) −40 125 −40 125 Junction temperature (TJ) Ambient temperature (TA) (1) (2) (3) (4) (5) 6 (5) UNIT V °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pin. Minimum (Min) and Maximum (Max) limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm. Buck VIN ≥ VOUT + 1V. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 7.4 Thermal Information (1) (2) (3) LP3907-Q1 THERMAL METRIC (4) RTW YZR 24 PINS 25 PINS RθJA Junction-to-ambient thermal resistance 32.7 58.7 RθJC(top) Junction-to-case (top) thermal resistance 31.2 0.3 RθJB Junction-to-board thermal resistance 11.2 8.0 ψJT Junction-to-top characterization parameter 0.2 0.6 ψJB Junction-to-board characterization parameter 11.2 8.0 RθJC(bot) Junction-to-case (bottom) thermal resistance 1.4 N/A (1) (2) (3) (4) UNIT °C/W Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160°C (typ.) and disengages at TJ = 140°C (typ.) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP − (RθJA × PD-MAX). For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 General Electrical Characteristics Unless otherwise noted, VIN = 3.6 V and TJ = 25°C. (1) (2) (3) (4) PARAMETER TEST CONDITIONS IQ VINLDO12 shutdown current VIN = 3.6 V VPOR Power-On reset threshold VDD falling edge (4) TSD TSDH UVLO (1) (2) (3) (4) 7.6 (6) (7) (8) (9) UNIT µA V Thermal shutdown threshold 160 °C Thermal shutdown hysteresis 20 °C Undervoltage lock out Rising 2.9 Falling 2.7 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pin. This specification is ensured by design. VPOR is voltage at which the EPROM resets. This is different from the UVLO on VINLDO12, which is the voltage at which the regulators shut off, and is also different from the nPOR function, which signals if the regulators are in a specified range. Low Dropout Regulators, LDO1 And LDO2 Operational voltage range VOUT Accuracy Output voltage accuracy (default VOUT) (3) (4) (5) MAX 1.9 PARAMETER (1) (2) TYP 3 Unless otherwise noted, VIN = 3.6 V, CIN = 1 µF, COUT = 0.47 µF, and TJ = 25°C. VIN MIN (1) (2) (3) (4) (5) (6) (7) TEST CONDITIONS VINLDO1 and VINLDO2 PMOS pins Load current = 1 mA MIN (8) MAX UNIT 1.74 (9) TYP 5.5 (9) V –3% (9) 3% (9) All voltages are with respect to the potential at the GND pin. Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm. CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. The device maintains a stable, regulated output voltage without a load. Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value. Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT. VIN minimum for line regulation values is 1.8 V. Pins 24, 19 can operate from VIN min of 1.74 V to a VIN max of 5.5 V. This rating is only for the series pass PMOS power FET. It allows the system design to use a lower voltage rating if the input voltage comes from a buck output. Limits apply over the entire junction temperature range for operation, −40°C to 125°C. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 7 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com Low Dropout Regulators, LDO1 And LDO2 (continued) Unless otherwise noted, VIN = 3.6 V, CIN = 1 µF, COUT = 0.47 µF, and TJ = 25°C. PARAMETER ΔVOUT ISC UNIT %/V Load regulation VIN = 3.6 V, Load current = 1 mA to IMAX 0.011 (9) %/mA Short circuit current limit LDO1-2, VOUT = 0 V θn 500 Load current = 50 mA mA 30 Power supply ripple rejection ƒ = 10 kHz, load current = IMAX 45 dB Supply output noise 10 Hz < F < 100 KHz 80 µVrms Quiescent current “on” IOUT = 0 mA 40 µA Quiescent current “on” IOUT = IMAX 60 µA 0.03 µA 300 µs 0.33 (9) 0.47 µF 0.68 1 (11) Quiescent current “off” EN is de-asserted Turnon time Start-up from shutdown Output capacitor −40°C ≤ TJ ≤ 125°C 5 (9) ESR 200 (9) (5) Capacitance for stability 0°C ≤ TJ ≤ 125°C COUT MAX 0.15 (9) PSRR TON TYP VIN = (VOUT + 0.3 V) to 5 V, (7) , load current = 1 mA Dropout voltage (10) MIN Line regulation VIN – VOUT IQ (6) TEST CONDITIONS (1)(2)(3)(4)(5)(6)(7) mV µF 500 (9) mΩ (10) The IQ can be defined as the standing current of the LP3907-Q1 when the I2C bus is active and all other power blocks have been disabled via the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two values can be used by the system designer when the LP3907-Q1 is powered using a battery. (11) The IQ exhibits a higher current draw when the EN pin is de-asserted because the I2C buffer pins draw an additional 2 µA. 7.7 Buck Converters SW1, SW2 Unless otherwise noted, VIN = 3.6 V, CIN = 10 µF, COUT = 10 µF, LOUT = 2.2 µH ceramic, and TJ = 25°C. PARAMETER VFB TEST CONDITIONS Line regulation 2.8 V < VIN < 5.5 V IOUT = 10 mA Load regulation 100 mA < IOUT < IMAX Eff Efficiency Load current = 250 mA ISHDN Shutdown supply current EN is de-asserted fOSC Internal oscillator frequency IPEAK IQ (8) TYP –3% (7) Feedback voltage VOUT MIN (1) (2) (3) (4) (5) (6) MAX UNIT 3% (7) 0.089 %/V 0.0013 %/mA 96% 0.01 µA 2.1 MHz Buck1 peak switching current limit 1.5 A Buck2 peak switching current limit 1 33 µA RDSON (P) Pin-pin resistance PFET 200 mΩ RDSON (N) Pin-pin resistance NFET 180 mΩ TON Turnon time Start up from shutdown CIN Input capacitor Capacitance for stability 10 µF CO Output capacitor Capacitance for stability 10 µF (1) (2) (3) (4) (5) (6) (7) (8) 8 Quiescent current “on” 1.7 (7) No load PFM mode 500 µs All voltages are with respect to the potential at the GND pin. Minimum (Min) and Maximum (Max) limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm. CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. The device maintains a stable, regulated output voltage without a load. Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT. Buck VIN ≥ VOUT + 1 V. Limits apply over the entire junction temperature range for operation, −40°C to 125°C. The IQ can be defined as the standing current of the LP3907-Q1 when the I2C bus is active and all other power blocks have been disabled via the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two values can be used by the system designer when the device is powered using a battery. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com 7.8 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 I/O Electrical Characteristics Unless otherwise noted: Limits apply over the entire junction temperature range for operation, TJ = −40°C to 125°C. PARAMETER VIL Input low level VIH Input high level (1) TEST CONDITIONS MIN (1) MAX UNIT 0.4 1.2 V This specification is ensured by design. 7.9 Power-On Reset Threshold/Function (POR) PARAMETER TEST CONDITIONS MIN TYP MAX nPOR = Power on reset forBuck1 and Default Buck2 nPOR threshold Percentage of target voltage Buck1 or Buck2 VBUCK1 AND VBUCK2 rising 94% VBUCK1 OR VBUCK2 falling 85% VOL Output level low Load = IoL = 500 mA 0.23 0.5 V NOM MAX UNIT 400 kHz 7.10 50 UNIT nPOR ms I2C Interface Timing Requirements Unless otherwise noted, VIN = 3.6 V and TJ = 25°C. (1) MIN (1) ƒCLK Clock frequency tBF Bus-free time between start and stop 1.3 µs tHOLD Hold time repeated start condition 0.6 µs tCLKLP CLK low period 1.3 µs tCLKHP CLK high period 0.6 µs tSU Set-up time repeated start condition 0.6 µs tDATAHLD Data hold time 0 µs tDATASU Data set-up time 100 ns TSU Set-up time for start condition 0.6 µs TTRANS Maximum pulse width of spikes that must be suppressed by the input filter of both DATA & CLK signals See (1) 50 ns This specification is ensured by design. 7.11 Typical Characteristics — LDO 2.00 2.00 1.50 1.50 1.00 1.00 VOUT CHANGE (%) VOUT CHANGE (%) TA = 25°C unless otherwise noted. 0.50 0.00 -0.50 0.50 0.00 -0.50 -1.00 -1.00 -1.50 -1.50 -2.00 -50 -35 -20 -5 10 25 40 55 70 85 100 -2.00 -50 -35 -20 -5 10 25 40 55 70 85 100 TEMPERATURE (°C) TEMPERATURE (°C) VIN = 3.6 V VOUT = 2.6 V 100-mA Load Figure 1. Output Voltage Change vs Temperature (LDO1) VIN = 3.6 V VOUT = 2.6 V 100-mA Load Figure 2. Output Voltage Change vs Temperature (LDO2) Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 9 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com Typical Characteristics — LDO (continued) TA = 25°C unless otherwise noted. VIN = 3.6 V VOUT = 2.6 V 0 to 150-mA Load VIN = 3.6 V Figure 3. Load Transient (LDO1) VIN = 3.6 to 4.2 V VOUT = 2.6 V VOUT = 2.6 V 300-mA Load VIN = 3.6 to 4.2 V VOUT = 3.3 V 300-mA Load Figure 6. Line Transient (LDO2) 1-mA Load VIN = 0 to 3.6 V Figure 7. Enable Start-Up Time (LDO1) 10 0 to 150-mA Load Figure 4. Load Transient (LDO2) Figure 5. Line Transient (LDO1) VIN = 0 to 3.6 V VOUT = 3.3 V Submit Documentation Feedback VOUT = 3.3 V 1-mA Load Figure 8. Enable Start-Up Time (LDO2) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 Typical Characteristics — LDO (continued) TA = 25°C unless otherwise noted. 300 MAXIMUM LOAD (mA) VIN = 1.74V 250 200 150 100 1.00 1.10 1.20 1.30 1.40 1.50 1.60 VOUT(V) VIN = 1.74 V Figure 9. LDO Maximum Load 7.12 Typical Characteristics — Bucks 0.15 1.05 0.12 1.03 IOUT = 750 mA VIN = 5.5V 0.09 VOUT (V) SHUTDOWN CURRENT (éA) VIN= 2.8 V to 5.5 V, TA = 25°C VIN = 3.6V 0.06 IOUT = 20 mA 1.01 0.99 IOUT = 1.0A VIN = 2.7V 0.03 0.00 -40 0.97 -20 0 20 40 60 0.95 2.5 80 TEMPERATURE (°C) 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) VOUT = 1 V Figure 10. Shutdown Current vs. Temp Figure 11. Output Voltage vs. Supply Voltage 1.85 3.35 1.83 3.33 IOUT = 20 mA VOUT (V) VOUT (V) IOUT = 300 mA 1.81 IOUT = 750 mA 1.79 IOUT = 20 mA 3.31 3.29 IOUT = 600 mA 1.77 1.75 2.7 3.27 IOUT = 1.0A 3.3 3.8 4.4 3.25 4.0 4.9 SUPPLY VOLTAGE (V) 4.5 5.0 5.5 SUPPLY VOLTAGE (V) VOUT = 1.8 V VOUT = 3.5 V Figure 12. Output Voltage vs. Supply Voltage Figure 13. Output Voltage vs. Supply Voltage Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 11 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com 7.13 Typical Characteristics — Buck1 VIN= 2.8 V to 5.5 V, TA = 25°C, VOUT = 1.2 V, 2 V 100 100 90 90 80 VIN= 2.8V 70 EFFICIENCY (%) EFFICIENCY (%) 80 60 50 VIN= 3.6V 40 60 50 VIN = 3.6V 40 VIN = 5.5V 30 VIN= 5.5V 30 VIN = 2.8V 70 20 20 10 0.1 1 10 100 10 0.1 1000 1 OUTPUT CURRENT (mA) VOUT = 1.2 V L= 2.2 µH VOUT = 2V 100 90 90 VIN = 5.5V 60 50 40 0.1 L= 2.2 µH 80 VIN= 3.6V VIN= 5.5V 70 60 50 1 10 100 40 0.1 1000 OUTPUT CURRENT (mA) VOUT = 1.2 V 1000 VIN= 2.8V VIN = 2.8V VIN = 3.6V 70 100 Figure 15. Efficiency vs Output Current (Forced PWM Mode) 100 EFFICIENCY (%) EFFICIENCY (%) Figure 14. Efficiency vs Output Current (Forced PWM Mode) 80 10 OUTPUT CURRENT (mA) 1 10 100 1000 OUTPUT CURRENT (mA) VOUT = 2 V L= 2.2 µH Figure 16. Efficiency vs Output Current (PWM-to-PFM Mode) L= 2.2 µH Figure 17. Efficiency vs Output Current (PWM-to-PFM Mode) 7.14 Typical Characteristics — Buck2 100 100 90 90 80 80 70 EFFICIENCY (%) EFFICIENCY (%) VIN= 4.5 V to 5.5 V, TA = 25°C, VOUT = 1.8 V, 3.3 V VIN= 4.5V 60 50 VIN= 5.5V 40 50 20 20 1 10 100 OUTPUT CURRENT (mA) VIN= 5.5V 40 30 VOUT = 1.8 V 10 0.1 1000 1 10 100 1000 OUTPUT CURRENT (mA) L= 2.2 µH VOUT = 3.3 V Figure 18. Efficiency vs Output Current (Forced PWM Mode) 12 60 30 10 0.1 VIN= 4.5V 70 L= 2.2 µH Figure 19. Efficiency vs Output Current (Forced PWM Mode) Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 Typical Characteristics — Buck2 (continued) VIN= 4.5 V to 5.5 V, TA = 25°C, VOUT = 1.8 V, 3.3 V 100 100 90 90 EFFICIENCY (%) EFFICIENCY (%) VIN= 4.5V VIN= 4.5V 80 VIN= 5.5V 70 60 VOUT = 1.2 V 70 60 50 50 40 0.1 VIN= 5.5V 80 1 10 100 OUTPUT CURRENT (mA) 40 0.1 1000 1 10 100 1000 OUTPUT CURRENT (mA) VOUT = 2 V L= 2.2 µH Figure 20. Efficiency vs Output Current (PWM-to-PFM Mode) L= 2.2 µH Figure 21. Efficiency vs Output Current (PWM-to-PFM Mode) 7.15 Typical Characteristics — Bucks VIN= 3.6 V, TA = 25°C, VOUT = 1.2 V unless otherwise noted. VOUT = 1.2 V ILOAD = 300 to 500 mA Figure 22. Load Transient Response (PWM Mode) VIN = 3.6 to 4.2 V VOUT = 1.2 V 250-mA Load VOUT = 1.2 V ILOAD = 50 to 150 mA Figure 23. Mode Change By Load Transient (PFM-to-PWM Mode) VIN = 3.6 to 4.2 V Figure 24. Line Transient Response VOUT = 3.3 V 250-mA Load Figure 25. Line Transient Response Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 13 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com Typical Characteristics — Bucks (continued) VIN= 3.6 V, TA = 25°C, VOUT = 1.2 V unless otherwise noted. VOUT = 1.2 V 1-A Load VOUT = 3.3 V Figure 26. Start-Up Into PWM Mode VOUT = 1.2 V Figure 27. Start-Up Into PWM Mode VOUT = 3.3 V 30-mA Load Figure 28. Start-Up Into PFM Mode 14 600-mA Load Submit Documentation Feedback 30-mA load Figure 29. Start-Up Into PFM Mode Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 8 Detailed Description 8.1 Overview The LP3907 supplies the various power needs of the application by means of two Linear Low Drop Regulators (LDO1 and LDO2) and two Buck converters (SW1 and SW2). Table 4 lists the output characteristics of the various regulators. Table 4. Supply Specification OUTPUT SUPPLY (1) (1) LOAD VOUT RANGE (V) RESOLUTION (mV) IMAX MAXIMUM OUTPUT CURRENT (mA) 300 LDO1 analog 1 to 3.5 100 LDO2 analog 1 to 3.5 100 300 SW1 digital 0.8 to 2 50 1000 SW2 digital 1 to 3.5 100 600 *For default values of the regulators, please consult Table 3. 8.2 Functional Block Diagram DC SOURCE 4.5V - 5.5V 1 uF 10 PF 10 PF LP3907-Q1 PMIC VIN1 1P F VIN2 1P F AVDD 1P F VINLDO2 VINLDO12 Cvdd 4.7 PF VINLDO1 + Li-ion/polymer cell 3.3V - 4.2V ULVO OSC Vin OK BUCK1 AVDD Lsw1 2.2 PH 1.2V VBUCK1 SW1 10 PF VFB1 ENLDO1 Lsw1 2.2 PH ENLDO2 Power ON-OFF Logic ENSW 1 AVDD BUCK2 3.3V VBUCK2 SW2 10 PF VFB2 ENSW 2 EN_T Thermal Shutdown VINLDO1 3.3V LDO1 LDO1 Cldo1 0.47 PF RESET VinLDO12 VINLDO2 2 I C_SCL BIAS I2C 2 LDO2 RDY1 Logic Control and Registers GND_SW1 1.8V LDO2 I C_SDA GND_SW2 Cldo2 0.47 PF RDY2 VDD nPOR Power On Reset GND_C 100k GND_L Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 15 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com 8.3 Feature Description 8.3.1 DC-DC Converters 8.3.1.1 Linear Low Dropout Regulators (LDOs) LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements. LDO1 and LDO2 are enabled through the ENLDO pin or through the corresponding LDO1 or LDO2 control register. The output voltages of both LDOs are register programmable. The default output voltages are factory programmed during Final Test, which can be tailored to the specific needs of the system designer. VLDO VIN LDO Register controlled + - ENLDO Vref GND Figure 30. LDO Block Diagram 8.3.1.2 No-Load Stability The LDOs remain stable and in regulation with no external load. This is an important consideration in some circuits, for example, CMOS RAM keep-alive applications. 8.3.1.3 LDO and LDO2 Control Registers LDO1 and LDO2 can be configured by means of the LDO1 and LDO2 control registers. The output voltage is programmable in steps of 100 mV from 1 V to 3.5 V by programming bits D4-D0 in the LDO Control registers. Both LDO1 and LDO2 are enabled by applying a logic 1 to the ENLDO1 and ENLDO2 pin. Enable/disable control is also provided through enable bit of the LDO1 and LDO2 control registers. The value of the enable LDO bit in the register is logic 1 by default. The output voltage can be altered while the LDO is enabled. 8.3.2 SW1, SW2: Synchronous Step-Down Magnetic DC-DC Converters 8.3.2.1 Functional Description The LP3907-Q1 incorporates two high-efficiency synchronous switching buck regulators, SW1 and SW2, that deliver a constant voltage from a single Li-Ion battery to the portable system processors. Using a voltage mode architecture with synchronous rectification, both bucks have the ability to deliver up to 1000 mA and 600 mA, respectively, depending on the input voltage and output voltage (voltage headroom), and the inductor chosen (maximum current capability). There are three modes of operation depending on the current required: PWM, PFM, and shutdown. PWM mode handles current loads of approximately 70 mA or higher, delivering voltage precision of ±3% with 90% efficiency or better. Lighter output current loads cause the device to automatically switch into PFM for reduced current consumption (IQ = 15 µA typ.) and a longer battery life. The Standby operating mode turns off the device, offering the lowest current consumption. PWM or PFM mode is selected automatically or PWM mode can be forced through the setting of the buck control register. Both SW1 and SW2 can operate up to a 100% duty cycle (PMOS switch always on) for low drop out control of the output voltage. In this way the output voltage is controlled down to the lowest possible input voltage. Additional features include soft-start, undervoltage lockout, current overload protection, and thermal overload protection. 16 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 Feature Description (continued) 8.3.2.2 Circuit Operation Description A buck converter contains a control block, a switching PFET connected between input and output, a synchronous rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path. During the first portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of VIN - VOUT (1) L by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of -VOUT (2) L The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load. 8.3.2.3 PWM Operation During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, feed forward voltage inversely proportional to the input voltage is introduced. 8.3.2.4 Internal Synchronous Rectification While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. 8.3.2.5 Current Limiting A current limit feature allows the converter to protect itself and external components during overload conditions. PWM mode implements current limiting using an internal comparator that trips at 1.5 A for Buck1 and at 1 A for Buck2 (typ). If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing runaway. 8.3.2.6 PFM Operation At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply current to maintain high efficiency. The part automatically transitions into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles: 1. The inductor current becomes discontinuous, or 2. The peak PMOS switch current drops below the IMODE level (Typically IMODE < 66 mA + VIN ) 160: (3) During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output voltage. If the output voltage is below the ‘low’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for PFM mode. The typical peak current in PFM mode is: Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 17 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com Feature Description (continued) IPFM = 66 mA + VIN 80: (4) Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see Figure 31), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this ‘sleep’ mode is less than 30 µA, which allows the part to achieve high efficiencies under extremely light load conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage to approximately 1.6% above the nominal PWM output voltage. If the load current should increase during PFM mode (see Figure 31) causing the output voltage to fall below the ‘low2’ PFM threshold, the part automatically transitions into fixed-frequency PWM mode. 8.3.2.7 SW1, SW2 Operation SW1 and SW2 have selectable output voltages ranging from 0.8 V to 3.5 V (typ.). Both SW1 and SW2 in the LP3907-Q1 are I2C register controlled and are enabled by default through the internal state machine of the device following a power-on event that moves the operating mode to the Active state. (See Flexible Power Sequencing of Multiple Power Supplies.) The SW1 and SW2 output voltages revert to default values when the power-on sequence has been completed. The default output voltage for each buck converter is factory programmable. (See Application and Implementation.) 8.3.2.8 SW1, SW2 Control Registers SW1, SW2 can be enabled/disabled through the corresponding control register. The Modulation mode PWM/PFM is by default automatic and depends on the load as described above in the functional description. The modulation mode can be overridden by setting I2C bit to a logic 1 in the corresponding buck control register, forcing the buck to operate in PWM mode regardless of the load condition. High PFM Threshold ~1.016 * Vout PFM Mode at Light Load Load current increases Low1 PFM Threshold ~1.008 * Vout ZA xi s High PFM Voltage Threshold reached, go into sleep mode Low PFM Threshold, turn on PFET Low2 PFM Threshold, switch back to PWMmode Zs Axi Pfet on until Ipfm limit reached Nfet on drains inductor current until I inductor = 0 Current load increases, draws Vout towards Low2 PFM Threshold Low2 PFM Threshold Vout PWM Mode at Moderate to Heavy Loads Figure 31. Operation in PFM Mode and Transfer to PWM Mode 18 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 Feature Description (continued) 8.3.2.9 Soft Start The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus reducing start-up stresses and surges. The two LP3907-Q1 buck converters have a soft-start circuit that limits inrush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after VIN reaches 2.8V. Soft start is implemented by increasing switch current limit in steps of 180 mA, 300 mA, and 720 mA for Buck1; 161 mA, 300 mA, and 536 mA for Buck2 (typical switch current limit). The start-up time thereby depends on the output capacitor and load current demanded at start-up. 8.3.2.10 Low Dropout Operation The LP3907-Q1 can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout support of the output voltage. In this way the output voltage is controlled down to the lowest possible input voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum input voltage needed to support the output voltage is: VIN, MIN = ILOAD × (RDSON, PFET + RINDUCTOR) + VOUT where • • • ILOAD = Load current RDSON, PFET = Drain to source resistance of RINDUCTOR = Inductor resistance PFET switch in the triode region (5) 8.3.2.11 Flexible Power Sequencing of Multiple Power Supplies The LP3907-Q1 provides several options for power on sequencing. The two bucks can be individually controlled with ENSW1 and ENSW2. The two LDOs can also be individually controlled with ENLDO1 and ENLDO2. If the user desires a set power on sequence, the chip is programmable through I2C and raise EN_T from LOW to HIGH to activate the power on sequencing. 8.3.2.12 Power-Up Sequencing Using the EN_T Function EN_T assertion causes the LP3907-Q1 to emerge from Standby mode to Full Operation mode at a preset timing sequence. By default, the enables for the LDOs and Bucks (ENLDO1, ENLDO2, EN_T, ENSW1, ENSW2) are 500 KΩ internally pulled down, which causes the part to stay OFF until enabled. If the user wishes to use the preset timing sequence to power on the regulators, transition the EN_T pin from Low to High. Otherwise, simply tie the enables of each specific regulator HIGH to turn on automatically. EN_T is edge triggered with rising edge signaling the chip to power on. The EN_T input is deglitched, and the default is set at 1 ms. As shown inFigure 32 and Figure 33, a rising EN_T edge starts a power-on sequence, while a falling EN_T edge starts a shutdown sequence. If EN_T is high, toggling the external enables of the regulators has no effect on the chip. The regulators can also be programmed through I2C to turn on and off. By default, I2C enables for the regulators turned ON. The regulators are on following the pattern below: Regulators on = (I2C enable) AND (External pin enable OR EN_T high). NOTE The EN_T power-up sequencing may also be employed immediately after VIN is applied to the device. However, VIN must be stable for approximately 8 ms minimum before EN_T be asserted high to ensure internal bias, reference, and the Flexible POR timing are stabilized. This initial EN_T delay is necessary only upon first time device power on for power sequencing function to operate properly. If the device is powered, the EN_T logic must be stable for 12 ms minimum before switching state. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 19 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com Feature Description (continued) 2 I C Regulator ON Ext_Enable Pins 0 1 Start Programmed Timing Sequence EN_T Figure 32. Power Rail Enable Logic EN_T t1 Vout Buck1 t2 Vout Buck2 t3 Vout LDO1 t4 Vout LDO2 Figure 33. LP3907-Q1 Default Power-Up Sequence Table 5. Power-On Timing Specification DESCRIPTION MIN NOM TYP UNIT t1 Programmable Delay from EN_T assertion to VCC_Buck1 On 1.5 ms t2 Programmable Delay from EN_T assertion to VCC_Buck2 On 2 ms t3 Programmable Delay from EN_T assertion to VCC_LDO1 On 3 ms t4 Programmable Delay from EN_T assertion to VCC_LDO2 On 6 ms EN_T Vout Buck1 t1 Vout Buck2 t2 Vout LDO1 t3 Vout LDO2 t4 Figure 34. LP3907-Q1 Default Power-Off Sequence 20 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 Table 6. Power-Off Timing Specification DESCRIPTION MIN NOM MAX UNIT t1 Programmable Delay from EN_T deassertion to VCC_Buck1 Off 1.5 ms t2 Programmable Delay from EN_T deassertion to VCC_Buck2 Off 2 ms t3 Programmable Delay from EN_T deassertion to VCC_LDO1 Off 3 ms t4 Programmable Delay from EN_T deassertion to VCC_LDO2 Off 6 ms 8.3.3 Flexible Power-On Reset (Power Good with Delay) The LP3907-Q1 is equipped with an internal Power-On-Reset (POR) circuit which monitors the output voltage levels on Bucks 1 and 2. The nPOR is an open drain logic output which is logic LOW when either of the buck outputs are below 91% of the rising value , or when one or both outputs fall below 82% of the desired value. The time delay between output voltage level and nPOR is enabled is (50 µs, 50 ms, 100 ms, 200 ms) 50 ms by default. The system designer can choose the external pull-up resistor (that is, 100 kΩ) for the nPOR pin. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 21 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com t2 t1 Case1 EN1 EN2 RDY1 RDY2 0V Counter delay nPOR t2 t1 Case2 EN1 EN2 RDY1 0V RDY2 Counter delay nPOR t2 t1 Case3 EN1 EN2 RDY1 RDY2 Counter delay nPOR Figure 35. nPOR with Counter Delay Figure 35 shows the simplest application of the Power On Reset, where both switcher enables are tied together. In Case 1, EN1 causes nPOR to transition LOW and triggers the nPOR delay counter. If the power supply for Buck2 does not come on within that period, nPOR stays LOW, indicating a power fail mode. Case 2 indicates the vice versa scenario if Buck1 supply did not come on. In both cases the nPOR remains LOW. Case 3 shows a typical application of the Power On Reset, where both switcher enables are tied together. Even if RDY1 ramps up slightly faster than RDY2 (or vice versa), then nPOR signal triggers a programmable delay before going HIGH, as explained below. 22 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 t0 t1 t2 t3 t4 EN1 RDY1 Counter delay Counter delay nPOR EN2 RDY2 Figure 36. Faults Occurring in Counter Delay After Start-Up Figure 36 details the Power good with delay with respect to the enable signals EN1, and EN2. The RDY1, RDY2 are internal signals derived from the output of two comparators. Each comparator has been trimmed as follows: COMPARATOR LEVEL BUCK SUPPLY LEVEL HIGH Greater than 94% LOW Less than 85% The circuits for EN1 and RDY1 is symmetrical to EN2 and RDY2, so each reference to EN1 and RDY1 also works for EN2 and RDY2 and vice versa. If EN1 and RDY1 signals are High at time t1, then the RDY1 signal rising edge triggers the programmable delay counter (50 μs, 50 ms, 100 ms, 200 ms). This delay forces nPOR LOW between time interval t1 and t2. nPOR is then pulled high after the programmable delay is completed. Now if EN2 and RDY2 are initiated during this interval the nPOR signal ignores this event. If either RDY1or RDY2 were to go LOW at t3 then the programmable delay is triggered again. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 23 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com t0 t1 t2 t3 t4 EN1 RDY1 Counter delay nPOR Case 1: EN2 RDY2 Mask Time Mask Window Counter delay nPOR Case 2: EN2 RDY2 0V Mask Time nPOR Mask Window Counter delay Figure 37. nPOR Mask Window If the EN1 and RDY1 are initiated in normal operation, then nPOR is asserted and deasserted as explained in Figure 37. Case 1 shows the case where EN2 and RDY2 are initiated after triggered programmable delay. To prevent the nPOR being asserted again, a masked window (5 ms) counter delay is triggered off the EN2 rising edge. nPOR is still held HIGH for the duration of the mask, whereupon the nPOR status afterwards depends on the status of both RDY1 and RDY2 lines. Case 2 shows the case where EN2 is initiated after the RDY1 triggered programmable delay, but RDY2 never goes HIGH (Buck2 never turns on). Normal operation operation of nPOR occurs wilth respect to EN1 and RDY1, and the nPOR signal is held HIGH for the duration of the mask window. We see that nPOR goes LOW after the masking window has timed out because it is now dependent on RDY1 and RDY2, where RDY2 is LOW. 24 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 Delay Mask Counter EN1 RDY1 EN2 RDY2 S Q R Q Delay nPOR POR Delay Mask Counter Figure 38. Design Implementation of the Flexible Power-On Reset An internal Power-on reset of the IC is used with EN1, and EN2 to produce a reset signal (LOW) to the delay timer nPOR. EN1 and RDY1 or EN2 and RDY2 are used to generate the set signal (HIGH) to the delay timer. S=R=1 never occurs. The mask timers are triggered off EN1 and EN2 which are gated with RDY1, and RDY2 to generate outputs to the final AND gate to generate the nPOR. 8.3.4 Undervoltage Lockout The LP3907-Q1 features an undervoltage lockout circuit. The function of this circuit is to continuously monitor the raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this supply voltage is less than 2.8 VDC. The circuit incorporates a bandgap based circuit that establishes the reference used to determine the 2.8 VDC trip point for a VIN OK – Not OK detector. This VIN OK signal is then used to gate the enable signals to the four regulators of the device. When VINLDO12 is greater than 2.8 VDC the four enables control the four regulators, when VINLDO12 is less than 2.8 VDC the four regulators are disabled by the VIN detector being in the “Not OK” state. The circuit has built-in hysteresis to prevent chattering occurring. 8.4 Device Functional Modes 8.4.1 Shutdown Mode During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The NFET switch is on in shutdown to discharge the output. When the converter is enabled, soft start is activated. It is recommended to disable the converter during the system power up and undervoltage conditions when the supply is less than 2.8 V. 8.5 Programming 8.5.1 I2C-Compatible Serial Interface 8.5.1.1 I2C Signals The LP3907-Q1features an I2C-compatible serial interface, using two dedicated pins: SCL and SDA for I2C clock and data respectively. Both signals need a pull-up resistor according to the I2C specification. The LP3907-Q1 interface is an I2C slave that is clocked by the incoming SCL clock. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 25 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com Programming (continued) Signal timing specifications are according to the I2C bus specification. The maximum bit rate is 400kbit/s. See I2C specification from NXP Semiconductors for further details. 8.5.1.2 I2C Data Validity The data on the SDA line must be stable during the HIGH period of the clock signal (SCL); for example, the state of the data line can only be changed when CLK is LOW. 2 I C_SCL 2 I C_SDA data change allowed data valid data change allowed data change allowed data valid Figure 39. I2C Signals: Data Validity 8.5.1.3 I2C Start and Stop Conditions START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as the SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while the SCL is HIGH. The 2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. 2 I C_SDA 2 I C_SCL S START condition P STOP condition Figure 40. Start and Stop Conditions 8.5.1.4 Transferring Data Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying acknowledgment. A receiver which has been addressed must generate an acknowledgment (“ACK”) after each byte has been received. After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). NOTE Please note that according to industry I2C standards for 7-bit addresses, the MSB of an 8bit address is removed, and communication actually starts with the 7th most significant bit. For the eighth bit (LSB), a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register. The LP3907-Q1 has factory-programmed I2C addresses. The WQFN chip has a chip address of 60'h, while the DSBGA chip has a chip address of 61'h. 26 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 Programming (continued) LSB MSB ADR6 bit7 ADR5 bit6 ADR4 bit5 ADR3 bit4 ADR2 bit3 ADR1 bit2 ADR0 bit1 1 1 0 0 0 0 0 R/W bit0 I2C SLAVE address (chip address) Figure 41. I2C Chip Address (see note above) start msb Chip Address lsb w ack ack from slave ack from slave ack from slave msb Register Add lsb ack msb DATA lsb ack stop ack stop SCL 1 2 3 4 5 6 7 8 9 1 2 3 ... SDA start id = K¶60 addr = K¶02 w ack DGGUHVVK¶$$GDWD ack w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled down by either master or slave) rs = repeated start id = LP3907-Q1 WQFN chip address: 0x60; DSBGA chip address: 0x61 Figure 42. I2C Write Cycle When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform. ack from slave start msb Chip Address lsb w ack ack from slave repeated start msb Register Add lsb ack rs SCL ack from slave msb Chip Address lsb r ack id = K¶60 r ack data from slave msb DATA ack from master lsb ack stop . SDA start id = K¶60 w ack register addr = K¶10 ack rs GDWDDGGUK¶6A ack stop Figure 43. I2C Read Cycle 8.5.2 Factory Programmable Options Table 7 shows options EPROM programmed during final test of the LP3907-Q1. The system designer that needs specific options is advised to contact the TI sales office. Table 7. Factory-Programmable Options FACTORY PROGRAMMABLE OPTIONS Enable delay for power on CURRENT VALUE code 010 (see Control 1 Register (SCR1) 0x07) SW1 ramp speed 8 mV/µs SW2 ramp speed 8 mV/µs The I2C Chip ID address is offered as a metal mask option. The current address for the WQFN chip equals 0x60, while the address for the DSBGA chip is 0x61. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 27 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com 8.6 Register Maps 8.6.1 LP3907-Q1 Control Registers REGISTER ADDRESS REGISTER NAME READ/WRITE REGISTER DESCRIPTION 0x02 ICRA R Interrupt Status Register A 0x07 SCR1 R/W System Control 1 Register 0x10 BKLDOEN R/W Buck and LDO Output Voltage Enable Register 0x11 BKLDOSR R Buck and LDO Output Voltage Status Register 0x20 VCCR R/W Voltage Change Control Register 1 0x23 B1TV1 R/W Buck1 Target Voltage 1 Register 0x24 B1TV2 R/W Buck1 Target Voltage 2 Register 0x25 B1RC R/W Buck1 Ramp Control 0x29 B2TV1 R/W Buck2 Target Voltage 1 Register 0x2A B2TV2 R/W Buck2 Target Voltage 2 Register 0x2B B2RC R/W Buck2 Ramp Control 0x38 BFCR R/W Buck Function Register 0x39 LDO1VCR R/W LDO1 Voltage Control Registers 0x3A LDO2VCR R/W LDO2 Voltage Control Registers 8.6.1.1 Interrupt Status Register (ISRA) 0x02 This register informs the System Engineer of the temperature status of the chip. D7-D2 D1 D0 Name — Temp 125°C — Access — R — Data Reserved Status bit for thermal warning PMIC T>125°C 0 – PMIC Temp. < 125°C 1 – PMIC Temp. > 125°C Reserved Reset 0 0 0 8.6.1.2 Control 1 Register (SCR1) 0x07 This register allows the user to select the preset delay sequence for power-on timing, to switch between PFM and PWM mode for the bucks, and also to select between an internal and external clock for the bucks. D7 D6-D4 D3 D2 D1 D0 Name — EN_DLY — FPWM2 FPWM1 ECEN Access — R/W — R/W R/W R/W Data Reserved Selects the preset delay sequence from EN_T assertion (shown below) Reserved Buck2 PWM /PFM Mode select 0 – Auto Switch PFM PWM operation 1 – PWM Mode Only Buck 1 PWM /PFM Mode select 0 – Auto Switch PFM PWM operation 1 – PWM Mode Only Reserved Reset 0 Factory-Programmed Default 1 Factory-Programmed Default Factory-Programmed Default 0 28 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 8.6.1.3 EN_DLY Preset Delay Sequence After EN_T Assertion DELAY (ms) EN_DLY<2:0> BUCK1 BUCK2 LDO1 LDO2 000 1 1 1 1 001 1 1.5 2 2 010 1.5 2 3 6 011 1.5 2 1 1 100 1.5 2 3 6 101 1.5 1.5 2 2 110 3 2 1 1.5 111 2 3 6 11 8.6.1.4 Buck and LDO Output Voltage Enable Register (BKLDOEN) – 0x10 This register controls the enables for the Bucks and LDOs. D7 D6 D5 D4 D3 D2 D1 D0 Name — LDO2EN — LDO1EN — BK2EN — BK1EN Access — R/W — R/W — R/W — R/W Data Reserved 0 – Disable 1 – Enable Reserved 0 – Disable 1 – Enable Reserved 0 – Disable 1 – Enable Reserved 0 – Disable 1 – Enable Reset 0 1 1 1 0 1 0 1 8.6.1.5 Buck and LDO Status Register (BKLDOSR) – 0x11 This register monitors whether the Bucks and LDOs meet the voltage output specifications. D7 D6 D5 D4 D3 D2 D1 D0 Name BKS_OK LDOS_OK LDO2_OK LDO1_OK — BK2_OK — BK1_OK Access R R R R — R — R Data 0 – Buck 1-2 Not Valid 1 – Bucks Valid 0 – LDO 1-2 Not Valid 1 – LDOs Valid 0 – LDO2 Not Valid 1 – LDO2 Valid 0 – LDO1 Not Valid 1 – LDO1 Valid Reserve d 0 – Buck2 Not Valid 1 – Buck2 Valid Reserve d 0 – Buck1 Not Valid 1 – Buck1 Valid Reset 0 0 0 0 0 0 0 0 8.6.1.6 Buck Voltage Change Control Register 1 (VCCR) – 0x20 This register selects and controls the output target voltages for the buck regulators. D7-6 D5 D4 D3-2 D1 D0 Name — B2VS B2GO — B1VS B1GO Access — R/W R/W — R/W R/W Data Reserved Buck2 Target Voltage Select 0 – B2VT1 1 – B2VT2 Buck2 Voltage Ramp CTRL 0 – Hold 1 – Ramp to B2VS selection Reserved Buck1 Target Voltage Select 0 – B1VT1 1 – B1VT2 Buck1 Voltage Ramp CTRL 0 – Hold 1 – Ramp to B1VS selection Reset 00 0 0 00 0 0 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 29 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com 8.6.1.7 Buck1 Target Voltage 1 Register (B1TV1) – 0x23 This register allows the user to program the output target voltage of Buck1. D7-D5 D4-D0 Name — BK1_VOUT1 Access — R/W Data Reserved Buck1 Output Voltage (V) 5’h00 Ext Ctrl 5’h01 0.80 5’h02 0.85 5’h03 0.90 5’h04 0.95 5’h05 1.00 5’h06 1.05 5’h07 1.10 5’h08 1.15 5’h09 1.20 5’h0A 1.25 5’h0B 1.30 5’h0C 1.35 5’h0D 1.40 5’h0E 1.45 5’h0F 1.50 5’h10 1.55 5’h11 1.60 5’h12 1.65 5’h13 1.70 5’h14 1.75 5’h15 1.80 5’h16 1.85 5’h17 1.90 5’h18 1.95 5’h19 2.00 5’h1A–5’h1F Reset 30 000 2.00 Factory-Programmed Default Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 8.6.1.8 Buck1 Target Voltage 2 Register (B1TV2) – 0x24 This register allows the user to program the output target voltage of Buck1. D7-D5 D4-D0 Name — BK1_VOUT2 Access — R/W Data Reserved Buck1 Output Voltage (V) 5’h00 Ext Ctrl 5’h01 0.80 5’h02 0.85 5’h03 0.90 5’h04 0.95 5’h05 1.00 5’h06 1.05 5’h07 1.10 5’h08 1.15 5’h09 1.20 5’h0A 1.25 5’h0B 1.30 5’h0C 1.35 5’h0D 1.40 5’h0E 1.45 5’h0F 1.50 5’h10 1.55 5’h11 1.60 5’h12 1.65 5’h13 1.70 5’h14 1.75 5’h15 1.80 5’h16 1.85 5’h17 1.90 5’h18 1.95 5’h19 2.00 5’h1A–5’h1F Reset (1) 000 (1) 2.00 Factory-Programmed Default If using Ext Ctrl, contact TI Sales for support. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 31 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com 8.6.1.9 Buck1 Ramp Control Register (B1RC) - 0x25 This register allows the user to program the rate of change between the target voltages of Buck1. D7 D6-D4 D3-D0 Name ---- ---- B1RS Access ---- ---- R/W Reserved Reserved Data Data Code Ramp Rate mV/us 4h'0 Instant 4h'1 1 4h'2 2 4h'3 3 4h'4 4 4h'5 5 4h'6 6 4h'7 7 4h'8 8 4h'9 9 4h'A 10 4h'B - 4h'F Reset 32 0 010 Submit Documentation Feedback 10 1000 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 8.6.1.10 Buck2 Target Voltage 1 Register (B2TV1) – 0x29 This register allows the user to program the output target voltage of Buck2. D7-D5 D4-D0 Name — BK2_VOUT1 Access — R/W Data Reserved Buck2 Output Voltage (V) 5’h00 Ext Ctrl 5’h01 1.0 5’h02 1.1 5’h03 1.2 5’h04 1.3 5’h05 1.4 5’h06 1.5 5’h07 1.6 5’h08 1.7 5’h09 1.8 5’h0A 1.9 5’h0B 2.0 5’h0C 2.1 5’h0D 2.2 5’h0E 2.4 5’h0F 2.5 5’h10 2.6 5’h11 2.7 5’h12 2.8 5’h13 2.9 5’h14 3.0 5’h15 3.1 5’h16 3.2 5’h17 3.3 5’h18 3.4 5’h19 3.5 5’h1A–5’h1F Reset 000 3.5 Factory-Programmed Default Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 33 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com 8.6.1.11 Buck2 Target Voltage 2 Register (B2TV2) – 0x2A This register allows the user to program the output target voltage of Buck2. D7-5 D4-0 Name — BK2_VOUT2 Access — R/W Data Reserved Buck2 Output Voltage (V) 5’h00 Ext Ctrl 5’h01 1.0 5’h02 1.1 5’h03 1.2 5’h04 1.3 5’h05 1.4 5’h06 1.5 5’h07 1.6 5’h08 1.7 5’h09 1.8 5’h0A 1.9 5’h0B 2.0 5’h0C 2.1 5’h0D 2.2 5’h0E 2.4 5’h0F 2.5 5’h10 2.6 5’h11 2.7 5’h12 2.8 5’h13 2.9 5’h14 3.0 5’h15 3.1 5’h16 3.2 5’h17 3.3 5’h18 3.4 5’h19 3.5 5’h1A–5’h1F Reset (1) 34 000 (1) 3.5 Factory-Programmed Default If using Ext Ctrl, contact TI Sales for support. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 8.6.1.12 Buck2 Ramp Control Register (B2RC) - 0x2B This register allows the user to program the rate of change between the target voltages of Buck2. D7 D6-D4 D3-D0 Name ---- ---- B2RS Access ---- ---- R/W Reserved Reserved Data Data Code Ramp Rate mV/us 4h'0 Instant 4h'1 1 4h'2 2 4h'3 3 4h'4 4 4h'5 5 4h'6 6 4h'7 7 4h'8 8 4h'9 9 4h'A 10 4h'B - 4h'F Reset 0 10 010 1000 8.6.1.13 Buck Function Register (BFCR) – 0x38 Clock Frequency This register allows the Buck switcher clock frequency to be spread across a wider range, allowing for less Electro-magnetic Interference (EMI). The spread spectrum modulation frequency refers to the rate at which the frequency ramps up and down, centered at 2 MHz. Spread Spectrum frequency Peak frequency deviation 2 kHz triangle wave 10 kHz triangle wave 2 MHz Time Figure 44. Spread Spectrum Modulation Frequency This register also allows dynamic scaling of the nPOR Delay Timing. The LP3907-Q1 is equipped with an internal Power-On-Reset (POR) circuit which monitors the output voltage levels on the buck regulators, allowing the user to more actively monitor the power status of the chip. The undervoltage lockout (UVLO) feature continuously monitor the raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this supply voltage is less than 2.8 VDC. This prevents the user from damaging the power source (such as battery), but can be disabled if the user wishes. Note that if the supply to VDD_M is close to 2.8 V with a heavy load current on the regulators, the chip is in danger of powering down due to UVLO. If the user wishes to keep the chip active under those conditions, enable the “Bypass UVLO” feature. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 35 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 D7-D5 Name Access www.ti.com D4 D3-D2 D1 D0 — BP_UVLO TPOR BK_SLOMOD BK_SSEN — R/W R/w R/W R/W Bypass UVLO monitoring 0 - Allow UVLO 1 - Disable UVLO nPOR Delay Timing 00 - 50 µs 01 - 50 ms 10 - 100 ms 11 - 200 ms Buck Spread Spectrum Modulation 0 – 10 kHz triangular wave 1 – 2 kHz triangular wave Spread Spectrum Function Output 0 – Disabled 1 – Enabled Data Reserved Reset 000 Factory-Programmed Default 01 1 0 8.6.1.14 LDO1 Control Register (LDO1VCR) – 0x39 This register allows the user to program the output target voltage of LDO 1. Name Access Data D7-D5 D4-D0 — LDO1_OUT — R/W Reserved LDO1 Output voltage (V) 5’h00 1.0 5’h01 1.1 5’h02 1.2 5’h03 1.3 5’h04 1.4 5’h05 1.5 5’h06 1.6 5’h07 1.7 5’h08 1.8 5’h09 1.9 5’h0A 2.0 5’h0B 2.1 5’h0C 2.2 5’h0D 2.3 5’h0E 2.4 5’h0F 2.5 5’h10 2.6 5’h11 2.7 5’h12 2.8 5’h13 2.9 5’h14 3.0 5’h15 3.1 5’h16 3.2 5’h17 3.3 5’h18 3.4 5’h19 3.5 5’h1A–5’h1F Reset 36 000 3.5 Factory-Programmed Default Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 8.6.1.15 LDO2 Control Register (LDO2VCR) – 0x3A This register allows the user to program the output target voltage of LDO 2. D7-D5 D4-D0 Name — LDO2_OUT Access — R/W Data Reserved LDO2 Output voltage (V) 5’h00 1.0 5’h01 1.1 5’h02 1.2 5’h03 1.3 5’h04 1.4 5’h05 1.5 5’h06 1.6 5’h07 1.7 5’h08 1.8 5’h09 1.9 5’h0A 2.0 5’h0B 2.1 5’h0C 2.2 5’h0D 2.3 5’h0E 2.4 5’h0F 2.5 5’h10 2.6 5’h11 2.7 5’h12 2.8 5’h13 2.9 5’h14 3.0 5’h15 3.1 5’h16 3.2 5’h17 3.3 5’h18 3.4 5’h19 3.5 5’h1A–5’h1F Reset 000 3.5 Factory-Programmed Default Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 37 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LP3907-Q1 provides three control methods to turn ON/OFF four power rails: 1. EN_T Control: Provides pre-defined power up/down sequence. (Note: VIN/Battery voltage must be settled approximately 8 ms, minimum, before EN_T be asserted high). 2. Individual GPIO/EN pin control: four EN pins provide max control flexibility without I2C. 3. I2C control: besides simple ON/OFF control, also provides access to all the user programmable registers. Please see Register Maps section for details. 9.2 Typical Application VINLDO12 EN_T VDD ENLDO1 1 PF 100k ENLDO2 nPOR ENSW1 VIN1 10 PF ENSW2 2.2 PH LDO1 SW1 0.47 PF 10 PF FB1 VINLDO1 GND_SW1 LP3907-Q1 1 PF VINLDO2 VIN2 1 PF 10 PF LDO2 2.2 PH 0.47 PF SW2 SDA 10 PF FB2 SCL GND_SW2 GND_L GND_C AVDD DAP 1 PF Figure 45. LP3907-Q1 Typical Application 9.2.1 Design Requirements Ten ceramic capacitors and two inductors required for this application. These three external components need to be selected very carefully for property operation. Please read Detailed Design Procedure section. 38 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 Typical Application (continued) 9.2.2 Detailed Design Procedure 9.2.2.1 Component Selection 9.2.2.1.1 Inductors for SW1 And SW2 There are two main considerations when choosing an inductor; the inductor should not saturate and the inductor current ripple is small enough to achieve the desired output voltage ripple. Care should be taken when reviewing the different saturation current ratings that are specified by different manufacturers. Saturation current ratings are typically specified at 25ºC, so ratings at maximum ambient temperature of the application should be requested from the manufacturer. There are two methods to choose the inductor saturation current rating: 9.2.2.1.1.1 Method 1: The saturation current is greater than the sum of the maximum load current and the worst case average-to-peak inductor current. This can be written as follows: Isat > Ioutmax + Iripple where Iripple = §1· ©f¹ x §VIN - VOUT· x § VOUT· © 2L ¹ © VIN ¹ where • • • • • • IRIPPLE = Maximum load current IOUTMAX = Average to peak inductor current VIN = Maximum input voltage to the buck L = Min inductor value including worse case tolerances (30% drop can be considered for method 1) f = Minimum switching frequency (1.6 MHz) VOUT = Buck output voltage (6) 9.2.2.1.1.2 Method 2: A more conservative and recommended approach is to choose an inductor that has saturation current rating greater than the maximum current limit of 1250 mA for Buck1 and 1750 mA for Buck2. Given a peak-to-peak current ripple (IPP) the inductor needs to be at least Lt §VIN - VOUT· x § VOUT· x § 1 · © IPP ¹ © VIN ¹ © f ¹ (7) Table 8. Suggested Inductor Values INDUCTOR VALUE (µH) DESCRIPTION NOTES LSW1,2 2.2 SW1,2 inductor DCR. 70 mΩ 9.2.2.1.2 External Capacitors The regulators on the LP3907-Q1 require external capacitors for regulator stability. These are specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. 9.2.2.2 LDO Capacitor Selection 9.2.2.2.1 Input Capacitor An input capacitor is required for stability. It is recommended that a 1-μF capacitor be connected between the LDO input pin and ground (this capacitance value may be increased without limit). Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 39 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: Tantalum capacitors can suffer catastrophic failures due to surge currents when connected to a low impedance source of power (such as a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the equivalent series resistance (ESR) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance remains approximately 1 μF over the entire operating temperature range. 9.2.2.2.2 Output Capacitor The LDOs on the LP3907-Q1 are designed specifically to work with very small ceramic output capacitors. A 0.47µF ceramic capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500 mΩ, is suitable in the application circuit. It is also possible to use tantalum or film capacitors at the device output, COUT (or VOUT), but these are not as attractive for reasons of size and cost. The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR value that is within the range 5 mΩ to 500 mΩ for stability. 9.2.2.2.3 Capacitor Characteristics The LDOs are designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability for the LDOs. For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly, depending on the operating conditions and capacitor type. CAP VALUE (% of NOMINAL 1 PF) In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging. The capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer performance figures in general. As an example, Figure 46 is a typical graph comparing different capacitor case sizes. 0603, 10V, X5R 100% 80% 60% 0402, 6.3V, X5R 40% 20% 0 1.0 2.0 3.0 4.0 5.0 DC BIAS (V) Figure 46. Graph Showing Typical Variation in Capacitance vs. DC Bias 40 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 As shown in the graph, increasing the DC Bias condition can result in the capacitance value that falls below the minimum value given in the recommended capacitor specifications table. Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers' specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (for example, 0402) may not be suitable in the actual application. The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of −55°C to 125°C, only varies the capacitance to within ±15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of −55°C to 85°C. Many large value ceramic capacitors, larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore, X7R is recommended over Z5U and Y5V in applications where the ambient temperature changes significantly above or below 25°C. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 0.47-µF to 4.7-µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum increases about 2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed. 9.2.2.2.4 Input Capacitor Selection for SW1 And SW2 A ceramic input capacitor of 10 µF, 6.3 V is sufficient for the magnetic DC-DC converters. Place the input capacitor as close as possible to the input of the device. A large value may be used for improved input voltage filtering. The recommended capacitor types are X7R or X5R. Y5V type capacitors should not be used. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The input filter capacitor supplies current to the PFET switch of the DC-DC converter in the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor’s low ESR (Equivalent Series Resistance) provides the best noise filtering of the input voltage spikes due to fast current transients. A capacitor with sufficient ripple current rating should be selected. The Input current ripple can be calculated as: Irms = Ioutmax VOUT VIN § 1 + r2 · © 12 ¹ where r= (Vin ± Vout) x Vout L x f x Ioutmax x Vin (8) The worse case is when VIN = 2 VOUT. 9.2.2.2.5 Output Capacitor Selection for SW1, SW2 A 10-μF, 6.3-V ceramic capacitor should be used on the output of the SW1 and SW2 magnetic DC-DC converters. The output capacitor needs to be mounted as close as possible to the output of the device. A large value may be used for improved input voltage filtering. The recommended capacitor types are X7R or X5R. Y5V type capacitors should not be used. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and DC bias curves should be requested from them and analyzed as part of the capacitor selection process. The output filter capacitor of the magnetic DC-DC converter smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESD to perform these functions. The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its ESR and can be calculated as follows: Vpp-c = Iripple 4xfxC (9) Voltage peak-to-peak ripple due to ESR can be expressed as follows: VPP–ESR = 2 × IRIPPLE × RESR (10) Because the VPP-C and VPP-ESR are out of phase, the rms value can be used to get an approximate value of the peak-to-peak ripple: Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 41 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 Vpp-rms = www.ti.com Vpp-c2 + Vpp-esr2 (11) Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the output capacitor (RESR). The RESR is frequency dependent as well as temperature dependent. The RESR should be calculated with the applicable switching frequency and ambient temperature. Table 9. Suggested Capacitor Values CAPACITOR MIN VALUE (µF) DESCRIPTION RECOMMENDED TYPE CLDO1 0.47 LDO1 output capacitor Ceramic, 6.3 V, X5R CLDO2 0.47 LDO2 output capacitor Ceramic, 6.3 V, X5R CSW1 10 SW1 output capacitor Ceramic, 6.3 V, X5R CSW2 10 SW2 output capacitor Ceramic, 6.3 V, X5R 9.2.2.2.6 I2C Pull-Up Resistor Both SDA and SCL terminals need to have pull-up resistors connected to VINLDO12 or to the power supply of the I2C master. The values of the pull-up resistors (typical approximately 1.8 kΩ) are determined by the capacitance of the bus. Too large of a resistor combined with a given bus capacitance results in a rise time that would violate the max. rise time specification. A too-small resistor results in a contention with the pull-down transistor on either slave(s) or master. 9.2.2.3 Operation Without I2C Interface Operation of the LP3907-Q1 without the I2C interface is possible if the system can operate with default values for the LDO and Buck regulators (see Factory Programmable Options.) The I2C-less system must rely on the correct default output values of the LDO and Buck converters. 9.2.2.3.1 High VIN High-Load Operation Additional information is provided when the IC is operated at extremes of VIN and regulator loads. These are described in terms of the Junction temperature and, Buck output ripple management. 9.2.2.3.2 Junction Temperature The maximum junction temperature TJ-MAX-OP of 125°C of the IC package. Equation 12 through Equation 17 demonstrate junction temperature determination, ambient temperature TA-MAX, and total chip power must be controlled to keep TJ below this maximum: TJ-MAX-OP = TA-MAX + (RθJA) [°C/ Watt] × (PD-MAX) [Watts] (12) Total IC power dissipation PD-MAX is the sum of the individual power dissipation of the four regulators plus a minor amount for chip overhead. Chip overhead is Bias, TSD, and LDO analog. PD-MAX = PLDO1 + PLD02 + PBUCK1 + PBUCK2 + (0.0001A × VIN) [Watts]. (13) Power dissipation of LDO1: PLDO1 = (VINLDO1 – VOUTLDO1) × IOUTLDO1 [V × A] (14) Power dissipation of LDO2: PLDO2 = (VINLDO2 – VOUTLDO2) × IOUTLDO2 [V × A] (15) Power dissipation of Buck1: PBuck1 = PIN – POUT = VOUTBuck1 × IOUTBuck1 × (1 – η1) / η1 [V × A] where • η1 = efficiency of buck 1 (16) Power dissipation of Buck2: PBuck2 = PIN – POUT = VOUTBuck2 × IOUTBuck2 × (1 – η2) / η2 [V × A] where • 42 η2 = efficiency of Buck2 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 where • η is the efficiency for the specific condition taken from efficiency graphs. (17) 9.2.3 Application Curves 100 100 90 90 VIN= 4.5V VIN = 2.8V 70 EFFICIENCY (%) EFFICIENCY (%) 80 60 50 VIN = 3.6V 40 70 60 VIN = 5.5V 30 50 20 10 0.1 1 10 100 40 0.1 1000 OUTPUT CURRENT (mA) VOUT = 2 V VIN= 5.5V 80 1 10 100 1000 OUTPUT CURRENT (mA) VOUT = 2 V L= 2.2 µH Figure 47. Efficiency vs Output Current (Forced PWM Mode) L= 2.2 µH Figure 48. Efficiency vs Output Current (PWM-to-PFM Mode) 10 Power Supply Recommendations If the EN_T is used to power up the device instead individual ENs , then VIN must be stable for approximately 8 ms minimum before EN_T be asserted high to ensure internal bias, reference, and the Flexible POR timing are stabilized. This initial EN_T delay is necessary only upon first time device power on for power sequencing function to operate properly. 10.1 Analog Power Signal Routing All power inputs should be tied to the main VDD source (for example, battery), unless the user wishes to power it from another source. (that is, external LDO output). The analog VDD inputs power the internal bias and error amplifiers, so they should be tied to the main VDD. The analog VDD inputs must have an input voltage between 2.8 V and 5.5 V, as specified in the Recommended Operating Conditions (Bucks) table earlier in the datasheet. The other VINs (VINLDO1, VINLDO2) can have inputs lower than 2.8 V, as long as the input it higher than the programmed output (0.3 V). The analog and digital grounds should be tied together outside of the chip to reduce noise coupling. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 43 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com 11 Layout 11.1 DSBGA Layout Guidelines PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or instability. Good layout for the LP3907-Q1 device bucks can be implemented by following a few simple design rules below. Refer to Figure 49 for top-layer board Buck layout. 1. Place the LP3907 bucks, inductor, and filter capacitors close together and make the traces short. The traces between these components carry relatively high switching currents and act as antennas. Following this rule reduces radiated noise. Special care must be given to place the input filter capacitor very close to the VIN and GND pin. 2. Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle, current flows from the input filter capacitor through the LP3907-Q1 bucks and inductor to the output filter capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground through the LP3907-Q1 bucks by the inductor to the output filter capacitor and then back through ground forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two half-cycles and reduces radiated noise. 3. Connect the ground pins of the LP3907-Q1 bucks and filter capacitors together using generous componentside copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several vias. This reduces ground-plane noise by preventing the switching currents from circulating through the ground plane. It also reduces ground bounce at the LP3907-Q1 bucks by giving it a low-impedance ground connection. 4. Use wide traces between the power components and for power connections to the DC-DC converter circuit. This reduces voltage errors caused by resistive losses across the traces. 5. Route noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power components. The voltage feedback trace must remain close to the LP3907-Q1 buck's circuit and should be direct but should be routed opposite to noisy components. This reduces EMI radiated onto the DC-DC converter’s own voltage feedback trace. A good approach is to route the feedback trace on another layer and to have a ground plane between the top layer and layer on which the feedback trace is routed. In the same manner for the adjustable part it is desired to have the feedback dividers on the bottom layer. 6. Place noise sensitive circuitry, such as radio IF blocks, away from the DC-DC converter, CMOS digital blocks and other noisy circuitry. Interference with noise-sensitive circuitry in the system can be reduced through distance. For more detailed layout specifications and information, please refer to Application Report AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009). 44 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 11.2 Layout Example Figure 49. LP3907-Q1 DSBGA Layout Example 11.3 Thermal Considerations of WQFN Package The LP3907-Q1 is a monolithic device with integrated power FETs. For that reason, it is important to pay special attention to the thermal impedance of the WQFN package and to the PCB layout rules in order to maximize power dissipation of the WQFN package. The WQFN package is designed for enhanced thermal performance and features an exposed die attach pad at the bottom center of the package that creates a direct path to the PCB for maximum power dissipation. Compared to the traditional leaded packages where the die attach pad is embedded inside the molding compound, the WQFN reduces one layer in the thermal path. The thermal advantage of the WQFN package is fully realized only when the exposed die attach pad is soldered down to a thermal land on the PCB board with thermal vias planted underneath the thermal land. Based on thermal analysis of the WQFN package, the junction-to-ambient thermal resistance (RθJA) can be improved by a factor of two when the die attach pad of the WQFN package is soldered directly onto the PCB with thermal land and thermal vias, as opposed to an alternative with no direct soldering to a thermal land. Typical pitch and outer diameter for thermal vias are 1.27 mm and 0.33 mm, respectively. Typical copper via barrel plating is 1 oz, although thicker copper may be used to further improve thermal performance. The LP3907-Q1 die attach pad is connected to the substrate of the IC, and therefore, the thermal land and vias on the PCB board need to be connected to ground (GND pin). For more information on board layout techniques, refer to Application Note AN–1187 Leadless Lead Frame Package (LLP) (SNOA401) on http://www.ti.com. This application note also discusses package handling, solder stencil, and the assembly process. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 45 LP3907-Q1 SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: Application Report AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009). Application Note AN–1187 Leadless Lead Frame Package (LLP) (SNOA401). 12.2 Trademarks All trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 46 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LP3907-Q1 PACKAGE OPTION ADDENDUM www.ti.com 5-May-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP3907QSQ-JJXP/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 07QJJXP LP3907QSQ-JXI7/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 07QJXI7 LP3907QSQ-JXIP/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 07QJXIP LP3907QSQX-JJXP/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 07QJJXP LP3907QSQX-JXI7/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 07QJXI7 LP3907QSQX-JXIP/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 07QJXIP LP3907QTL-VXSS/NOPB ACTIVE DSBGA YZR 25 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 V025 LP3907QTLX-VXSS/NOPB ACTIVE DSBGA YZR 25 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 V025 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 5-May-2015 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF LP3907-Q1 : • Catalog: LP3907 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP3907QSQ-JJXP/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP3907QSQ-JXI7/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP3907QSQ-JXIP/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP3907QSQX-JJXP/NOP B WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP3907QSQX-JXI7/NOPB WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP3907QSQX-JXIP/NOPB WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP3907QTL-VXSS/NOPB DSBGA YZR 25 250 178.0 8.4 2.69 2.69 0.76 4.0 8.0 Q1 YZR 25 3000 178.0 8.4 2.69 2.69 0.76 4.0 8.0 Q1 LP3907QTLX-VXSS/NOP B DSBGA Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3907QSQ-JJXP/NOPB WQFN RTW 24 1000 210.0 185.0 35.0 LP3907QSQ-JXI7/NOPB WQFN RTW 24 1000 210.0 185.0 35.0 LP3907QSQ-JXIP/NOPB WQFN RTW 24 1000 210.0 185.0 35.0 LP3907QSQX-JJXP/NOPB WQFN RTW 24 4500 367.0 367.0 35.0 LP3907QSQX-JXI7/NOPB WQFN RTW 24 4500 367.0 367.0 35.0 LP3907QSQX-JXIP/NOPB WQFN RTW 24 4500 367.0 367.0 35.0 LP3907QTL-VXSS/NOPB DSBGA YZR 25 250 210.0 185.0 35.0 LP3907QTLX-VXSS/NOPB DSBGA YZR 25 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA RTW0024A SQA24A (Rev B) www.ti.com MECHANICAL DATA YZR0025xxx 0.600±0.075 D E TLA25XXX (Rev D) D: Max = 2.521 mm, Min = 2.46 mm E: Max = 2.521 mm, Min = 2.46 mm 4215055/A NOTES: A. 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