32-bit automotive MCUs MAC57D5xx MCUs for Automotive and Industrial Instrument Clusters The MAC57D5xx family is the next-generation platform of instrument cluster devices specifically targeted to the cluster market using single and dual high-resolution displays. TARGET APPLICATIONS }} Instrument clusters }} Heads-up display }} Multifunction display Leveraging a highly successful MPC56xxS product family, we are introducing a multicore architecture powered by ARM® Cortex®-M (for real-time applications) and ARM Cortex-A processors (for applications and HMI), coupled with 2D graphics accelerators, a heads-up display (HUD) warping engine, dual TFT display drive, integrated stepper motor drivers and a powerful I/O processor that will offer leading-edge performance and scalability for cost-effective applications. This family supports up to two WVGA resolution displays, including one with in-line HUD hardware warping. Graphics content is generated using a powerful Vivante 2D graphics processing unit (GPU) supporting OpenVG1.1, and the 2D animation and composition engine (2D-ACE), which significantly reduces memory footprint for content creation. Embedded memories include up to 4 MB flash, 1 MB SRAM with error correcting codes (ECC) and up to 1.3 MB of graphics SRAM without ECC. Memory expansion is available through DDR2 and SDR DRAM interfaces while two flexible QuadSPI modules provide SDR and DDR serial flash expansion. In response to the growing desire for security and functional safety, the MAC57D5xx family integrates our latest SHE-compliant cryptographic services engine (CSE2) and delivers support for ISO26262 ASIL-B functional safety compliance. FEATURES Cortex-A5, 32-bit CPU (application processor) }} Floating point unit (FPU) supporting double-precision floating-point operations }} ARM NEON™ media processing engine }} Memory management unit }} Up to 320 MHz RSDS/RGB Power System Modules LVD/HVD Low Power Ctrl Reset Ctrl Debug INT Router SJTAG RTC w/calib Clock Monitor Cortex-M0+, 32-bit CPU (I/O processor) 64 KB TCM 16 KB D-Cache 2D-ACE 2D-ACE ARM® Cortex®-A5 (CSE2) FPU DAP TPIU Trace Buffer 16 KB I-Cache LDB PLLs MBIST }} Up to 160 MHz TCON1 TCON0 16MHz/128kHz IRC Temp Sensor ARM® Cortex®-M4 LVDS OpenLDI/LVDS RSDS 4-40MHz/32kHz X0SC SECURITY }} Single precision FPU GIC I/O Ctrl RGB Clocking 1.2 v Regulator NVIC 64:16 mux + HUD OpenVG1.1 Video Input NEON™ FPU ENET + AVB MLB50 32 KB I-Cache 32 KB D-Cache System Bus Fabric Memory Protection }} Intelligent stepper motor drive QuadSPI SDR SGM (I2S) SMD & SSD (6) Timer/PWM (8-ch.) DDR2 Timer/PWM (8-ch.) Timer/PWM (8-ch.) QuadSPI DRAM Controller 16/32 Bit AIPS- Lite 12-bit ADC (24) Watchdog (3) PIT (8CH) CRC STM (4CH) SEMA42 UART/LIN (3) I2C (2) DSPI (5) FlexCAN (3) }} System memory protection unit RLE Decoder Boot ROM 1.3 MB GRAM ( (FlexECC) OTP Memory Subsystem Port Splitter Pixel Converter 1 MB System SRAM (ECC) Alarm CMP (2) Flash BIU 4 MB FLASH (ECC) LCD }} Low-power mode peripheral management Timer/PWM (8-ch.) }} 64 KB tightly-coupled memory (TCM) MAC57D5xx BLOCK DIAGRAM 16ch DMA 16ch DMA Cortex-M4, 32-bit CPU (vehicle processor) ARM Cortex-M0+ Interrupt Router IOP 32 KB SRAM (ECC) }} 4 MB on-chip flash including small sectors for EEPROM }} 1 MB on-chip SRAM with ECC Peripherals Key Electrical Characteristics }} 1.3 MB on-chip graphics SRAM with FlexECC }} 6 stepper motor drivers with patented stall detection technology }} –40°C to +105°C (ambient) Expandable Memory Interfaces }} Sound generator module (SGM) with PWM and I2S outputs }} 2 x Dual QuadSPI serial flash controllers (including HyperFlash™ support) }} Supports SDR and DDR serial flash }} DRAM controller supporting SDR and DDR2 Graphics Features }} Vivante GC355 GPU supporting OpenVG™ 1.1 }} 2 x 2D-ACE display controllers supporting up to 2 x WVGA displays }} Digital video input Tools }} Rich set of communication peripherals, including Ethernet-AVB, MLB50, CANFD, LIN, SPI, I2C }} S32 Design Studio }} Up to 32 timer/PWM channels }} Multicore compiler: ARM, Green Hills }} Latest CSE2 security—Secure Boot, secure mileage and component protection }} Debugger: Green Hills Probe, Lauterbach, IAR™ }} 12-bit ADC and analog comparators MAC57D5xx FAMILY MATRIX Family Product Flash SRAM SAC57D54H 4 MB 1.3 MB (non ECC)/ 2 x 512 kbit (w/ECC) SAC57D53H 3 MB }} RLE decoder for memory-memory decompression Safety and Security }} 516 MAPBGA, 208 LQFP }} Autonomous RTC (self calibrating) }} In-line hardware HUD warping engine }} Digital RGB, TCON0 (RSDS), TCON1 and OpenLDI/LVDS output options Package Options SAC57D52L 2 MB 1.3 MB (non ECC)/ 2 x 512 kbit (w/ECC) 1.3 MB (non ECC)/ 1 x 512 kbit (w/ECC) Package Options SDR DDR2 QUAD SPI GPU 208 LQFP 16-bit, 160 MHz None 516 MAPBGA 16-bit, 160 MHz 16- or 32-bit, 320 MHz 2 x Dual SDR/DDR QuadSPI, 100 MHz (200 MB/s) (OpenVG) 208 LQFP 16-bit, 160 MHz None 516 MAPBGA 16-bit, 160 MHz 16- or 32-bit, 320 MHz 2 x Dual SDR/DDR QuadSPI, 100 MHz (200 MB/s) (OpenVG) 208 LQFP 16-bit, 160 MHz None 2 x Dual SDR/DDR QuadSPI, 100 MHz (200 MB/s) **Not all feature differences shown in table above, refer to datasheet for specific feature details }} ISO 26262 ASIL-B compliant MCU www.nxp.com/MAC57D5xx NXP, the NXP logo, Freescale, the Energy Efficient Solutions logo and the Safe Assure logo are trademarks of NXP B.V. All other product or service names are the property of their respective owners. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. © 2014–2016 NXP B.V. Document Number: MAC57D5xxFS REV 2 GC355 GC355 GC355 (OpenVG)