SPICE Device Model SUM110N08-07L Vishay Siliconix N-Channel 75-V (D-S), 175°C MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70308 09-Jun-04 www.vishay.com 1 SPICE Device Model SUM110N08-07L Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Simulated Data Measured Data VGS(th) VDS = VGS, ID = 250 µA 2.1 ID(on) VDS ≥ 5 V, VGS = 10 V 865 VGS = 10 V, ID = 30 A 0.0056 VGS = 10 V, ID = 30 A, TJ = 125°C 0.0089 VGS = 10 V, ID = 30 A, TJ = 175°C 0.011 VGS = 4.5 V, ID = 20 A 0.0076 0.0075 IF = 110 A, VGS = 0 V 0.93 1 4700 4420 678 700 310 Unit Static Gate Threshold Voltage On-State Drain Current a Drain-Source On-State Resistancea Forward Voltage a rDS(on) VSD V A 0.0055 Ω V Dynamicb Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 330 Total Gate Chargec Qg 82 81 Gate-Source Chargec Qgs 20 20 20 c VGS = 0 V, VDS = 25 V, f = 1 MHz VDS = 30 V, VGS = 10 V, ID = 110 A Gate-Drain Charge Qgd 20 Turn-On Delay Timec td(on) 19 15 tr 12 20 Rise Timec Turn-Off Delay Timec td(off) Fall Timec tf Source-Drain Reverse Recovery Time trr VDD = 30 V, RL = 0.47 Ω ID ≅ 110 A, VGEN = 10 V, RG = 2.5 Ω IF = 110 A, di/dt = 100 A/µs 18 40 16 15 31 55 pF nC ns Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature. www.vishay.com 2 Document Number: 70308 09-Jun-04 SPICE Device Model SUM110N08-07L Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 70308 09-Jun-04 www.vishay.com 3