Freescale Semiconductor, Inc. MOTOROLA Order number: MC100ES8014 Rev 0, 05/2004 DATA SHEET SEMICONDUCTOR TECHNICAL DATA MC100ES8014 MC100ES8014 LVDS The MC100ES8014 is a HSTL differential clock fanout buffer. Designed for the most demanding clock distribution systems, the MC100ES8014 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are in high performance clock distribution in computing, networking and telecommunication systems. The MC100ES8014 is designed for low skew clock distribution systems and supports clock frequencies up to 400MHz. The device accepts two clock sources. The CLK0 input accepts HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input signal is distributed to 5 identical, differential HSTL compatible outputs. 1:5 DIFFERENTIAL HSTL CLOCK FANOUT DRIVER Features • • • • • • • • • DT SUFFIX 20 LEAD TSSOP PACKAGE CASE 948E 1:5 differential clock fanout buffer 50 ps maximum device skew SiGe Technology Supports DC to 400 MHz operation 1.5V HSTL compatible differential clock outputs PECL and HSTL compatible differential clock inputs 3.3V power supply for device core, 1.5V or 1.8V HSTL output supply Supports industrial temperature range Standard 20 lead TSSOP package VCCO 20 NC 19 VEE 18 CLK1 CLK1 17 16 EN 15 Device Package MC100ES8014DT TSSOP-20 MC100ES8014DTR2 TSSOP-20 CLK0 CLK0 CLK_SEL VCC 14 13 12 11 0 D 1 ORDERING INFORMATION Q Freescale Semiconductor, Inc... Product Low VoltagePreview 1:5 Differential LVDS Clock Buffer LowFanout Voltage 1:5 Differential 1 2 3 4 5 6 7 8 9 10 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Figure 1. 20-Lead Pinout (Top View) and Logic Diagram This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Motorola, Inc. 2004 IDT™ Low Voltage 1:5 Differential LVDS Clock Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc For More Information On This Product, 1 Go to: www.freescale.com MC100ES8014 MC100ES8014 Low Voltage 1:5 Differential LVDS Clock Fanout BufferSemiconductor, Freescale Inc. NETCOM MC100ES8014 Freescale Semiconductor, Inc... Table 1. Pin Description Pin Function CLK0, CLK0 HSTL Data Inputs CLK1, CLK1 PECL Data Inputs Q[0:4], Q[0:4] HSTL Data Outputs CLK_SEL LVCMOS Active Clock Select Input EN LVCMOS Sync Enable VCC Positive Supply of device core (3.3V) VCCO Positive power supply of the HSTL outputs. All VCCO pins must be connected to the positive power supply (1.5V or 1.8V) for correct DC and AC operation. VEE Negative Supply nc no connect Table 2. Function Table Control Default 0 1 CLK_SEL 0 CLK0, CLK0 (HSTL) is the active differential clock input CLK1, CLK1 (PECL) is the active differential clock input EN 0 Q[0:4], Q[0:4] are active. Deassertion of EN can be asynchronous to the reference clock without generation of output runt pulses. Q[0:4] = L, Q[0:4] = H (outputs disabled). Assertion of EN can be asynchronous to the reference clock without generation of output runt pulses. Table 3. General Specifications Characteristics Value Internal Input Pulldown Resistor TBD Internal Input Pullup Resistor TBD ESD Protection Human Body Model Machine Model TBD θJA Thermal Resistance (Junction to Ambient) 0 LFPM, 8 SOIC 500 LFPM, 8 SOIC TBD Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Table 4. Absolute Maximum Ratings1 Symbol Parameter Conditions Rating Unit 3.9 V VCC + 0.3 VEE – 0.3 V V 50 100 mA mA VSUPPLY Power Supply Voltage Difference between VCC & VEE VIN Input Voltage VCC – VEE ≤ 3.6V IOUT Output Current Continuous Surge TA Operating Temperature Range –40 to +85 °C TSTG Storage Temperature Range –65 to +150 °C 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. MOTOROLA IDT™ Low Voltage 1:5 Differential LVDS Clock Fanout Buffer 2 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 2 For More Information On This Product, TIMING SOLUTIONS MC100ES8014 MC100ES8014 Low Voltage 1:5 Differential LVDS Clock Fanout BufferSemiconductor, Freescale Inc. NETCOM MC100ES8014 Table 5. DC Characteristics (VCC = 3.3V±5%; TJ = 0°C to 110°C)1 Symbol Characteristic Min Typ Max Unit Condition HSTL differential input signals (CLK0, CLK0) VDIF Differential input voltage2 0.2 VX, IN Differential cross point voltage3 0.25 VIH Input high voltage VIL Input low voltage IIN Input current V 0.68 – 0.9 VCC – 1.3 VX + 0.1 V V VX – 0.1 V ±150 mA VIN = VX ± 0.1V Freescale Semiconductor, Inc... PECL differential input signals (CLK1, CLK1) VPP Differential input voltage4 0.15 1.0 V Differential Operation VCMR Differential cross point voltage5 1.0 VCC – 0.6 V Differential Operation VIH Input high voltage VCC – 1.165 VCC – 0.880 V VIL Input low voltage VCC – 1.810 VCC – 1.475 V IIN Input current ±150 mA 0.8 V VIN = VIH or VIN LVCMOS control inputs EN, CLK_SEL VIL Input low voltage VIH Input high voltage IIN Input current 2.0 V ±150 mA 0.9 V VIN = VIH or VIN HSTL clock outputs (Q[0:4], Q[0:4]) VX, OUT Output differential crosspoint VOH Output high voltage VOL Ouput low voltage 0.68 0.75 1 V 0.4 V Supply Current ICC Maximum Quiescent Supply Current without output termination current TBD TBD mA VCC pin (core) ICCO Maximum Quiescent Supply Current, outputs terminated 50Ω to VTT TBD TBD mA VCCO pin (outputs) 1. DC characteristics are design targets and pending characterization. 2. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. 3. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. 4. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 5. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. TIMING SOLUTIONS IDT™ Low Voltage 1:5 Differential LVDS Clock Fanout Buffer 3 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 3 For More Information On This Product, MOTOROLA MC100ES8014 MC100ES8014 Low Voltage 1:5 Differential LVDS Clock Fanout BufferSemiconductor, Freescale Inc. NETCOM MC100ES8014 Table 6. AC Characteristics (VCC = 3.3V±5%; TJ = 0°C to 110°C)1 2 Symbol Characteristic Min Typ Max Unit Condition HSTL/LVDS differential input signals (CLK0, CLK0) VDIF Differential input voltage (peak-to-peak)3 0.4 VX, IN Differential cross point voltage4 0.68 fCLK Input Frequency tPD Propagation Delay V 0.9 V TBD MHz Differential TBD ps Differential 0.2 1.0 V 1 VCC – 0.6 V 0 – 400 Freescale Semiconductor, Inc... PECL differential input signals (CLK1, CLK1) VPP Differential input voltage (peak-to-peak)5 VCMR Differential cross point voltage6 fCLK Input Frequency tPD Propagation Delay 0 – 400 MHz Differential TBD ps Differential 0.9 V HSTL clock outputs (Q[0:4], Q[0:4]) VX, OUT Output differential crosspoint VOH Output high voltage 0.68 0.75 1 VOL Ouput low voltage VO(P-P) Differential output voltage (peak-to-peak) tSK(O) Output-to-output skew tSK(PP) V 0.5 0.5 V V 50 ps Differential Output-to-output skew (part-to-part) TBD ps Differential tJIT(CC) Output cycle-to-cycle jitter TBD DCO Output duty cycle TBD TBD % DCfref = 50% tr / tf Output Rise/Fall Times 0.05 TBD ns 20% to 80% tPDL Output disable time7 2.5*T +tPD 3.5*T +tPD ns T = CLK period tPLD Output enable time8 3*T +tPD 4*T +tPD ns T = CLK period 1. 2. 3. 4. 5. 6. 7. 8. 50 AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50Ω to VTT. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VX (AC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (AC) range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF(AC) impacts the device propagation delay, device and part-to-part skew. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VCMR (AC) is the crosspoint of the differential PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew. Propagation delay EN deassertion to differential output disabled (differential low: true output low, complementary output high). Propagation delay EN assertion to output enabled (active). MOTOROLA IDT™ Low Voltage 1:5 Differential LVDS Clock Fanout Buffer 4 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 4 For More Information On This Product, TIMING SOLUTIONS MC100ES8014 MC100ES8014 Low Voltage 1:5 Differential LVDS Clock Fanout BufferSemiconductor, Freescale Inc. NETCOM MC100ES8014 CLKx CLKx 50% EN tPDL (EN to Qx[]) tPLD (EN to Qx[]) Qx[] Outputs disabled Qx[] Freescale Semiconductor, Inc... Figure 2. MC100ES8014 AC Test Reference Differential Pulse Generator Z = 50Ω ZO = 50Ω ZO = 50Ω RT = 50Ω DUT MC100ES8014 RT = 50Ω VTT=GND VTT=GND Figure 3. MC100ES8014 AC Test Reference CLK0,1 CLK0,1 VDIF=1.0V VX=0.75V CLK0,1 CLK0,1 Q[0–4] Q[0–4] Q[0–4] Q[0–4] VPP=0.8V tPD (CLK0,1 to Q[0–4]) tPD (CLK0,1 to Q[0–4]) Figure 4. MC100ES8014 AC Reference Measurement Waveform (HSTL Input) TIMING SOLUTIONS IDT™ Low Voltage 1:5 Differential LVDS Clock Fanout Buffer VCMR=VCC–1.3V Figure 5. MC100ES8014 AC Reference Measurement Waveform (PECL Input) 5 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 5 For More Information On This Product, MOTOROLA MC100ES8014 MC100ES8014 Low Voltage 1:5 Differential LVDS Clock Fanout BufferSemiconductor, Freescale Inc. NETCOM MC100ES8014 PACKAGE DIMENSIONS DT SUFFIX 20 LEAD TSSOP PACKAGE CASE 948E-02 ISSUE A 20X 0.15 (0.006) T U K REF 0.10 (0.004) S M T U V S S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND BE ARE TO BE DETERMINED AT DATUM PLANE -W-. K K1 2X L/2 20 11 Freescale Semiconductor, Inc... J J1 B -U- L PIN 1 IDENT SECTION N-N 10 0.25 (0.010) N 0.15 (0.006) T U S M A -VN F DETAIL E -W- C D G H DETAIL E 0.100 (0.004) –T– SEATING PLANE DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0˚ 8˚ INCHES MIN MAX 0.252 0.260 0.169 0.177 0.047 --0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 8˚ 0˚ CASE 948E 02 MOTOROLA IDT™ Low Voltage 1:5 Differential LVDS Clock Fanout Buffer 6 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 6 For More Information On This Product, TIMING SOLUTIONS MC100ES8014 MC100ES8014 MPC92459 PART NUMBERS 900 Low MHz Voltage Low1:5 Voltage Differential LVDS Clock LVDS Clock Synthesizer Fanout Buffer INSERT PRODUCT NAME AND DOCUMENT TITLE NETCOM NETCOM Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA XX-XXXX-XXXXX