Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer ICS8543 DATA SHEET General Description Features The ICS8543 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8543 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100Ω. The ICS8543 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. • • • Four differential LVDS output pairs • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL • • Maximum output frequency: 800MHz • • • • • • • Additive phase jitter, RMS: 0.164ps (typical) Guaranteed output and part-to-part skew characteristics make the ICS8543 ideal for those applications demanding well defined performance and repeatability. Q LE 00 PCLK Pulldown nPCLK Pullup 1 Translates any single-ended input signals to LVDS levels with resistor bias on nCLK input Output skew: 40ps (maximum) Part-to-part skew: 500ps (maximum) Propagation delay: 2.6ns (maximum) Full 3.3V supply mode 0°C to 70°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages GND CLK_EN CLK_SEL CLK nCLK PCLK nPCLK D CLK Pulldown nCLK Pullup CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL Pin Assignment Block Diagram CLK_EN Pullup Selectable differential CLK, nCLK or LVPECL clock inputs 1 CLK_SEL Pulldown Q0 nQ0 Q1 nQ1 OE GND VDD Q2 nQ2 OE Pullup 1 2 3 4 5 6 7 8 9 10 Q0 nQ0 VDD Q1 nQ1 Q2 nQ2 GND 20 19 18 17 16 15 14 13 12 11 Q3 nQ3 ICS8543 Q3 nQ3 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View ICS8543BG REVISION E DECEMBER 17, 2010 1 ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Table 1. Pin Descriptions Number Name 1, 9, 13 GND Power Type Description 2 CLK_EN Input Pullup 3 CLK_SEL Input Pulldown Clock select input. When HIGH, selects PCLK, nPCLK inputs. When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. 4 CLK Input Pulldown Non-inverting differential clock input. 5 nCLK Input Pullup 6 PCLK Input Pulldown 7 nPCLK Input Pullup Inverting differential LVPECL clock input. 8 OE Input Pullup Output enable. Controls enabling and disabling of outputs Q[0:3], nQ[0:3]. LVCMOS/LVTTL interface levels. 10, 18 VDD Power Positive supply pins. 11, 12 nQ3, Q3 Output Differential output pair. LVDS interface levels. 14, 15 nQ2, Q2 Output Differential output pair. LVDS interface levels. 16, 17 nQ1, Q1 Output Differential output pair. LVDS interface levels. 19, 20 nQ0, Q0 Output Differential output pair. LVDS interface levels. Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follows clock input. When LOW, Qx outputs are forced low, nQx outputs are forced high. LVCMOS / LVTTL interface levels. Inverting differential clock input. Non-inverting differential LVPECL clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ICS8543BG REVISION E DECEMBER 17, 2010 Test Conditions 2 Minimum Typical Maximum Units ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Function Tables Table 3A. Control Input Function Table Inputs Outputs OE CLK_EN CLK_SEL 0 X X 1 0 0 1 0 1 1 Selected Source Q[0:3] nQ[0:3] Hi-Z Hi-Z CLK, nCLK Disabled; Low Disabled; High 1 PCLK, nPCLK Disabled; Low Disabled; High 1 0 CLK, nCLK Enabled Enabled 1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK/nCLK and PCLK/nPCLK inputs as described in Table 3B. Enabled Disabled nCLK, nPCLK CLK, PCLK CLK_EN nQ0:nQ3 Q0:Q3 Figure 1. CLK_EN Timing Diagram Table 3B. Clock Input Function Table Inputs Outputs CLK or PCLK nCLK or nPCLK Q[0:3] nQ[0:3] Input to Output Mode Polarity 0 1 LOW HIGH Differential to Differential Non-Inverting 1 0 HIGH LOW Differential to Differential Non-Inverting 0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting 1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels. ICS8543BG REVISION E DECEMBER 17, 2010 3 ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 50 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum 2 Typical Maximum Units 3.765 V 0.8 V OE, CLK_EN VDD = VIN = 3.465V 5 µA CLK_SEL VDD = VIN = 3.465V 150 µA OE, CLK_EN VDD = 3.465V, VIN = 0V -150 µA CLK_SEL VDD = 3.465V, VIN = 0V -5 µA ICS8543BG REVISION E DECEMBER 17, 2010 4 ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 0.5 VDD – 0.85 V Maximum Units CLK VDD = VIN = 3.465V 150 µA nCLK VDD = VIN = 3.465V 5 µA CLK VDD = 3.465V, VIN = 0V -5 µA nCLK VDD = 3.465V, VIN = 0V -150 µA NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVPECL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage 0.3 1.0 V VCMR Common Mode Input Voltage; NOTE 1 1.5 VDD V PCLK VDD = VIN = 3.465V 150 µA nPCLK VDD = VIN = 3.465V 5 µA PCLK VDD = 3.465V, VIN = 0V -5 µA nPCLK VDD = 3.465V, VIN = 0V -150 µA NOTE 1: Common mode input voltage is defined as VIH. Table 4E. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Minimum Typical Maximum Units VOD Differential Output Voltage 200 280 360 mV ∆VOD VOD Magnitude Change 0 40 mV VOS Offset Voltage 1.25 1.375 V ∆VOS VOS Magnitude Change 5 25 mV IOz High Impedance Leakage -10 +10 µA IOFF Power Off Leakage -20 ±1 +20 µA IOSD Differential Output Short Circuit Current -3.5 -5 mA IOS Output Short Circuit Current -3.5 -5 mA VOH Output Voltage High 1.34 1.6 V VOL Output Voltage Low ICS8543BG REVISION E DECEMBER 17, 2010 Test Conditions 1.125 0.9 5 1.06 V ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER AC Electrical Characteristics Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum ƒ ≤ 800MHz 1.7 fMAX Maximum Output Frequency tPD Propagation Delay; NOTE 1 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section tsk(o) Output Skew; NOTE 2, 4 40 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 500 ps tR / tF Output Rise/Fall Time 350 ps odc Output Duty Cycle 55 % 153.6MHz, Integration Range: 12kHz – 20MHz 20% to 80% @ 50MHz odc Typical Maximum Units 800 MHz 2.6 ns 0.164 150 45 50 ps NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. ICS8543BG REVISION E DECEMBER 17, 2010 6 ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. SSB Phase Noise dBc/Hz Additive Phase Jitter @ 153.6MHz 12kHz to 20MHz = 0.164ps (typical) Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This ICS8543BG REVISION E DECEMBER 17, 2010 is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. 7 ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Parameter Measurement Information VDD SCOPE Qx VDD 3.3V±5% POWER SUPPLY + Float GND – nCLK, nPCLK V LVDS Cross Points PP V CMR CLK, PCLK nQx GND 3.3V LVDS Output Load AC Test Circuit Differential Input Level VDD nQx nQ[0:3] Qx V Cross Points OD nQy Q[0:3] Qy V OS tsk(o) GND Differential Output Level Output Skew Par t 1 nCLK, nPCLK nQx Qx nQy CLK, PCLK Par t 2 nQ[0:3] Qy Q[0:3] tsk(pp) tPD Part-to-Part Skew ICS8543BG REVISION E DECEMBER 17, 2010 Propagation Delay 8 ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Parameter Measurement Information, continued nQ[0:3] nQ[0:3] Q[0:3] 80% 80% t PW VOD Q[0:3] t PERIOD 20% 20% tF tR odc = t PW x 100% t PERIOD Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period VDD VDD out LVDS ➤ out ➤ ➤ out DC Input ➤ LVDS 100 VOD/∆ VOD VOS/∆ VOS out ➤ DC Input ➤ Offset Voltage Setup Differential Output Voltage Setup VDD out 3.3V±5% POWER SUPPLY + Float GND _ IOZ DC Input ➤ out LVDS DC Input IOZ ➤ IOSD out out High Impedance Leakage Current Setup ICS8543BG REVISION E DECEMBER 17, 2010 ➤ LVDS Differential Output Short Circuit Setup 9 ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Parameter Measurement Information, continued VDD out DC Input ➤ IOS LVDS LVDS ➤ ➤ IOSB out VDD IOFF Output Short Circuit Current Setup Power Off Leakage Setup Applications Information Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50Ω applications, R3 and R4 can be 100Ω. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS8543BG REVISION E DECEMBER 17, 2010 10 ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER 3.3V Differential Clock Input Interface Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω Zo = 50Ω nCLK nCLK R1 50Ω IDT LVHSTL Driver R2 50Ω Differential Input LVPECL Differential Input LVHSTL R2 50Ω R1 50Ω R2 50Ω Figure 3A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V R3 125Ω 3.3V R4 125Ω 3.3V Zo = 50Ω Zo = 50Ω CLK CLK R1 100Ω Zo = 50Ω nCLK Differential Input LVPECL R1 84Ω R2 84Ω nCLK Zo = 50Ω Receiver LVDS Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V 3.3V 3.3V 3.3V 2.5V *R3 33Ω R3 120Ω Zo = 50Ω R4 120Ω Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK nCLK HCSL *R4 33Ω R1 50Ω R2 50Ω Differential Input SSTL R1 120Ω R2 120Ω Differential Input *Optional – R3 and R4 can be 0Ω Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS8543BG REVISION E DECEMBER 17, 2010 11 ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER 3.3V LVPECL Clock Input Interface The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK/nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the PCLK/nPCLK input driven by the most common driver types. 3.3V 3.3V 3.3V 3.3V 3.3V R1 50Ω Zo = 50Ω R2 50Ω PCLK Zo = 50Ω R1 100Ω PCLK Zo = 50Ω nPCLK Zo = 50Ω nPCLK LVPECL Input CML LVPECL Input CML Built-In Pullup Figure 4B. PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver Figure 4A. PCLK/nPCLK Input Driven by a CML Driver 3.3V 3.3V 3.3V 3.3V 3.3V R3 125Ω R4 125Ω 3.3V LVPECL Zo = 50Ω C1 Zo = 50Ω C2 PCLK Zo = 50Ω PCLK VBB nPCLK Zo = 50Ω nPCLK LVPECL R1 84Ω R5 R6 100Ω - 200Ω 100Ω - 200Ω LVPECL Input R2 84Ω R1 50Ω R2 50Ω LVPECL Input Figure 4D. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple Figure 4C. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver 2.5V 3.3V 2.5V R3 120 R4 120 Zo = 60Ω PCLK Zo = 60Ω nPCLK SSTL R1 120 R2 120 LVPECL Input Figure 4E. PCLK/nPCLK Input Driven by a 2.5V SSTL Driver ICS8543BG REVISION E DECEMBER 17, 2010 12 ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Recommendations for Unused Input and Output Pins Inputs: Outputs: CLK/nCLK INPUTS LVDS Outputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. All unused LVDS outputs should be terminated with 100Ω resistor between the differential pair. PCLK/nPCLK INPUTS For applications not requiring the use of the differential input, both PCLK and nPCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from PCLK to ground. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LVDS Driver Termination A general LVDS interface is shown in Figure 5. Standard termination for LVDS type output structure requires both a 100Ω parallel resistor at the receiver and a 100Ω differential transmission line environment. In order to avoid any transmission line reflection issues, the 100Ω resistor must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 5 can be used with either type of output structure. If using a non-standard termination, it is recommended to contact IDT and confirm if the output is a current source or a voltage source type structure. In addition, since these outputs are LVDS compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. + LVDS Driver LVDS Receiver 100Ω – 100Ω Differential Transmission Line Figure 5. Typical LVDS Driver Termination ICS8543BG REVISION E DECEMBER 17, 2010 13 ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS8543. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8543 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.25mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 73.2°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.173W * 73.2°C/W = 82.7°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resitance θJA for 20 Lead TSSOP, Forced Convection θJA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W ICS8543BG REVISION E DECEMBER 17, 2010 14 ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Reliability Information Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP θJA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W Transistor Count The transistor count for ICS8543 is: 636 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS8543BG REVISION E DECEMBER 17, 2010 15 ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Ordering Information Table 9. Ordering Information Part/Order Number 8543BG 8543BGT 8543BGLF 8543BGLFT Marking ICS8543BG ICS8543BG ICS8543BGLF ICS8543BGLF Package 20 Lead TSSOP 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS8543BG REVISION E DECEMBER 17, 2010 16 ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Revision History Sheet Rev Table Page A T4E 5 In the VOL row, 1.06 has been moved to the Typical column from the maximum column. 9/18/01 A 3 Updated Figure 1, CLK_EN Timing Diagram. 10/17/01 A 3 Updated Figure 1, CLK_EN Timing Diagram. 11/2/01 A 1 6 - 10 Features section, Bullet 6 to read 3.3V LVDS levels instead of LVPECL. Updated Parameter Measurement Information figures. 5/6/02 5 AC Characteristics table - revised Output Frequency from 650MHz to 800MHz. 6/5/02 1 Features - deleted bullet "Designed to meet or exceed the requirements of ANSI TIA/EIA-644". LVDS Table - changed VOD typical value from 350mV to 280mV. 9/19/02 12/31/03 B T5 C D 5 T2 2 4 9 10 11 Pin Characteristics - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings - changed Output rating. Added Differential Clock Input Interface section. Added LVPECL Clock Input Interface section. Added LVDS Driver Termination section. Updated format throughout data sheet. T1 2 Pin Description table - added function description to the OE pin. 4/7/04 T8 10 13 Updated LVPECL Clock Input Interface section. Added Lead Free part number to Ordering Information table. 6/16/04 3 10 11 12 13 Updated Figure 1, CLK_EN Timing Diagram. Updated Differential Clock Input Interface section. Updated LVPECL Clock Input Interface section. Added Recommendation for Unused Input and Output Pins section. Added Power Considerations section. Updated format throughout the datasheet. 2/27/08 1 6 7 10 11 12 13 16 Features section - added Additive Phase Jitter bullet. AC Characteristics Table - added Added Phase Jitter spec and thermal note. Added Additive Phase Jitter plot. Updated Wiring the Differential Input to Accept Single-ended Levels section. Updated 3.3V Differential Clock Input Interface section. Updated 3.3V LVPECL Clock Input Interface section. Updated LVDS Driver Termination section. Ordering Information Table - deleted “ICS” prefix from Part/Order Number column. Updated datasheet header/footer style. 11/12/10 1 14 Page 1, corrected Header Title. Power Considerations - corrected typo for junction temperature from 827.7°C to 82.7°C. 12/17/10 D T5 E T9 E Date 4E D D Description of Change ICS8543BG REVISION E DECEMBER 17, 2010 17 ©2010 Integrated Device Technology, Inc. ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2010. All rights reserved.