3.3 V/2.5 V 1:15 PECL/LVCMOS Clock Fanout Buffer MPC9449 NRND DATASHEET NRND – Not Recommend for New Designs The MPC9449 is a 3.3 V or 2.5 V compatible, 1:15 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews less than 200 ps the device meets the needs of the most demanding clock applications. Features • • • • • • • • • • • • 15 LVCMOS compatible clock outputs Two selectable LVCMOS and one differential LVPECL compatible clock inputs Selectable output frequency divider (divide-by-one and divide-by-two) Maximum clock frequency of 200 MHz Maximum clock skew of 200 ps High-impedance output control 3.3 V or 2.5 V power supply Drives up to 30 series terminated clock lines Ambient temperature range –40C to +85C 52-lead LQFP packaging, Pb-free Supports clock distribution in networking, telecommunication and computing applications Pin and function compatible to MPC949 3.5 V/2.5 V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER AE SUFFIX 52-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 848D-03 Functional Description The MPC9449 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 200 MHz. The device has 15 identical outputs, organized in four output banks. Each output bank provides a retimed or frequency divided copy of the input signal with a near zero skew. The output buffer supports driving of 50 terminated transmission lines on the incident edge: each output is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable LVCMOS compatible clock inputs are available. This feature supports redundant differential clock sources. In addition, the MPC9449 accepts one differential PECL clock signal. The DSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the four output banks. Applying the OE control will force the outputs into high-impedance mode. All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a 2.5 V or 3.3 V power supply and an ambient temperature range of –40C to +85C. The MPC9449 is pin and function compatible but performance-enhanced to the MPC949. The device is packaged in a 52-lead LQFP package. MPC9449 REVISION 6 DECEMBER 21, 2012 1 ©2012 Integrated Device Technology, Inc. MPC9449 Data Sheet 3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER PACKAGE DIMENSIONS DSELA VCC CCLK0 0 CCLK1 1 0 1 CCLK_SEL VCC 0 QA0 1 QA1 QB0 1 0 2 1 QB1 QB2 QC0 PCLK PCLK PCLK_SEL 0 QC1 1 QC2 QC3 DSELB DSELC QD0 QD1 0 1 QD2 QD3 DSELD QD4 QD5 MR/OE NC GND QC0 VCC QC1 GND QC2 VCC QC3 GND GND QD5 NC Figure 1. MPC9449 Logic Diagram NC VCC QB2 GND QB1 VCC QB0 44 45 46 47 48 49 50 51 52 1 2 3 4 22 21 20 MPC9449 19 18 17 16 15 14 5 6 7 8 9 10 11 12 13 NC VCC QD4 GND QD3 VCC QD2 GND QD1 VCC QD0 GND NC MR/OE CCLK_SEL VCC CCLK0 CCLK1 PCLK PCLK PCLK_SEL DSELA DSELB DSELC DSELD GND GND GND QA1 VCC QA0 GND 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 25 41 24 42 23 43 Figure 2. PC9449 52-Lead Package Pinout (Top View) MPC9449 REVISION 6 DECEMBER 21, 2012 2 ©2012 Integrated Device Technology, Inc. MPC9449 Data Sheet 3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER Table 1. Function Table Control Default 0 1 PCLK_SEL 0 LVCMOS clock input selected (CCLK0 or CCLK1) PCLK differential input selected CCLK_SEL 0 CCLK0 selected CCLK1 selected DSELA, DSELB, DSELC, DSELD 00 00 1 2 MR/OE 1 Outputs enabled Outputs disabled (high impedance) Table 2. Pin Configuration Pin PCLK, PCLK I/O Type Input LVPECL Function Differential LVPECL clock input CCLK0, CCLK1 Input LVCMOS LVCMOS clock inputs PCLK_SEL Input LVCMOS LVPECL clock input select CCLK_SEL Input LVCMOS LVCMOS clock input select DSELA, DSELB, DSELC, DSELD Input LVCMOS Clock divider selection MR/OE Input LVCMOS Output enable/disable (high-impedance tristate) QA0-1, QB0-2, QC0-3, QD0-5 Output LVCMOS Clock outputs GND Supply Ground Negative power supply (GND) VCC Supply VCC Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Table 3. General Specifications Symbol Characteristics Min Typ Max VCC 2 Unit Condition VTT Output Termination Voltage MM ESD Protection (Machine Model) 200 V V HBM ESD Protection (Human Body Model) 2000 V LU Latch-Up Immunity 200 mA CPD Power Dissipation Capacitance 12 pF Per output CIN Input Capacitance 4.0 pF Inputs Table 4. Absolute Maximum Ratings(1) Symbol Characteristics Min Max Unit VCC Supply Voltage –0.3 3.8 V VIN DC Input Voltage –0.3 VCC0.3 V DC Output Voltage –0.3 VCC0.3 V 20 mA 50 mA 125 C VOUT IIN IOUT TS DC Input Current DC Output Current Storage Temperature –65 Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. MPC9449 REVISION 6 DECEMBER 21, 2012 3 ©2012 Integrated Device Technology, Inc. MPC9449 Data Sheet 3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER Table 5. DC Characteristics (VCC = 3.3 V ± 5%, TA = –40C to 85°C) Symbol Characteristics VIH Input High Voltage VIL Input Low Voltage Output High Voltage VPP Peak-to-Peak Input Voltage Common Mode Range VCMR VOL Output Low Voltage ZOUT Output Impedance Typ 2.0 VOH (2) Min Unit VCC 0.3 V 0.8 Condition LVCMOS V LVCMOS 2.4 V IOH = –24 mA(1) PCLK, PCLK 250 mV LVPECL PCLK, PCLK 1.0 VCC –0.6 V LVPECL 0.55 0.30 V V IOL = 24 mA IOL = 12 mA 14 – 17 Input Current IIN ICCQ Max Maximum Quiescent Supply Current 200 A VIN = VCC or GND 10 mA All VCC Pins 1. The MPC9449 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40C to 85°C)(1) Symbol VPP VCMR (2) Characteristics Min Typ Max Unit Peak-to-Peak Input Voltage PCLK, PCLK 400 1000 mV LVPECL Common Mode Range PCLK, PCLK 1.0 VCC –0.6 V LVPECL fmax Output Frequency 0 200 MHz fref Input Frequency 0 200 MHz tP, REF tr, tf tsk(O) Reference Input Pulse Width Output-to-Output Skew tsk(PP) Device-to-Device Skew tsk(P) Output Pulse Skew tPLH, HL Propagation Delay tPLZ, HZ Output Disable Time tPZL, LZ Output Enable Time tJIT(CC) 1.5 ns CCLK0, CCLK1 Input Rise/Fall Time Same Frequency Different Frequencies tr, tf Condition Qa outputs Qb outputs Qc outputs Qd outputs All outputs All outputs ns 50 50 50 100 200 300 ps ps ps ps ps ps 2.5 ps 5.0 5.0 ns ns OE to any Q 11 ns OE to any Q 11 ns 1.0 ns (3) Output Rise/Fall Time 1.0 1.0 3.0 3.0 0.1 RMS (1 ) TBD 0.8 to 2.0 V ns 250 CCLK0 or CCLK1 to any Q PCLK to any Q Cycle-to-Cycle Jitter 1.0 DCREF = 50% 0.55 to 2.4 V ps 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts propagation delay. 3. An input rise/fall time greater than that specified may be used, but AC characteristics are not guaranteed under such a condition. MPC9449 REVISION 6 DECEMBER 21, 2012 4 ©2012 Integrated Device Technology, Inc. MPC9449 Data Sheet 3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER Table 7. DC Characteristics (VCC = 2.5 V ± 5%, TA = –40C to 85°C) Symbol Characteristics Min Max Unit 1.7 VCC 0.3 V –0.3 0.7 VIH Input High Voltage VIL Input Low Voltage VPP Peak-to-Peak Input Voltage PCLK, PCLK 250 Common Mode Range PCLK, PCLK 1.0 VCMR(1) VOH Output High Voltage VOL Output Low Voltage ZOUT Output Impedance Typ VCC –0.6 1.8 0.6 Input Current(3) ICC Maximum Quiescent Supply Current LVCMOS V LVCMOS mV LVPECL V LVPECL V IOH = –15 mA(2) V IOL = 15 mA 17–20 IIN Condition 200 A VIN = VCC or GND 10 mA All VCC Pins 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9449 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. 3. Inputs have pull-down or pull-up resistors affecting the input current. Table 8. AC Characteristics (VCC = 2.5 V ± 5%, TA = -40C to 85°C)(1) Symbol VPP VCMR (2) Characteristics Min Typ Max Unit Peak-to-Peak Input Voltage PCLK, PCLK 400 1000 mV LVPECL Common Mode Range PCLK, PCLK 1.2 VCC–0.6 V LVPECL fmax Output Frequency 0 200 MHz fref Input Frequency 0 200 MHz tP, REF Reference Input Pulse Width tr, tf CCLK Input Rise/Fall Time tsk(O) Output-to-Output Skew Same Frequency Different Frequencies tsk(PP) Device-to-Device Skew tSK(P) Output Pulse Skew tPLH, HL Propagation Delay tPLZ, HZ Output Disable Time tPZL, LZ Output Enable Time tr, tf tJIT(CC) Condition Output Rise/Fall Time 1.5 Qa outputs Qb outputs Qc outputs Qd outputs All outputs All outputs 1.0 ns 50 50 50 100 200 300 ps ps ps ps ps ps 5.0 ps 7.0 7.0 ns ns OE to any Q 11 ns OE to any Q 11 ns 1.0 ns (3) 1.0 1.0 3.5 3.5 0.1 RMS (1 ) TBD 0.7 to 1.7 V ns 350 CCLK0 or CCLK1 to any Q PCLK to any Q Cycle-to-Cycle Jitter ns DCREF = 50% 0.6 to 1.8 V ps 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts propagation delay. 3. An input rise/fall time greater than that specified may be used, but AC characteristics are not guaranteed under such a condition. MPC9449 REVISION 6 DECEMBER 21, 2012 5 ©2012 Integrated Device Technology, Inc. MPC9449 Data Sheet 3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER APPLICATIONS INFORMATION Driving Transmission Lines The MPC9449 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Freescale Semiconductor application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9449 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9449 clock driver is effectively doubled due to its capability to drive multiple lines. output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = Z0 = RS = R0 = VL = = At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 1. Final skew data pending specification. 3.0 2.5 14 OutA tD = 3.8956 OutB tD = 3.9386 Voltage (V) 2.0 MPC9449 Output Buffer IN VS (Z0 (RS + R0 + Z0)) 50 || 50 36 || 36 14 3.0 (25 (18 + 17 + 25) 1.31 V In 1.5 1.0 RS = 36 ZO = 50 0.5 OutA 0 MPC9449 Output Buffer IN 2 RS = 36 ZO = 50 14 10 12 14 Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 5 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. ZO = 50 OutB1 Figure 3. Single versus Dual Transmission Lines The waveform plots in Figure 4 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9449 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9449. The output waveform in Figure 4 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the MPC9449 REVISION 6 DECEMBER 21, 2012 6 8 Time (nS) Figure 4. Single versus Dual Waveforms OutB0 RS = 36 4 MPC9449 Output Buffer RS = 22 ZO = 50 RS = 22 ZO = 50 14 14 + 22 || 22 = 50 || 50 25 = 25 Figure 5. Optimized Dual Line Termination 6 ©2012 Integrated Device Technology, Inc. MPC9449 Data Sheet 3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER MPC9449 DUT ZO = 50 Pulse Generator Z = 50 ZO = 50 RT = 50 RT = 50 VTT VTT Figure 6. CCLK MPC9449 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V Differential Pulse Generator Z = 50 ZO = 50 MPC9449 DUT ZO = 50 RT = 50 RT = 50 VTT VTT Figure 7. PCLK MPC9449 AC Test Reference MPC9449 REVISION 6 DECEMBER 21, 2012 7 ©2012 Integrated Device Technology, Inc. MPC9449 Data Sheet 3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER VCC VCC CCLK VCC ÷2 VCC ÷2 VPP GND GND VCC VCC ÷2 VCC VCC ÷2 QX GND GND tSK(O) t(HL) t(LH) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 9. Propagation Delay (tPD) Test Reference Figure 8. Output-to-Output Skew tSK(O) VCC CCLK PCLK PCLK VCC ÷2 VCMR VPP GND VCC VCC ÷2 QX VCC VCC ÷2 QX GND GND t(HL) t(LH) t(HL) t(HL) t(LH) tSK(P) = tPLH–tPLH Figure 11. Propagation Delay tSK(P) Test Reference Figure 10. Propagation Delay (tPD) Test Reference VCC=3.3 V tF VCC=2.5 V 2.4 1.8 V 0.55 0.6 V TN TJIT(CC) = |TN -TN+1| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs tR Figure 12. Output Transition Time Test Reference MPC9449 REVISION 6 DECEMBER 21, 2012 TN+1 Figure 13. Cycle-to-Cycle Jitter Figure 14 8 ©2012 Integrated Device Technology, Inc. MPC9449 Data Sheet 3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER PACKAGE DIMENSIONS 4X 4X 13 TIPS 0.20 (0.008) H L-M N 0.20 (0.008) T L-M N -XX=L, M, N 52 40 1 CL 39 AB G 3X VIEW Y -L- -M- AB B B1 13 V VIEW Y BASE METAL F PLATING V1 27 14 J 26 U -N- A1 D 0.13 (0.005) M T L-M S N S S1 SECTION AB-AB A ROTATED 90˚ CLOCKWISE S 4X θ2 C 0.10 (0.004) T -H-T- 4X θ3 SEATING PLANE VIEW AA 0.05 (0.002) S W 2X R θ1 NOTES: 1. CONTROLLING DIMENSIONS: MILLIMETER. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSTION 0.07 (0.003). R1 0.25 (0.010) C2 θ GAGE PLANE K C1 E Z VIEW AA DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z θ θ1 θ2 θ3 MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0˚ 7˚ --0˚ 12˚ REF 12˚ REF INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0˚ 7˚ --0˚ 12˚ REF 12˚ REF CASE 848D-03 CASE 848D-03 ISSUEDD ISSUE 52-LEAD LQFP PACKAGE DATE 11/15/94 MPC9449 REVISION 6 DECEMBER 21, 2012 9 ©2012 Integrated Device Technology, Inc. MPC9449 Data Sheet 3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER Revision History Sheet Rev 6 Table Page 1 Description of Change Date NRND – Not Recommend for New Designs MPC9449 REVISION 6 DECEMBER 21, 2012 10 12/21/12 ©2012 Integrated Device Technology, Inc. MPC9449 Data Sheet 3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. 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