PRELIMINARY ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER GENERAL DESCRIPTION FEATURES • Two differential LVPECL outputs Each output supports independent frequency selection at 19.44MHz, 77.76MHz, 155.52MHz and 622.08MHz The ICS813322-02 is a member of the ICS HiperClockS™ family of high performance clock HiPerClockS™ solutions from IDT. The ICS813322-02 is a PLL based synchronous multiplier that is optimized for Ethernet or SONET-to-SONET clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock™ frequency multiplier that provides the low jitter, high frequency SONET output clock that meets up to SONET OC-48 jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in Ether net and SONET applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-VFQFN package. • Two differential inputs support the following input types: LVPECL, LVDS, HCSL • Accepts input frequencies from 8kHz to 156.25MHz including 8kHz,19.44MHz, 25MHz, 62.5MHZ, 77.76MHz, 125MHz, 155.52MHz and 156.25MHz • Each output has independently controlled dividers for common SONET clock rates • Attenuates the phase jitter of the input clock by using a lowcost pullable funamental mode VCXO crystal • VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking using external loop filter connection • FemtoClock frequency multiplier provides low jitter, high frequency output • Absolute pull range: 50ppm • FemtoClock VCO frequency: 622.08MHz • RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz – 20MHz): 1.16ps (typical) PIN ASSIGNMENT • 3.3V supply voltage nCLK1 VCC CLK1 CLK0 nCLK0 XTAL_OUT VCCX XTAL_IN • 0°C to 70°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages 32 31 30 29 28 27 26 25 LF1 1 24 VEE LF0 2 23 nQB ISET 3 22 QB VEE 4 21 VCCO CLK_SEL 5 20 nQA VCC 6 19 QA nc 7 18 VEE VEE 8 17 ODASEL_0 ICS813322-02 ODASEL_1 ODBSEL_0 ODBSEL_1 VCC VCCA PDSEL_0 PDSEL_1 PDSEL_2 9 10 11 12 13 14 15 16 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 1 ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY BLOCK DIAGRAM XTAL_IN LF1 LF0 3 ISET PDSEL_[2:0] Pullup VCXO Input Pre-Divider CLK0 nCLK0 CLK1 nCLK1 CLK_SEL Pulldown 0 1 000 = 4 001 = 9720 010 = 12500 011 = 31250 100 = 38880 101 = 62500 110 = 77760 111 = 78125 XTAL_OUT Loop Filter Output Divider QA 00 = 32 01 = 8 10 = 4 11 = 1 19.44MHz Phase Detector nQA 2 VCXO Charge Pump VCXO Feedback Divider ÷9720 VCXO Jitter Attenuation PLL FemtoClock PLL 622.08MHz Output Divider QB 00 = 32 01 = 8 10 = 4 11 = 1 nQB 2 IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 2 ODASEL_[1:0] ODBSEL_[1:0] ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number Name Type Analog Input/Output Analog Input/Output Power 1, 2 LF1, LF0 3 ISET 4, 8, 18, 24 V EE 5 CLK_SEL Input 6, 12, 27 VCC Power 7, 20, 23 9, 1 0, 11 nc PDSEL_2, PDSEL_1, PDSEL_0 Unused 13 VCCA Power 14, 15 16, 17 19, 20 ODBSEL_1, ODBSEL_0 ODASEL_1, ODASEL_0 QA, nQA Input Input Input Output Description Loop filter connection node pins. Charge pump current setting pin. Negative supply pins. Input clock select. When HIGH selects CLK1/nCLK1. Pulldown When LOW, selects CLK0/nCLK0. LVCMOS/LVTTL interface levels. Core power supply pins. No connect. Pullup Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A. Analog supply pin. Frequency select pins for Bank B output. See Table 3B. LVCMOS/LVTTL interface levels. Frequency select pins for Bank A output. See Table 3B. Pulldown LVCMOS/LVTTL interface levels. Bank A differential clock outputs. LVPECL interface levels. Pulldown 21 VCCO Power Output power supply pin. 22, 23 QB, nQB Output Bank B differential clock outputs. LVPECL interface levels. 25 nCLK1 Input 26 CLK1 Input 28 nCLK0 Input 29 30, 31 CLK0 XTAL_OUT, XTAL_IN Input 32 VCCX Power Pullup/ Pulldown Pulldown Pullup/ Pulldown Pulldown Input Inver ting differential clock input. VDD/2 bias voltage when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 bias voltage when left floating. Non-inver ting differential clock input. Cr ystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Power supply pin for VCXO charge pump. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER Test Conditions 3 Minimum Typical Maximum Units ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY TABLE 3A. PRE-DIVIDER FUNCTION TABLE Inputs Pre-Divider Value PDSEL_2 PDSEL_1 PDSEL_0 0 0 0 4 0 0 1 9720 0 1 0 12500 0 1 1 31250 1 0 0 38880 1 0 1 62500 1 1 0 77760 1 1 1 78125 (default) TABLE 3B. OUTPUT DIVIDER FUNCTION TABLE Inputs ODxSEL_1 ODxSEL_0 0 0 Output Divider Value 32 (default) 0 1 8 1 0 4 1 1 1 IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 4 ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY TABLE 3C. FREQUENCY FUNCTION TABLE Input Frequency (MHz) 0.008 4 VCXO Frequency (MHz) 19.44 FemtoClock Feedback Divider Value 32 Femtoclock VCO Frequency (MHz) 622.08 0.008 4 19.44 32 0.008 4 19.44 0.008 4 19.44 19.44 9720 19.44 19.44 19.44 Output Divider Value Output Frequency (MHz) 32 19.44 622.08 8 77.76 32 622.08 4 155.52 32 622.08 1 622.08 19.44 32 622.08 32 19.44 9720 19.44 32 622.08 8 77.76 9720 19.44 32 622.08 4 155.52 9720 19.44 32 622.08 1 622.08 Pre-Divider Value 25 12500 19.44 32 622.08 32 19.44 25 12500 19.44 32 622.08 8 77.76 25 12500 19.44 32 622.08 4 155.52 25 12500 19.44 32 622.08 1 622.08 62.5 31250 19.44 32 622.08 32 19.44 62.5 31250 19.44 32 622.08 8 77.76 62.5 31250 19.44 32 622.08 4 155.52 62.5 31250 19.44 32 622.08 1 622.08 77.76 38880 19.44 32 622.08 32 19.44 77.76 38880 19.44 32 622.08 8 77.76 77.76 38880 19.44 32 622.08 4 155.52 77.76 38880 19.44 32 622.08 1 622.08 125 62500 19.44 32 622.08 32 19.44 125 62500 19.44 32 622.08 8 77.76 125 62500 19.44 32 622.08 4 155.52 125 62500 19.44 32 622.08 1 622.08 155.52 77760 19.44 32 622.08 32 19.44 155.52 77760 19.44 32 622.08 8 77.76 155.52 77760 19.44 32 622.08 4 155.52 155.52 77760 19.44 32 622.08 1 622.08 156.25 78125 19.44 32 622.08 32 19.44 156.25 78125 19.44 32 622.08 8 77.76 156.25 78125 19.44 32 622.08 4 155.52 156.25 78125 19.44 32 622.08 1 622.08 IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 5 ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Inputs, VI 4.6V -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 37°C/W (0 mps) -65°C to 150°C Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C Symbol Parameter VCC Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VCCA Analog Supply Voltage VCC – 0.15 3.3 VCC V VCCO Output Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 3.465 VCCX Charge Pump Supply Voltage ICCA Analog Supply Current 15 mA V IEE Output Supply Current 250 mA ICCX Charge Pump Supply Current 0.250 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage CLK_SEL, ODASEL_[0:1], Input High Current ODBSEL_[0:1] PDSEL[0:2] CLK_SEL, ODASEL_[0:1], Input Low Current ODBSEL_[0:1] IIH IIL Test Conditions PDSEL[0:2] Minimum Maximum Units 2 Typical VCC + 0.3 V -0.3 0.8 V VCC = VIN = 3.465V 150 µA VCC = VIN = 3.465V 5 µA VCC = 3.465V, VIN = 0V -5 µA VCC = 3.465V, VIN = 0V -150 µA NOTE 1: Outputs terminated with 50Ω to VCCO/2. TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum CLK0/nCLK0, CLK1/nCLK1 CLK0, CLK1 VIN = 0V, VCC = 3.465V -5 nCLK0, nCLK1 VIN = 0V, VCC = 3.465V -150 IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage VCMR Common Mode Input Voltage; NOTE 1, 2 Typical VIN = VCC = 3.465V Maximum Units 150 µA µA µA 0.15 1.3 V VEE + 0.5 VCC – 0.85 V NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VCC + 0.3V. IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 6 ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 Typical VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1. 0 V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. TABLE 5. AC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fIN Input Frequency 0.008 156.25 MHz fOUT 19.44 622.08 MHz tjit(cc) Output Frequency RMS Phase Jitter (Random); NOTE 1 Cycle-to-Cycle Jitter; NOTE 2, 3 tjit(per) tjit(Ø) 155.52MHz fOUT, 19.44MHz crystal, Integration Range: 12kHz - 20MHz 1.16 ps 50 ps Period Jitter; NOTE 4 5 ps tsk(o) Output Skew; NOTE 3, 5 50 ps odc Output Duty Cycle t R / tF Output Rise/Fall Time 50 % 600 ps PLL Lock Time 100 tLOCK NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Outputs terminated with 50Ω to VCCO - 2V. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Jitter performance using crystal inputs. NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load condtions. Measured at the output differential cross points. ms IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 20% to 80% 7 ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY ➤ TYPICAL PHASE NOISE AT 155.52MHZ 155.52MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 1.16ps (typical) Raw Phase Noise Data ➤ ➤ NOISE POWER dBc Hz SONET Filter Phase Noise Result by adding a SONET Filter to raw data OFFSET FREQUENCY (HZ) IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 8 ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY PARAMETER MEASUREMENT INFORMATION 2V 2V VCC, VCCO, VCCX VCC Qx SCOPE nCLK0, nCLK1 VCCA V V Cross Points PP CMR CLK0, CLK1 LVPECL nQx VEE VEE -1.3V ± 0.165V 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQA, nQB nFOUTx QA, QB FOUTx ➤ ➤ ➤ tcycle n tcycle n+1 ➤ nFOUTy tjit(cc) = tcycle n – tcycle n+1 1000 Cycles FOUTy tsk(o) CYCLE-TO-CYCLE JITTER OUTPUT SKEW Phase Noise Plot Noise Power VOH VREF Phase Noise Mask f1 Offset Frequency VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements f2 Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) RMS Jitter = Area Under the Masked Phase Noise Plot PERIOD JITTER PHASE JITTER nQA, nQB nQA, nQB 80% 80% QA, QB VSW I N G t PW t odc = PERIOD t PW QA, QB 20% 20% tR tF x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER OUTPUT RISE/FALL TIME 9 ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS813322-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCX, VCCA, and VCCO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. 3.3V VCC .01μF 10Ω VCCA .01μF 10 μF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio VCC R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 10 ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK/nCLK INPUTS For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. TERMINATION FOR 3.3V LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω 3.3V Zo = 50Ω 125Ω FOUT FIN 125Ω Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION 11 ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY VFQFN EPAD THERMAL RELEASE PATH In order to maximize both the removal of heat from the package and the electrical performance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE SOLDER LAND PATTERN THERMAL VIA PIN PIN PAD (GROUND PAD) FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 12 ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY SCHEMATIC EXAMPLE LVPECL driver. An optional 3-pole filter can also be used for additional spur reduction. It is recommended that the loop filter components be laid out for the 3-pole option. This will also allow the 2-pole filter to be used. Figure 5 shows an example of the ICS813322-02 application schematic. In this example, the device is operated at VCC = VCCX = VCCO = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V VC C R1 125 R2 125 CLK1 Zo = 50 Logic Control Input Examples nCLK1 Zo = 50 Set Logic Input to '1' VCC VC C R3 84 LVPECL Driv er R5 125 R4 84 RU1 1K R6 125 Set Logic Input to '0' VCC R U2 N ot Install To Logic Input pins CLK0 Zo = 50 RD1 Not Install To Logic Input pins R D2 1K nC LK0 Zo = 50 R7 84 XTAL_OUT R8 85 LVPECL Driv er C1 SP X1 XTAL_IN R 12 R10 133 10 VC CX U1 LF Rs TBDk Cp TBD uF Cs TBDuF VC C C8 0.1u 3-pole loop filter example - (optional) LF1 LF0 ISET VEE CLK_SEL VC C nc VEE R15 2.21K IC S813322-02 - 0.1u C7 R 13 82.5 VEE nQB QB VC CO nQA QA VEE ODASEL_0 24 23 22 21 20 19 18 17 nQA QA R14 82.5 VCC = VCCX = VCCO= 3.3V nQB QB ODASEL_0 PDSEL_2 PDSEL_1 PDSEL_0 VCC VCCA ODBSEL_1 ODBSEL_0 ODASEL_1 CLK_SEL 1 2 3 4 5 6 7 8 + Zo = 50 Ohm VCCX XTAL_IN XTAL_OUT CLK0 nCLK0 VCC CLK1 nCLK1 2-pole loop filter for Mid Bandwidth setting VC CO 0.1u 32 31 30 29 28 27 26 25 C6 10u R11 133 Zo = 50 Ohm C4 Zo = 50 Ohm + 9 10 11 12 13 14 15 16 C5 0.01u LF 3.3V VCC C2 SP CLK0 nCLK0 VCC Zo = 50 Ohm - Cs TBD uF PDSEL_2 PDSEL_1 PDSEL_0 LF TBD k Cp TBDuF C3 TBDpF VC C ODBSEL_1 ODBSEL_0 ODASEL_1 R9 LF Rs TBD k R16 50 Optional Y-Termination R19 VC CA 10 R17 50 R18 50 VCC C9 0.1u C 10 0.01u C11 10u FIGURE 5. ICS813322-02 SCHEMATIC LAYOUT IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 13 ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY VCXO-PLL EXTERNAL COMPONENTS Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (CL). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. the crystal specification. In either case, the absolute tuning range is reduced. The correct value of C L is dependant on the characteristics of the VCXO. The recommended CL in the Crystal Parameter Table balances the tuning range by centering the tuning curve. The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS and CP values for recommended high, mid and low loop bandwidth configurations. The device has been characterized using these parameters. For other configurations, refer to the Loop Filter Component Selection for VCXO Based PLLs Application Note. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not r un under neath the device, loop filter or crystal components. The crystal’s load capacitance CL characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (CTUNE). If the crystal CL is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal CL is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than LF0 LF1 ISET RS CP RSET CS XTAL_IN CTUNE 19.44MHz XTAL_OUT CTUNE VCXO CHARACTERISTICS TABLE Symbol Parameter Typical Unit kVCXO VCXO Gain 6000 Hz/V CV_LOW Low Varactor Capacitance 15.9 pF CV_HIGH High Varactor Capacitance 29.8 pF VCXO-PLL LOOP BANDWIDTH SELECTION TABLE Bandwidth RS (kΩ ) Crystal Frequency (MHz) CS (µF) CP (µF) RSET (kΩ ) 10Hz (Low) 19.44MHz 800 1.8 0.0034 8.5 80Hz (Mid) 19.44MHz 540 0.15 0.0015 2.3 240Hz (High) 19.44MHz 1000 0.25 0.0008 2.1 CRYSTAL CHARACTERISTICS Symbol Parameter Minimum Mode of Operation fN Frequency fT Frequency Tolerance fS Frequency Stability Operating Temperature Range Typical Maximum Units Fundamental 19.44 MHz 0 ±20 ppm ±20 ppm 70 °C CL Load Capacitance 10 pF CO Shunt Capacitance 4 pF CO /C1 Pullability Ratio ESR Equivalent Series Resistance 22 0 24 0 20 Drive Level Aging @ 25°C IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 1 mW ±3 per year ppm 14 ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS813322-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS813322-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 250mA = 866.25mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.465V, with all outputs switching) = 866.25mW + 60mW = 926.25mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.926W * 37°C/W = 104.2°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 32-LEAD VFQFN, FORCED CONVECTION θ JA vs. 0 Air Flow (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 15 0 1 2.5 37.0°C/W 32.4°C/W 29.0°C/W ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V – 2V. CCO • For logic high, VOUT = V OH_MAX =V CCO_MAX – 0.9V (VCCO_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (V CCO_MAX –V OL_MAX ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX – 2V))/R ] * (V CCO_MAX L –V OH_MAX ) = [(2V – (V CCO_MAX –V OH_MAX ))/R ] * (V CCO_MAX L –V OH_MAX )= [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CCO_MAX – 2V))/R ] * (V L CCO_MAX –V OL_MAX ) = [(2V – (V CCO_MAX –V OL_MAX ))/R ] * (V L CCO_MAX –V OL_MAX )= [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 16 ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN θ JA vs. 0 Air Flow (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 37.0°C/W 32.4°C/W 29.0°C/W TRANSISTOR COUNT The transistor count for ICS813322-02 is: 6331 IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 17 ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY PACKAGE OUTLINE AND DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below. TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS (VHHD -2/ -4) SYMBOL Minimum Maximum 32 N A 0.80 1.0 A1 0 0.05 0.25 Reference A3 b 0.18 0.30 e 0.50 BASIC ND 8 NE 8 5.0 D, E D2, E2 3.0 3.3 L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 18 ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 813322BK-02 ICS13322B02 32 Lead VFQFN tray 0°C to 70°C 813322BK-02T ICS13322B02 32 Lead VFQFN 2500 tape & reel 0°C to 70°C 813322BK-02LF ICS3322B02L 32 Lead "Lead-Free" VFQFN tray 0°C to 70°C 813322BK-02LFT ICS3322B02L 32 Lead "Lead-Free" VFQFN 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 19 ICS813322BK-02 REV. B AUGUST 14, 2008 ICS813322-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support Corporate Headquarters 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT [email protected] +480-763-2056 Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA