PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL GENERAL DESCRIPTION FEATURES The ICS810001-21 is a member of the HiperClockS™ family of high performance clock HiPerClockS™ solutions from ICS. The ICS810001-21 is a PLL based synchronous clock generator that is optimized for digital video clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation, and to support the complex PLL multiplication ratios needed for video rate conversion. The second stage is a FemtoClock frequency multiplier that provides the low jitter, high frequency video output clock. • Accepts various HD and SD references including hsync, transport and pixel clock rates ICS • Outputs HD and SD pixel rates • One LVCMOS/LVTTL PLL clock output • Two selectable LVCMOS/LVTTL input clocks • LVCMOS input select lines • VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking • FemtoClock frequency multiplier provides low jitter, high frequency output • FemtoClock range: 560MHz - 700MHz Preset multiplication ratios are selected from internal lookup tables using device input selection pins. The multiplication ratios are optimized to support most common video rates used in professional video system applications. The VCXO requires the use of an external, inexpensive pullable crystal. Two crystal connections are provided (pin selectable) so that both 60 and 59.94 base frame rates can be supported. The VCXO requires external passive loop filter components which are used to set the PLL loop bandwidth and damping characteristics. • RMS phase jitter @148.3516484MHz, using a 26.973027MHz crystal (12kHz - 20MHz): 0.81ps (typical) • 3.3V supply voltage • 0°C to 70°C ambient operating temperature PIN ASSIGNMENT OUTPUT RATES SUPPORTED: VDD 32 31 30 29 28 27 26 25 SMPTE 292M/59.94 SMPTE 292M/60, 1080P SMPTE 292M/59.94, 1080P SMPTE 259M Level “D” EXAMPLE FREQUENCY CONVERSIONS: All nine combinations from / to: 27MHz 74.175MHz 74.25MHz LF1 1 24 N0 LF0 2 23 N1 ISET 3 22 nBP1 VDD 4 21 OE nBP0 5 20 GND GND 6 19 Q CLK_SEL 7 18 VDDO CLK1 8 17 VDDA ICS810001-21 NTSC or PAL hsync to 27MHz NTSC or PAL hsync to 4xFsc V3 V2 V1 MF MR V0 CLK0 9 10 11 12 13 14 15 16 VDD 36MHz XTAL_SEL 148.3516484MHz XTAL_OUT1 148.5MHz GND 74.17582418MHz 27MHz x 1000/1001 SMPTE 292M/60 XTAL_IN1 74.25MHz VDDX 26.973027MHz Application MPEG Transpor t, ITU-R601, CCIR 656 XTAL_OUT0 27MHz XTAL_IN0 Frequency (MHz) 32-Lead VFQFN 5mm x 5mm x 0.95 package body K Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 810001BK-21 www.icst.com/products/hiperclocks.html 1 REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL 0 CLK0 0 CLK1 1 VCXO Input Pre-Divider XTAL_SEL XTAL_OUT1 XTAL_IN1 XTAL_IN0 LF1 LF0 ISET Loop Filter XTAL_OUT0 BLOCK DIAGRAM 1 Phase Detector VCXO (P Value from Table) Charge Pump VCXO Feedback Divider (M Value from Table) CLK_SEL V3:V0 4 MR VCXO Divider Table VCXO Jitter Attenuation PLL 10 FemtoClock Frequency Multiplier 11 0= x22 1= x24 Master Reset 01 10 11 Output Divider 00 = 4 01 = 8 10 = 12 11 = 18 00 01 10 11 MF N1:N0 nBP1:nBP0 2 2 810001BK-21 www.icst.com/products/hiperclocks.html 2 REV. A AUGUST 12, 2005 Q OE PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 LF1, LF0 3 ISET 4, 11, 25 6, 20, 29 VDD nBP0, nBP1 GND 7 CLK_SEL Input 8, 9 10, 14, 15, 16 CLK1, CLK0 V0, V1, V2, V3 Input Power supply ground. Input clock select. When HIGH selects CLK1. When LOW, selects Pulldown CLK0. LVCMOS/LVTTL interface levels. Pulldown Clock inputs. LVCMOS/LVTTL interface levels. Input Pulldown VCXO PLL divider selection pins. LVCMOS/LVTTL interface levels. 5, 22 Type Analog Input/Output Analog Input/Output Power Input MR Input 13 MF Input 17 VDDA Power 18 VDDO Power 19 Q Output 21 OE Input 23, 24 N1, N0 Input 26 XTAL_SEL Input 27, 28 30, 31 XTAL_OUT1, XTAL_IN1 XTAL_OUT0, XTAL_IN0 32 VDDX Loop filter connection node pins. Charge pump current setting pin. Core power supply pins. Pullup Power 12 Description PLL Bypass control pins. See block diagram. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the output to go low. When logic LOW, the Pulldown internal dividers and the output is enabled. LVCMOS / LVTTL interface levels. FemtoClock multiplication factor select pin. Pulldown LVCMOS/LVTTL interface levels. Analog supply pin. Output power supply pin. VCXO PLL clock output. LVCMOS/LVTTL interface levels. Output enable. When logic LOW, the clock output is in tristate. When logic HIGH, the output is enabled. Pullup LVCMOS/LVTTL interface levels. Pulldown FemtoClock output divide select. LVCMOS/LVTTL interface levels. Cr ystal select. When HIGH, selects XTAL1. When LOW, selects Pulldown XTAL0. LVCMOS/LVTTL interface levels. Cr ystal oscillator interface. XTAL_IN1 is the input. XTAL_OUT1 is the output. Cr ystal oscillator interface. XTAL_IN0 is the input. XTAL_OUT0 is the output. Input Input Power Power supply pin for VCXO charge pump. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN RPULLUP Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor RPULLDOWN Input Pulldown Resistor CPD 810001BK-21 Test Conditions VDD, VDDA, VDDO = 3.465V www.icst.com/products/hiperclocks.html 3 Minimum Typical Maximum Units 4 pF TBD pF 51 kΩ 51 kΩ REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL TABLE 3A. FIRST FREQUENCY TRANSLATION STAGE: VCXO PLL VCXO PLL Divider Look-Up Table Video Clock Application Alternate Video Clock Application V3:V0 Pins P Value M Value Input (kHz/MHz) VCXO (MHz) Input (kHz/MHz) VCXO (MHz) 0000 1000 1000 27MHz 27MHz 26.973MHz 26.973MHz 26.973MHz 26.973MHz 26.973MHz 44.955kHz (720P/59.94) 33.716kHz (1080I/59.94) 26.973MHz 0001 1001 1000 27MHz 26.973MHz 0010 11000 4004 74.175MHz 27MHz 0011 11011 4000 74.25MHz 26.973MHz 0100 11000 4000 74.25MHz 27MHz 0101 4004 4004 27MHz 27MHz 0110 4004 4000 27MHz 26.973MHz 0111 1000 1001 26.973MHz 27MHz 1000 25 0 91 74.175MHz 27MHz 1001 253 92 74.25MHz 27MHz 1010 92 92 27MHz 1011 1 600 1100 1 800 1101 1 1728 1110 1 1716 1111 1 960 27MHz 45kHz (720P/60 hsync) 33.75kHz (1080I/60 hsync) 15.625kHz (PAL hsync) 15.734kHz (NTSC hsync) 28.125kHz (1080I/50 hsync) 27MHz 27MHz 26.973MHz 26.973MHz 27MHz 27MHz 27MHz TABLE 3B. SECOND FREQUENCY TRANSLATION STAGE: FEMTOCLOCK MULTIPLIER FemtoClock Look-Up Table Video Clock Application Alternate Video Clock Application MF, N1:N0 Pins FB Div Out Div VCXO (MHz) Q (MHz) VCXO (MHz) Q (MHz) 0, 00 22 4 27MHz 148.5MHz 26.973MHz 148.35MHz 0, 01 22 8 27MHz 74.25MHz 26.973MHz 74.175MHz 0, 10 22 12 0, 11 22 18 1, 00 24 4 1, 01 24 8 1, 10 24 12 27MHz 54MHz 1, 11 24 18 27MHz 36MHz TABLE 3C. BYPASS FUNCTION TABLE Inputs Operation nBP1 nBP0 0 0 Bypass Frequency Translator PLL and Output Divider 0 1 Test Mode: Bypass VCXO Jitter Attenuation PLL and Frequency Translator PLL 1 0 LC Mode: Bypass VCXO Jitter Attenuation PLL 1 1 PLL Mode: Active 810001BK-21 www.icst.com/products/hiperclocks.html 4 REV. A AUGUST 12, 2005 810001BK-21 www.icst.com/products/hiperclocks.html 5 27 27 41 74.175824 30 42 27 27 74.175824 22 23 40 74.25 21 74.175824 74.175824 20 33 27 18 74.25 292M/59.94 27 17 74.25 Transpor t 27 16 31 292M/60 74.25 15 Transpor t Transpor t Transpor t 292M/59.94 292M/60 292M/60 292M/59.94 292M/60 292M/59.94 Transpor t Transpor t Transpor t 4004 92 92 253 11011 253 250 92 253 253 250 4004 4004 4004 11000 11000 11000 11000 11011 11000 4004 92 92 92 4000 92 91 92 92 92 91 4004 4000 4004 4000 4004 4000 4000 4000 4004 1000 1000 1000 1000 1000 1000 M Feedback Divider VCXO PLL 27 27 27 26.973027 26.973027 27 27 27 26.973027 27 27 27 26.973027 27 27 27 27 26.973027 26.973027 27 27 26.973027 27 26.973027 27 26.973027 XTAL Frequency (MHz) 8 24 24 24 na na na na 22 22 22 22 22 22 na na na 18 18 12 na na na na 8 8 8 8 8 8 na na na 8 22 22 8 8 na na 4 4 8 8 N Output Divider 22 22 na na 22 22 22 22 MF Feedback Divider FemtoClock PLL CONTINUED ON NEXT PAGE 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 VCO_SEL 36 36 54 26.973027 26.973027 27 27 74.25 74.17582418 74.25 74.25 74.25 74.17582418 27 27 27 74.25 74.17582418 74.17582418 74.25 27 26.973027 148.5 148.3516484 74.25 74.17582418 Output Frequency (MHz) Output Description 259M Level "D" Oversample 259M Level "D" Oversample ITU-R601/656 Oversample Transpor t x 1000/1001 Transpor t x 1000/1001 Transpor t Transpor t SMPTE 292M/60 SMPTE 292M/59.94 SMPTE 292M/60 (1080P) SMPTE 292M/60 HD B SMPTE 292M/59.94 Transpor t Transpor t Transpor t SMPTE 292M/60 SMPTE 292M/59.94 SMPTE 292M/59.94 SMPTE 292M/60 Transpor t Transpor t x 1000/1001 SMPTE 292M/60 (1080P) SMPTE 292M/59.94 (1080P) SMPTE 292M/60 SMPTE 292M/59.94 Integrated Circuit Systems, Inc. 32 292M/59.94 74.175824 14 292M/60 292M/59.94 292M/60 74.25 292M/59.94 1000 1001 Transpor t Transpor t 74.175824 27 6 12 27 5 1001 1000 Transpor t Transpor t 13 27 74.25 27 3 4 1000 1001 P Input Divider Transpor t 74.175824 27 2 Transpor t 11 27 1 Reference Clock Description 10 Input Reference Frequency (MHz) Configuration Example Number TABLE 3D. EXAMPLE FREQUENCY CONFIGURATION TABLE, PRELIMINARY ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL REV. A AUGUST 12, 2005 810001BK-21 0.015625 0.015734 64 65 0.015625 0.015734 NTSC Hsync PAL Hsync NTSC Hsync PAL Hsync 0.015734 61 62 NTSC Hsync 0.015625 60 63 PAL Hsync F1 50 Reference Clock Description Input Reference Frequency (MHz) Configuration Example Number 1 1 1 1 1 1 92 P Input Divider 1716 1728 1716 1728 910 1135 92 M Feedback Divider VCXO PLL TABLE 3D. EXAMPLE FREQUENCY CONFIGURATION TABLE 27 27 27 27 14.31818 17.735 F1 XTAL Frequency (MHz) 24 24 na na na na na FC Feedback Divider 12 12 na na na na na N Output Divider FemtoClock PLL 1 1 0 0 0 0 0 VCO_SEL 54 54 27 27 14.31818 17.735 F1 Output Frequency (MHz) Output Clock Description ITU-R601/656 Oversample ITU-R601/656 Oversample Transpor t Transpor t 4x NTSC subcarrier (4xFsc) 4x PAL subcarrier (4xFsc) F1 = 15 to 30MHz PRELIMINARY Integrated Circuit Systems, Inc. www.icst.com/products/hiperclocks.html 6 ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 34.8°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = VDDX = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V VDDX Charge Pump Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 210 mA IDDA Analog Supply Current 10 mA IDDO Output Supply Current IDDX Charge Pump Supply Current 5 mA TBD mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = VDDX = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VIH Input High Voltage 3.0 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current VDD = VIN = 3.465V 150 µA VDD = VIN = 3.465V 5 µA IIL Input Low Current Test Conditions CLK0, CLK1, MR, MF, P1:P0, V3:0, N1:0, CLK_SEL, XTAL_SEL OE, nBP0, nBP1 CLK0, CLK1, MR, MF, P1:P0, V3:0, N1:0, CLK_SEL, XTAL_SEL OE, nBP0, nBP1 VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 Minimum Typical VDD = 3.465V, VIN = 0V -5 µA VDD = 3.465V, VIN = 0V -150 µA 2.6 V 0.5 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. 810001BK-21 www.icst.com/products/hiperclocks.html 7 REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Typical Maximum Mode of Oscillation Units Fundamental 35 MHz Equivalent Series Resistance (ESR) Frequency 14 50 Ω Shunt Capacitance 7 pF VCXO KVCO (KVCXO); NOTE 1 Frequency Pull Range (FP); NOTE 1 7000 Hz/V 100 ppm Drive Level NOTE 1: These parameters are only guaranteed when using an ICS recommended quar tz cr ystal device. Contact ICS regarding quar tz cr ystal device recommendations. 1 mW TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = VDDX = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT tjit(ø) t R / tF Output Frequency RMS Phase Jitter, (Random), Configuration 3 of Table 3D; NOTE 1 Output Rise/Fall Time Test Conditions Minimum Maximum Units nBP0, nBP1 = 00 14 35 MHz nBP1 = 1 31 175 MHz 148.3516484MHz, (Integration Range: 12kHz - 20MHz) 0.81 ps 20% to 80% 450 ps 50 % odc Output Duty Cycle See Parameter Measurement Information section. NOTE 1: Please refer to the Phase Noise Plot. 810001BK-21 Typical www.icst.com/products/hiperclocks.html 8 REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL TYPICAL PHASE NOISE AT 148.3516484MHZ ➤ 0 Fibre Channel Filter 148.3516484MHz RMS Phase Noise Jitter 12k to 20MHz = 0.81ps (typical) Raw Phase Noise Data -90 -100 -110 -120 -130 -140 -150 -160 ➤ Z (dBc H ) -40 -50 -60 -70 -80 ➤ PHASE NOISE -10 -20 -30 Phase Noise Result by adding Fibre Channel Filter to raw data -170 -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 810001BK-21 www.icst.com/products/hiperclocks.html 9 REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL PARAMETER MEASUREMENT INFORMATION 1.65V±5% Phase Noise Plot Noise Power SCOPE VDD, VDDA, VDDO, VDDX Qx LVCMOS Phase Noise Mask VEE f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot -1.65V±5% PHASE JITTER 3.3V OUTPUT LOAD AC TEST CIRCUIT V DDO 80% 80% tR tF 2 Q t PW t odc = Clock Outputs PERIOD t PW 20% 20% x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD 810001BK-21 OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 10 REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL APPLICATION INFORMATION EXAMPLE LOOP FILTER COMPONENT VALUES VCXO PLL Divider Selection FOR VARIOUS VCXO DIVIDER SELECTIONS Loop Filter Component Selection VCXO PLL Performance Rset (kΩ ) Iset (µA) Rs (kΩ ) Cs (µF) Cp (pF) VCXO PLL Loop BW (Hz/-3dB) Damping Factor Loop Filter Example Number 2.2 500 261 0.033 1500 200 1.4 1 4.4 250 261 0.068 3300 100 1.4 2 4.4 250 53.6 1.5 68000 20 1.4 3 2.2 500 499 0.033 1500 100 1.3 4 2.2 500 261 0.15 6800 50 1. 5 5 2.2 500 105 1 33000 20 1.6 6 4.4 250 23.2 1 33000 100 1.6 7 600 170 1.8 800 125 1.6 105 1.5 100 1.4 1726, 1728 58 1 4000, 4004 27 0.7 100 1.5 FB Divider (MValue) 1000, 1001 4000, 4001 91, 92 960 1000, 1000 1726, 1728 810001BK-21 4.4 2.2 250 500 261 1000 0.068 0.01 2200 47 0 www.icst.com/products/hiperclocks.html 11 8 9 REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL 0 CLK0 = 27 MHz 0 CLK1 = GND 1 VCXO Input Pre-Divider XTAL_SEL = 1 XTAL_OUT1 1 Phase Detector VCXO Charge Pump = 1000 VCXO Feedback Divider = 1000 CLK_SEL = 0 V3:V0 = 0000 27.000 MHz XTAL_IN1 XTAL_OUT0 XTAL_IN0 LF1 LF0 RSET = 4.4k (Makes ISET = 250 A) ISET Cs = 0.068 F Rs = 261 k Cp = 3300 pf VCXO PLL Loop Characteristics with this configuration: - Bandwidth (-3dB) = 100 Hz - Damping Factor = 1.4 26.973 MHz APPLICATION EXAMPLE 1: 27MHZ TO 74.25MHZ 4 VCXO Divider Table VCXO Jitter Attenuation PLL 01 10 11 MR = 0 FemtoClock Frequency Multiplier 10 11 = x 22 Master Reset Output Divider 00 = 4 01 = 8 10 = 12 11 = 18 00 01 10 11 Q = 74.25 MHz OE = 1 MF = 0 N1:N0 = 01 nBP1:nBP0 = 11 810001BK-21 2 2 www.icst.com/products/hiperclocks.html 12 REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL 0 CLK0 = 27 MHz 0 CLK1 = GND 1 VCXO Input Pre-Divider XTAL_SEL = 0 XTAL_OUT1 1 Phase Detector VCXO Charge Pump = 1001 VCXO Feedback Divider = 1000 CLK_SEL = 0 V3:V0 = 0001 27.000 MHz XTAL_IN1 XTAL_IN0 LF1 LF0 RSET = 4.4k (Makes ISET = 250 A) ISET Cs = 0.068 F Rs = 261 k Cp = 3300 pf XTAL_OUT0 VCXO PLL Loop Characteristics with this configuration: - Bandwidth (-3dB) = 100 Hz - Damping Factor = 1.4 26.973 MHz APPLICATION EXAMPLE 2: 27MHZ TO 74.175MHZ 4 VCXO Divider Table VCXO Jitter Attenuation PLL 01 MR = 0 10 FemtoClock Frequency Multiplier 11 = x 22 10 11 Master Reset Output Divider 00 = 4 01 = 8 10 = 12 11 = 18 00 01 10 11 Q = 74.125 MHz OE = 1 MF = 0 N1:N0 = 01 nBP1:nBP0 = 11 810001BK-21 2 2 www.icst.com/products/hiperclocks.html 13 REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL DESCRIPTION OF THE PLL STAGES SETTING THE VCXO PLL LOOP RESPONSE The ICS843002-21 is a two stage device, a VCXO PLL followed by a low phase noise FemtoClock frequency multiplier. The VCXO uses an external pullable crystal which can be pulled ±100ppm by the VCXO PLL circuitry to phase lock it to the input reference frequency. There are two VCXO crystal ports in order to provide VCXO frequency versatility. For HDTV applications, this allows the use of a 26.973027MHz crystal for the generation of 74.175MHz, or a 27.00MHz crystal for the generation of 74.25MHz, for example. The VCXO PLL loop response is determined both by fixed device characteristics and by other characterizes set by the user. This includes the values of RS, CS, CP and RSET as shown in the External VCXO PLL Components figure on this page. The VCXO output frequency can be output directly from the device, or it can be passed to the FemtoClock frequency multiplier which will multiply it up to a higher frequency. WHERE: RS = Value of resistor RS in loop filter in Ohms The VCXO PLL loop bandwidth is approximated by: NBW (VCXO PLL) = ICP = Charge pump current in amps (see table on page 12) KO = VCXO Gain in Hz/V Feedback Divider = 1 to 11011 (as determined by inputs V3:V0) VCXO PLL LOOP RESPONSE CONSIDERATIONS Loop response characteristics of the VCXO PLL is affected by the VCXO feedback divider value (bandwidth and damping factor), and by the external loop filter components (bandwidth, damping factor, and 2nd frequency response). A practical range of VCXO PLL bandwidth is from about 1Hz to about 1kHz. The setting of VCXO PLL bandwidth and damping factor is covered later in this document. A PC based PLL bandwidth calculator is also under development. For assistance with loop bandwidth suggestions or value calculation, please contact ICS applications. The above equation calculates the “normalized” loop bandwidth (denoted as “NBW”) which is approximately equal to the - 3dB bandwidth. NBW does not take into account the effects of damping factor or the second pole imposed by CP. It does, however, provide a useful approximation of filter performance. To prevent jitter on the clock output due to modulation of the VCXO PLL by the phase detector frequency, the following general rule should be observed: Table 3A shows frequency translation configuration examples. Note that in the first two V3:V0 selections the VCXO PLL feedback divider is the same value of 1000. This means the VCXO PLL loop response (bandwidth and damping factor) will be the same for all of these settings. NBW (VCXO PLL) ≤ ƒ (Phase Detector) 20 ƒ(Phase Detector) = Input Frequency ÷ Pre-Divider) The same is true for V3:V0 = 0010 through 0110. This means the device can be configured to translate between 74.175MHz, 74.25MHz, and 27MHz (from any one to another, all nine combinations) and it will maintain the same loop response characteristics. This is also true for V3:V0 = 1000 through 1010. The PLL loop damping factor is determined by: DF = x For high VCXO PLL feedback divider values, the phase detector rate, and therefore loop filter charge pulse rate, is greatly reduced. To prevent output clock wander, low leakage capacitors should be used. In addition, when loop bandwidth is low (say below 20Hz), capacitors with low microphonic sensitivity should be used. PPS film type capacitors are one type that perform well in this environment. Below 5Hz, shielding should be considered to prevent excessive phase wander (low frequency phase jitter or clock phase deviation). 810001BK-21 RS x ICP x KO 2π x Feedback Divider RS ICP x CS x KO 2 Feedback Divider WHERE: CS = Value of capacitor CS in loop filter in Farads www.icst.com/products/hiperclocks.html 14 REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL EXTERNAL VCXO PLL COMPONENTS The best way to set the value of CP is to use the filter response software available from ICS (please refer to the following section). CP should be increased in value until it just starts affecting the passband peak. In general, the loop damping factor should be 0.7 or greater to ensure output stability. A higher damping factor will create less peaking in the passband. A higher damping factor may also increase lock time and output clock jitter when there is excess digital noise in the system application, due to the reduced ability of the PLL to respond to and therefore compensate for phase noise ingress. LF1 LF0 CP RS ISET 64 1 27/30 NOTES ON EXTERNAL CRYSTAL LOAD CAPACITORS In the loop filter schematic diagram, capacitors are shown between pins 27/30 to ground and between pins 38/31 to ground. These are optional crystal load capacitors which can be used to center tune the external pullable crystal (the crystal frequency can only be lowered by adding capacitance, it cannot be raised). Note that the addition of external load capacitors will decrease the crystal pull range and the Kvco value. 28/31 2 LOOP FILTER RESPONSE SOFTWARE 3 Online tools to calculate loop filter response can be found at www.icst.com. Contact your local sales representative if a tool cannot be found for this product. CS RSET The external crystal devices and loop filter components should be kept close to the device. Loop filter and crystal PCB connection traces should be kept short and well separated from each other and from other signal traces. Other signal traces shouldnot run underneath the device, the loop filter or crystal components. NOTES ON SETTING THE VALUE OF CP As another general rule, the following relationship should be maintained between components CS and CP in the loop filter: CP = CS 20 CP establishes a second pole in the VCXO PLL loop filter. For higher damping factors (> 1), calculate the value of CP based on a CS value that would be used for a damping factor of 1. This will minimize baseband peaking and loop instability that can lead to output jitter. CP also dampens VCXO PLL input voltage modulation by the charge pump correction pulses. A CP value that is too low will result in increased output phase noise at the phase detector frequency due to this. In extreme cases where input jitter is high, charge pump current is high, and CP is too small, the VCXO PLL input voltage can hit the supply or ground rail resulting in nonlinear loop response. 810001BK-21 www.icst.com/products/hiperclocks.html 15 REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL VCXO CRYSTAL SELECTION accuracy of a VCXO. Below are the key variables and an example of using the crystal parameters to calculate the tuning range of the VCXO. Choosing a crystal with the correct characteristics is one of the most critical steps in using a Voltage Controlled Crystal Oscillator (VCXO). The crystal parameters affect the tuning range and VC Oscillator “Control Voltage” CV CV VCXO (Internal) XTAL CS1 CS2 CL1 CL2 Optional FIGURE 1: VCXO OSCILLATOR CIRCUIT EXAMPLE CL1, CL2 Load tuning capacitance used for fine tuning or centering nominal frequency VC Control voltage used to tune frequency CV Varactor capacitance, varies due to the change in control voltage CS1, CS2 Stray Capacitance caused by pads, vias, and other board parasitics CRYSTAL PARAMETER EXAMPLES Symbol Parameter fN Nominal Frequency fT Frequency Tolerance fS Frequency Stability Minimum Typical Maximum 19.44 Operating Temperature Range 0 Units MHz ±20 ppm ±20 pp m 70 °C CL Load Capacitance 12 pF CO Shunt Capacitance 4 pF C0/C1 Pullability Ratio ESR Equivalent Series Resistance 22 0 240 20 Drive Level 1 Aging @ 25°C ±3 per year mW ppm Fundemental Mode of Operation VARACTOR PARAMETERS Symbol Parameter Test Condition Typical Unit CV LOW Low Varactor Capacitance VC = 0V 15.4 pF CV HIGH High Varactor Capacitance VC = 3.3V 29.6 pF 810001BK-21 www.icst.com/products/hiperclocks.html 16 REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL FORMULAS CLOW = (CL1 + CS1 + CV_LOW) · (CL2 + CS2 + CV_LOW) CHIGH = (CL1 + CS1 + CV_LOW) + (CL2 + CS2 + CV_LOW) CHigh is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance. CHigh determines the low frequency component on the TPR (Total Pull Range). CLow is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance. CLow determines the high frequency component on the TPR (Total Pull Range). ( 1 TPR = 2 · C0/C1 · (1+CLOW /C0) – 1 2 · C0/C1 · (1+CHIGH/C0) (CL1 + CS1 + CV_HIGH · (CL2 + CS2 + CV_HIGH) (CL1 + CS1 + CV_HIGH) + (CL2 + CS2 + CV_HIGH) ) · 106 AbsolutePullRange (APR) = TotalPullRange – (FrequencyTolerance + FrequencyStability + Aging) EXAMPLE CALCULATIONS the inaccuracy due to aging is ±15ppm. Third, though many boards will not require load tuning capacitors (CL1, CL2), it is recommended for long-term consistent performance of the system that two tuning capacitor pads be placed into every design. Typical values for the load tuning capacitors will range from 0 to 4pF. Using the tables and figures above, we can now calculate the TPR and APR of the VCXO using the example crystal parameters. For the numerical example below there were some assumptions made. First, the stray capacitance (CS1, CS2), which is all the excess capacitance due to board parasitic, is 4pF. Second, the expected lifetime of the project is 5 years; hence CLOW = ( TPR = (0 + 4pF + 15.4pF) · (0 + 4pF + 15.4pF) = 9.7pF CHIGH = (0 + 4pF + 15.4pF) + (0 + 4pF + 15.4pF) 1 2 · 220 · (1+9.7pF/4pF) – 1 2 · 220 · (1+16.8pF/4pF) ) (0 + 4pF + 29.6pF) · (0 + 4pF + 29.6pF) = 16.8pF (0 + 4pF + 29.6pF) + (0 + 4pF + 29.6pF) · 106 = 226.5ppm TPR = ±113.25ppm APR = 113.25ppm – (20ppm + 20ppm + 15ppm) = ±58.25ppm The example above will ensure a total pull range of ±113.25 ppm with an APR of ±58.25ppm. Many times, board designers may select their own crystal based on their application. If the application requires a tighter APR, a crystal with better pullability 810001BK-21 (C0/C1 ratio) can be used. Also, with the equations above, one can vary the frequency tolerance, temperature stability, and aging or shunt capacitance to achieve the required pullability. www.icst.com/products/hiperclocks.html 17 REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL NOTES ON SETTING CHARGE PUMP CURRENT The recommended range for the charge pump current is 50μA to 300μA. Below 50μA, loop filter charge leakage, due to PCB or capacitor leakage, can become a problem. This loop filter leakage can cause locking problems, output clock cycle slips, or low frequency phase noise. As can be seen in the loop bandwidth and damping factor equations or by using the filter response software available from ICS, increasing charge pump current (ICP) increases both bandwidth and damping factor. CHARGE PUMP CURRENT, EXAMPLE SETTINGS RSET Charge Pump Current (ICP) 17.6k 62.5µA 8.8k 125µA 4.4k 250µA 2.2k 500µA ICP, Amps 1E-3 100E-6 10E-6 1k 10k RSET, Ω FIGURE 2. CHARGE PUMP CURRENT VS. VALUE OF 100k RSET (EXTERNAL RESISTOR) GRAPH POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS810001-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, VDDx, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 3 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VDDA pin. 810001BK-21 3.3V VDD .01μF 10Ω V DDA .01μF 10μF FIGURE 3. POWER SUPPLY FILTERING www.icst.com/products/hiperclocks.html 18 REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN θJA vs. 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 34.8°C/W TRANSISTOR COUNT The transistor count for ICS810001-21 is: 9365 810001BK-21 www.icst.com/products/hiperclocks.html 19 REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE AND ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS VHHD-2 SYMBOL MINIMUM NOMINAL 32 N A 0.80 A1 0 -- 1.00 -- 0.05 0.25 Ref. A3 b 0.18 0.25 8 NE 5.00 BASIC D 1.25 2.25 1.25 2.25 3.25 0.50 BASIC e L 3.25 5.00 BASIC E E2 0.30 8 ND D2 MAXIMUM 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 810001BK-21 www.icst.com/products/hiperclocks.html 20 REV. A AUGUST 12, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS810001-21 FEMTOCLOCKS™ DUAL VCXO VIDEO PLL TABLE 9. ORDERING INFORMATION Part/Order Number ICS810001BK-21 ICS810001BK-21T Marking ICS10001B21 ICS10001B21 Package 32 Lead VFQFN 32 Lead VFQFN Shipping Packaging tray 2500 tape & reel Temperature 0°C to 70°C 0°C to 70°C The aforementioned trademarks, HiPerClockS™ and FEMTOCLOCKS™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 810001BK-21 www.icst.com/products/hiperclocks.html 21 REV. A AUGUST 12, 2005