IDT ICS843002I-72

ICS843002I-72
FEMTOCLOCKS™ VCXO BASED WCDMA
CLOCK GENERATOR/JITTER ATTENUATOR
GENERAL DESCRIPTION
FEATURES
The ICS843002I-72 is a member of the
ICS
HiperClockS™ family of high performance clock
HiPerClockS™
solutions from IDT. The ICS843002I-72 is a
PLL based synchronous clock generator that is
optimized for WCDMA channel card applications
where jitter attenuation and frequency translation is needed.
The device contains two internal PLL stages that are cascaded
in series. The first PLL stage uses a VCXO which is optimized
to provide reference clock jitter attenuation and to be jitter
tolerant, and to provide a stable reference clock for the second
PLL stage. The second PLL stage provides additional frequency
multiplication (x32), and it maintains low output jitter by using a
low phase noise FemtoClock™ VCO. The device performance
and the PLL multiplication ratios are optimized to support
WCDMA applications. The VCXO requires the use of an
external, inexpensive pullable crystal. VCXO PLL uses external
passive loop filter components which are used to optimize the
PLL loop bandwidth and damping characteristics for the given
application.
• Two differential LVPECL outputs
• CLK input accepts the following input levels:
LVCMOS or LVTTL levels
• Output frequency: 122.88MHz (typical)
• FemtoClock VCO frequency range: 490MHz - 680MHz
• RMS phase jitter @ 122.88MHz, using a 19.2MHz crystal
(1.875MHz to 10MHz): 0.49ps (typical)
• Deterministic jitter: 30fs (typical)
• Random jitter, RMS: 2.2ps (typical)
• Full 3.3V or mixed 3.3V core/2.5V output supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
The ICS843002I-72 can accept a single-ended input. LOCK_DT
reports the lock status of VCXO PLL loop. If the reference clock
input is lost, it will set LOCK_DT to logic LOW.
Typical ICS843002I-72 configuration in WCDMA Systems:
• 19.2MHz pullable crystal
PIN ASSIGNMENT
• Input Reference clock frequency: 3.84MHz
nc
VEE
VEE
VCC
VCC
VCC
XTAL_IN
XTAL_OUT
• Output clock frequency: 122.88MHz
32 31 30 29 28 27 26 25
LF1
1
24
LF0
2
23
VEE
ISET
3
22
VCC
VCC
4
21
VCCO
VCC
5
20
VCCO
VEE
6
19
nQ1
VEE
7
18
Q1
CLK
8
17
VEE
LOCK_DT
Q0
nQ0
VEE
VCCO
VCCA
VEE
nOE
VEE
9 10 11 12 13 14 15 16
ICS843002I-72
32-Lead VFQFN
5mm x 5mm x 0.925 package body
K Package
Top View
IDT ™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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ICS843002BKI-72 REV. A NOVEMBER 21, 2007
ICS843002I-72
FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
BLOCK DIAGRAM
122.88MHz
CLK
Q0
FemtoClock
x32
3.84MHz
Pulldown
nQ0
XTAL_IN
19.2MHz
VCXO
Pullable Xtal
÷5
Phase
Detect
XTAL_OUT
External
Loop
Components
LF0
LF1
Q1
Charge
Pump
nQ1
Pulldown
nOE
LF
ISET
LOCK_DT
NOTE 1: 19.2MHz pullable crystal shown is typical for WCDMA device applications.
IDT ™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 2
LF1, LF0
3
ISET
4, 5, 22, 28,
29, 30
6, 7, 9, 10, 13,
17, 2 3 , 2 6 , 2 7
8
11
Type
Analog
Input/Output
Analog
Input/Output
Description
Loop filter connection node pins.
Charge pump current setting pin.
VCC
Power
Core power supply pins.
VEE
Power
Negative supply pins.
CLK
Input
nOE
Input
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable pin. When LOW, output is enabled.
Pulldown
LVCMOS/LVTTL interface levels. See Table 3.
Analog supply pin.
12
VCCA
Power
14, 20, 21
VCCO
Power
Output power supply pin.
15, 16
Q0, nQ0
Output
Differential clock output pair. LVPECL interface levels.
18, 19
Q1, nQ1
Output
Differential clock output pair. LVPECL interface levels.
24
LOCK_DT
Output
Lock detect. Logic HIGH when VCXO PLL loop is locked.
25
nc
Unused
31,
XTAL_OUT,
Input
32
XTAL_IN
NOTE: Pulldown refers to internal input resistors. See Table
No connect.
Cr ystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
50
kΩ
TABLE 3. INPUT REFERENCE SELECTION FUNCTION TABLE
Inputs
Outputs
nOE
Q0/nQ0, Q1/nQ1
0
Enabled
1
Hi-Z
IDT ™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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ICS843002BKI-72 REV. A NOVEMBER 21, 2007
ICS843002I-72
FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
Storage Temperature, TSTG
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
37°C/W (0 mps)
tended periods may affect product reliability.
-65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VCC – 0.13
3. 3
VCC
V
3.135
3.3
VCCO
Output Supply Voltage
3.465
V
IEE
Power Supply Current
140
mA
ICCA
Analog Supply Current
13
mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCC – 0.13
3.3
VCC
V
2.375
2.5
VCCO
Output Supply Voltage
2.625
V
IEE
Power Supply Current
140
mA
ICCA
Analog Supply Current
13
mA
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VIH
Input High Voltage
2
VCC + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High Current
CLK, nOE
VCC = VIN = 3.465V
150
µA
IIL
InputLow Current
CLK, nOE
VCC = 3.465V, VIN = 0V
-5
µA
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
1.0
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V. See "Parameter Measurement Information" section,
"Output Load Test Circuit" diagrams.
IDT ™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
VCCO - 1.4
Typical
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.5
V
1.0
V
Maximum
Units
Peak-to-Peak Output Voltage Swing
0.4
VSWING
NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V. See "Parameter Measurement Information" section,
"Output Load Test Circuit" diagrams.
TABLE 5A. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
tDJ
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
Deterministic Jitter; NOTE 2
tRJ
Random Jitter, RMS; NOTE 2
tsk(o)
Output Skew; NOTE 3, 4
tR / tF
Output Rise/Fall Time
FOUT
tjit(ø)
Test Conditions
Minimum
122.88MHz, Integration range:
1.875MHz - 10MHz
20% to 80%
Typical
122.88
MHz
0.49
ps
30
fs
2.2
ps
30 0
odc
Output Duty Cycle
49
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Measured using Wavecrest SIA-3000.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
50
ps
55 0
ps
51
%
Maximum
Units
TABLE 5B. AC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
tDJ
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
Deterministic Jitter; NOTE 2
FOUT
tjit(ø)
tRJ
Random Jitter, RMS; NOTE 2
tsk(o)
Output Skew; NOTE 3, 4
tR / tF
Output Rise/Fall Time
Test Conditions
Minimum
122.88MHz, Integration range:
1.875MHz - 10MHz
Typical
122.88
MHz
0.49
ps
30
fs
2.2
20% to 80%
30 0
odc
Output Duty Cycle
49
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Measured using Wavecrest SIA-3000.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT ™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
5
ps
50
ps
55 0
ps
51
%
ICS843002BKI-72 REV. A NOVEMBER 21, 2007
ICS843002I-72
FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
➤
TYPICAL PHASE NOISE AT 122.88MHZ @ 3.3V/3.3V
122.88MHz
10Gb Ethernet Filter
Raw Phase Noise Data
➤
➤
NOISE POWER dBc
Hz
RMS Phase Jitter (Random)
1.875MHz to 10MHz = 0.49ps (typical)
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
IDT ™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
PARAMETER MEASUREMENT INFORMATION
2.8V±0.04V
2V
2V
2.8V±0.04V
2V
VCC,
VCCO
Qx
SCOPE
VCC VCCO
VCCA
Qx
SCOPE
VCCA
LVPECL
LVPECL
nQx
nQx
VEE
VEE
-1.3V ± 0.165V
-0.5V ± 0.125V
3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
nQx
Qx
Phase Noise Mask
nQy
Qy
f1
Offset Frequency
tsk(o)
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
PHASE JITTER
OUTPUT SKEW
nQ0, nQ1
80%
80%
Q0, Q1
VSW I N G
Clock
Outputs
t PW
t
20%
20%
tR
tF
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT RISE/FALL TIME
IDT ™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
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ICS843002BKI-72 REV. A NOVEMBER 21, 2007
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS843002I-72
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be used
for each pin. Figure 1 illustrates this for a generic VCC pin and
also shows that VCCA requires that an additional10Ω resistor
along with a 10µF bypass capacitor be connected to the VCCA pin.
3.3V or 2.5V
VCC
.01µF
10Ω
.01µF
10µF
VCCA
FIGURE 1. POWER SUPPLY FILTERING
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
IDT ™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
84Ω
FIGURE 2B. LVPECL OUTPUT TERMINATION
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ICS843002BKI-72 REV. A NOVEMBER 21, 2007
ICS843002I-72
FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination
is shown in Figure 5C.
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
R1
250
Zo = 50 Ohm
R3
250
+
Zo = 50 Ohm
+
Zo = 50 Ohm
-
Zo = 50 Ohm
2,5V LVPECL
Driv er
-
R1
50
2,5V LVPECL
Driv er
R2
62.5
R2
50
R4
62.5
R3
18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT ™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
VFQFN EPAD THERMAL RELEASE PATH
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadfame Base Package, Amkor Technology.
In order to maximize both the removal of heat from the package
and the electrical perfor mance, a land patter n must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 4. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”)
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
SOLDER
LAND PATTERN
THERMAL VIA
PIN
PIN PAD
(GROUND PAD)
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
IDT ™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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ICS843002BKI-72 REV. A NOVEMBER 21, 2007
ICS843002I-72
FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
LAYOUT GUIDELINE
Figure 5 shows an example of ICS843002I-72 application
schematic. In this example, the device is operated at VCC = 3.3V.
The 19.2MHz pullable crystal is used. The bypass capacitor
should be placed as close as possible to the power pins. Two
examples of LVPECL terminations are shown in this schematic.
Additional termination approaches are shown in the LVPECL
Termination Application Note.
Logic Control Input Examples
XTAL_OUT
C1
SP
RU2
Not Install
RD1
Not Install
To Logic
Input
pins
XTAL_IN
VCC
To Logic
Input
pins
VCC
X1
C2
SP
RD2
1K
VCC
VEE
RU1
1K
Set Logic
Input to
'0'
VCC
R1
2-pole loop filter for Mid Bandwidth setting
LF
LF
1
2
3
4
5
6
7
8
R6
VCC
VCC
100K
C3
VEE
C5
0.0001uF
CLK
LF1
LF0
ISET
VCC
VCC
VEE
VEE
CLK
LD1
3.3V
VCC
LOCK_DT
VEE
VCC
VCCO
VCCO
nQ1
Q1
VEE
24
23
22
21
20
19
18
17
+
nQ1
Zo = 50 Ohm
VCC=3.3V
-
R8
82.5
R9
82.5
VCCO=3.3V
nOE
ICS843002I_72
R4
133
Zo = 50 Ohm
Q1
9
10
11
12
13
14
15
16
R7
8K
R3
133
VCCO
VCC
VCCO
VCCO
VEE
VEE
nOE
VCCA
VEE
VCCO
Q0
nQ0
0.1uF
2.7K
XTAL_IN
XTAL_OUT
VCC
VCC
VCC
VEE
VEE
NC
U1
VCC
LOCK_DT
32
31
30
29
28
27
26
25
Set Logic
Input to
'1'
VCC
Zo = 50 Ohm
Q0
+
VCC
R10
10
Zo = 50 Ohm
nQ0
VCCA
VCC
C6
10u
C7
-
VCCO
R11
50
0.01u
C8
0.1u
(U1:4)
(U1:5)
VCC
C9
0.1uF
(U1:22)
VCC
C10
0.1uF
(U1:28)
VCC
C11
0.1uF
(U1:29)
VCC
C12
0.1uF
(U1:30)
VCC
C13
0.1uF
Optional
Y-Termination
(U1:14)
C14
0.1uF
R12
50
R13
50
(U1:20)
(U1:21)
VCCO
VCCO
C15
0.1uF
C16
0.1uF
C17
0.1uF
FIGURE 5. SCHEMATIC OF RECOMMENDED LAYOUT
IDT ™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
VCXO-PLL EXTERNAL COMPONENTS
the crystal specification. In either case, the absolute tuning
range is reduced. The correct value of CL is dependent on the
characteristics of the VCXO. The recommended CL in the Crystal
Parameter Table balances the tuning range by centering the
tuning curve.
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality
operation of the VCXO-PLL. In choosing a crystal, special
precaution must be taken with the package and load
capacitance (C L ). In addition, frequency, accuracy and
temperature range must also be considered. Since the pulling
range of a cr ystal also var ies with the package, it is
recommended that a metal-canned package like HC49 be used.
Generally, a metal-canned package has a larger pulling range
than a surface mounted device (SMD). For crystal selection
information, refer to the VCXO Crystal Selection Application
Note.
The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS
and C P values for recommended high, mid and low loop
bandwidth configurations. The device has been characterized
using these parameters. For other configurations, refer to the
Loop Filter Component Selection for VCXO Based PLLs
Application Note.
The crystal and external loop
filter components should be
kept as close as possible to the
device. Loop filter and crystal
traces should be kept short and
separated from each other.
Other signal traces should be
kept separate and not run
underneath the device, loop
filter or crystal components.
The crystal’s load capacitance CL characteristic determines its
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance,
IC package lead capacitance, internal varactor capacitance and
any installed tuning capacitors (CTUNE).
If the crystal’s CL is greater than the total external capacitance,
the VCXO will oscillate at a higher frequency than the crystal
specification. If the crystal’s C L is lower than the total external
capacitance, the VCXO will oscillate at a lower frequency than
LF0
LF1
ISET
RS
CP
RSET
CS
XTAL_IN
CTUNE
19.2MHz
XTAL_OUT
CTUNE
VCXO CHARACTERISTICS TABLE
Symbol
Parameter
Typical
Unit
kVCXO
VCXO Gain
7.8
kHz/V
CV_LOW
Low Varactor Capacitance
2
pF
CV_HIGH
High Varactor Capacitance
8
pF
VCXO-PLL APPROXIMATE LOOP BANDWIDTH SELECTION TABLE
RS (kΩ )
CS (µF)
19.2MHz
15
1.0
0.01
8
19.2MHz
10 0
0.1
0.0001
8
19.2MHz
100
0.1
0.0001
4
Bandwidth
Crystal Frequency (MHz)
75Hz (Low)
500Hz (Mid)
1kHz (High)
CP (µF)
RSET (kΩ )
CRYSTAL CHARACTERISTICS
Symbol
Parameter
Minimum
Mode of Operation
fN
Frequency
fT
Frequency Tolerance
fS
Frequency Stability
Operating Temperature Range
CL
Load Capacitance
CO
Shunt Capacitance
CO /C1
Pullability Ratio
ESR
Equivalent Series Resistance
Typical
Maximum
Units
Fundamental
19.2
MHz
-40
±20
ppm
±20
ppm
85
°C
12
pF
4
pF
22 0
24 0
20
Ω
1
mW
±3 per year
ppm
Drive Level
Aging @ 25°C
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002I-72.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843002I-72 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485.15mW
•
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 485.1mW + 60mW = 545.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 37°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.541W * 37°C/W = 105.1°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA
FOR
32-PIN VFQFN, FORCED CONVECTION
θJA vs. Air Flow (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
IDT ™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
13
0
1
2.5
37.0°C/W
32.4°C/W
29.0°C/W
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V – 2V.
CCO
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/R ] * (VCCO_MAX – VOH_MAX) = [(2V – (V
L
CCO_MAX
– VOH_MAX))/R ] * (VCCO_MAX – VOH_MAX) =
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/R ] * (VCCO_MAX – VOL_MAX) = [(2V – (V
L
CCO_MAX
– VOL_MAX))/R ] * (VCCO_MAX – VOL_MAX) =
L
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT ™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
32 LEAD VFQFN
θJA vs. Air Flow (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
37.0°C/W
32.4°C/W
29.0°C/W
TRANSISTOR COUNT
The transistor count for ICS843002I-72 is: 3199
IDT ™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
L
A3
N
N
e (Ty p.)
2 If N & N
1
Anvil
Singula tion
are Even
2
OR
E2
(N -1)x e
(Re f.)
E2
2
To p View
b
A
(Ref.)
D
e
D2
2
N &N
Odd
0. 08
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
C
Th er mal
Ba se
D2
C
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of
this device. The pin count and pinout are shown on the front page.
The package dimensions are in Table 11 below.
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS (VHHD -2/ -4)
SYMBOL
Minimum
Maximum
32
N
A
0.80
1. 0
A1
0
0.05
0.25 Reference
A3
b
0.18
0.30
e
0.50 BASIC
ND
8
NE
8
5.0 BASIC
D, E
D2, E2
3.0
3.3
L
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
IDT ™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
843002BKI-72LF
ICS002BI72L
32 lead "Lead-Free" VFQFN
tube
-40°C to 85°C
843002BKI-72LFT
ICS002BI72L
32 lead "Lead-Free" VFQFN
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT ™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
800-345-7015
408-284-8200
Fax: 408-284-2775
[email protected]
480-763-2056
Corporate Headquarters
Asia Pacific and Japan
Europe
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
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