R61505U 262,144-color, 240RGB x 320 dot graphics liquid crystal controller driver for Amorphous-Silicon TFT Panel REJxxxxxxx-xxxx Rev.1.0 September 13, 2006 Description ......................................................................................................... 6 Features ......................................................................................................... 7 Difference between R61505 and R61505U................................................................................................................. 10 Block Diagram .................................................................................................... 11 Block Function .................................................................................................... 12 1. System Interface .................................................................................................................................................... 12 2. External Display Interface (RGB, VSYNC interfaces) ....................................................................................... 13 3. Address Counter (AC) ........................................................................................................................................... 13 4. Graphics RAM (GRAM) ....................................................................................................................................... 14 5. Grayscale Voltage Generating Circuit ................................................................................................................. 14 6. Liquid crystal drive power supply circuit ............................................................................................................. 14 7. Timing Generator .................................................................................................................................................. 14 8. Oscillator (OSC) .................................................................................................................................................... 14 9. Liquid crystal driver Circuit.................................................................................................................................. 14 10. Internal logic power supply regulator .................................................................................................................. 14 Pin Function ........................................................................................................ 15 PAD arrangement................................................................................................ 22 PAD coordinates ................................................................................................. 24 BUMP arrangement ............................................................................................ 39 Connection example............................................................................................ 40 GRAM address map ............................................................................................ 41 Instruction ......................................................................................................... 43 Outline .......................................................................................................................................................................... 43 Instruction Data Format ............................................................................................................................................. 43 Index (IR) ..................................................................................................................................................................... 44 Display control ............................................................................................................................................................. 44 Device code read (R00h)........................................................................................................................................ 44 Rev. 1.0 September 13, 2006, page 1 of 199 R61505U Driver Output Control (R01h)................................................................................................................................45 LCD Driving Wave Control (R02h) .......................................................................................................................45 Entry Mode (R03h) .................................................................................................................................................46 Resizing Control (R04h) .........................................................................................................................................49 Display Control 1 (R07h) .......................................................................................................................................50 Display Control 2 (R08h) .......................................................................................................................................52 Note on Setting BP and FP.....................................................................................................................................52 Display Control 3 (R09h) .......................................................................................................................................53 Display Control 4 (R0Ah).......................................................................................................................................55 External Display Interface Control 1 (R0Ch)........................................................................................................55 Frame Marker Position (R0Dh) .............................................................................................................................57 External Display Interface Control 2 (R0Fh) ........................................................................................................58 Power control ...............................................................................................................................................................59 Power Control 1 (R10h) .........................................................................................................................................59 Power Control 2 (R11h) .........................................................................................................................................62 Power Control 3 (R12h) .........................................................................................................................................63 Power Control 4 (R13h) .........................................................................................................................................65 Power Control 5 (R17h) .........................................................................................................................................65 RAM access instruction ...............................................................................................................................................66 RAM Address Set (Horizontal Address) (R20h) RAM Address Set (Vertical Address) (R21h) ............................66 Write Data to GRAM (R22h)..................................................................................................................................67 Read Data from GRAM (R22h) ..............................................................................................................................70 NVM(NON-VOLATILE MEMORY) write control instruction.................................................................................71 NVM read data (R28h), VCOM High Voltage (R29h, R2Ah)................................................................................71 γ Control .......................................................................................................................................................................74 γ Control 1 ~ 14 (R30h to R3Dh) ...........................................................................................................................74 Window address control instruction............................................................................................................................76 Window Horizontal RAM Address Start/End (R50h/ R51h) ..................................................................................76 Window Vertical RAM Address Start/End (R52h/R53h) .......................................................................................76 Base image display control instruction .......................................................................................................................77 Driver Output Control (R60h),...............................................................................................................................77 Base Image Display Control (R61h) ......................................................................................................................77 Vertical Scroll Control (R6Ah)...............................................................................................................................77 Partial display control instruction...............................................................................................................................80 Partial Image 1: Display Position (R80h), RAM Address (Start/End Line Address) (R81h/R82h)......................80 Partial Image 2: Display Position (R83h), RAM Address (Start/End Line Address) (R84h/R85h)......................80 Panel interface control instruction .............................................................................................................................81 Panel interface control 1(R90h).............................................................................................................................81 Panel interface control 2(R92h).............................................................................................................................82 Panel interface control 3(R93h).............................................................................................................................83 Panel interface control 4(R95h).............................................................................................................................84 Panel interface control 5(R97h).............................................................................................................................86 Panel interface control 6(R98h).............................................................................................................................86 NVM(NON-VOLATILE MEMORY) control .............................................................................................................87 NVM access control 1 (RA0h), NVM access control 2 (RA1h) .............................................................................87 Calibration control (RA4h) ....................................................................................................................................88 Setting disabled instruction (Inhibition RA5h ~ RFFh) ...........................................................................................89 Rev.1.0 September 13, 2006, page 2 of 199 R61505U Instruction List .................................................................................................... 90 Reset Function..................................................................................................... 91 Basic mode operation of the R61505U ............................................................... 93 Interface and data format .................................................................................... 94 System Interface.................................................................................................. 97 80-system 18-bit Bus Interface .................................................................................................................................... 98 80-system 16-bit Bus Interface .................................................................................................................................... 99 Data Transfer Synchronization in 16-bit Bus Interface operation ........................................................................... 101 80-system 9-bit Bus Interface ...................................................................................................................................... 102 Data Transfer Synchronization in 9-bit Bus Interface operation ............................................................................. 103 80-system 8-bit Bus Interface ...................................................................................................................................... 104 Data Transfer Synchronization in 8-bit Bus Interface operation ............................................................................. 106 Serial Interface............................................................................................................................................................. 107 VSYNC Interface ................................................................................................ 110 Notes to VSYNC Interface operation .......................................................................................................................... 112 External Display Interface................................................................................... 114 RGB Interface .............................................................................................................................................................. 115 Polarities of VSYNC, HSYNC, ENABLE, and DOTCLK Signals ............................................................................ 115 RGB Interface Timing ................................................................................................................................................. 116 16-/18-bit RGB Interface Timing ........................................................................................................................... 116 6-bit RGB Interface Timing.................................................................................................................................... 117 RAM access via system interface in RGB interface operation .................................................................................. 118 6-bit RGB interface ...................................................................................................................................................... 120 Data Transfer Synchronization in 6-bit Bus Interface operation ............................................................................. 121 16-bit RGB interface .................................................................................................................................................... 122 18-bit RGB interface .................................................................................................................................................... 123 Notes to external display interface operation ............................................................................................................. 124 RAM Address and Display Position on the Panel .............................................. 126 Restrictions in setting display control instruction...................................................................................................... 127 Instruction setting example ......................................................................................................................................... 129 Resizing function ................................................................................................ 131 Resizing setting............................................................................................................................................................. 132 Example of 1/2 resizing ............................................................................................................................................... 133 Resizing instruction ..................................................................................................................................................... 133 Notes to Resizing function ........................................................................................................................................... 134 FMARK function ................................................................................................ 135 FMP setting example ................................................................................................................................................... 136 Display operation synchronous data transfer using FMARK................................................................................... 137 Notes to display operation synchronous data transfer using FMARK signal .......................................................... 139 Rev.1.0 September 13, 2006, page 3 of 199 R61505U High-speed RAM Write Function....................................................................... 140 Notes to high-speed RAM write function....................................................................................................................141 High-speed RAM data write in a window address area .............................................................................................142 Window Address Function ................................................................................. 143 Scan Mode Setting .............................................................................................. 144 8-color Display Mode ......................................................................................... 145 Line Inversion AC Drive .................................................................................... 146 Alternating Timing.......................................................................................................................................................147 Frame-Frequency Adjustment Function ............................................................. 148 Relationship between liquid crystal drive duty and frame frequency .......................................................................148 Partial Display Function ..................................................................................... 149 Liquid crystal panel interface timing .................................................................. 150 Internal clock operation...............................................................................................................................................150 RGB interface operation..............................................................................................................................................151 Oscillator ......................................................................................................... 152 γ Correction function .......................................................................................... 153 γ Correction registers ...................................................................................................................................................153 γ Correction register settings and γ curve relationship ..............................................................................................155 Power-supply Generating Circuit ....................................................................... 156 Power supply circuit connection example 1 (VCI1 = VCIOUT) ...............................................................................156 Power supply circuit connection example 2 (VCI1 = VCI direct input) ...................................................................157 Specifications of Power-supply Circuit External Elements................................ 158 Voltage Setting Pattern Diagram ........................................................................ 159 Liquid crystal application voltage waveform and electrical potential.......................................................................160 VCOMH voltage adjustment sequence............................................................... 161 NVM control sequence ....................................................................................... 163 NVM Write In Sequence..............................................................................................................................................164 NVM Read Out Sequence ............................................................................................................................................164 Power supply Instruction Setting ........................................................................ 167 Notes to Power Supply ON sequence ................................................................. 168 Instruction setting................................................................................................ 169 Rev.1.0 September 13, 2006, page 4 of 199 R61505U Display ON/OFF sequences ........................................................................................................................................ 169 Sleep mode SET/EXIT sequences ............................................................................................................................... 170 Deep standby mode IN/EXIT sequences..................................................................................................................... 171 8-color mode setting..................................................................................................................................................... 174 Partial display setting................................................................................................................................................... 174 Absolute Maximum Ratings ........................................................................................................................................ 175 Electrical Characteristics..................................................................................... 176 DC characteristics (VCC= 2.50V~3.30V,IOVCC=1.65V~3.30V,Ta=-40C~+85C See note 1)...................... 176 Step-Up Circuit Characteristics............................................................................................................................. 178 Internal Reference Voltage (Condition: VCC= 2.50V~3.30V, Ta=-40℃~+85℃) .......................................... 178 AC Characteristics ....................................................................................................................................................... 179 1. Clock Characteristics ......................................................................................................................................... 179 2. 80-System Bus Interface Timing Characteristics (18-/ 16- bit interface) ....................................................... 179 3. 80-System Bus Interface Timing Characteristics (9-/ 8- bit interface) ............................................................. 181 4. Clock-synchronized Serial Interface Timing Characteristics............................................................................ 182 5. Reset Timing Characteristics (IOVCC=1.65~3.30V)........................................................................................ 182 6. RGB Interface Timing Characteristics .............................................................................................................. 183 7. LCD driver Output Characteristics ................................................................................................................... 184 Notes on Electrical Characteristics ....................................................................................................................... 185 Rev.1.0 September 13, 2006, page 5 of 199 R61505U Description The R61505U is a single-chip liquid crystal controller driver LSI for a-Si TFT panel, comprising RAM for a maximum 240 RGB x 320 dot graphics display, source driver, gate driver and power supply circuit. For efficient data transfer, the R61505U supports high-speed interface via 8-/9-/16-/18-bit ports as system interface to the microcomputer and high-speed RAM write function. As moving picture interface, the R61505U supports RGB interface (VSYNC, HSYNC, DOTCLK, ENABLE, DB17-0). Also, the R61505U incorporates step-up circuit and voltage follower circuit to generate TFT liquid crystal panel drive voltages. The R61505U’s power management functions such as 8-color display and deep standby and so on make this LSI an ideal driver for the medium or small sized portable products with color display systems such as digital cellular phones or small PDAs, where long battery life is a major concern. Rev.1.0 September 13, 2006, page 6 of 199 R61505U Features • • • • • • • • • • • • • • • • • • A single-chip controller driver incorporating a gate circuit and a power supply circuit for a maximum 240RGB x 320dots graphics display on amorphous TFT panel in 262k colors System interface – High-speed interfaces via 8-, 9-, 16-, 18-bit parallel ports – Clock synchronous serial interface Moving picture display interface – 6-, 16-, 18-bit RGB interface (VSYNC, HSYNC, DOTCLK, ENABLE, DB17-0) – VSYNC interface (System interface + VSYNC) – FMARK interface (System interface + FMARK) High-speed RAM write function Window address function to specify a rectangular area in the internal RAM to write data Write data within a rectangular area in the internal RAM via moving picture interface Reduce data transfer by specifying the area in the RAM to rewrite data Enable displaying the data in the still picture RAM area with a moving picture simultaneously Resizing function (x 1/2, x 1/4) Abundant color display and drawing functions – Programmable γ-correction function for 262k-color display – Partial display function Low -power consumption architecture (allowing direct input of interface I/O power supply) – Deep standby function – 8-color display function – Input power supply voltages: VCC = 2.5V ~ 3.3 V (logic regulator power supply) IOVCC = 1.65V ~ 3.3 V (interface I/O power supply) VCI = 2.5V ~ 3.3 V (liquid crystal analog circuit power supply) Incorporates a liquid crystal drive power supply circuit – Source driver liquid crystal drive/VCOM power supply: DDVDH-GND = 4.5V ~ 6.0 V VCL-GND = -1.9V ~ -3.0V VCI-VCL ≤ 6.0V – Gate drive power supply: VGH-GND = 10.0V ~ 20.0 V VGL-GND = -4.5V ~ -13.5V VGH-VGL ≤ 28.0V – VCOM drive (VCOM power supply): VCOMH = 3.0V ~ (DDVDH-0.5)V VCOML = (VCL+0.5)V ~ 0V VCOMH-VCOML amplitude = 6.0V (max.) Liquid crystal power supply startup sequencer TFT storage capacitance: Cst only (common VCOM formula) 172,800-byte internal RAM Internal 720-channel source driver and 320-channel gate driver Single-chip solution for COG module with the arrangement of gate circuits on both sides of the glass substrate Internal NVM: User identification code, 4 bits, VCOM level adjustment, 5 bits x 2 sets Rev.1.0 September 13, 2006, page 7 of 199 R61505U • Internal reference voltage: to generate VREG1OUT (VCIR) Product Number • The R61505U has two variations of frequencies enabling users to choose whichever suitable for display system. Product Number Oscillation Frequency R61505U0 376KHz R61505U1 600KHz Rev.1.0 September 13, 2006, page 8 of 199 R61505U • Power supply specifications Table 1 No. Item R61505U 1 TFT data lines 720 2 TFT gate lines 320 3 TFT display storage capacitance Cst only (Common VCOM formula) 4 Liquid crystal drive output S1~S720 V0 ~ V31 grayscales G1~320 VGH-VGL VCOM Change VCOMH-VCOML amplitude with electronic volume Change VCOMH with either electronic volume or from VCOMR 5 Input voltage IOVCC (interface voltage) 1.65V ~ 3.30V Power supply to IM0/ID, IM1-3, RESET*, DB17-0, RD*, SDI, SDO, WR/SCL, RS, CS*, VSYNC, HSYNC, DOTCLK, ENABLE, FMARK Connect to VCC and VCI on the FPC when the electrical potentials are the same. VCC (logic regulator power supply) 2.50V ~ 3.30V VCI (liquid crystal drive power supply voltage) 2.50V ~ 3.30V VPP (NVM power supply) VPP1: 9.0±0.1V Connect to IOVCC and VCI on the FPC when the electrical potentials are the same. Connect to IOVCC and VCC on the FPC when the electrical potentials are the same. VPP2: 7.5±0.1V VPP3: GND 6 6 Liquid crystal drive voltages Internal step-up circuits DDVDH 4.5V ~ 6.0V VGH 10.0V ~ 20.0V VGL -4.5V ~ -13.5V VGH-VGL Max. 28.0V VCL -1.9V ~ -3.0V VCI-VCL Max. 6.0V VLOUT1 (DDVDH) VCI1 x 2, x 3 VLOUT2 (VGH) VCI1 x 6, x 7, x 8 VLOUT3 (VGL) VCI1 x -3, x -4, x -5 VCL VCI1 x -1 Rev.1.0 September 13, 2006, page 9 of 199 R61505U Difference between R61505 and R61505U Table 2 R61505 BT[3:0] 4’h0 DDVDH VCL VGH VGL Capacitor connection pins VLOUT1, VLOUT2, VLOUT3, VCL, C11±, C12±, C13±, C21 ±, C22±, C23± VCI1 x 2 -VCI1 DDVDH x 4 -(VCI1+DDVDH x 2) [x 2] [x -1] [x 8] [x -5] VCL VGH VGL Capacitor connection pins See “Specifications of Powersupply Circuit External Elements”. C23±may be omitted. Table 3 R61505U BT[3:0] 4’h0 DDVDH VCI1 x 2 -VCI1 DDVDH x 3 -(VCI1+DDVDH x 2) [x 2] [x -1] [x 6] [x -5] Table 4 VCOM amplitude VCOM amplitude (Max.) R61505 R61505U VREG1OUT x 1.0 VREG1OUT x 1.24 R61505 R61505U External resistor Internal resistor Table 5 Oscillator RC Oscillation Rev.1.0 September 13, 2006, page 10 of 199 R61505U Block Diagram RGND GND Index register (IR) AGND Control register (CR) IOGND Address counter IOVCC 18 RD* Read data latch SDI SDO DB0-17 VSYNC Write data 18 latch 18 Graphics RAM (GRAM) 172,800 bytes Latch circuit WR/SCL 18 18-bit 16-bit 9-bit 8-bit 8-bit serial Latch circuit RS Latch circuit BGR circuit CS* M alternating timing System interface Source line drive circuit IM3-1,IM0/ID External display interface HSYNC timing generator RESET* grayscale voltage generating circuit ENABLE V31-0 VSYNC HSYNC DOTCLK ENABLE DB17-0 γ-correction circuit DOTCLK S1-720 VGS VTEST V0T V31T VMON FMARK CPG Internal reference voltage generating circuit VCC gate line drive circuit scan data generating circuit TS8-0 TSC VPP1-3 Internal logic power supply regulator TEST1 TEST2 TEST3 TEST4 TEST5 VREFC VRTEST VREF VDDTEST VREFD VDD Figure 1 Rev.1.0 September 13, 2006, page 11 of 199 TESTA5 Vcom VcomL VcomR VcomH VREG1OUT VCL VLOUT2 VGH VLOUT3 VGL VLOUT1 DDVDH C22+/C22C23+/C23- VCI1 C11+/C11C12+/C12C13+/C13C21+/C21- VCIOUT VCI Liquid crystal drive level generating circuit VCILVL G1-G320 R61505U Block Function 1. System Interface The R61505U supports 80-system high-speed interface via 8-, 9-, 16-, 18-bit parallel ports and a clock synchronous serial interface. The interface is selected by setting the IM3-0 pins. The R61505U has a 16-bit index register (IR), an 18-bit write-data register (WDR), and an 18-bit read-data register (RDR). The IR is the register to store index information from control register and internal GRAM. The WDR is the register to temporarily store data to be written to control register and internal GRAM. The RDR is the register to temporarily store the data read from the GRAM. The data from the MPU to be written to the internal GRAM is first written to the WDR and then automatically written to the internal GRAM in internal operation. The data is read via RDR from the internal GRAM. Therefore, invalid data is sent to the data bus when the R61505U performs the first read operation from the internal GRAM. Valid data is read out when the R61505U performs the second and subsequent read operation. The instruction execution time except that of starting oscillation takes 0 clock cycle to allow writing instructions consecutively. Table 6 Register Selection (80-system 8/9/16/18-bit Parallel Interface) WR* RD* RS Function 0 1 0 Write index to IR 1 0 0 Setting disabled 0 1 1 Write to control register or internal GRAM via WDR 1 0 1 Read from internal GRAM and register via RDR Table 7 Register Selection (Clock synchronous serial interface) Start byte R/W RS Function 0 0 Write index to IR 1 0 Setting disabled 0 1 Write to control register or internal GRAM via WDR 1 1 Read from internal GRAM and register via RDR Rev.1.0 September 13, 2006, page 12 of 199 R61505U Table 8 Instruction write transfer IM3 IM2 IM1 IM0 System interface DB pins RAM write data 0 0 0 0 0 0 0 1 Setting disabled - - - Setting disabled - - - 0 0 1 0 80-system 16-bit interface DB17-10, DB8-1 Single transfer (16 bits) 2 transfers (1st: 2 bits, 2nd: 16 bits) 2 transfers (1st: 16 bits, 2nd: 2 bits) 0 0 1 1 80-system 8-bit interface DB17-10 2 transfers (1st: 8 bits, 2nd: 8 bits) 3 transfers (1st: 6 bits, 2nd: 6 bits, 3rd: 6 bits) 0 1 0 * Clock synchronous serial interface (SDI, SDO) 2 transfers (1st: 8 bits, 2nd: 8 bits) 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 Setting disabled - - - Setting disabled - - - Setting disabled - - - Setting disabled - - - 1 0 1 0 80-system 18-bit interface DB17-0 Single transfer (18 bits) Single transfer (16 bits) 1 0 1 1 80-system 9-bit interface DB17-9 2 transfers (1st: 9 bits, 2nd: 9 bits) 2 transfers (1st: 8 bits, 2nd: 8 bits) 1 1 * * Setting disabled 2. External Display Interface (RGB, VSYNC interfaces) - Single transfer (16 bits) 2 transfers (1st: 8 bits, 2nd: 8 bits) 2 transfers (1st: 8 bits, 2nd: 8 bits) - The R61505U supports RGB interface and VSYNC interface as the external interface to display moving picture. When the RGB interface is selected, the display operation is synchronized with externally supplied signals, VSYNC, HSYNC, and DOTCLK. In RGB interface operation, data (DB17-0) is written in synchronization with these signals when the polarity of enable signal (ENABLE) allows write operation in order to prevent flicker while updating display data. In VSYNC interface operation, the display operation is synchronized with the internal clock except frame synchronization, which synchronizes the display operation with the VSYNC signal. The display data is written to the internal GRAM via system interface. When writing data via VSYNC interface, there are constraints in speed and method in writing data to the internal RAM. For details, see the “VSYNC interface” section. The R61505U allows switching interface by instruction according to the display, i.e. still and/or moving picture(s). The R61505U writes all display data via RGB interface to the internal GRAM in order to transfer data only when updating the data and thereby reduce the data transfer and power consumption for moving picture display. 3. Address Counter (AC) The address counter (AC) gives an address to the internal GRAM. When the index of the register to set a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC. As the R61505U writes data to the internal GRAM, the address in the AC is automatically updated plus or minus 1. The window address function enables writing data only within the rectangular area specified in the GRAM. Rev.1.0 September 13, 2006, page 13 of 199 R61505U 4. Graphics RAM (GRAM) GRAM is graphics RAM, which can store bit-pattern data of 172,800 (240RGB x 320 (dots) x 18(bits)) bytes at maximum, using 18 bits per pixel. 5. Grayscale Voltage Generating Circuit The grayscale voltage generating circuit generates liquid crystal drive voltages according to the grayscale data in the γ-correction registers to enable 262k-color display. For details, see the γ-Correction Register section. 6. Liquid crystal drive power supply circuit The liquid crystal drive power supply circuit generates DDVDH, VGH, VGL and VCOM levels to drive liquid crystal. 7. Timing Generator The timing generator generates a timing signal for the operation of internal circuit such as the internal GRAM. The timing signal for display operation such as RAM read operation and the timing signal for internal operation such as RAM access from the MPU are generated separately in order to avoid mutual interference. 8. Oscillator (OSC) The R61505U generates the RC oscillation clock by internal RC oscillator. Adjusting the frequency by external resistance is impossible. Adjust the oscillation frequency and line numbers by Frame-Frequency Adjustment Function. During the deep standby mode, RC oscillation halts to reduce power consumption. See “Oscillator” for details. 9. Liquid crystal driver Circuit The liquid crystal driver circuit of the R61505U consists of a 720-output source driver (S1 ~ S720) and a 320-output gate driver (G1~G320). The display pattern data is latched when 720 bits of data are inputted. The latched data control the source driver and output drive waveforms. The gate driver for scanning gate lines outputs either VGH or VGL level. The shift direction of 720-bit source output from the source driver can be changed by setting the SS bit and the shift direction of gate output from the gate driver can be changed by setting the GS bit. The scan mode by the gate driver can be changed by setting the SM bit. Sets the gate driver pin arrangement in combination with the GS bit to select the optimal scan mode for the module. 10. Internal logic power supply regulator The internal logic power supply regulator generates internal logic power supply VDD. Rev.1.0 September 13, 2006, page 14 of 199 R61505U Pin Function Table 9 Interface Signal I/O IM3-1, IM0/ID I Connect Function to IOGND or Select a mode to interface to an MPU. In serial interface operation, IOVCC the IM0 pin is used to set the ID bit of device code. IM3 IM2 IM1 IM0/I D Interface Mode DB Pin Colors 0 0 0 0 Setting disabled - 0 0 0 1 Setting disabled - - DB17-10, DB8-1 262,144 0 0 0 0 1 1 0 80-system 16-bit interface When not in use - - see Note 1 262,144 1 80-system 8-bit interface DB17-10 - 65,536 see Note 2 0 1 0 *(ID) Clock synchronous serial interface 0 1 1 0 Setting disabled - - 0 1 1 1 Setting disabled - - 1 0 0 0 Setting disabled - - 1 0 0 1 Setting disabled - - DB17-0 262,144 1 0 1 0 80-system 18-bit interface 1 0 1 1 80-system 9-bit interface DB17-9 262,144 1 1 0 0 Setting disabled - - 1 1 0 1 Setting disabled - - 1 1 1 0 Setting disabled - - 1 1 1 1 Setting disabled - - Notes: 1. 65,536 colors in one transfer mode 2. 65,536 colors in two transfers mode CS* I MPU Chip select signal. Amplitude: IOVCC-IOGND Low: the R61505U is selected and accessible High: the R61505U is not selected and not accessible. IOVCC RS I MPU Register select signal. Amplitude: IOVCC-IOGND Low: select Index or status register High: select control register IOVCC WR*/SCL I MPU Write strobe signal in 80-system bus interface operation and enables write operation when WR* is low. Synchronous clock signal (SCL) in serial interface operation. Amplitude: IOVCC-IOGND IOVCC RD* I MPU Read strobe signal in 80-system bus interface operation and enables read operation when RD* is low. Amplitude: IOVCC-IOGND IOVCC SDI I MPU SDO I/O MPU Serial data input (SDI) pin in serial interface operation. The data is IOGND or inputted on the rising edge of the SCL signal. Amplitude: IOVCCIOVCC IOGND Serial data output (SDO) pin in serial interface operation. The data is Open outputted on the falling edge of the SCL signal. Amplitude: IOVCC-IOGND Rev.1.0 September 13, 2006, page 15 of 199 R61505U Signal I/O DB0-DB17 I/O Connect to MPU When not in use 18-bit parallel bi-directional data bus for 80-system interface operation IOGND or IOVCC (Amplitude: IOVCC-IOGND). Function 8-bit I/F: DB17-DB10 are used. 9-bit I/F: DB17-DB9 are used. 16-bit I/F: DB17-DB10 and DB8-1 are used. 18-bit I/F: DB17-DB0 are used. 18-bit parallel bi-directional data bus for RGB interface operation (Amplitude: IOVCC-IOGND). 6-bit I/F: DB17-DB12 are used. 16-bit I/F: DB17-DB13 and DB11-1 are used. 18-bit I/F: DB17-DB0 are used. ENABLE I MPU Data enable signal for RGB interface operation. (Amplitude: IOVCC-IOGND). IOGND or IOVCC Low: accessible (select) High: Not accessible (Not select) The polarity of ENABLE signal can be inverted by setting the EPL bit. VSYNC I MPU Frame synchronous signal for RGB interface operation. Low active. (Amplitude: IOVCC-IOGND). IOGND or IOVCC HSYNC I MPU Line synchronous signal for RGB interface operation. Low active. (Amplitude: IOVCC-IOGND). IOGND or IOVCC DOTCLK I MPU Dot clock signal for RGB interface operation. The data input timing is IOGND or on the rising edge of DOTCLK. (Amplitude: IOVCC-IOGND). IOVCC FMARK O MPU Frame head pulse signal, which is used when writing data to the internal RAM. (Amplitude: IOVCC-IOGND). Open Table 10 Reset, RC oscillation Signal I/O RESET* I OSC1 OSC2 I O Connect to MPU or external RC circuit Open Function Reset signal. Initializes the R61505U when it is low. Make sure to execute a power-on reset when turning on power supply (IOVCCIOGND amplitude signal). Leave them open. Rev.1.0 September 13, 2006, page 16 of 199 When not in use - Open R61505U Table 11 Power supply Connect to Power supply When not in use - Signal I/O VCC - GND - Power supply Internal logic GND: GND = 0V. - RGND - Power supply Internal RAM GND. RGND must be at the same electrical potential as GND. In case of COG, connect to GND on the FPC to prevent noise. - VDD O Stabilizing Internal logic regulator output, which is used as the power supply to capacitor internal logic. Connect a stabilizing capacitor. - IOVCC - Power supply Power supply to the interface pins: RESET*, CS*, WR, RD*, RS, DB17-0, VSYNC, HSYNC, DOTCLK, ENABLE. IOVCC = 1.65V ~ 3.3V. VCC ≥ IOVCC. In case of COG, connect to VCC on the FPC if IOVCC=VCC, to prevent noise. - IOGND - Power supply GND for the interface pins: RESET*, CS*, WR, RD*, RS, DB17-0, VSYNC, HSYNC, DOTCLK, ENABLE. IOGND = 0V. In case of COG, connect to GND on the FPC to prevent noise. - AGND - Power supply Analog GND (for logic regulator and liquid crystal power supply circuit): AGND = 0V. In case of COG, connect to GND on the FPC to prevent noise. - VCI I Power supply Power supply to the liquid crystal power supply analog circuit. Connect to an external power supply of 2.5V ~ 3.3V. - VCILVL I Reference VCILVL must be at the same electrical potential as VCI. power VCILVL = 2.5V ~ 3.3V. Connect to external power supply. In case of supply COG, connect to VCI on the FPC to prevent noise. VPP1 I Power supply or open VPP2 I Power supply or open Operation mode VPP1 VPP2 VPP3 NVM write 9.0±0.1V 7.5±0.1V GND Power supply or open NVM read Open Open Open or GND VPP3 I Function Power supply to internal logic regulator circuit: VCC = 2.5V~3.3V. VCC ≥ IOVCC Internal NVM power supply. Apply the following voltages on VPP1 ~ VPP3 respectively according to the power supply ON sequence. Rev.1.0 September 13, 2006, page 17 of 199 - Open Open Open or GND R61505U Table 12 Step-up circuit Signal I/O VCIOUT O Connect to Stabilizing capacitor, VCI1 VCI1 I/O VCIOUT VLOUT1 O Stabilizing Output voltage from the step-up circuit 1, generated from VCI1. The capacitor, step-up factor is set by instruction (BT bits). Make sure to connect to DDVDH stabilizing capacitor. VLOUT1 = 4.5V ~ 6.0V - DDVDH I VLOUT1 - VLOUT2 O Stabilizing Output voltage from the step-up circuit 2, generated from VCI1 and capacitor, DDVDH. The step-up factor is set by instruction (BT bits). Make sure VGH to connect to stabilizing capacitor. VLOUT2 = max 20.0V - VGH I VLOUT2 - VLOUT3 O Stabilizing Output voltage from the step-up circuit 2, generated from VCI1 and capacitor, DDVDH. The step-up factor is set by instruction (BT bits). Make sure VGL to connect to stabilizing capacitor. VLOUT3 = min –13.5V - VGL I VLOUT3 - VCL O Stabilizing VCOML drive power supply. Make sure to connect to stabilizing capacitor capacitor. VCL = -1.9V ~ -3.0V - C11+, C11C12+, C12- I O Step-up capacitor Capacitor connection pins for the step-up circuit 1. - C13+, C13C21+, C21C22+, C22C23+, C23- I O Step-up capacitor Capacitor connection pins for the step-up circuit 2. Connect capacitors to C23± according to the step-up factor. - Function Output voltage from the step-up circuit 1, generated from the reference voltage. The output factor is set by VC bits. Make sure to connect to stabilizing capacitor. Reference voltage of step-up circuit 1. Make sure the output voltage levels from VLOUT1, VLOUT2, VLOUT3 do not exceed the respective setting ranges. Power supply for the source driver liquid crystal drive unit and VCOM drive. Connect to VLOUT1. DDVDH = 4.5V ~ 6.0V Liquid crystal drive power supply. Connect to VLOUT2. Liquid crystal drive power supply. Connect to VLOUT3. Rev.1.0 September 13, 2006, page 18 of 199 When not in use - - R61505U Table 13 LCD drive Signal I/O VREG1 OUT O Connect Function to Stabilizing Output voltage generated from the reference voltage (VCILVL or capacitor VCIR). The factor is determined by instruction (VRH bits). When not in use Open VREG1OUT is used for (1) source driver grayscale reference voltage, (2) VCOMH level reference voltage, and (3) VCOM amplitude reference voltage. Connect to a stabilizing capacitor when in use. VREG1OUT = 4.0V ~ (DDVDH – 0.5)V VCOM O TFT panel Power supply to TFT panel’s common electrode. VCOM alternates Open common between VCOMH and VCOML. The alternating cycle is set by internal electrode register. Also, the VCOM output can be started and halted by register setting. VCOMH O Stabilizing The High level of VCOM amplitude. The output level can be adjusted Open capacitor by either external resistor (VCOMR) or electronic volume. Make sure to connect to stabilizing capacitor. VCOML O Stabilizing The Low level of VCOM amplitude. The output level can be adjusted capacitor by instruction (VDV bits). VCOML = (VCL+0.5)V ~ 0V. Make sure to connect to stabilizing capacitor. VCOMR I Variable Connect a variable resistor when adjusting the VCOMH level between Open resistor or VREG1OUT and GND. open VGS I GND Reference level for the grayscale voltage generating circuit. S1~S720 O LCD Liquid crystal application voltages. To change the shift direction of segment signal output, set the SS bit as follows. Open Open When SS = 0, the data in the RAM address h00000 is outputted from S1. When SS = 1, the data in the RAM address h00000 is outputted from S720. G1~G320 O LCD Gate line output signals. VGH: gate line select level VGL: gate line non-select level Rev.1.0 September 13, 2006, page 19 of 199 Open R61505U Table 14 Others (test, dummy pins) I/O Connect to Open Test pins. Leave them open. When not in use Open VTEST O Open Test pin. Leave it open. Open VREFC I AGND Test pin. Make sure to fix to the AGND level. VREF O Open Test pin. Leave it open. VDDTEST I AGND Test pin. Make sure to fix to the AGND level. VREFD O Open Test pin. Leave it open. Open VMON O Open Test pin. Leave it open. Open TESTA5 O Open Test pin. Leave it open. Open IOVCCDUM1-2 O - Use them to fix the electrical potentials of unused interface pins and fixed pins. When not in use, leave it open. Open VCCDUM1 O - Test pin. Leave it open Open IOGNDDUM1-3 O - Use them to fix the electrical potentials of unused interface pins and fixed pins. When not in use, leave it open. Open OSC1DUM1-4 O - Test pins. Leave them open. Open OSC2DUM1-2 O - Test pins. Leave them open. Open AGNDDUM1-4 O - Use them to fix VREFC, VDDTEST. Open DUMMYR 1-10 - - DUMMYR1 and DUMMYR10, DUMMYR2 and DUMMYR9, DUMMYR3 and DUMMYR4, DUMMYR5 and DUMMYR8, and DUMMYR6 and DUMMYR7 are short-circuited within the chip for COG contact resistance measurement. Open VGLDMY 1-4 O - Dummy pads. Leave them open. Open Signal I/O V0T, V31T Function Rev.1.0 September 13, 2006, page 20 of 199 Open - R61505U Signal I/O TESTO1-38 O Connect to - Dummy pads. Leave them open. When not in use Open TEST1, 2 I IOGND Test pins. Connect to IOGND. IOGND TEST3 TEST4 I IOVCC Test pin. Connect to IOVCC. IOVCC I IOVCC Test pin. Connect to IOVCC. IOVCC TEST5 I IOGND NVM operation enable pin. Connect to IOGND. IOGND TSC I IOGND Test pin. Connect to IOGND. IOGND TS8-0 O Open Test pins. Leave them open. Open Function Patents of dummy pin which is used to fix pin to VCC or GND are pending or granted. PATENT ISSUED: United States Patent No. 6,323,930 PATENT PENDING: Japanese Application No. 10-514484, Korean Application No. 19997002322 Taiwanese Application No.086103756, (PCT/JP96/02728(W098/12597) Rev.1.0 September 13, 2006, page 21 of 199 R61505U PAD arrangement Rev0.0 2005.11.30 ●Chip size: 21.56mm× 1.28mm ●Chip thickness: 280/400μm(typ.) ●PAD coordinates: PAD center ●Coordinates origin: Chip center □ □ □ (1-a) ●Au BUMP size: (1) 50.00 μm x 80.00μm No.1 - 298 (2) 21.00μm x 100.00μm No.299 - 1354 ●Au BUMP pitch: See PAD coordinates Table ●Au BUMP height: 15μm(typ.) ●No. in the Figure corresponds to No. in PAD coordinates Table ●Alignment mark (1-a), (1-b) 100μm 40 30 50 100μm 30 50 30 40 30 Top View BUMP Chip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 No.1 No.298 DUMMYR1 □ DUMMYR2 □ TESTO1 □ VCCDUM1 □ VPP1 □ VPP1 □ VPP1 □ VPP2 □ VPP2 □ VPP2 □ VPP2 □ VPP2 □ VPP3 □ VPP3 □ VPP3 □ TESTO2 □ IOGNDDUM1 □ TESTO3 □ TEST1 □ TEST2 □ TEST4 □ TEST5 □ TEST3 □ IM0/ID □ IM1 □ IM2 □ IM3 □ TESTO4 □ IOVCCDUM1 □ TESTO5 □ RESET* □ VSYNC □ HSYNC □ DOTCLK □ ENABLE □ DB17 □ DB16 □ DB15 □ DB14 □ DB13 □ DB12 □ DB11 □ DB10 □ DB9 □ DB8 □ TESTO6 □ IOGNDDUM2 □ TESTO7 □ DB7 □ DB6 □ DB5 □ DB4 □ DB3 □ DB2 □ DB1 □ DB0 □ SDO □ SDI □ RD* □ WR*/SCL □ RS □ CS* □ TESTO8 □ IOVCCDUM2 □ TESTO9 □ FMARK □ TS8 □ TS7 □ TS6 □ TS5 □ TS4 □ TS3 □ TS2 □ TS1 □ TS0 □ TSC □ TESTO10 □ IOGNDDUM3 □ TESTO11 □ TESTO12 □ OSC1DUM1 □ OSC1DUM2 □ OSC1 □ OSC1DUM3 □ OSC1DUM4 □ OSC2 □ OSC2DUM1 □ OSC2DUM2 □ DUMMYR3 □ DUMMYR4 □ IOGND □ IOGND □ IOGND □ IOGND □ IOGND □ IOGND □ IOGND □ IOVCC □ IOVCC □ IOVCC □ IOVCC □ IOVCC □ IOVCC □ IOVCC □ VCC □ VCC □ VCC □ VCC □ VCC □ VCC □ VCC □ VCC □ VDD □ VDD □ VDD □ VDD □ VDD □ VDD □ VDD □ VDD □ VDD □ VDD □ VDD □ VDD □ VDD □ TESTO13 □ VREFD □ TESTO14 □ VREF □ TESTO15 □ VREFC □ TESTO16 □ VDDTEST □ AGND □ AGND □ AGND □ AGND □ AGND □ AGND □ AGND □ AGND □ AGND □ AGND □ AGND □ GND □ GND □ GND □ GND □ GND □ GND □ RGND □ RGND □ RGND □ RGND □ RGND □ RGND □ RGND □ RGND □ RGND □ RGND □ TESTO17 □ VTEST □ TESTO18 □ VGS □ TESTO19 □ V0T □ TESTO20 □ VMON □ TESTO21 □ V31T □ VCOM □ VCOM □ VCOM □ VCOM □ VCOM □ VCOM □ VCOMH □ VCOMH □ VCOMH □ VCOMH □ VCOMH □ VCOMH □ VCOML □ VCOML □ VCOML □ VCOML □ VCOML □ VCOML □ TESTO22 □ TESTO23 □ VREG1OUT □ TESTO24 □ TESTA5 □ TESTO25 □ VCOMR □ TESTO26 □ VCL □ VCL □ VCL □ VLOUT1 □ VLOUT1 □ VLOUT1 □ DDVDH □ DDVDH □ DDVDH □ DDVDH □ DDVDH □ DDVDH □ DDVDH □ VCIOUT □ VCIOUT □ VCIOUT □ VCI1 □ VCI1 □ VCI1 □ VCI1 □ VCI1 □ VCILVL □ VCI □ VCI □ VCI □ VCI □ VCI □ VCI □ VCI □ VCI □ C12- □ C12- □ C12- □ C12- □ C12- □ C12+ □ C12+ □ C12+ □ C12+ □ C12+ □ C11- □ C11- □ C11- □ C11- □ C11- □ C11+ □ C11+ □ C11+ □ C11+ □ C11+ □ AGNDDUM1 □ VLOUT3 □ VLOUT3 □ VGL □ VGL □ VGL □ VGL □ VGL □ VGL □ VGL □ VGL □ VGL □ VGL □ AGNDDUM2 □ AGNDDUM3 □ AGNDDUM4 □ VLOUT2 □ VLOUT2 □ VGH □ VGH □ VGH □ VGH □ TESTO27 □ C13- □ C13- □ C13- □ TESTO28 □ C13+ □ C13+ □ C13+ □ TESTO29 □ C21- □ C21- □ C21- □ C21+ □ C21+ □ C21+ □ C22- □ C22- □ C22- □ C22+ □ C22+ □ C22+ □ C23- □ C23- □ C23- □ C23+ □ C23+ □ C23+ □ TESTO30 □ DUMMYR5 □ DUMMYR6 □ □ □ □ □ □ DUMMYR1-DUMMYR10: short -circuit DUMMYR2-DUMMYR9: short-circuit □ □ □ □ □ □ □ □ □ TESTO38 TESTO37 DUMMYR10 DUMMYR9 VGLDMY4 G2 G4 G6 G8 G10 G312 G314 G316 G318 G320 VGLDMY3 TESTO36 60μm □ □ □ □ □ □ □ □ □ TESTO35 S1 S2 S3 S4 S5 S6 S7 S8 R61505U Staggered output Top View (Bump View) Y X □ □ □ □ □ □ S716 S717 S718 S719 S720 TESTO34 220μm □ □ □ □ □ □ □ □ □ DUMMYR5-DUMMYR8: short-circuit DUMMYR6-DUMMYR7: short-circuit □ □ □ □ (1-b) □ □ □ □ TESTO33 VGLDMY2 G319 G317 G315 G313 G311 G9 G7 G5 G3 G1 VGLDMY1 DUMMYR8 DUMMYR7 TESTO32 TESTO31 R61505U ● Chip size: 21.56 mm x 1.28 mm ● Chip thickness: 280/400μm (typ.) ● PAD coordinates: PAD center ● PAD coordinates origin: Chip center a ● Au bump size (1) 50μm× 80μm I/O output side: No. 1 - No. 298 (2) 21μm× 100μm Liquid crystal output side: No. 299 - No. 1354 ● Au bump pitch: See PAD coordinates table ● Au bump height: 15μm(typ.) ● No. in the Figure corresponds to No. in the PAD coordinates table Type A b e f Non-pattern area X -10613.0 10613.0 c d ● Alignment mark Alignment mark shape g Type A Y -468.0 -468.0 Rev.1.0 September 13, 2006, page 23 of 199 Unit (μm) e: 40 a: 30 f: 30 b: 40 g: 100 c: 30 h: 100 d: 30 h R61505U Pad Coordinate (Unit:μm) pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pad name DUMMYR1 DUMMYR2 TESTO1 VCCDUM1 VPP1 VPP1 VPP1 VPP2 VPP2 VPP2 VPP2 VPP2 VPP3A VPP3A VPP3B TESTO2 IOGNDDUM1 TESTO3 TEST1 TEST2 TEST4 TEST5 PROTECT IM0/ID IM1 IM2 IM3 TESTO4 IOVCCDUM1 TESTO5 RESET* VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 TESTO6 IOGNDDUM2 TESTO7 DB7 DB6 X -10395.0 -10325.0 -10255.0 -10185.0 -10115.0 -10045.0 -9975.0 -9905.0 -9835.0 -9765.0 -9695.0 -9625.0 -9555.0 -9485.0 -9415.0 -9345.0 -9275.0 -9205.0 -9135.0 -9065.0 -8995.0 -8925.0 -8855.0 -8785.0 -8715.0 -8645.0 -8575.0 -8505.0 -8435.0 -8365.0 -8295.0 -8225.0 -8155.0 -8085.0 -8015.0 -7945.0 -7875.0 -7805.0 -7735.0 -7665.0 -7595.0 -7525.0 -7455.0 -7385.0 -7315.0 -7245.0 -7175.0 -7105.0 -7035.0 -6965.0 Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 2005.11.30 rev0.1 pad No 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pad name DB5 DB4 DB3 DB2 DB1 DB0 SDO SDI RD* WR*/SCL RS CS* TESTO8 IOVCCDUM2 TESTO9 FMARK TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 TSC TESTO10 IOGNDDUM3 TESTO11 TESTO12 OSC1DUM1 OSC1DUM2 OSC1 OSC1DUM3 OSC1DUM4 OSC2 OSC2DUM1 OSC2DUM2 DUMMYR3 DUMMYR4 IOGND IOGND IOGND IOGND IOGND IOGND IOGND IOVCC IOVCC IOVCC X -6895.0 -6825.0 -6755.0 -6685.0 -6615.0 -6545.0 -6475.0 -6405.0 -6335.0 -6265.0 -6195.0 -6125.0 -6055.0 -5985.0 -5915.0 -5845.0 -5775.0 -5705.0 -5635.0 -5565.0 -5495.0 -5425.0 -5355.0 -5285.0 -5215.0 -5145.0 -5075.0 -5005.0 -4935.0 -4865.0 -4795.0 -4725.0 -4655.0 -4585.0 -4515.0 -4445.0 -4375.0 -4305.0 -4235.0 -4165.0 -4095.0 -4025.0 -3955.0 -3885.0 -3815.0 -3745.0 -3675.0 -3605.0 -3535.0 -3465.0 Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 R61505U Pad Coordinate (Unit:μm) pad No 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 pad name IOVCC IOVCC IOVCC IOVCC VCC VCC VCC VCC VCC VCC VCC VCC VDDOUT VDDOUT VDDOUT VDDOUT VDD VDD VDD VDD VDD VDD VDD VDD VDD TESTO13 VREFD TESTO14 VREF TESTO15 VREFC TESTO16 VDDTEST AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND X -3395.0 -3325.0 -3255.0 -3185.0 -3115.0 -3045.0 -2975.0 -2905.0 -2835.0 -2765.0 -2695.0 -2625.0 -2555.0 -2485.0 -2415.0 -2345.0 -2275.0 -2205.0 -2135.0 -2065.0 -1995.0 -1925.0 -1855.0 -1785.0 -1715.0 -1645.0 -1575.0 -1505.0 -1435.0 -1365.0 -1295.0 -1225.0 -1155.0 -1085.0 -1015.0 -945.0 -875.0 -805.0 -735.0 -665.0 -595.0 -525.0 -455.0 -385.0 -315.0 -245.0 -175.0 -105.0 -35.0 35.0 Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 2005.11.30 rev0.1 pad No 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 pad name RGND RGND RGND RGND RGND RGND RGND RGND RGND RGND TESTO17 VTEST TESTO18 VGS TESTO19 V0T TESTO20 VMON TESTO21 V31T VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCOML VCOML TESTO22 TESTO23 VREG1OUT TESTO24 TESTA5 TESTO25 VCOMR TESTO26 VCL VCL VCL VLOUT1 X 105.0 175.0 245.0 315.0 385.0 455.0 525.0 595.0 665.0 735.0 805.0 875.0 945.0 1015.0 1085.0 1155.0 1225.0 1295.0 1365.0 1435.0 1505.0 1575.0 1645.0 1715.0 1785.0 1855.0 1925.0 1995.0 2065.0 2135.0 2205.0 2275.0 2345.0 2415.0 2485.0 2555.0 2625.0 2695.0 2765.0 2835.0 2905.0 2975.0 3045.0 3115.0 3185.0 3255.0 3325.0 3395.0 3465.0 3535.0 Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 R61505U Pad Coordinate (Unit:μm) pad No 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 pad name VLOUT1 VLOUT1 DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCI1 VCILVL VCI VCI VCI VCI VCI VCI VCI VCI C12C12C12C12C12C12+ C12+ C12+ C12+ C12+ C11C11C11C11C11C11+ C11+ C11+ C11+ C11+ AGNDDUM1 VLOUT3 VLOUT3 VGL X 3605.0 3675.0 3745.0 3815.0 3885.0 3955.0 4025.0 4095.0 4165.0 4235.0 4305.0 4375.0 4445.0 4515.0 4585.0 4655.0 4725.0 4795.0 4865.0 4935.0 5005.0 5075.0 5145.0 5215.0 5285.0 5355.0 5425.0 5495.0 5565.0 5635.0 5705.0 5775.0 5845.0 5915.0 5985.0 6055.0 6125.0 6195.0 6265.0 6335.0 6405.0 6475.0 6545.0 6615.0 6685.0 6755.0 6825.0 6895.0 6965.0 7035.0 Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 2005.11.30 rev0.1 pad No 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 pad name VGL VGL VGL VGL VGL VGL VGL VGL VGL AGNDDUM2 AGNDDUM3 AGNDDUM4 VLOUT2 VLOUT2 VGH VGH VGH VGH TESTO27 C13C13C13TESTO28 C13+ C13+ C13+ TESTO29 C21C21C21C21+ C21+ C21+ C22C22C22C22+ C22+ C22+ C23C23C23C23+ C23+ C23+ TESTO30 DUMMYR5 DUMMYR6 TESTO31 TESTO32 X 7105.0 7175.0 7245.0 7315.0 7385.0 7455.0 7525.0 7595.0 7665.0 7735.0 7805.0 7875.0 7945.0 8015.0 8085.0 8155.0 8225.0 8295.0 8365.0 8435.0 8505.0 8575.0 8645.0 8715.0 8785.0 8855.0 8925.0 8995.0 9065.0 9135.0 9205.0 9275.0 9345.0 9415.0 9485.0 9555.0 9625.0 9695.0 9765.0 9835.0 9905.0 9975.0 10045.0 10115.0 10185.0 10255.0 10325.0 10395.0 10670.0 10650.0 Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 511.5 386.5 R61505U Pad Coordinate (Unit:μm) pad No 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 pad name DUMMYR7 DUMMYR8 VGLDMY1 G1 G3 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 G59 G61 G63 G65 G67 G69 G71 G73 G75 G77 G79 G81 G83 G85 G87 G89 G91 G93 X 10630.0 10610.0 10590.0 10570.0 10550.0 10530.0 10510.0 10490.0 10470.0 10450.0 10430.0 10410.0 10390.0 10370.0 10350.0 10330.0 10310.0 10290.0 10270.0 10250.0 10230.0 10210.0 10190.0 10170.0 10150.0 10130.0 10110.0 10090.0 10070.0 10050.0 10030.0 10010.0 9990.0 9970.0 9950.0 9930.0 9910.0 9890.0 9870.0 9850.0 9830.0 9810.0 9790.0 9770.0 9750.0 9730.0 9710.0 9690.0 9670.0 9650.0 Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 2005.11.30 rev0.1 pad No 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 pad name G95 G97 G99 G101 G103 G105 G107 G109 G111 G113 G115 G117 G119 G121 G123 G125 G127 G129 G131 G133 G135 G137 G139 G141 G143 G145 G147 G149 G151 G153 G155 G157 G159 G161 G163 G165 G167 G169 G171 G173 G175 G177 G179 G181 G183 G185 G187 G189 G191 G193 X 9630.0 9610.0 9590.0 9570.0 9550.0 9530.0 9510.0 9490.0 9470.0 9450.0 9430.0 9410.0 9390.0 9370.0 9350.0 9330.0 9310.0 9290.0 9270.0 9250.0 9230.0 9210.0 9190.0 9170.0 9150.0 9130.0 9110.0 9090.0 9070.0 9050.0 9030.0 9010.0 8990.0 8970.0 8950.0 8930.0 8910.0 8890.0 8870.0 8850.0 8830.0 8810.0 8790.0 8770.0 8750.0 8730.0 8710.0 8690.0 8670.0 8650.0 Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 R61505U Pad Coordinate (Unit:μm) pad No 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 pad name G195 G197 G199 G201 G203 G205 G207 G209 G211 G213 G215 G217 G219 G221 G223 G225 G227 G229 G231 G233 G235 G237 G239 G241 G243 G245 G247 G249 G251 G253 G255 G257 G259 G261 G263 G265 G267 G269 G271 G273 G275 G277 G279 G281 G283 G285 G287 G289 G291 G293 X 8630.0 8610.0 8590.0 8570.0 8550.0 8530.0 8510.0 8490.0 8470.0 8450.0 8430.0 8410.0 8390.0 8370.0 8350.0 8330.0 8310.0 8290.0 8270.0 8250.0 8230.0 8210.0 8190.0 8170.0 8150.0 8130.0 8110.0 8090.0 8070.0 8050.0 8030.0 8010.0 7990.0 7970.0 7950.0 7930.0 7910.0 7890.0 7870.0 7850.0 7830.0 7810.0 7790.0 7770.0 7750.0 7730.0 7710.0 7690.0 7670.0 7650.0 Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 2005.11.30 rev0.1 pad No 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 pad name G295 G297 G299 G301 G303 G305 G307 G309 G311 G313 G315 G317 G319 VGLDMY2 TESTO33 TESTO34 S720 S719 S718 S717 S716 S715 S714 S713 S712 S711 S710 S709 S708 S707 S706 S705 S704 S703 S702 S701 S700 S699 S698 S697 S696 S695 S694 S693 S692 S691 S690 S689 S688 S687 X 7630.0 7610.0 7590.0 7570.0 7550.0 7530.0 7510.0 7490.0 7470.0 7450.0 7430.0 7410.0 7390.0 7370.0 7350.0 7130.0 7110.0 7090.0 7070.0 7050.0 7030.0 7010.0 6990.0 6970.0 6950.0 6930.0 6910.0 6890.0 6870.0 6850.0 6830.0 6810.0 6790.0 6770.0 6750.0 6730.0 6710.0 6690.0 6670.0 6650.0 6630.0 6610.0 6590.0 6570.0 6550.0 6530.0 6510.0 6490.0 6470.0 6450.0 Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 R61505U Pad Coordinate (Unit:μm) pad No 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 pad name S686 S685 S684 S683 S682 S681 S680 S679 S678 S677 S676 S675 S674 S673 S672 S671 S670 S669 S668 S667 S666 S665 S664 S663 S662 S661 S660 S659 S658 S657 S656 S655 S654 S653 S652 S651 S650 S649 S648 S647 S646 S645 S644 S643 S642 S641 S640 S639 S638 S637 X 6430.0 6410.0 6390.0 6370.0 6350.0 6330.0 6310.0 6290.0 6270.0 6250.0 6230.0 6210.0 6190.0 6170.0 6150.0 6130.0 6110.0 6090.0 6070.0 6050.0 6030.0 6010.0 5990.0 5970.0 5950.0 5930.0 5910.0 5890.0 5870.0 5850.0 5830.0 5810.0 5790.0 5770.0 5750.0 5730.0 5710.0 5690.0 5670.0 5650.0 5630.0 5610.0 5590.0 5570.0 5550.0 5530.0 5510.0 5490.0 5470.0 5450.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 2005.11.30 rev0.1 pad No 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 pad name S636 S635 S634 S633 S632 S631 S630 S629 S628 S627 S626 S625 S624 S623 S622 S621 S620 S619 S618 S617 S616 S615 S614 S613 S612 S611 S610 S609 S608 S607 S606 S605 S604 S603 S602 S601 S600 S599 S598 S597 S596 S595 S594 S593 S592 S591 S590 S589 S588 S587 X 5430.0 5410.0 5390.0 5370.0 5350.0 5330.0 5310.0 5290.0 5270.0 5250.0 5230.0 5210.0 5190.0 5170.0 5150.0 5130.0 5110.0 5090.0 5070.0 5050.0 5030.0 5010.0 4990.0 4970.0 4950.0 4930.0 4910.0 4890.0 4870.0 4850.0 4830.0 4810.0 4790.0 4770.0 4750.0 4730.0 4710.0 4690.0 4670.0 4650.0 4630.0 4610.0 4590.0 4570.0 4550.0 4530.0 4510.0 4490.0 4470.0 4450.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 R61505U Pad Coordinate (Unit:μm) pad No 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 pad name S586 S585 S584 S583 S582 S581 S580 S579 S578 S577 S576 S575 S574 S573 S572 S571 S570 S569 S568 S567 S566 S565 S564 S563 S562 S561 S560 S559 S558 S557 S556 S555 S554 S553 S552 S551 S550 S549 S548 S547 S546 S545 S544 S543 S542 S541 S540 S539 S538 S537 X 4430.0 4410.0 4390.0 4370.0 4350.0 4330.0 4310.0 4290.0 4270.0 4250.0 4230.0 4210.0 4190.0 4170.0 4150.0 4130.0 4110.0 4090.0 4070.0 4050.0 4030.0 4010.0 3990.0 3970.0 3950.0 3930.0 3910.0 3890.0 3870.0 3850.0 3830.0 3810.0 3790.0 3770.0 3750.0 3730.0 3710.0 3690.0 3670.0 3650.0 3630.0 3610.0 3590.0 3570.0 3550.0 3530.0 3510.0 3490.0 3470.0 3450.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 2005.11.30 rev0.1 pad No 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 pad name S536 S535 S534 S533 S532 S531 S530 S529 S528 S527 S526 S525 S524 S523 S522 S521 S520 S519 S518 S517 S516 S515 S514 S513 S512 S511 S510 S509 S508 S507 S506 S505 S504 S503 S502 S501 S500 S499 S498 S497 S496 S495 S494 S493 S492 S491 S490 S489 S488 S487 X 3430.0 3410.0 3390.0 3370.0 3350.0 3330.0 3310.0 3290.0 3270.0 3250.0 3230.0 3210.0 3190.0 3170.0 3150.0 3130.0 3110.0 3090.0 3070.0 3050.0 3030.0 3010.0 2990.0 2970.0 2950.0 2930.0 2910.0 2890.0 2870.0 2850.0 2830.0 2810.0 2790.0 2770.0 2750.0 2730.0 2710.0 2690.0 2670.0 2650.0 2630.0 2610.0 2590.0 2570.0 2550.0 2530.0 2510.0 2490.0 2470.0 2450.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 R61505U Pad Coordinate (Unit:μm) pad No 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 pad name S486 S485 S484 S483 S482 S481 S480 S479 S478 S477 S476 S475 S474 S473 S472 S471 S470 S469 S468 S467 S466 S465 S464 S463 S462 S461 S460 S459 S458 S457 S456 S455 S454 S453 S452 S451 S450 S449 S448 S447 S446 S445 S444 S443 S442 S441 S440 S439 S438 S437 X 2430.0 2410.0 2390.0 2370.0 2350.0 2330.0 2310.0 2290.0 2270.0 2250.0 2230.0 2210.0 2190.0 2170.0 2150.0 2130.0 2110.0 2090.0 2070.0 2050.0 2030.0 2010.0 1990.0 1970.0 1950.0 1930.0 1910.0 1890.0 1870.0 1850.0 1830.0 1810.0 1790.0 1770.0 1750.0 1730.0 1710.0 1690.0 1670.0 1650.0 1630.0 1610.0 1590.0 1570.0 1550.0 1530.0 1510.0 1490.0 1470.0 1450.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 2005.11.30 rev0.1 pad No 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 pad name S436 S435 S434 S433 S432 S431 S430 S429 S428 S427 S426 S425 S424 S423 S422 S421 S420 S419 S418 S417 S416 S415 S414 S413 S412 S411 S410 S409 S408 S407 S406 S405 S404 S403 S402 S401 S400 S399 S398 S397 S396 S395 S394 S393 S392 S391 S390 S389 S388 S387 X 1430.0 1410.0 1390.0 1370.0 1350.0 1330.0 1310.0 1290.0 1270.0 1250.0 1230.0 1210.0 1190.0 1170.0 1150.0 1130.0 1110.0 1090.0 1070.0 1050.0 1030.0 1010.0 990.0 970.0 950.0 930.0 910.0 890.0 870.0 850.0 830.0 810.0 790.0 770.0 750.0 730.0 710.0 690.0 670.0 650.0 630.0 610.0 590.0 570.0 550.0 530.0 510.0 490.0 470.0 450.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 R61505U Pad Coordinate (Unit:μm) pad No 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 pad name S386 S385 S384 S383 S382 S381 S380 S379 S378 S377 S376 S375 S374 S373 S372 S371 S370 S369 S368 S367 S366 S365 S364 S363 S362 S361 S360 S359 S358 S357 S356 S355 S354 S353 S352 S351 S350 S349 S348 S347 S346 S345 S344 S343 S342 S341 S340 S339 S338 S337 X 430.0 410.0 390.0 370.0 350.0 330.0 310.0 290.0 270.0 250.0 230.0 210.0 190.0 170.0 150.0 130.0 110.0 90.0 70.0 50.0 30.0 10.0 -10.0 -30.0 -50.0 -70.0 -90.0 -110.0 -130.0 -150.0 -170.0 -190.0 -210.0 -230.0 -250.0 -270.0 -290.0 -310.0 -330.0 -350.0 -370.0 -390.0 -410.0 -430.0 -450.0 -470.0 -490.0 -510.0 -530.0 -550.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 2005.11.30 rev0.1 pad No 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 pad name S336 S335 S334 S333 S332 S331 S330 S329 S328 S327 S326 S325 S324 S323 S322 S321 S320 S319 S318 S317 S316 S315 S314 S313 S312 S311 S310 S309 S308 S307 S306 S305 S304 S303 S302 S301 S300 S299 S298 S297 S296 S295 S294 S293 S292 S291 S290 S289 S288 S287 X -570.0 -590.0 -610.0 -630.0 -650.0 -670.0 -690.0 -710.0 -730.0 -750.0 -770.0 -790.0 -810.0 -830.0 -850.0 -870.0 -890.0 -910.0 -930.0 -950.0 -970.0 -990.0 -1010.0 -1030.0 -1050.0 -1070.0 -1090.0 -1110.0 -1130.0 -1150.0 -1170.0 -1190.0 -1210.0 -1230.0 -1250.0 -1270.0 -1290.0 -1310.0 -1330.0 -1350.0 -1370.0 -1390.0 -1410.0 -1430.0 -1450.0 -1470.0 -1490.0 -1510.0 -1530.0 -1550.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 R61505U Pad Coordinate (Unit:μm) pad No 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 pad name S286 S285 S284 S283 S282 S281 S280 S279 S278 S277 S276 S275 S274 S273 S272 S271 S270 S269 S268 S267 S266 S265 S264 S263 S262 S261 S260 S259 S258 S257 S256 S255 S254 S253 S252 S251 S250 S249 S248 S247 S246 S245 S244 S243 S242 S241 S240 S239 S238 S237 X -1570.0 -1590.0 -1610.0 -1630.0 -1650.0 -1670.0 -1690.0 -1710.0 -1730.0 -1750.0 -1770.0 -1790.0 -1810.0 -1830.0 -1850.0 -1870.0 -1890.0 -1910.0 -1930.0 -1950.0 -1970.0 -1990.0 -2010.0 -2030.0 -2050.0 -2070.0 -2090.0 -2110.0 -2130.0 -2150.0 -2170.0 -2190.0 -2210.0 -2230.0 -2250.0 -2270.0 -2290.0 -2310.0 -2330.0 -2350.0 -2370.0 -2390.0 -2410.0 -2430.0 -2450.0 -2470.0 -2490.0 -2510.0 -2530.0 -2550.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 2005.11.30 rev0.1 pad No 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 pad name S236 S235 S234 S233 S232 S231 S230 S229 S228 S227 S226 S225 S224 S223 S222 S221 S220 S219 S218 S217 S216 S215 S214 S213 S212 S211 S210 S209 S208 S207 S206 S205 S204 S203 S202 S201 S200 S199 S198 S197 S196 S195 S194 S193 S192 S191 S190 S189 S188 S187 X -2570.0 -2590.0 -2610.0 -2630.0 -2650.0 -2670.0 -2690.0 -2710.0 -2730.0 -2750.0 -2770.0 -2790.0 -2810.0 -2830.0 -2850.0 -2870.0 -2890.0 -2910.0 -2930.0 -2950.0 -2970.0 -2990.0 -3010.0 -3030.0 -3050.0 -3070.0 -3090.0 -3110.0 -3130.0 -3150.0 -3170.0 -3190.0 -3210.0 -3230.0 -3250.0 -3270.0 -3290.0 -3310.0 -3330.0 -3350.0 -3370.0 -3390.0 -3410.0 -3430.0 -3450.0 -3470.0 -3490.0 -3510.0 -3530.0 -3550.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 R61505U Pad Coordinate (Unit:μm) pad No 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 pad name S186 S185 S184 S183 S182 S181 S180 S179 S178 S177 S176 S175 S174 S173 S172 S171 S170 S169 S168 S167 S166 S165 S164 S163 S162 S161 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 S144 S143 S142 S141 S140 S139 S138 S137 X -3570.0 -3590.0 -3610.0 -3630.0 -3650.0 -3670.0 -3690.0 -3710.0 -3730.0 -3750.0 -3770.0 -3790.0 -3810.0 -3830.0 -3850.0 -3870.0 -3890.0 -3910.0 -3930.0 -3950.0 -3970.0 -3990.0 -4010.0 -4030.0 -4050.0 -4070.0 -4090.0 -4110.0 -4130.0 -4150.0 -4170.0 -4190.0 -4210.0 -4230.0 -4250.0 -4270.0 -4290.0 -4310.0 -4330.0 -4350.0 -4370.0 -4390.0 -4410.0 -4430.0 -4450.0 -4470.0 -4490.0 -4510.0 -4530.0 -4550.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 2005.11.30 rev0.1 pad No 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 pad name S136 S135 S134 S133 S132 S131 S130 S129 S128 S127 S126 S125 S124 S123 S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 S88 S87 X -4570.0 -4590.0 -4610.0 -4630.0 -4650.0 -4670.0 -4690.0 -4710.0 -4730.0 -4750.0 -4770.0 -4790.0 -4810.0 -4830.0 -4850.0 -4870.0 -4890.0 -4910.0 -4930.0 -4950.0 -4970.0 -4990.0 -5010.0 -5030.0 -5050.0 -5070.0 -5090.0 -5110.0 -5130.0 -5150.0 -5170.0 -5190.0 -5210.0 -5230.0 -5250.0 -5270.0 -5290.0 -5310.0 -5330.0 -5350.0 -5370.0 -5390.0 -5410.0 -5430.0 -5450.0 -5470.0 -5490.0 -5510.0 -5530.0 -5550.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 R61505U Pad Coordinate (Unit:μm) pad No 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 pad name S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 X -5570.0 -5590.0 -5610.0 -5630.0 -5650.0 -5670.0 -5690.0 -5710.0 -5730.0 -5750.0 -5770.0 -5790.0 -5810.0 -5830.0 -5850.0 -5870.0 -5890.0 -5910.0 -5930.0 -5950.0 -5970.0 -5990.0 -6010.0 -6030.0 -6050.0 -6070.0 -6090.0 -6110.0 -6130.0 -6150.0 -6170.0 -6190.0 -6210.0 -6230.0 -6250.0 -6270.0 -6290.0 -6310.0 -6330.0 -6350.0 -6370.0 -6390.0 -6410.0 -6430.0 -6450.0 -6470.0 -6490.0 -6510.0 -6530.0 -6550.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 2005.11.30 rev0.1 pad No 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 pad name S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 TESTO35 TESTO36 VGLDMY3 G320 G318 G316 G314 G312 G310 G308 G306 G304 G302 G300 X -6570.0 -6590.0 -6610.0 -6630.0 -6650.0 -6670.0 -6690.0 -6710.0 -6730.0 -6750.0 -6770.0 -6790.0 -6810.0 -6830.0 -6850.0 -6870.0 -6890.0 -6910.0 -6930.0 -6950.0 -6970.0 -6990.0 -7010.0 -7030.0 -7050.0 -7070.0 -7090.0 -7110.0 -7130.0 -7150.0 -7170.0 -7190.0 -7210.0 -7230.0 -7250.0 -7270.0 -7290.0 -7350.0 -7370.0 -7390.0 -7410.0 -7430.0 -7450.0 -7470.0 -7490.0 -7510.0 -7530.0 -7550.0 -7570.0 -7590.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 R61505U Pad Coordinate (Unit:μm) pad No 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 pad name G298 G296 G294 G292 G290 G288 G286 G284 G282 G280 G278 G276 G274 G272 G270 G268 G266 G264 G262 G260 G258 G256 G254 G252 G250 G248 G246 G244 G242 G240 G238 G236 G234 G232 G230 G228 G226 G224 G222 G220 G218 G216 G214 G212 G210 G208 G206 G204 G202 G200 X -7610.0 -7630.0 -7650.0 -7670.0 -7690.0 -7710.0 -7730.0 -7750.0 -7770.0 -7790.0 -7810.0 -7830.0 -7850.0 -7870.0 -7890.0 -7910.0 -7930.0 -7950.0 -7970.0 -7990.0 -8010.0 -8030.0 -8050.0 -8070.0 -8090.0 -8110.0 -8130.0 -8150.0 -8170.0 -8190.0 -8210.0 -8230.0 -8250.0 -8270.0 -8290.0 -8310.0 -8330.0 -8350.0 -8370.0 -8390.0 -8410.0 -8430.0 -8450.0 -8470.0 -8490.0 -8510.0 -8530.0 -8550.0 -8570.0 -8590.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 2005.11.30 rev0.1 pad No 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 pad name G198 G196 G194 G192 G190 G188 G186 G184 G182 G180 G178 G176 G174 G172 G170 G168 G166 G164 G162 G160 G158 G156 G154 G152 G150 G148 G146 G144 G142 G140 G138 G136 G134 G132 G130 G128 G126 G124 G122 G120 G118 G116 G114 G112 G110 G108 G106 G104 G102 G100 X -8610.0 -8630.0 -8650.0 -8670.0 -8690.0 -8710.0 -8730.0 -8750.0 -8770.0 -8790.0 -8810.0 -8830.0 -8850.0 -8870.0 -8890.0 -8910.0 -8930.0 -8950.0 -8970.0 -8990.0 -9010.0 -9030.0 -9050.0 -9070.0 -9090.0 -9110.0 -9130.0 -9150.0 -9170.0 -9190.0 -9210.0 -9230.0 -9250.0 -9270.0 -9290.0 -9310.0 -9330.0 -9350.0 -9370.0 -9390.0 -9410.0 -9430.0 -9450.0 -9470.0 -9490.0 -9510.0 -9530.0 -9550.0 -9570.0 -9590.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 R61505U Pad Coordinate (Unit:μm) pad No 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 pad name G98 G96 G94 G92 G90 G88 G86 G84 G82 G80 G78 G76 G74 G72 G70 G68 G66 G64 G62 G60 G58 G56 G54 G52 G50 G48 G46 G44 G42 G40 G38 G36 G34 G32 G30 G28 G26 G24 G22 G20 G18 G16 G14 G12 G10 G8 G6 G4 G2 VGLDMY4 X -9610.0 -9630.0 -9650.0 -9670.0 -9690.0 -9710.0 -9730.0 -9750.0 -9770.0 -9790.0 -9810.0 -9830.0 -9850.0 -9870.0 -9890.0 -9910.0 -9930.0 -9950.0 -9970.0 -9990.0 -10010.0 -10030.0 -10050.0 -10070.0 -10090.0 -10110.0 -10130.0 -10150.0 -10170.0 -10190.0 -10210.0 -10230.0 -10250.0 -10270.0 -10290.0 -10310.0 -10330.0 -10350.0 -10370.0 -10390.0 -10410.0 -10430.0 -10450.0 -10470.0 -10490.0 -10510.0 -10530.0 -10550.0 -10570.0 -10590.0 Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 2005.11.30 rev0.1 pad No 1351 1352 1353 1354 pad name DUMMYR9 DUMMYR10 TESTO37 TESTO38 X -10610.0 -10630.0 -10650.0 -10670.0 Y 386.5 511.5 386.5 511.5 R61505U Pad Coordinate (Unit:μm) Alignment mark 1-a 1-b X -10613.0 10613.0 Y -468.0 -468.0 2005.11.30 rev0.1 R61505U BUMP arrangement 20 21 100 S1 ~ S720, G1 ~ G320 DUMMY* DUMMYR* TESTO* VGLDMY* (No.299 ~ No.1354) 25 225 S = 2100 μm2 Unit: μm 50 I/O pins (No.1 ~ No.298) 20 S = 4000 μm2 80 Min. 70 Figure 2 Rev.1.0 September 13, 2006, page 39 of 199 Unit: μm ■R61505U Recommended connection example and resistance Rev1.1 2006.02.16 □ □ □ PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 □ (1-a) open open open open VPP1 ≦25ohm VPP2 ≦15ohm VPP3 ≦25ohm open open IOVCC ≦100ohm IM0/ID IM1 IM2 IM3 ≦100ohm ≦100ohm ≦100ohm ≦100ohm RESET* VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm open open open open open DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDO SDI RD* WR*/SCL RS CS* ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm ≦100ohm FMARK ≦100ohm open open open open open open open open open open open open open open open open open open open open open open open open open ≦10ohm IOVCC ≦10ohm VCC ≦10ohm 1uF ≦5ohm open open open open open open ≦5ohm ≦15ohm GND ≦5ohm open open open VGS ≦100ohm open open open open open open ≦10ohm 1u ≦10ohm 1u ≦10ohm open open 1uF open open open open 1uF ≦25ohm 1uF ≦10ohm 1uF ≦10ohm ≦100ohm VCI ≦5ohm 1uF ≦15ohm ≦15ohm 1uF ≦15ohm ≦15ohm open 1uF ≦10ohm open open open 1uF ≦20ohm open 1uF ≦25ohm open ≦25ohm open 1uF ≦25ohm ≦25ohm 1uF ≦25ohm ≦25ohm 1uF ≦25ohm ≦25ohm open open open DUMMYR1 □ DUMMYR2 □ TESTO1 □ VCCDUM1 □ VPP1 □ VPP1 □ VPP1 □ VPP2 □ VPP2 □ VPP2 □ VPP2 □ VPP2 □ VPP3 □ VPP3 □ VPP3 □ TESTO2 □ IOGNDDUM1 □ TESTO3 □ TEST1 □ TEST2 □ TEST4 □ TEST5 □ TEST3 □ IM0/ID □ IM1 □ IM2 □ IM3 □ TESTO4 □ IOVCCDUM1 □ TESTO5 □ RESET* □ VSYNC □ HSYNC □ DOTCLK □ ENABLE □ DB17 □ DB16 □ DB15 □ DB14 □ DB13 □ DB12 □ DB11 □ DB10 □ DB9 □ DB8 □ TESTO6 □ IOGNDDUM2 □ TESTO7 □ DB7 □ DB6 □ DB5 □ DB4 □ DB3 □ DB2 □ DB1 □ DB0 □ SDO □ SDI □ RD* □ WR*/SCL □ RS □ CS* □ TESTO8 □ IOVCCDUM2 □ TESTO9 □ FMARK □ TS8 □ TS7 □ TS6 □ TS5 □ TS4 □ TS3 □ TS2 □ TS1 □ TS0 □ TSC □ TESTO10 □ IOGNDDUM3 □ TESTO11 □ TESTO12 □ OSC1DUM1 □ OSC1DUM2 □ OSC1 □ OSC1DUM3 □ OSC1DUM4 □ OSC2 □ OSC2DUM1 □ OSC2DUM2 □ DUMMYR3 □ DUMMYR4 □ IOGND □ IOGND □ IOGND □ IOGND □ IOGND □ IOGND □ IOGND □ IOVCC □ IOVCC □ IOVCC □ IOVCC □ IOVCC □ IOVCC □ IOVCC □ VCC □ VCC □ VCC □ VCC □ VCC □ VCC □ VCC □ VCC □ VDD □ VDD □ VDD □ VDD □ VDD □ VDD □ VDD □ VDD □ VDD □ VDD □ VDD □ VDD □ VDD □ TESTO13 □ VREFD □ TESTO14 □ VREF □ TESTO15 □ VREFC □ TESTO16 □ VDDTEST □ AGND □ AGND □ AGND □ AGND □ AGND □ AGND □ AGND □ AGND □ AGND □ AGND □ AGND □ GND □ GND □ GND □ GND □ GND □ GND □ RGND □ RGND □ RGND □ RGND □ RGND □ RGND □ RGND □ RGND □ RGND □ RGND □ TESTO17 □ VTEST □ TESTO18 □ VGS □ TESTO19 □ V0T □ TESTO20 □ VMON □ TESTO21 □ V31T □ VCOM □ VCOM □ VCOM □ VCOM □ VCOM □ VCOM □ VCOMH □ VCOMH □ VCOMH □ VCOMH □ VCOMH □ VCOMH □ VCOML □ VCOML □ VCOML □ VCOML □ VCOML □ VCOML □ TESTO22 □ TESTO23 □ VREG1OUT □ TESTO24 □ TESTA5 □ TESTO25 □ VcomR □ TESTO26 □ VCL □ VCL □ VCL □ VLOUT1 □ VLOUT1 □ VLOUT1 □ DDVDH □ DDVDH □ DDVDH □ DDVDH □ DDVDH □ DDVDH □ DDVDH □ VCIOUT □ VCIOUT □ VCIOUT □ VCI1 □ VCI1 □ VCI1 □ VCI1 □ VCI1 □ VCILVL □ VCI □ VCI □ VCI □ VCI □ VCI □ VCI □ VCI □ VCI □ C12- □ C12- □ C12- □ C12- □ C12- □ C12+ □ C12+ □ C12+ □ C12+ □ C12+ □ C11- □ C11- □ C11- □ C11- □ C11- □ C11+ □ C11+ □ C11+ □ C11+ □ C11+ □ AGNDDUM1 □ VLOUT3 □ VLOUT3 □ VGL □ VGL □ VGL □ VGL □ VGL □ VGL □ VGL □ VGL □ VGL □ VGL □ AGNDDUM2 □ AGNDDUM3 □ AGNDDUM4 □ VLOUT2 □ VLOUT2 □ VGH □ VGH □ VGH □ VGH □ TESTO27 □ C13- □ C13- □ C13- □ TESTO28 □ C13+ □ C13+ □ C13+ □ TESTO29 □ C21- □ C21- □ C21- □ C21+ □ C21+ □ C21+ □ C22- □ C22- □ C22- □ C22+ □ C22+ □ C22+ □ C23- □ C23- □ C23- □ C23+ □ C23+ □ C23+ □ TESTO30 □ DUMMYR5 □ DUMMYR6 □ No.1 □ □ □ □ □ □ □ □ □ □ □ □ □ TESTO38 TESTO37 DUMMYR10 DUMMYR9 VGLDMY4 G2 G4 G6 G8 G10 G312 G314 G316 G318 G320 VGLDMY3 TESTO36 60um □ □ □ □ □ □ □ □ □ TESTO35 S1 S2 S3 S4 S5 S6 S7 S8 R61505U Staggered output Top View (Bump View) Y X □ □ □ □ □ □ S716 S717 S718 S719 S720 TESTO34 220um □ □ □ □ □ □ □ □ □ □ □ □ No.298 (1-b) □ □ □ □ □ FPC Glass substrate Note: The wiring resistance is a recommended value and it is desirable to set the resistance as small as possible. TESTO33 VGLDMY2 G319 G317 G315 G313 G311 G9 G7 G5 G3 G1 VGLDMY1 DUMMYR8 DUMMYR7 TESTO32 TESTO31 R61505U GRAM address map GS=0 GS=1 S720 S719 S718 S717 S716 S715 S714 S713 S712 S711 S710 ...... S709 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S/G pin S1 Table 15 GRAM address and display position on the panel (SS = 0, BGR = 0) WD[17:0] WD[17:0] WD[17:0] WD[17:0] ..... WD[17:0] WD[17:0] WD[17:0] WD[17:0] G1 G320 h00000 h00001 h00002 h00003 ...... h000EC h000ED h000EE h000EF G2 G319 h00100 h00101 h00102 h00103 ...... h001EC h001ED h001EE h001EF G3 G318 h00200 h00201 h00202 h00203 ...... h002EC h002ED h002EE h002EF G4 G317 h00300 h00301 h00302 h00303 ...... h003EC h003ED h003EE h003EF G5 G316 h00400 h00401 h00402 h00403 ...... h004EC h004ED h004EE h004EF G6 G315 h00500 h00501 h00502 h00503 ...... h005EC h005ED h005EE h005EF G7 G314 h00600 h00601 h00602 h00603 ...... h006EC h006ED h006EE h006EF G8 G313 h00700 h00701 h00702 h00703 ...... h007EC h007ED h007EE h007EF G9 G312 h00800 h00801 h00802 h00803 ...... h008EC h008ED h008EE h008EF G10 G311 h00900 h00901 h00902 h00903 ...... h009EC h009ED h009EE h009EF G11 G310 h00A00 h00A01 h00A02 h00A03 ...... h00AEC h00AED h00AEE h00AEF G12 G309 h00B00 h00B01 h00B02 h00B03 ...... h00BEC h00BED h00BEE h00BEF G13 G308 h00C00 h00C01 h00C02 h00C03 ...... h00CEC h00CED h00CEE h00CEF G14 G307 h00D00 h00D01 h00D02 h00D03 ...... h00DEC h00DED h00DEE h00DEF G15 G306 h00E00 h00E01 h00E02 h00E03 ...... h00EEC h00EED h00EEE h00EEF G16 G305 h00F00 h00F01 h00F02 h00F03 ...... h00FEC h00FED h00FEE h00FEF G17 G304 h01000 h01001 h01002 h01003 ...... h010EC h010ED h010EE h010EF G18 G303 h01100 h01101 h01102 h01103 ...... h011EC h011ED h011EE h011EF G19 G302 h01200 h01201 h01202 h01203 ...... h012EC h012ED h012EE h012EF G20 G301 h01300 h01301 h01302 h01303 ...... h013EC h013ED h013EE h013EF : : : : : : : : : : : G305 G16 h13000 h13001 h13002 h13003 ...... h130EC h130ED h130EE h130EF G306 G15 h13100 h13101 h13102 h13103 ...... h131EC h131ED h131EE h131EF G307 G14 h13200 h13201 h13202 h13203 ...... h132EC h132ED h132EE h132EF G308 G13 h13300 h13301 h13302 h13303 ...... h133EC h133ED h133EE h133EF G309 G12 h13400 h13401 h13402 h13403 ...... h134EC h134ED h134EE h134EF G310 G11 h13500 h13501 h13502 h13503 ...... h135EC h135ED h135EE h135EF G311 G10 h13600 h13601 h13602 h13603 ...... h136EC h136ED h136EE h136EF G312 G9 h13700 h13701 h13702 h13703 ...... h137EC h137ED h137EE h137EF G313 G8 h13800 h13801 h13802 h13803 ...... h138EC h138ED h138EE h138EF G314 G7 h13900 h13901 h13902 h13903 ...... h139EC h139ED h139EE h139EF G315 G6 h13A00 h13A01 h13A02 h13A03 ...... h13AEC h13AED h13AEE h13AEF G316 G5 h13B00 h13B01 h13B02 h13B03 ...... h13BEC h13BED h13BEE h13BEF G317 G4 h13C00 h13C01 h13C02 h13C03 ...... h13CEC h13CED h13CEE h13CEF G318 G3 h13D00 h13D01 h13D02 h13D03 ...... h13DEC h13DED h13DEE h13DEF G319 G2 h13E00 h13E01 h13E02 h13E03 ...... h13EEC h13EED h13EEE h13EEF G320 G1 h13F00 h13F01 h13F02 h13F03 ...... h13FEC h13FED h13FEE h13FEF Rev.1.0 September 13, 2006, page 41 of 199 R61505U GS=0 GS=1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 ...... S12 S709 S710 S711 S712 S713 S714 S715 S716 S717 S718 S719 S/G pin S720 Table 16 GRAM address and display position on the panel (SS = 1, BGR = 1) WD[17:0] WD[17:0] WD[17:0] WD[17:0] ..... WD[17:0] WD[17:0] WD[17:0] WD[17:0] G1 G320 h00000 h00001 h00002 h00003 ...... h000EC h000ED h000EE h000EF G2 G319 h00100 h00101 h00102 h00103 ...... h001EC h001ED h001EE h001EF G3 G318 h00200 h00201 h00202 h00203 ...... h002EC h002ED h002EE h002EF G4 G317 h00300 h00301 h00302 h00303 ...... h003EC h003ED h003EE h003EF G5 G316 h00400 h00401 h00402 h00403 ...... h004EC h004ED h004EE h004EF G6 G315 h00500 h00501 h00502 h00503 ...... h005EC h005ED h005EE h005EF G7 G314 h00600 h00601 h00602 h00603 ...... h006EC h006ED h006EE h006EF G8 G313 h00700 h00701 h00702 h00703 ...... h007EC h007ED h007EE h007EF G9 G312 h00800 h00801 h00802 h00803 ...... h008EC h008ED h008EE h008EF G10 G311 h00900 h00901 h00902 h00903 ...... h009EC h009ED h009EE h009EF G11 G310 h00A00 h00A01 h00A02 h00A03 ...... h00AEC h00AED h00AEE h00AEF G12 G309 h00B00 h00B01 h00B02 h00B03 ...... h00BEC h00BED h00BEE h00BEF G13 G308 h00C00 h00C01 h00C02 h00C03 ...... h00CEC h00CED h00CEE h00CEF G14 G307 h00D00 h00D01 h00D02 h00D03 ...... h00DEC h00DED h00DEE h00DEF G15 G306 h00E00 h00E01 h00E02 h00E03 ...... h00EEC h00EED h00EEE h00EEF G16 G305 h00F00 h00F01 h00F02 h00F03 ...... h00FEC h00FED h00FEE h00FEF G17 G304 h01000 h01001 h01002 h01003 ...... h010EC h010ED h010EE h010EF G18 G303 h01100 h01101 h01102 h01103 ...... h011EC h011ED h011EE h011EF G19 G302 h01200 h01201 h01202 h01203 ...... h012EC h012ED h012EE h012EF G20 G301 h01300 h01301 h01302 h01303 ...... h013EC h013ED h013EE h013EF : : : : : : : : : : : G305 G16 h13000 h13001 h13002 h13003 ...... h130EC h130ED h130EE h130EF G306 G15 h13100 h13101 h13102 h13103 ...... h131EC h131ED h131EE h131EF G307 G14 h13200 h13201 h13202 h13203 ...... h132EC h132ED h132EE h132EF G308 G13 h13300 h13301 h13302 h13303 ...... h133EC h133ED h133EE h133EF G309 G12 h13400 h13401 h13402 h13403 ...... h134EC h134ED h134EE h134EF G310 G11 h13500 h13501 h13502 h13503 ...... h135EC h135ED h135EE h135EF G311 G10 h13600 h13601 h13602 h13603 ...... h136EC h136ED h136EE h136EF G312 G9 h13700 h13701 h13702 h13703 ...... h137EC h137ED h137EE h137EF G313 G8 h13800 h13801 h13802 h13803 ...... h138EC h138ED h138EE h138EF G314 G7 h13900 h13901 h13902 h13903 ...... h139EC h139ED h139EE h139EF G315 G6 h13A00 h13A01 h13A02 h13A03 ...... h13AEC h13AED h13AEE h13AEF G316 G5 h13B00 h13B01 h13B02 h13B03 ...... h13BEC h13BED h13BEE h13BEF G317 G4 h13C00 h13C01 h13C02 h13C03 ...... h13CEC h13CED h13CEE h13CEF G318 G3 h13D00 h13D01 h13D02 h13D03 ...... h13DEC h13DED h13DEE h13DEF G319 G2 h13E00 h13E01 h13E02 h13E03 ...... h13EEC h13EED h13EEE h13EEF G320 G1 h13F00 h13F01 h13F02 h13F03 ...... h13FEC h13FED h13FEE h13FEF Rev.1.0 September 13, 2006, page 42 of 199 R61505U Instruction Outline The R61505U adopts 18-bit bus architecture in order to interface to high-performance microcomputer in high speed. The R61505U starts internal processing after storing control information of externally sent data (16, 8, 1 bit(s)) in the instruction register (IR) and the data register (DR). Since the internal operation of the R61505U is controlled by the signals sent from the microcomputer, the register selection signal (RS), the read/write signal (R/W), and the internal 16-bit data bus signals (IB15 ~ IB0) are called instruction. When accessing the R61505U’s internal RAM, data is processed in units of 18 bits. The following are the kinds of instruction of the R61505U. 1. 2. 3. 4. Specify index Display control Power management control Set internal GRAM address 5. 6. 7. 8. Transfer data to and from the internal GRAM γ-correction Window address control Panel Display Control Normally, the instruction to write data is used the most often. The internal GRAM address is updated automatically as data is written to the internal GRAM, which, in combination with the window address function, contributes to minimizing data transfer and thereby lessens the load on the microcomputer. The R61505U writes instructions consecutively by executing the instruction within the cycle when it is written (instruction execution time: 0 cycle). Instruction Data Format As the following figure shows, the data bus used to transfer 16 instruction bits (IB[15:0]) is different according to the interface format. Make sure to transfer the instruction bits according to the format of the selected interface. Rev.1.0 September 13, 2006, page 43 of 199 R61505U The following are detail descriptions of instruction bits (IB15-0). Note that the instruction bits IB[15:0] in the following figures are transferred according to the format of the selected interface. Index (IR) R/W W RS 0 IB15 * IB14 * IB13 IB12 * * IB11 * IB10 * IB9 * IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 * ID [7] ID [6] ID [5] ID [4] ID [3] ID [2] ID [1] ID [0] The index register specifies the index R00h to RFFh of the control register or RAM control to be accessed using a binary number from “0000_0000” to “1111_1111”. The access to the register and instruction bits in it is prohibited unless the index is specified in the index register. Display control Device code read (R00h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R 1 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 1 The device code “1505”H is read out when reading out this register forcibly. Rev.1.0 September 13, 2006, page 44 of 199 R61505U Driver Output Control (R01h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 0 0 0 SM 0 SS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default value SS: Sets the shift direction of output from the source driver. When SS = “0”, the source driver output shift from S1 to S720. When SS = “1”, the source driver output shift from S720 to S1. The combination of SS and BGR settings determines the RGB assignment to the source driver pins S1 ~ S720. When SS = “0” and BGR = “0”, RGB dots are assigned one to one from S1 to S720. When SS = “1” and BGR = “1”, RGB dots are assigned one to one from S720 to S1. When changing the SS and BGR bits, RAM data must be rewritten. SM: Controls the scan mode in combination with GS setting. See “ Scan mode setting”. LCD Driving Wave Control (R02h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 0 0 0 1 BC0 EOR 0 0 0 0 0 0 0 NW0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Default value NW0: When BC0=1, NW bit sets number of line, N, as alternating cycle of line inversion. Line inversion is operated every N+1 line cycle. NW bit can be set to 1 or 2. BC0: Selects the liquid crystal drive waveform VCOM. See “Line Inversion AC Drive” for details. BC = 0: frame inversion waveform is selected. BC = 1: line inversion waveform is selected when EOR = 1. In either liquid crystal drive method; the polarity inversion is halted in blank period (back and front porch periods). EOR: Enables liquid-crystal line-inversion drive when EOR = 1 and BC0 = 1 Rev.1.0 September 13, 2006, page 45 of 199 R61505U Entry Mode (R03h) R/W RS W 1 Default value IB15 IB14 IB13 TRIR DFM 0 EG 0 0 0 IB12 IB11 IB10 IB9 IB8 IB7 IB6 BGR 0 0 HWM 0 ORG 0 0 0 0 0 0 0 0 IB5 I/D [1] IB4 I/D [0] 1 1 IB3 IB2 IB1 IB0 AM 0 0 0 0 0 0 0 The entry mode register includes instruction bits for setting how to write data from the microcomputer to the internal GRAM of the R61505U. AM: Sets either horizontal or vertical direction in updating the address counter automatically as the R61505U writes data to the internal GRAM. AM = “0”, sets the horizontal direction. AM = “1”, sets the vertical direction. When making a window address area, the data is written only within the area in the direction determined by I/D1-0, AM bits. I/D[1:0]: Either increments (+1) or decrements (-1) the address counter (AC) automatically as the data is written to the GRAM. The I/D[0] bit sets either increment or decrement in horizontal direction (updates the address AD[7:0]). The I/D[1] bit sets either increment or decrement in vertical direction (updates the address AD[8:16]). The AM bit sets either horizontal or vertical direction in updating RAM address counter automatically when writing data to the internal RAM. ORG: Moves the origin address according to the ID setting when a window address area is made. This function is enabled when writing data within the window address area using high-speed RAM write function. Also see Figure 3 and Figure 4. ORG = 0: The origin address is not moved. In this case, specify the address to start write operation according to the GRAM address map within the window address area. ORG = 1: The origin address “h00000” is moved according to the I/D[1:0] setting. Notes: 1. When ORG = 1, only the origin address “h00000” can be set in the RAM address set registers (R20h, R21h). 2. In RAM read operation, make sure to set ORG = 0. HWM: The R61505U writes data in high speed with low power consumption by setting HWM = 1. The data to be written within the window address area is buffered in order to write the data in units of horizontal lines. This can minimize the number of RAM access and the power consumption required in data write operation. When HWM = 1, make sure to set AM = 0 (horizontal direction) and write the data in each horizontal line of the window address area at a time. If the data is not enough to rewrite the horizontal line of the window address area, the GRAM data in that line is not overwritten. Notes: 1. The R61505U requires no dummy write operation in high-speed write operation. 2. When terminating RAM data write operation in the middle of the line and executing another instruction, the data in the buffer is cleared. Rev.1.0 September 13, 2006, page 46 of 199 R61505U 3. When switching from high-speed RAM write operation to index write operation, wait at least 2 normal-write cycle periods (2 tcycw periods). BGR: Reverses the order from RGB to BGR in writing 18-bit pixel data in the GRAM. BGR = 0: BGR = 1: Write data in the order of RGB to the GRAM. Reverse the order from RGB to BGR in writing data to the GRAM. BGR = 0 D17 R5 D16 R4 D15 R3 D14 R2 D13 R1 D12 R0 D11 G5 D10 G4 D9 G3 D8 G2 D7 G1 D6 G0 D5 B5 D4 B4 D3 B3 D2 B2 D1 B1 D0 B0 D15 B3 D14 B2 D13 B1 D12 B0 D11 G5 D10 G4 D9 G3 D8 G2 D7 G1 D6 G0 D5 R5 D4 R4 D3 R3 D2 R2 D1 R1 D0 R0 BGR = 1 D17 B5 D16 B4 DFM: In combination with the TRIREG setting, sets the format to develop 16-/8-bit data to 18-bit data when using either 16-bit or 8-bit bus interface. Make sure to set DFM = 0 when not transferring data via 16-bit or 8-bit interface. TRIREG: Selects the format to transfer data bits via 16-bit or 8-bit interface. In 8-bit interface operation, TRIREG = 0: 16-bit RAM data is transferred in two transfers. TRIREG = 1: 18-bit RAM data is transferred in three transfers. In 16-bit bus interface operation, TRIREG = 0: 16-bit RAM data is transferred in one transfer. TRIREG = 1: 18-bit RAM data is transferred in two transfers. Make sure TRIREG = 0 when not transferring data via 16-bit or 8-bit interface. Also, set TRIREG = 0 during read operation. Rev.1.0 September 13, 2006, page 47 of 199 R61505U ORG = 0 I/D1-0 = "00" Horizontal: Decrement Vertical: Decrement 17'h00000 I/D1-0 = "01" Horizontal: Increment Vertical: Decrement 17'h00000 I/D1-0 = "10" Horizontal: Decrement Vertical: Increment I/D1-0 ="11" Horizontal: Increment Vertical: Increment 17'h00000 17'h00000 AM = "0" Horizontal 17'h13FEF 17'h13FEF 17'h00000 17'h00000 17'h13FEF 17'h00000 17'h13FEF 17'h00000 AM = "1" Vertical 17'h13FEF 17'h13FEF 17'h13FEF 17'h13FEF Figure 3 Automatic address update (ORG = 0, AM, ID) Note: When writing data within the window address area with ORG = 0, any address within the window address area can be designated as the starting point of RAM write operation. ORG = 1 I/D1-0 = "00" Horizontal: Decrement Vertical: Decrement 17'h00000 I/D1-0 = "01" Horizontal: Increment Vertical: Decrement 17'h00000 I/D1-0 = "10" Horizontal: Decrement Vertical: Increment 17'h00000 I/D1-0 = "11" Horizontal: Increment Vertical: Increment 17'h00000 S S AM = "0" Horizontal S S 17'h13FEF 17'h00000 17'h13FEF 17'h00000 17'h13FEF 17'h00000 17'h13FEF 17'h00000 S S AM = "1" Vertical S 17'h13FEF S 17'h13FEF 17'h13FEF 17'h13FEF Figure 4 Automatic address update (ORG = 1, AM, ID) Notes: 1. When ORG = 1, make sure to set the address “h00000” in the RAM address set registers (R210h, R21h). Setting other addresses is inhibited. 2. When ORG = 1, the starting point of writing data within the window address area can be set at either corner of the window address area (“S” in circle in the above figure). Rev.1.0 September 13, 2006, page 48 of 199 R61505U Resizing Control (R04h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 W 1 0 0 0 0 0 0 0 0 0 0 0 0 Default value IB9 IB8 RCV RCV [1] [0] 0 0 IB7 IB6 0 0 0 0 IB5 IB4 RCH RCH [1] [0] 0 0 IB3 IB2 0 0 0 0 IB1 RSZ [1] IB0 RSZ [0] 0 0 RSZ[1:0]: Sets the resizing factor. When the RSZ bits are set for resizing, the R61505U writes the data according to the resizing factor so that the original image is displayed in horizontal and vertical dimensions contracted according to the factor . See “Resizing function”. RCH[1:0]: Sets the number of pixels made as the remainder in horizontal direction when resizing a picture. By specifying the number of remainder pixels with RCH bits, the data can be transferred without taking the reminder pixels into consideration. Make sure that RCH = 2’h0 when not using the resizing function (RSZ = 2’h0) or there are no remainder pixels. RCV[1:0]: Sets the number of pixels made as the remainder in vertical direction when resizing a picture. By specifying the number of remainder pixels with the RCV bits, the data can be transferred without taking the reminder pixels into consideration. Make sure that RCV = 2’h0 when not using the resizing function (RSZ = 2’h0) or there are no remainder pixels. Table 17 Resizing factor (RSR) RSZ [1:0] Resizing Scale 2’h0 No resizing (x1) 2’h1 x 1/2 2’h2 Setting inhibited 2’h3 x 1/4 Table 18 Remainder Pixels in Horizontal Direction (RCH) RCH [1:0] Number of remainder Pixels in Horizontal Direction 2’h0 0 pixel 2’h1 1 pixel 2’h2 2 pixels 2’h3 Note: 3 pixels 1 pixel = 1RGB Table 19 Remainder Pixels in Vertical Direction (RCV) RCV [1:0] Number of remainder Pixels in Vertical Direction 2’h0 0 pixel 2’h1 1 pixel 2’h2 2 pixels 2’h3 Note: 3 pixels 1 pixel = 1RGB Rev.1.0 September 13, 2006, page 49 of 199 R61505U Display Control 1 (R07h) R/W RS IB15 IB14 W 1 0 0 0 0 Default value IB13 IB12 IB11 PTDE PTDE 0 [1] [0] 0 0 IB10 IB9 0 0 0 0 0 IB8 BASE E IB7 IB6 IB5 IB4 IB3 IB2 0 VON GON DTE COL 0 0 0 0 0 0 0 0 IB1 D [1] IB0 D [0] 0 0 D[1:0]: A graphics display is turned on when writing D1 = “1”, and is turned off when writing D1 = “0”. When writing D1 = “0”, the graphics display data is retained in the internal GRAM and the R61505U displays the data when writing D1 = “1”. When D1 = “0”, i.e. while no display is shown on the panel, all source outputs becomes the GND level to reduce charging/discharging current, which is generated within the LCD while driving liquid crystal with AC voltage. When the display is turned off by setting D1-0 = 2’b01, the R61505U continues internal display operation. When the display is turned off by setting D1-0 = 2’b00, the R61505U’s internal display operation is halted completely. In combination with the GON setting, the D[1:0] setting controls display ON/OFF. For details, see “Instruction Setting”. Table 20 Source output level and display operation D[1:0] BASEE Source Output (S1-720) FMARK signal Internal Operation 2’h0 * GND Halt Halt 2’h1 * GND Operation Operation 2’h2 * Non-lit display Operation Operation 2’h3 0 Non-lit display Operation Operation 1 Base-image display Operation Operation Notes: 1: The data write operation from the microcomputer is not affected by the D[1:0] setting. 2: The PTS bits set the source output level for “Non-lit display”. 3: The LCD drive level during non-lit display period is determined by NDL setting. COL: When COL = 1, 30 grayscale amplifiers other than V0 and V30 halt to display using less power. When setting 8-color display mode, follow the sequence of 8-color display mode setting. Table 21 COL Operating amplifier Display color 0 32 262,144 1 2 8 Note: When COL = 1, do not write the data corresponding to the grayscales, for which the operation of amplifier is halted. Rev.1.0 September 13, 2006, page 50 of 199 R61505U GON, DTE: The combination of GON and DTE settings set the output level form gate lines (G1 ~ G320). When GON = 0, the VCOM output level becomes the GND level. Table 22 APE 0 1 GON DTE G1~G320 * * VGL (= GND) 0 0 VGH 0 1 VGH 1 0 VGL 1 1 VGH/VGL VON: Controls VCOMH, VCOML, VCOM amplitude signal output. Table 23 APE 0 1 AP[1:0] VON VCOM output * * GND 0 0 GND 0 1 Setting disabled 1~3 0 GND 1~3 1 VCOMH/VCOML BASEE: Base image display enable bit. BASEE = 0: No base image is displayed. The R61505U drives liquid crystal with non-lit display level or drives only partial image display areas. BASEE = 1: A base image is displayed on the screen. The D[1:0] setting has precedence over the BASEE setting. PTDE[1:0]: PTDE[0] is the display enable bit of partial image 1. PTDE[1] is the display enable bit of partial image 2. When PTDE1/0 = 0, the partial image is turned off and only base image is displayed on the screen. When PTDE1/0 = 1, the partial image is displayed on the screen. In this case, turn off the base image by setting BASEE = 0. Rev.1.0 September 13, 2006, page 51 of 199 R61505U Display Control 2 (R08h) R/W RS IB15 IB14 IB13 IB12 W 1 0 0 0 0 0 0 0 0 Default value IB11 FP [3] IB10 FP [2] IB9 FP [1] IB8 FP [0] IB7 IB6 IB5 IB4 0 0 0 0 1 0 0 0 0 0 0 0 IB3 BP [3] IB2 BP [2] IB1 BP [1] IB0 BP [0] 1 0 0 0 FP [3:0]: Sets the number of lines for a front porch period (a blank period following the end of display). BP [3:0]: Sets the number of lines for a back porch period (a blank period made before the beginning of display). In external display interface operation, a back porch (BP) period starts on the falling edge of the VSYNC signal and the display operation starts after the back porch period. A blank period will start after a front porch (FP) period and it will continue until next VSYNC input is detected. Note to Setting BP and FP Set the BP and FP bits as follows in respective operation modes. Table 24 BP and FP Settings Internal clock operation mode BP ≥ 2 lines FP ≥ 2 lines FP + BP ≤ 16 lines RGB interface operation BP ≥ 2 lines FP ≥ 2 lines FP + BP ≤ 16 lines VSYNC interface operation BP ≥ 2 lines FP ≥ 2 lines FP + BP = 16 lines Table 25 Front and Back Porch period (Line periods) FP[3:0] BP[3:0] Front and Back Porch period (Line periods) 4’h0 Setting inhibited 4’h1 Setting inhibited 4’h2 2 lines 4’h3 3 lines 4’h4 4 lines 4’h5 5 lines 4’h6 6 lines 4’h7 7 lines 4’h8 8 lines 4’h9 9 lines 4’hA 10 lines 4’hB 11 lines 4’hC 12 lines 4’hD 13 lines 4’hE 14 lines 4’hF Setting inhibited Rev.1.0 September 13, 2006, page 52 of 199 R61505U VSYNC Back porch Display area Front porch Note : The output timing to the LCD panel is delayed by two line periods from the synchronous signal (VSYNC) input timing. Figure 5 Front and Back Porch periods Display Control 3 (R09h) R/W RS IB15 IB14 IB13 IB12 IB11 W 1 0 0 0 0 0 0 0 0 0 0 Default value IB10 PTS [2] IB9 PTS [1] IB8 PTS [0] IB7 IB6 0 0 0 0 0 0 0 IB5 PTG [1] IB4 PTG [0] IB3 ISC [3] IB2 ISC [2] IB1 ISC [1] IB0 ISC [0] 0 0 0 0 0 0 ISC [3:0]: Set the scan cycle when PTG[1:0] selects interval scan in non-display area drive period. The scan cycle is defined by n frame periods, where n is an odd number from 3 to 31. The polarity of liquid crystal drive voltage from the gate driver is inverted in the same timing as the interval scan cycle. Table 26 ISC[3:0] Scan cycle Time for interval when (fFLM) = 60Hz ISC[3:0] Scan cycle Time for interval when (fFLM) = 60Hz 4’h0 Setting disabled - 4’h8 17 frames 284ms 4’h1 3 frames 50ms 4’h9 19 frames 317ms 4’h2 5 frames 84ms 4’hA 21 frames 351ms 4’h3 7 frames 117ms 4’hB 23 frames 384ms 4’h4 9 frames 150ms 4’hC 25 frames 418ms 4’h5 11 frames 184ms 4’hD 27 frames 451ms 4’h6 13 frames 217ms 4’hE 29 frames 484ms 4’h7 15 frames 251ms 4’hF 31 frames 518ms Rev.1.0 September 13, 2006, page 53 of 199 R61505U PTG[1:0]: Sets the scan mode in non-display area. The scan mode selected by PTG[1:0] bits is applied in the non-display area when the base image is turned off and the non-display area other than the first and second partial display areas. Table 27 PTG[1] PTG[0] Scan mode in nondisplay area 0 0 Normal scan 0 1 Setting disabled 1 0 Interval scan 1 1 Setting disabled Source output level in non-display area VCOM output PTS[2:0] setting VCOMH/VCOML amplitude PTS[2:0] setting VCOMH/VCOML amplitude - - Note: Select frame-inversion AC drive when interval scan is selected. PTS[2:0]: Sets the source output level in non-display area drive period. When PTS[2] = 1, the operation of amplifiers which generates the grayscales other than V0 and V31 are halted and the step-up clock frequency becomes half the normal frequency in non-display drive period in order to reduce power consumption. Table 28 Source output level and voltage generating operation in non-display drive period Source output level Positive polarity Negative polarity Grayscale amplifier in operation Step-up clock frequency 3’h0 V31 V0 to V31 Register setting (DC0, DC1) 3’h1 Setting inhibited Setting inhibited - - 3’h2 GND GND V0 to V31 Register setting (DC0, DC1) 3’h3 Hi-Z Hi-Z V0 to V31 Register setting (DC0, DC1) 3’h4 V31 V0 V0 and V31 1/2 the frequency set by DC0, DC1 3’h5 Setting inhibited Setting inhibited - - 3’h6 GND GND V0 and V31 1/2 the frequency set by DC0, DC1 3’h7 Hi-Z Hi-Z V0 and V31 1/2 the frequency set by DC0, DC1 PTS[2:0] V0 Notes: 1. The power efficiency improved by halting grayscale amplifiers and slowing down the step-up clock frequency can be obtained in non-display drive period. 2. The gate output level in non-display drive period is controlled by the PTG setting (off-scan mode). Rev.1.0 September 13, 2006, page 54 of 199 R61505U Display Control 4 (R0Ah) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default value IB3 IB2 FMAR FMI KOE [2] 0 IB1 FMI [1] IB0 FMI [0] 0 0 0 FMI[2:0]: Sets the output interval of FMARK signal according to the display data rewrite cycle and data transfer rate. FMARKOE: When FMARKOE = 1, the R61505U starts outputting FMARK signal from the FMARK pin in the output interval set by FMI[2:0] bits. See “FMARK ” for details. Table 29 FMI[2] FMI[1] FMI[0] Output interval 0 0 0 1 frame 0 0 1 2 frames 0 1 1 4 frames 1 0 1 6 frames Other settings Setting disabled External Display Interface Control 1 (R0Ch) R/W RS IB15 W 1 0 Default value 0 IB14 ENC [2] IB13 ENC [1] IB12 ENC [0] IB11 IB10 IB9 IB8 IB7 IB6 0 0 0 RM 0 0 0 0 0 0 0 0 0 0 0 IB5 DM [1] IB4 DM [0] IB3 IB2 0 0 0 0 0 0 IB1 RIM [1] IB0 RIM [0] 0 0 RIM[1:0]: Sets the interface format when RGB interface is selected by RM and DM bits. Set RIM[1:0] bits before starting display operation via RGB interface. Do not change the setting while the R61505U performs display operation. Table 30 RGB interface operation RIM[1:0] RGB Interface operation Colors 2’h0 18-bit RGB interface (1 transfer/pixel) via DB17-0 262,144 2’h1 16-bit RGB interface (1 transfer/pixel) via DB17-13 and DB11-1 65,536 2’h2 6-bit RGB interface (3 transfers/pixel) via DB17-12 262,144 2’h3 Setting inhibited - Notes: 1: Instruction bits are set via system interface. 2: Transfer the RGB dot data one by one in synchronization with DOTCLK in 6-bit RGB interface operation. Rev.1.0 September 13, 2006, page 55 of 199 R61505U DM[1:0]: Selects the interface for the display operation. The DM[1:0] setting allows switching between internal clock operation mode and external display interface operation mode. However, switching between the RGB interface operation mode and the VSYNC interface operation mode is prohibited. Table 31 Display Interface DM[1:0] Display Interface 2’h0 Internal clock operations 2’h1 RGB interface 2’h2 VSYNC interface 2’h3 Setting inhibited RM: Selects the interface for RAM access operation. RAM access is possible only via the interface selected by the RM bit. Set RM = 1 when writing display data via RGB interface. When RM = 0, it is possible to write data via system interface while performing display operation via RGB interface. Table 32 RAM Access Interface RM RAM Access Interface 0 System interface/VSYNC interface 1 RGB interface ENC[2:0]: Sets the RAM write cycle via RGB interface. Table 25 RAM Write Cycle ENC[2:0] RAM Write Cycle (frame periods) 3’h0 1 frame 3’h1 2 frames 3’h2 3 frames 3’h3 4 frames 3’h4 5 frames 3’h5 6 frames 3’h6 7 frames 3’h7 8 frames Rev.1.0 September 13, 2006, page 56 of 199 R61505U Frame Marker Position (R0Dh) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default value IB8 FMP [8] IB7 FMP [7] IB6 FMP [6] IB5 FMP [5] IB4 FMP [4] IB3 FMP [3] IB2 FMP [2] IB1 FMP [1] IB0 FMP [0] 0 0 0 0 0 0 0 0 0 FMP[8:0]: Sets the output position of frame cycle signal (frame marker). When FMP[8:0] = 9’h000, a high-active pulse FMARK is outputted at the start of back porch period for 1H period (IOVCC-IOGND amplitude signal). FMARK can be used as the trigger signal for frame synchronous write operation. See “FMARK ” for details. Make sure the setting restriction 9’h000 ≤ FMP ≤ BP+NL+FP. Table 33 FMP[8:0] FMARK output position 9’’h000 0 line 9’h001 1 line 9’’h002 2nd line : th st : 9’’h14E 334th line 9’h14F 335th line 9’’h150~1FF Setting disabled Rev.1.0 September 13, 2006, page 57 of 199 R61505U External Display Interface Control 2 (R0Fh) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default value IB4 0 DPL: Sets the signal polarity of DOTCLK pin. DPL = 0: input data on the rising edge of DOTCLK DPL = 1: input data on the falling edge of DOTCLK EPL: Sets the signal polarity of ENABLE pin. EPL = 0: writes data DB17-0 when ENABLE = “0” and disables data write operation when ENABLE = “1”. EPL = 1: writes data DB17-0 when ENABLE = “1” and disables data write operation when ENABLE = “0”. HSPL: Sets the signal polarity of HSYNC pin. HSPL = 0: low active HSPL = 1: high active VSPL: Sets the signal polarity of VSYNC pin. VSPL = 0: low active VSPL = 1: high active Rev.1.0 September 13, 2006, page 58 of 199 IB3 VSPL HSPL 0 IB2 IB1 IB0 0 EPL DPL 0 0 0 R61505U Power control Power Control 1 (R10h) R/W RS IB15 IB14 IB13 IB12 W 1 0 0 0 SAP 0 0 0 0 Default value IB11 BT [3] IB10 BT [2] IB9 BT [1] IB8 BT [0] 0 0 0 0 IB7 IB6 APE 0 0 0 IB5 AP [1] IB4 AP [0] IB3 0 0 0 0 IB2 IB1 DSTB SLP 0 0 SLP: When SLP = 1, the R61505U enters the sleep mode. In sleep mode, the internal display operation except RC oscillation is halted to reduce power consumption. No change to the GRAM data and instruction setting is accepted and he GRAM data and the instruction setting are maintained in sleep mode. DSTB: When DSTB = 1, the R61505U enters the deep standby mode. In deep standby mode, the internal logic power supply is turned off to reduce power consumption. The GRAM data and instruction setting are not maintained when the R61505U enters the deep standby mode, and they must be reset after exiting deep standby mode. AP[1:0]: Adjusts the constant current in the operational amplifier circuit in the LCD power supply circuit. The larger constant current enhances the drivability of the LCD, but it also increases the current consumption. Adjust the constant current taking the trade-off into account between the display quality and the current consumption. In no-display period, set AP1-0 = 2’h0 to halt the operational amplifier circuits and the step-up circuits to reduce current consumption. Table 34 Constant current in amplifier in LCD power supply, grayscale voltage generating circuits AP[1:0] LCD power supply circuits Grayscale voltage generating circuit 2’h0 Halt operation Halt operation 2’h1 0.5 0.62 2’h2 0.75 0.71 2’h3 1 1 Note: In this table, the constant current in operational amplifiers is the ratio to the constant current when AP[1:0] is set to 2’h3. APE: Liquid crystal power supply enable bit. Set APE = 1 and follow the sequence when starting up the liquid crystal power supply. Table 35 APE Liquid crystal power supply circuit Grayscale voltage generating circuit 0 Halt Halt 1 Operate Operate BT[3:0]: Sets the factor used in the step-up circuits. Select the optimal step-up factor for the operating voltage. To reduce power consumption, set a smaller factor. Rev.1.0 September 13, 2006, page 59 of 199 IB0 0 0 R61505U SAP: The grayscale voltage generating circuit is halted by setting SAP = 0. Grayscale voltages are generated when SAP = 1. When starting the operation of LCD power supply circuit in Power ON operation and so on, make sure SAP = 0. Set SAP = 1, after starting up the LCD power supply circuit. Rev.1.0 September 13, 2006, page 60 of 199 R61505U Table 36 Step up factor and output voltage level BT[3:0] DDVDH VCL VGH VGL Capacitor Connection Pins (see note 4) 4’h0 DDVDH x 3 –(VCI1 + DDVDH x 2) [x 6] [x –5] –(DDVDH x 2) 4’h1 4’h2 DDVDH x 4 [x –4] [x 8] –(VCI1 + DDVDH) [x –3] –(VCI1 + DDVDH x 2) 4’h3 4’h4 [x –5] VCI1 x 2 VCI1 + DDVDH x 3 –(DDVDH x 2) [x 2] [x 7] [x –4] –(VCI1 + DDVDH) 4’h5 [x –3] –(DDVDH x 2) 4’h6 4’h7 [x –4] [x 6] –(VCI1 + DDVDH) -VCI1 DDVDH x 3 –(VCI1 + DDVDH x 2) [x –1] [x 9] [x –7] 4’hA DDVDH x 4 [x –6] [x 12] –(VCI1 + DDVDH) 4’hF C23± may be omitted. C23± may be omitted. [x –4] –(VCI1 + DDVDH x 2) [x –7] VCI1 x 3 [x 3] VCI1 + DDVDH x 3 –(DDVDH x 2) [x 10] [x –6] –(VCI1 + DDVDH) 4’hD 4’hE C23± may be omitted. –(DDVDH x 2) 4’h9 4’hC DDVDH x 3 [x –3] 4’h8 4’hB C23± may be omitted. [x –4] –(DDVDH x 2) DDVDH x 3 [x –6] [x 9] –(VCI1 + DDVDH) [x –4] C23± may be omitted. C23± may be omitted. Notes: 1. The step-up factor from VCI1 is shown in the brackets [ ]. 2. Connect capacitors where required when using DDVDH, VGH, VGL and VCL voltages. 3. Set the following voltages within the respective ranges: DDVDH = 6.0V (max.) VGH = 20.0V (max.) VGL = -13.5V (max.) VCL=-3.0V(max.) 4. Connect capacitors according to “Specifications of Power-supply Circuit External Elements”. In this case, comments should be preceded. Rev.1.0 September 13, 2006, page 61 of 199 R61505U Power Control 2 (R11h) R/W RS IB15 IB14 IB13 IB12 IB11 W 1 0 0 0 0 0 0 0 0 0 0 Default value IB10 DC1 [2] IB9 DC1 [1] IB8 DC1 [0] IB7 1 1 0 0 0 Table 37 step-up frequency (Step-up Circuit 1) DC0[2:0] Step-up circuit 1: step-up frequency (fDCDC1) 3’h0 fosc 3’h1 fosc / 2 3’h2 fosc / 4 3’h3 fosc / 8 3’h4 fosc / 16 3’h5 Setting inhibited 3’h6 Halt Step-up circuit 1 3’h7 Setting inhibited Note: Make sure the DC0, DC1 setting restriction: fDCDC1 ≥ fDCDC2. Table 38 step-up frequency (Step-up Circuit 2) DC1[2:0] Step-up circuit 2: step-up frequency (fDCDC2) 3’h0 fosc / 16 3’h1 fosc / 32 3’h2 fosc / 64 3’h3 fosc / 128 3’h4 fosc / 256 3’h5 Setting inhibited 3’h6 Halt Step-up circuit 2 3’h7 Setting inhibited Note: Make sure the DC0, DC1 setting restriction: fDCDC1 ≥ fDCDC2. Rev.1.0 September 13, 2006, page 62 of 199 IB6 DC0 [2] IB5 DC0 [1] IB4 DC0 [0] IB3 1 1 0 0 0 IB2 VC [2] IB1 VC [1] IB0 VC [0] 0 0 0 R61505U Table 39 VCIOUT output level VC[2:0] VCIOUT (Reference Voltage) (VCI1 Voltage) 3’h0 0.94 x VCILVL 3’h1 0.89 x VCILVL 3’h2 Setting inhibited 3’h3 Setting inhibited 3’h4 0.76 x VCILVL 3’h5 Setting inhibited 3’h6 Setting inhibited 3’h7 1.00 x VCILVL Power Control 3 (R12h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default value IB8 VCM R[0] IB7 VRE G1R IB6 0 0 0 0 IB5 IB4 PSON PON 0 IB3 VRH [3] IB2 VRH [2] IB1 VRH [1] IB0 VRH [0] 0 0 0 0 0 VRH[3:0]: Sets the factor to generate VREG1OUT from VCILVL. Table 40 VREG1OUT VREG1OUT Voltage VREG1OUT Voltage (External Reference Electric potential; VCILVL) (Internal Reference Electric Potential; VCIR) 4’h0~ 4’h3 Halt (Hiz) Halt(Hiz) 4’h4~ 4’h7 Setting inhibited Setting inhibited 4’h8 VCILVL×1.60 2.5V×1.60 = 4.00V 4’h9 VCILVL×1.65 2.5V×1.65 = 4.13V 4’hA VCILVL×1.70 2.5V×1.70 = 4.25V 4’hB VCILVL×1.75 2.5V×1.75 = 4.38V 4’hC VCILVL×1.80 2.5V×1.80 = 4.50V 4’hD VCILVL×1.85 2.5V×1.85 = 4.63V 4’hE VCILVL×1.90 2.5V×1.90 = 4.75V 4’hF Setting inhibited Setting inhibited VRH Note: Make sure the VC and VRH setting restrictions: VREG1OUT ≤ (DDVDH-0.5)V. Rev.1.0 September 13, 2006, page 63 of 199 R61505U PON: Controls the operation to generate VLOUT3. In setting the PON bit, follows the power-supply startup sequence. PON = 0: Halts the step-up operation to generate VLOUT3. PON = 1: Starts the step-up operation to generate VLOUT3. PSON: Power supply ON bit. When turning on the power supply, set PSE = 1 first and then set PSON = 1 to start internal power supply operation. VREG1R: Set reference voltage to generate VREG1OUT. Table 41 VREG1R reference voltage for VREG1OUT 0 (Default Value) VCILVL (External) 1 VCIR (Internal Reference Voltage)) VCMR[0]: Selects either external resistance (VCOMR pin) or internal electronic volume (VCM[4:0]) to set the electrical potential of VCOMH. The internal electronic volume can be set by VCM1 and VCM2 bits Table 42 VCMR[0] VCOMH Electrical Potential setting 0 VCOMR 1 Internal electronic volume Rev.1.0 September 13, 2006, page 64 of 199 R61505U Power Control 4 (R13h) R/W RS IB15 IB14 IB13 W 1 0 0 0 0 0 0 Default value IB12 VDV [4] IB11 VDV [3] IB10 VDV [2] IB9 VDV [1] IB8 VDV [0] IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDV[4:0]: Set VCOM alternating amplitude in the range of VREG1OUTx0.70 to VREG1OUTx1.24. Table 43 VDV Setting VDV[4:0] VCOM Amplitude VDV[4:0] VCOM Amplitude 5’h0 VREG1OUT×0.70 5’h10 VREG1OUT×0.94 5’h1 VREG1OUT×0.72 5’h11 VREG1OUT×0.96 5’h2 VREG1OUT×0.74 5’h12 VREG1OUT×0.98 5’h3 VREG1OUT×0.76 5’h13 VREG1OUT×1.00 5’h4 VREG1OUT×0.78 5’h14 VREG1OUT×1.02 5’h5 VREG1OUT×0.80 5’h15 VREG1OUT×1.04 5’h6 VREG1OUT×0.82 5’h16 VREG1OUT×1.06 5’h7 VREG1OUT×0.84 5’h17 VREG1OUT×1.08 5’h8 VREG1OUT×0.86 5’h18 VREG1OUT×1.10 5’h9 VREG1OUT×0.88 5’h19 VREG1OUT×1.12 5’hA VREG1OUT×0.90 5’h1A VREG1OUT×1.14 5’hB VREG1OUT×0.92 5’h1B VREG1OUT×1.16 5’hC VREG1OUT×0.94 5’h1C VREG1OUT×1.18 5’hD VREG1OUT×0.96 5’h1D VREG1OUT×1.20 5’hE VREG1OUT×0.98 5’h1E VREG1OUT×1.22 5’hF VREG1OUT×1.00 5’h1F VREG1OUT×1.24 Note: Set VDV[4:0] so that VCOM amplitude becomes 6.0V or less. Power Control 5 (R17h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default value PSE: Power supply startup enable bit. PSE = 1: The R61505U’s power supply is started by setting PSON when PSE =1. When completing the power supply generating operation, PSE is set to 0. PSE = 0: Power supply sequencer is reset. When halting the operating power supply sequencer, set PSE = 0. When starting up power supply without power supply sequencer, set PSE = 0. The power sequencer enables the register settings sequentially at the designated timing and order. Rev.1.0 September 13, 2006, page 65 of 199 R61505U RAM access instruction RAM Address Set (Horizontal Address) (R20h) RAM Address Set (Vertical Address) (R21h) R 20 R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD [15] AD [14] AD [13] AD [12] AD [11] AD [10] AD [9] AD [8] 0 0 0 0 0 0 0 0 Default value R 21 W 1 Default value 0 0 0 0 0 0 0 AD [16] 0 0 0 0 0 0 0 0 IB7 AD [7] IB6 AD [6] IB5 AD [5] IB4 AD [4] IB3 AD [3] IB2 AD [2] AD[16:0]: A GRAM address set initially in the AC (Address Counter). The address in the AC is automatically updated according to the combination of AM, I/D[1:0] settings as the R61505U writes data to the internal GRAM so that data can be written consecutively without resetting the address in the AC. The address is not automatically updated when reading data from the internal GRAM. Note 1: In RGB interface operation (RM = “1”), the address AD16-0 is set in the address counter every frame on the falling edge of VSYNC. Note 2: In internal clock operation and VSYNC interface operation (RM = “0”), the address AD16-0 is set when executing the instruction. Table 44 GRAM Address setting range AD[16:0] GRAM Data Setting 17’h00000 – 17’h000EF Bitmap data on the first line 17’h00100 – 17’h001EF Bitmap data on the second line 17’h00200 – 17’h002EF Bitmap data on the third line 17’h00300 – 17’h003EF Bitmap data on the fourth line 17’h00400 – 17’h004EF Bitmap data on the fifth line : : 17’h13600 – 17’h13CEF Bitmap data on the 317th line 17’h13700 – 17’h13DEF Bitmap data on the 318th line 17’h13800 – 17’h13EEF Bitmap data on the 319th line 17’h13900 – 17’h13FEF Bitmap data on the 320th line Rev.1.0 September 13, 2006, page 66 of 199 IB1 AD [1] IB0 AD [0] R61505U Write Data to GRAM (R22h) R/W RS W 1 RAM write data WD[17:0] is transferred via different data bus in different interface operation. RGB interface RAM write data WD[17:0] is transferred via different data bus in different interface operation. WD[17:0]: The R61505U develops data into 18 bits internally in write operation. The format to develop data into 18 bits is different in different interface operation. The GRAM data represents the grayscale level. The R61505U automatically updates the address according to AM and I/D[1:0] settings as it writes data in the GRAM. The DFM bit sets the format to develop 16-bit data into the 18-bit data in 16-bit or 8-bit interface operation. Note: When writing data in the GRAM via system interface while using the RGB interface, make sure that write operations via two interfaces do not conflict one another. Rev.1.0 September 13, 2006, page 67 of 199 R61505U Table 45 GRAM data and corresponding LCD grayscale level (REV =1) Grayscale level GRAM data RGB Negative 6’h00 V31 6’h01 (V30+V31)/2 6’h02 V30 6’h03 (V29+V30)/2 6’h04 V29 6’h05 (V28+V29)/2 6’h06 V28 6’h07 6’h08 Grayscale level GRAM data RGB Negative V0 6’h20 V15 V16 (V0+V1)/2 6’h21 (V14+V15)/2 (V16+V17)/2 V1 6’h22 V14 V17 (V1+V2)/2 6’h23 (V13+V14)/2 (V17+V18)/2 V2 6’h24 V13 V18 (V2+V3)/2 6’h25 (V12+V13)/2 (V18+V19)/2 V3 6’h26 V12 V19 (V27+V28)/2 (V3+V4)/2 6’h27 (V11+V12)/2 (V19+V20)/2 V27 V4 6’h28 V11 V20 6’h09 (V26+V27)/2 (V4+V5)/2 6’h29 (V10+V11)/2 (V20+V21)/2 6’h0A V26 V5 6’h2A V10 V21 6’h0B (V25+V26)/2 (V5+V6)/2 6’h2B (V9+V10)/2 (V21+V22)/2 6’h0C V25 V6 6’h2C V9 V22 6’h0D (V24+V25)/2 (V6+V7)/2 6’h2D (V8+V9)/2 (V22+V23)/2 6’h0E V24 V7 6’h2E V8 V23 6’h0F (V23+V24)/2 (V7+V8)/2 6’h2F (V7+V8)/2 (V23+V24)/2 6’h10 V23 V8 6’h30 V7 V24 6’h11 (V22+V23)/2 (V8+V9)/2 6’h31 (V6+V7)/2 (V24+V25)/2 6’h12 V22 V9 6’h32 V6 V25 6’h13 (V21+V22)/2 (V9+V10)/2 6’h33 (V5+V6)/2 (V25+V26)/2 6’h14 V21 V10 6’h34 V5 V26 6’h15 (V20+V21)/2 (V10+V11)/2 6’h35 (V4+V5)/2 (V26+V27)/2 6’h16 V20 V11 6’h36 V4 V27 6’h17 (V19+V20)/2 (V11+V12)/2 6’h37 (V3+V4)/2 (V27+V28)/2 6’h18 V19 V12 6’h38 V3 V28 6’h19 (V18+V19)/2 (V12+V13)/2 6’h39 (V2+V3)/2 (V28+V29)/2 6’h1A V18 V13 6’h3A V2 V29 6’h1B (V17+V18)/2 (V13+V14)/2 6’h3B (V1+V2)/2 (V29+V30)/2 6’h1C V17 V14 6’h3C V1 V30 6’h1D (V16+V17)/2 (V14+V15)/2 6’h3D (V0+V1)/2 (V30+V31)/2 Positive Positive 6’h1E V16 V15 6’h3E (V1+2V0)/3 (V30+2V31)/3 6’h1F (V15+V16)/2 (V15+V16)/2 6’h3F V0 V31 Note: (Vn+Vn+1)/2, (Vn+2Vn+1)/3 are the effective grayscale levels by FRC (frame rate control). Rev.1.0 September 13, 2006, page 68 of 199 R61505U Table 46 GRAM data and corresponding LCD grayscale level (REV =0) Grayscale level GRAM data RGB Negative 6’h00 6’h01 Grayscale level Positive GRAM data RGB Negative V0 V31 6’h20 V16 V15 (V0+V1)/2 (V30+V31)/2 6’h21 (V16+V17)/2 (V14+V15)/2 6’h02 V1 V30 6’h22 V17 V14 6’h03 (V1+V2)/2 (V29+V30)/2 6’h23 (V17+V18)/2 (V13+V14)/2 6’h04 V2 V29 6’h24 V18 V13 6’h05 (V2+V3)/2 (V28+V29)/2 6’h25 (V18+V19)/2 (V12+V13)/2 6’h06 V3 V28 6’h26 V19 V12 6’h07 (V3+V4)/2 (V27+V28)/2 6’h27 (V19+V20)/2 (V11+V12)/2 6’h08 V4 V27 6’h28 V20 V11 Positive 6’h09 (V4+V5)/2 (V26+V27)/2 6’h29 (V20+V21)/2 (V10+V11)/2 6’h0A V5 V26 6’h2A V21 V10 6’h0B (V5+V6)/2 (V25+V26)/2 6’h2B (V21+V22)/2 (V9+V10)/2 6’h0C V6 V25 6’h2C V22 V9 6’h0D (V6+V7)/2 (V24+V25)/2 6’h2D (V22+V23)/2 (V8+V9)/2 6’h0E V7 V24 6’h2E V23 V8 6’h0F (V7+V8)/2 (V23+V24)/2 6’h2F (V23+V24)/2 (V7+V8)/2 6’h10 V8 V23 6’h30 V24 V7 6’h11 (V8+V9)/2 (V22+V23)/2 6’h31 (V24+V25)/2 (V6+V7)/2 6’h12 V9 V22 6’h32 V25 V6 6’h13 (V9+V10)/2 (V21+V22)/2 6’h33 (V25+V26)/2 (V5+V6)/2 6’h14 V10 V21 6’h34 V26 V5 6’h15 (V10+V11)/2 (V20+V21)/2 6’h35 (V26+V27)/2 (V4+V5)/2 6’h16 V11 V20 6’h36 V27 V4 6’h17 (V11+V12)/2 (V19+V20)/2 6’h37 (V27+V28)/2 (V3+V4)/2 6’h18 V12 V19 6’h38 V28 V3 6’h19 (V12+V13)/2 (V18+V19)/2 6’h39 (V28+V29)/2 (V2+V3)/2 6’h1A V13 V18 6’h3A V29 V2 6’h1B (V13+V14)/2 (V17+V18)/2 6’h3B (V29+V30)/2 (V1+V2)/2 6’h1C V14 V17 6’h3C V30 V1 6’h1D (V14+V15)/2 (V16+V17)/2 6’h3D (V30+V31)/2 (V0+V1)/2 6’h1E V15 V16 6’h3E (V30+2V31)/3 (V1+2V0)/3 6’h1F (V15+V16)/2 (V15+V16)/2 6’h3F V31 V0 Note: (Vn+Vn+1)/2, (Vn+2Vn+1)/3 are the effective grayscale levels by FRC (frame rate control). Rev.1.0 September 13, 2006, page 69 of 199 R61505U Read Data from GRAM (R22h) R/W RS R 1 RAM read data RD[17:0] is transferred via different data bus in different interface operation. RD[17:0]: 18-bit data read from the GRAM. RAM read data RD[17:0] is transferred via different data bus in different interface operation. When the R61505U reads data from the GRAM to the microcomputer, the first word read immediately after RAM address set is executed is taken in the internal read-data latch and invalid data is sent to the data bus. Valid data is sent to the data bus when the R61505U reads out the second and subsequent words. When either 8-bit or 16-bit interface is selected, the LSBs of R and B dot data are not read out. Note: This register is not available in RGB interface operation. Set I/D, AM, HSA, HEA, VSA, and VEA bits Set address N (AD16-0) First word Dummy read (invalid data to DB17-0) GRAM data ψ read data latch Second word Read (data of address N) Read data latch ψ DB17-0 Set address M (AD16-0) First word Dummy read (invalid data to DB17-0) GRAM data ψ read data latch Second word Read (data of address M) Read data latch ψ DB17-0 Read out data to microcomputer Figure 6 GRAM Read Sequence Rev.1.0 September 13, 2006, page 70 of 199 R61505U NVM(NON-VOLATILE MEMORY) write control instruction NVM read data (R28h), VCOM High Voltage (R29h, R2Ah) R28 R29 R2A R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 W 1 0 0 0 0 0 0 0 0 0 0 0 0 Default 0 0 0 0 0 0 0 0 0 0 0 W 1 0 0 0 0 0 0 0 0 0 0 0 Default 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 VCMS EL 0 0 Default 0 0 0 0 0 0 0 0 0 0 0 W 0 IB3 UID [3] IB2 UID [2] IB1 UID [1] IB0 UID [0] 0 0 0 0 VCM1 VCM1 VCM1 VCM1 VCM1 [4] [3] [2] [1] [0] 0 0 0 0 VCM2 VCM2 VCM2 VCM2 VCM2 [4] [3] [2] [1] [0] 0 0 0 UID[3:0]: The data bits UID[3:0] are written to the designated address in NVM and the written data can be read out from NVM by instruction setting (CALB) to this register. UID[3:0] can be used to write and read user identification code in NVM. The setting value in UID[3:0] bits is enabled when not reading out the setting value from NVM via CALB setting. VCM1[4:0]: Selects the factor of VREG1OUT to generate VCOMH. When enabling the setting valued in VCM1[4:0], make sure to set VCMSEL = 0. When using the data written in NVM for setting the VCOMH level, the data bits VCM1[4:0] are written to the designated address in NVM and the written data can be read out from NVM by instruction setting (CALB) to this register. When the data bits VCM2[4:0] are written in NVM before writing the data bits VCM1[4:0] to NVM, the VCM1[4:0] setting value written in NVM cannot be used for setting the VCOMH level. Rev.1.0 September 13, 2006, page 71 of 199 0 0 0 R61505U Table 47 VCM1[4:0] VCOMH voltage VCM1[4:0] VCOMH voltage 5’h00 VREG1OUT x 0.69 5’h10 VREG1OUT x 0.85 5’h01 VREG1OUT x 0.70 5’h11 VREG1OUT x 0.86 5’h02 VREG1OUT x 0.71 5’h12 VREG1OUT x 0.87 5’h03 VREG1OUT x 0.72 5’h13 VREG1OUT x 0.88 5’h04 VREG1OUT x 0.73 5’h14 VREG1OUT x 0.89 5’h05 VREG1OUT x 0.74 5’h15 VREG1OUT x 0.90 5’h06 VREG1OUT x 0.75 5’h16 VREG1OUT x 0.91 5’h07 VREG1OUT x 0.76 5’h17 VREG1OUT x 0.92 5’h08 VREG1OUT x 0.77 5’h18 VREG1OUT x 0.93 5’h09 VREG1OUT x 0.78 5’h19 VREG1OUT x 0.94 5’h0A VREG1OUT x 0.79 5’h1A VREG1OUT x 0.95 5’h0B VREG1OUT x 0.80 5’h1B VREG1OUT x 0.96 5’h0C VREG1OUT x 0.81 5’h1C VREG1OUT x 0.97 5’h0D VREG1OUT x 0.82 5’h1D VREG1OUT x 0.98 5’h0E VREG1OUT x 0.83 5’h1E VREG1OUT x 0.99 5’h0F VREG1OUT x 0.84 5’h1F VREG1OUT x 1.00 Notes: 1. Make sure the VCOMH level is set between 3.0V to (DDVDH-0.5)V. 2. The above setting is enabled when selecting internal electronic volume for setting the VCOMH level. VCM2[4:0]: Selects the factor of VREG1OUT to generate VCOMH. When enabling the setting valued in VCM2[4:0], make sure to set VCMSEL = 1. The function of VCM2[4:0] instruction is the same as that of VCM1[4:0]. Write the setting value in VCM2[4:0] bits and VCMSEL = 1 in the designated addresses of NVM, when reading out the setting value written in NVM for VCOMH level setting and the data is already written in the designated address of VCM1[4:0] in the NVM. The VCM2[4:0] data bits written in NVM can be read out via CALB setting for setting the VCOMH level. Rev.1.0 September 13, 2006, page 72 of 199 R61505U Table 48 VCM2[4:0] VCOMH voltage VCM2[4:0] VCOMH voltage 5’h00 VREG1OUT x 0.69 5’h10 VREG1OUT x 0.85 5’h01 VREG1OUT x 0.70 5’h11 VREG1OUT x 0.86 5’h02 VREG1OUT x 0.71 5’h12 VREG1OUT x 0.87 5’h03 VREG1OUT x 0.72 5’h13 VREG1OUT x 0.88 5’h04 VREG1OUT x 0.73 5’h14 VREG1OUT x 0.89 5’h05 VREG1OUT x 0.74 5’h15 VREG1OUT x 0.90 5’h06 VREG1OUT x 0.75 5’h16 VREG1OUT x 0.91 5’h07 VREG1OUT x 0.76 5’h17 VREG1OUT x 0.92 5’h08 VREG1OUT x 0.77 5’h18 VREG1OUT x 0.93 5’h09 VREG1OUT x 0.78 5’h19 VREG1OUT x 0.94 5’h0A VREG1OUT x 0.79 5’h1A VREG1OUT x 0.95 5’h0B VREG1OUT x 0.80 5’h1B VREG1OUT x 0.96 5’h0C VREG1OUT x 0.81 5’h1C VREG1OUT x 0.97 5’h0D VREG1OUT x 0.82 5’h1D VREG1OUT x 0.98 5’h0E VREG1OUT x 0.83 5’h1E VREG1OUT x 0.99 5’h0F VREG1OUT x 0.84 5’h1F VREG1OUT x 1.00 Notes: 1. Make sure the VCOMH level is set between 3.0V to (DDVDH-0.5)V. 2. The above setting is enabled when selecting internal electronic volume for setting the VCOMH level. VCMSEL: When VCMSEL = 0, VCM1[4:0] is selected. When VCMSEL = 1, VCM2[4:0] is selected. Rev.1.0 September 13, 2006, page 73 of 199 R61505U γ Control γ Control 1 ~ 14 (R30h to R3Dh) R 30 R/W RS IB15 IB14 IB13 IB12 IB11 W 1 0 0 0 0 0 0 0 0 0 0 Default value R 31 W 1 Default value R 32 W 1 Default value R 33 W 1 Default value R 34 W 1 Default value R 35 W 1 Default value R 36 W 1 Default value R 37 W 1 Default value R 38 W 1 Default value R 39 W 1 Default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB10 IB9 IB8 P0KP P0KP P0KP 1[2] 1[1] 1[0] 0 0 0 P0KP P0KP P0KP 3[2] 3[1] 3[0] 0 0 0 P0KP P0KP P0KP 5[2] 5[1] 5[0] IB7 IB6 IB5 IB4 IB3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0FP 1[1] P0FP 1[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0FP 2[1] P0FP 2[0] 0 0 0 0 0 0 0 0 0 0 0 0 P0FP 3[1] P0FP 3[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0RP P0RP P0RP 1[2] 1[1] 1[0] 0 0 0 V0RP V0RP V0RP V0RP V0RP 1[4] 1[3] 1[2] 1[1] 1[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev.1.0 September 13, 2006, page 74 of 199 0 0 0 P0K P0K P0K N1[2] N1[1] N1[0] 0 0 0 P0K P0K P0K N3[2] N3[1] N3[0] 0 0 0 P0K P0K P0K N5[2] N5[1] N5[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0KP P0KP P0KP 4[2] 4[1] 4[0] P0FP 0[0] 0 0 0 0 0 0 0 P0FP 0[1] 0 0 0 P0KP P0KP P0KP 2[2] 2[1] 2[0] 0 0 0 IB2 IB1 IB0 P0KP P0KP P0KP 0[2] 0[1] 0[0] 0 0 0 0 P0RP P0RP P0RP 0[2] 0[1] 0[0] 0 0 0 V0RP V0RP V0RP V0RP V0RP 0[4] 0[3] 0[2] 0[1] 0[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0K P0K P0K N0[2] N0[1] N0[0] 0 0 0 P0K P0K P0K N2[2] N2[1] N2[0] 0 0 0 P0K P0K P0K N4[2] N4[1] N4[0] 0 0 0 R61505U γ Control 1 ~ 14 (R30h to R3Dh) (continued) R 3A R/W RS IB15 IB14 IB13 IB12 IB11 IB10 W 1 0 0 0 0 0 0 0 0 0 0 0 0 Default value R 3B W 1 Default value R 3C R 3D W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default value 0 0 0 0 0 W 0 0 0 0 0 0 1 Default value P0KP5-0[2:0]: P0FP3-0[1:0]: P0RP1-0[2:0]: V0RP1-0[4:0]: P0KN5-0[2:0]: P0FN3-0[1:0]: P0RN1-0[2:0]: V0RN1-0[4:0]: 0 0 IB9 IB8 P0FN P0FN 1[1] 1[0] 0 0 P0FN P0FN 3[1] 3[0] 0 0 P0RN P0RN P0RN 1[2] 1[1] 1[0] 0 0 0 V0R V0R V0R V0R V0R N1[4] N1[3] N1[2] N1[1] N1[0] 0 0 0 0 0 IB7 IB6 IB5 IB4 IB3 IB2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0FN P0FN 2[1] 2[0] 0 0 P0RN P0RN P0RN 0[2] 0[1] 0[0] 0 0 0 V0R V0R V0R V0R V0R N0[4] N0[3] N0[2] N0[1] N0[0] γ fine-adjustment register for positive polarity γ fine-adjustment register for positive polarity γ gradient-adjustment register for positive polarity γ amplitude-adjustment register for positive polarity γ fine-adjustment register for negative polarity γ fine-adjustment register for negative polarity γ gradient-adjustment register for negative polarity γ amplitude-adjustment register for negative polarity Rev.1.0 September 13, 2006, page 75 of 199 0 IB1 IB0 P0FN P0FN 0[1] 0[0] 0 0 0 0 0 R61505U Window address control instruction Window Horizontal RAM Address Start/End (R50h/ R51h) Window Vertical RAM Address Start/End (R52h/R53h) R 50 R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HEA [7] HEA [6] HEA [5] HEA [4] HEA [3] HEA [2] HEA [1] HEA [0] Default value R 51 W 1 Default value R 52 W 1 Default value R 53 W 1 Default value IB7 HSA [7] IB6 HSA [6] IB5 HSA [5] IB4 HSA [4] IB3 HSA [3] IB2 HSA [2] IB1 HSA [1] IB0 HSA [0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 VSA [8] VSA [7] VSA [6] VSA [5] VSA [4] VSA [3] VSA [2] VSA [1] VSA [0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VEA [7] VEA [6] VEA [5] VEA [4] VEA [3] VEA [2] VEA [1] VEA [0] 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 VEA [8] 0 0 0 0 0 0 0 1 HSA[7:0], HEA[7:0]: HSA[7:0] and HEA[7:0] are the start and end addresses of the window address area in horizontal direction, respectively. HSA[7:0] and HEA[7:0] specify the horizontal range to write data. Set HSA[7:0] and HEA[7:0] before starting RAM write operation. In setting, make sure that 8’h00 ≤ HSA < HEA ≤ 8’hEF and 8’h04 ≤ HEA – HSA. VSA[8:0], VEA[8:0]: VSA[8:0] and VEA[8:0] are the start and end addresses of the window address area in vertical direction, respectively. VSA[8:0] and VEA[8:0] specify the vertical range to write data. Set VSA[8:0] and VEA[8:0] before starting RAM write operation. In setting, make sure that 9’h000 ≤ VSA < VEA ≤ 9’h13F. 17'h000-00 HSA HEA VSA Window address area setting range: 8'h00҇*5#㧨*'#҇J'(*'#*5#҈J 9'h000҇85#㧨8'#҇J( Window address area Notes: 1. Make window address area within the GRAM address area. 2. In high-speed write mode, the R61505U writes data to the internal GRAM line by line horizontally. When writing data to the GRAM, transfer the data to be written in one line at a time. VEA 3. Set an address within the window address area in RAM address set register (R20h, R21h). When using hight-speed write function, set an address at the start of a line. 17'h13F-EF Figure 7 GRAM Address Map and Window Address Area Rev.1.0 September 13, 2006, page 76 of 199 R61505U Base image display control instruction Driver Output Control (R60h), Base Image Display Control (R61h) Vertical Scroll Control (R6Ah) R/W RS IB15 IB14 W 1 GS 0 0 R 60 Default value R 61 W 1 Default value R 6A W 1 Default value IB13 NL [5] IB12 NL [4] IB11 NL [3] IB10 NL [2] IB9 NL [1] IB8 NL [0] IB7 IB6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VL [7] VL [6] VL [5] VL [4] VL [3] VL [2] VL [1] VL [0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VL [8] 0 0 0 0 0 0 0 0 IB5 SCN [5] IB4 SCN [4] IB3 SCN [3] IB2 SCN [2] IB1 SCN [1] IB0 SCN [0] 0 0 0 0 0 0 0 0 0 0 0 NDL VLE REV SCN[5:0]: Specifies the gate line where the gate driver starts scan. NL[5:0]: Sets the number of lines to drive the LCD at an interval of 8 lines. The GRAM address mapping is not affected by the number of lines set by NL[5:0]. The number of lines must be the same or more than the number of lines necessary for the size of the liquid crystal panel. GS: Sets the direction of scan by the gate driver. Set GS bit in combination with SM and SS bits for the convenience of the display module configuration and the display direction. REV: Enables the grayscale inversion of the image by setting REV = 1. This enables the R61505U to display the same image from the same set of data whether the liquid crystal panel is normally black or white. The source output level during front, back porch periods and blank periods is determined by register setting (PTS). Table 49 GRAM Data-grayscale level inversion REV 0 1 GRAM Data Source Output Level in Display Area Positive Polarity Negative Polarity 18’h00000 V31 V0 : : : 18’h3FFFFF V0 V31 18’h00000 V0 V31 : 18’h3FFFFF : V31 Rev.1.0 September 13, 2006, page 77 of 199 : V0 R61505U VLE: Vertical scroll display enable bit. When VLE = 1, the R61505U starts displaying the base image from the line (of the physical display) determined by VL[8:0] bits. VL[8:0] sets the amount of scrolling, which is the number of lines to shift the start line of the display from the first line of the physical display. Note that the partial image display position is not affected by the base image scrolling. The vertical scrolling is not available in external display interface operation. In this case, make sure to set VLE = “0”. Table 50 VLE Base image 0 Fixed 1 Enable scrolling NDL: Sets the source output level in non-lit display area. NDL bit can keep the non-display area lit on. Table 51 NDL Non-display area Positive Negative 0 V31 V0 1 V0 V31 VL[8:0]: Sets the amount of scrolling of the base image. The base image is scrolled in vertical direction and displayed from the line which is determined by VL[8:0]. Make sure VL[8:0] ≤ 320. Table 52 NL[5:0] Number of Lines NL[5:0] Number of Lines NL[5:0] Number of Lines 6’h00 Setting inhibited 6’h0E Setting inhibited 6’h1C Setting inhibited 6’h01 Setting inhibited 6’h0F Setting inhibited 6’h1D 240 (lines) 6’h02 Setting inhibited 6’h10 Setting inhibited 6’h1E 248 6’h03 Setting inhibited 6’h11 Setting inhibited 6’h1F 256 6’h04 Setting inhibited 6’h12 Setting inhibited 6’h20 264 6’h05 Setting inhibited 6’h13 Setting inhibited 6’h21 272 6’h06 Setting inhibited 6’h14 Setting inhibited 6’h22 280 6’h07 Setting inhibited 6’h15 176 lines 6’h23 288 6’h08 Setting inhibited 6’h16 Setting inhibited 6’h24 296 6’h09 Setting inhibited 6’h17 Setting inhibited 6’h25 304 6’h0A Setting inhibited 6’h18 Setting inhibited 6’h26 312 6’h0B Setting inhibited 6’h19 Setting inhibited 6’h27 320 6’h0C Setting inhibited 6’h1A Setting inhibited 6’h28-6’h3F Setting inhibited 6’h0D Setting inhibited 6’h1B Setting inhibited Rev.1.0 September 13, 2006, page 78 of 199 R61505U Table 53 Gate Line No (Scan start position) SCN[5:0] SM=0 GS=0 See note. SM=1 GS=1 GS=0 GS=1 6’h00 G1 G320 G1 G320 6’h01 G9 G312 G17 G304 6’h02 G17 G304 G33 G288 6’h03 G25 G296 G49 G272 6’h04 G33 G288 G65 G256 6’h05 G41 G280 G81 G240 6’h06 G49 G272 G97 G224 6’h07 G57 G264 G113 G208 6’h08 G65 G256 G129 G192 6’h09 G73 G248 G145 G176 6’h0A G81 G240 G161 G160 6’h0B G89 G232 G177 G144 6’h0C G97 G224 G193 G128 6’h0D G105 G216 G209 G112 6’h0E G113 G208 G225 G96 6’h0F G121 G200 G241 G80 6’h10 G129 G192 G257 G64 6’h11 G137 G184 G273 G48 6’h12 G145 G176 G289 G32 6’h13 G153 G168 G305 G16 6’h14 G161 G160 G2 G319 6’h15 G169 G152 G18 G303 6’h16 G177 G144 G34 G287 6’h17 G185 G136 G50 G271 6’h18 G193 G128 G66 G255 6’h19 G201 G120 G82 G239 6’h1A G209 G112 G98 G223 6’h1B G217 G104 G114 G207 6’h1C G225 G96 G130 G191 6’h1D G233 G88 G146 G175 6’h1E G241 G80 G162 G159 6’h1F G249 G72 G178 G143 6’h20 G257 G64 G194 G127 6’h21 G265 G56 G210 G111 6’h22 G273 G48 G226 G95 6’h23 G281 G40 G242 G79 6’h24 G289 G32 G258 G63 6’h25 G297 G24 G274 G47 6’h26 G305 G16 G290 G31 6’h27 G313 G8 G306 G15 Setting disabled Setting disabled Setting disabled Setting disabled 6’h28-6’h3F Note: Make sure that number of scan start position + number of scan end position is 320 lines or less. Rev.1.0 September 13, 2006, page 79 of 199 R61505U Partial display control instruction Partial Image 1: Display Position (R80h), RAM Address (Start/End Line Address) (R81h/R82h) Partial Image 2: Display Position (R83h), RAM Address (Start/End Line Address) (R84h/R85h) R 80 R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default value R 81 W 1 Default value R 82 W 1 Default value R 83 W 1 Default value R 84 W 1 Default value R 85 W 1 Default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 PTDP PTDP PTDP PTDP PTDP PTDP PTDP PTDP PTDP 0[8] 0[7] 0[6] 0[5] 0[4] 0[3] 0[2] 0[1] 0[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTE PTE PTE PTE PTE PTE PTE PTE PTE A0[8] A0[7] A0[6] A0[5] A0[4] A0[3] A0[2] A0[1] A0[0] 0 0 0 0 0 0 0 0 0 PTDP PTDP PTDP PTDP PTDP PTDP PTDP PTDP PTDP 1[8] 1[7] 1[6] 1[5] 1[4] 1[3] 1[2] 1[1] 1[0] 0 0 0 0 0 0 0 0 0 PTSA PTSA PTSA PTSA PTSA PTSA PTSA PTSA PTSA 1[8] 1[7] 1[6] 1[5] 1[4] 1[3] 1[2] 1[1] 1[0] 0 0 0 0 0 0 0 0 0 PTE PTE PTE PTE PTE PTE PTE PTE PTE A1[8] A1[7] A1[6] A1[5] A1[4] A1[3] A1[2] A1[1] A1[0] 0 0 0 0 0 0 0 PTDP0[8:0]: Sets the display position of partial image 1. PTDP1[8:0]: Sets the display position of partial image 2. The display areas of the partial images 1 and 2 must not overlap each another. In setting, make sure that Partial image 1 display area < Partial image 2 display area, and Coordinates of partial image 1 display position: (PTDP0, PTDP0 + (PTEA0 – PTSA0)) Coordinates of partial image 2 display position: (PTDP1, PTDP1 + (PTEA1 – PTSA1)) If PTDP0 = “9’h000”, the partial image 1 is displayed from the first line of the base image. PTSA0[8:0] and PTEA0[8:0]: Sets the start line and end line addresses of the RAM area, respectively for the partial image 1. In setting, make sure that PTSA0 ≤ PTEA0. PTSA1[8:0] and PTEA1[8:0]: Sets the start line and end line addresses of the RAM area, respectively for the partial image 2. In setting, make sure that PTSA1 ≤ PTEA1. Rev.1.0 September 13, 2006, page 80 of 199 0 PTSA PTSA PTSA PTSA PTSA PTSA PTSA PTSA PTSA 0[8] 0[7] 0[6] 0[5] 0[4] 0[3] 0[2] 0[1] 0[0] 0 0 R61505U Panel interface control instruction Panel interface control 1(R90h) R/W RS W 1 Default value IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 0 0 0 0 0 0 IB9 DIVI [1] IB8 DIVI [0] IB7 IB6 IB5 0 0 0 0 0 0 0 0 IB4 IB3 IB2 IB1 IB0 RTNI RTNI RTNI RTNI RTNI [4] [3] [2] [1] [0] 1 0 0 0 RTNI[4:0]: Sets 1H (line) period. This setting is enabled while the R61505U’s display operation is synchronized with internal clock. DIVI[1:0]: Sets the division ratio of the internal clock frequency. The R61505U’s internal operation is synchronized with the frequency divided internal clock. When DIVI[1:0] setting is changed, the width of the reference clock for liquid crystal panel control signals is changed. The frame frequency can be adjusted by register setting (RTNI and DIVI bits). When changing the number of lines to drive the liquid crystal panel, adjust the frame frequency too. For details, see “FrameFrequency Adjustment Function”. The setting in DIVI[1:0] is disabled in RGB interface operation. Frame Frequency Calculation Frame frequency = fosc Clocks per line x division ratio x (line + BP + FP) [Hz] fosc : RC oscillation frequency Line: Number of lines to drive the LCD (NL bits) Division ratio: DIVI Clocks per line: RTNI Table 54 clocks per line (internal clock operation: 1 clock = 1 OSC) RTNI[4:0] Clocks per Line RTNI[4:0] Clocks per Line RTNI[4:0] Clocks per Line 5’h00-5’h0F Setting inhibited 5’h15 21 clocks 5’h1B 27 clocks 5’h10 16 clocks 5’h16 22 clocks 5’h1C 28 clocks 5’h11 17 clocks 5’h17 23 clocks 5’h1D 29 clocks 5’h12 18 clocks 5’h18 24 clocks 5’h1E 30 clocks 5’h13 19 clocks 5’h19 25 clocks 5’h1F 31 clocks 5’h14 20 clocks 5’h1A 26 clocks Table 55 Division ratio of the internal clock DIVI[1:0] Division Ratio Internal operation clock unit 2’h0 1/1 1 OSC 2’h1 1/2 2 OSC 2’h2 1/4 4 OSC 2’h3 1/8 8 OSC Rev.1.0 September 13, 2006, page 81 of 199 0 R61505U Panel interface control 2(R92h) R/W RS W 1 IB15 IB14 Default value IB12 IB11 0 0 IB13 0 0 0 0 0 0 0 0 IB10 IB9 IB8 NOW NOW NOW I[2] I[1] I[0] 0 0 0 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOWI[2:0]: Sets the non-overlap period of adjacent gate outputs. The setting is enabled in display operation synchronizing with the internal clock. Table 56 NOWI[2:0] Non-overlap period *see note NOWI[2:0] Non-overlap period 3’h4 4 (internal clock 3’h0 0 (internal clock 3’h1 1 3’h5 5 3’h2 2 3’h6 6 3’h3 3 3’h7 7 Note: ) *see note ) The internal clock is the frequency divided clock, which is set by DIVI[[1:0] bits. Rev.1.0 September 13, 2006, page 82 of 199 R61505U Panel interface control 3(R93h) R/W RS W 1 IB15 IB14 Default value IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 0 0 IB13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB2 MCP I[2] IB1 MCP I[1] IB0 MCP I[0] 0 0 0 MCPI[2:0]: Sets the source output timing by the number of internal clock from the reference point. The setting is enabled in display operation synchronizing with the internal clock. Table 57 MCPI[2:0] Source output position *see note MCPI[2:0] Source output position 3’h0 0 (internal clock 3’h4 4 (internal clock) 3’h1 1 3’h5 5 3’h2 2 3’h6 6 3’h3 3 3’h7 7 Note: ) The internal clock is the frequency divided clock, which is set by DIVI[[1:0] bits. The source output position is measured from the reference point by the number of internal clock cycle. Rev.1.0 September 13, 2006, page 83 of 199 R61505U Panel interface control 4(R95h) R/W RS W 1 IB15 IB14 Default value IB12 IB11 IB10 0 0 IB13 0 0 0 0 0 0 0 0 0 0 IB9 IB8 DIVE DIVE [1] [0] 1 0 IB7 IB6 0 0 0 0 IB5 RTN E[5] IB4 RTN E[4] IB3 RTN E[3] IB2 RTN E[2] IB1 RTN E[1] IB0 RTN E[0] 0 1 1 1 1 0 RTNE[5:0]: Sets RTNE[5:0] and DIVE[1:0] bits so that the number of DOTCLK calculated from the following formula becomes the number of DOTCLK which should be inputted in 1H period. The RTNE[5:0] setting is enabled in display operation via RGB interface. DIVE[1:0] (division ratio) x RTNE[5:0] (Number of DOTCLK) ≤ Number of DOTCLK in 1H period DIVE[1:0]: Sets the division ratio of DOTCLK frequency. The R61505U’s internal operation is synchronized with the frequency divided DOTCLK. The setting in DIVE[1:0] is enabled in RGB interface operation. Table 58 Division ratio of DOTCLK DIVE[1:0] Division Ratio Internal operation clock unit (DOTCLK) 18-bit, 1 transfer RGB interface 2’h0 Setting disabled Setting disabled 2’h1 1/4 2’h2 2’h3 DOTCLK = 5 MHz 8-bit, 3 transfers RGB interface DOTCLK = 15 MHz - Setting disabled - 4 DOTCLKs 0.8μs 12 DOTCLKs 0.8μs 1/8 8 DOTCLKs 1.6μs 24 DOTCLKs 1.6μs 1/16 16 DOTCLKs 3.2μs 48 DOTCLKs 3.2μs Rev.1.0 September 13, 2006, page 84 of 199 R61505U Table 59 DOTCLK per line (1H period) RTNE[5:0] DOTCLK per line (1H) RTNE[5:0] DOTCLK per line (1H) 6’h00 Setting disabled 6’h20 32 clocks 6’h01 Setting disabled 6’h21 33 clocks 6’h02 Setting disabled 6’h22 34 clocks 6’h03 Setting disabled 6’h23 35 clocks 6’h04 Setting disabled 6’h24 36 clocks 6’h05 Setting disabled 6’h25 37 clocks 6’h06 Setting disabled 6’h26 38 clocks 6’h07 Setting disabled 6’h27 39 clocks 6’h08 Setting disabled 6’h28 40 clocks 6’h09 Setting disabled 6’h29 41 clocks 6’h0A Setting disabled 6’h2A 42 clocks 6’h0B Setting disabled 6’h2B 43 clocks 6’h0C Setting disabled 6’h2C 44 clocks 6’h0D Setting disabled 6’h2D 45 clocks 6’h0E Setting disabled 6’h2E 46 clocks 6’h0F Setting disabled 6’h2F 47 clocks 6’h10 16 clocks 6’h30 48 clocks 6’h11 17 clocks 6’h31 49 clocks 6’h12 18 clocks 6’h32 50 clocks 6’h13 19 clocks 6’h33 51 clocks 6’h14 20 clocks 6’h34 52 clocks 6’h15 21 clocks 6’h35 53 clocks 6’h16 22 clocks 6’h36 54 clocks 6’h17 23 clocks 6’h37 55 clocks 6’h18 24 clocks 6’h38 56 clocks 6’h19 25 clocks 6’h39 57 clocks 6’h1A 26 clocks 6’h3A 58 clocks 6’h1B 27 clocks 6’h3B 59 clocks 6’h1C 28 clocks 6’h3C 60 clocks 6’h1D 29 clocks 6’h3D 61 clocks 6’h1E 30 clocks 6’h3E 62 clocks 6’h1F 31 clocks 6’h3F 63 clocks Rev.1.0 September 13, 2006, page 85 of 199 R61505U Panel interface control 5(R97h) R/W RS W 1 IB15 IB14 Default value IB13 IB12 0 0 0 0 0 0 0 0 IB11 IB10 IB9 IB8 NOW NOW NOW NOW E[3] E[2] E[1] E[0] 0 0 0 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB2 MCP E[2] IB1 MCP E[1] IB0 MCP E[0] 0 0 0 0 NOWE[3:0]: Sets the non-overlap period of adjacent gate outputs. The setting is enabled in display operation via RGB interface. Table 60 NOWE[3:0] Non-overlap period *see note NOWE[3:0] Non-overlap period 4’h8 8 (clocks 4’h0 0 (clock 4’h1 1 4’h9 9 4’h2 2 4’hA 10 4’h3 3 4’hB 11 4’h4 4 4’hC 12 4’h5 5 4’hD 13 4’h6 6 4’hE 14 4’h7 7 4’hF 15 Note: ) *see note) 1 clock = (Number of data transfers/pixel) x DIVE (division ratio) [DOTCLK]. Panel interface control 6(R98h) R/W RS W 1 IB15 IB14 Default value IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCPE[2:0]: Sets the source output timing by the number of internal clock from the reference point. The setting is enabled in display operation via RGB interface. Table 61 MCPE[2:0] Source output position MCPE[2:0] Source output position 3’h0 Setting Disabled 3’h4 4 (clocks 3’h1 1 clock 3’h5 5 3’h2 2 3’h6 6 3 3’h7 7 3’h3 Note: *see note ) 1 clock = (Number of data transfers/pixel) x DIVE (division ratio) [DOTCLK]. Rev.1.0 September 13, 2006, page 86 of 199 R61505U NVM(NON-VOLATILE MEMORY) control NVM access control 1 (RA0h), NVM access control 2 (RA1h) RA0 R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 0 0 0 0 0 0 0 0 TE 0 EOP [1] EOP [0] 0 0 EAD [1] EAD [0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ED [7] 0 0 ED [4] ED [3] ED [2] ED [1] ED [0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default RA1 W Default EAD[1:0]: Designates the address in NVM, where the data is written. See also description of ED7 and ED4-0 bits below. Table 62 EAD[1:0] Data written in NVM 2’h0 UID[3:0] 2’h1 VCM1[4:0] 2’h2 VCMSEL, VCM2[4:0] 2’h3 Setting disabled EOP[1:0]: Internal NVM control bits to write-in data to NVM, halt write-in operation, and store write-in data to register. Table 63 EOP[1:0] NVM control 2’h0 Halt 2’h1 Write 2’h2 Setting disabled 2’h3 Setting disabled TE: Enable internal NVM control bit (EOP). Follow the NVM control sequence when setting TE. ED[7], [4:0]: The data written in the Internal NVM. Table 64 EAD[1:0] ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0 2’h0 0 0 0 0 UID[3] UID[2] UID[1] UID[0] 2’h1 0 0 0 VCM1[4] VCM1[3] VCM1[2] VCM1[1] VCM1[0] 2’h2 VCMSEL 0 0 VCM2[4] VCM2[3] VCM2[2] VCM2[1] VCM2[0] Rev.1.0 September 13, 2006, page 87 of 199 R61505U Calibration control (RA4h) R/W RS R A4 W Default Value 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALB: Instruction to read in data on NVM. When CALB=1, data written to NVM is read out to internal register. CALB sets oscillation frequency at 376kHz +/- 7% (R61505U0) or 600kHz +/- 7% (R61505U1). (IOVCC=VCC=3V, 25C). Rev.1.0 September 13, 2006, page 88 of 199 R61505U Setting disabled instruction (Inhibition RA5h ~ RFFh) Setting is inhibited for the registers listed as follows. DO NOT ACCESS TO THESE REGISTERS. R05h-R06h, R0Bh, R0Eh, R14h-R16h, R18h-R1Fh, R23h-R27h, R2Bh-R2Fh, R54h-R5Fh, R62h-R69h, R6Bh-R6Fh, R86h-R8Fh, R91h, R94h, R96h, R99h-R9Fh, RA5h-RAFh, RB*h-RF*h Rev.1.0 September 13, 2006, page 89 of 199 ●R61505U Instruction List Main Category Upper Index Index 1* Power Control Index - 6 Sept. 2006 Rev1.0 Sub Category Command Index IB15 * IB14 * IB13 * Upper Code IB12 IB11 * * 00h Device Code Read 0 0 0 1 0 01h Driver Output Control 0 0 0 0 0 IB10 * 1 SM (0) 1 (1) 02h LCD Drive Waveform Cotrol 0 0 0 0 0 03h Entry Mode TRIREG (0) DFM (0) 0 BGR (0) 0 0 04h Resize Control 0 0 0 0 0 0 05h-06h Setting inhibited Setting inhibited Setting inhibited Setting inhibited Display Control 1 0 0 Setting inhibited PTDE[0] (0) Setting inhibited 07h Setting inhibited PTDE[1] (0) 08h Display Control 2 0 0 0 0 IB9 * 0 0 BC0 (0) HWM (0) RCV[1] (0) Setting inhibited IB8 * 1 SS (0) EOR (0) 0 0 0 0 FP[3] (1) FP[2] (0) PTS[2] (0) FP[1] (0) PTS[1] (0) RCV[0] (0) Setting inhibited BASEE (0) FP[0] (0) PTS[0] (0) IB5 ID5 Lower Code IB4 IB3 ID4 ID3 0 0 0 0 1 0 1 0 0 0 0 0 0 NW0 (0) 0 0 ORG (0) 0 0 0 0 0 0 ID0 (1) RCH[0] (0) Setting inhibited DTE (0) AM (0) 0 0 0 0 0 Setting inhibited VON (0) ID1 (1) RCH[1] (0) Setting inhibited GON (0) 0 0 Setting inhibited 0 0 0 0 PTG[0] (0) Setting inhibited COL (0) BP[3] (1) ISC[3] (0) FMARKOE (0) Setting inhibited RSZ[1] (0) Setting inhibited D[1] (0) BP[1] (0) ISC[1] (0) FMI[1] (0) Setting inhibited RIM[1] (0) FMP[1] (0) Setting inhibited EPL (0) SLP (0) VC[1] (0) VRH[1] (0) RSZ[0] (0) Setting inhibited D[0] (0) BP[0] (0) ISC[0] (0) FMI[0] (0) Setting inhibited RIM[0] (0) FMP[0] (0) Setting inhibited DPL (0) Setting inhibited 0 0 0 0 0 0 0 0 PTG[1] (0) 0 0 0 0 0 0 0 0 0 0 0 0 0Bh Setting inhibited Setting inhibited Setting inhibited Setting inhibited 0 0 0 0Dh Frame Marker Control 0 0 0 0 0 0 0 0Eh Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited RM (0) FMP[8] (0) Setting inhibited Setting inhibited 0 Setting inhibited ENC[0] (0) Setting inhibited External Display Interface Control 1 Setting inhibited ENC[1] (0) Setting inhibited 0Ch Setting inhibited ENC[2] (0) Setting inhibited DM[1] (0) FMP[5] (0) Setting inhibited 0Fh External Display Interface Control 2 0 0 0 0 0 0 0 0 10h Power Control 1 0 0 0 SAP (0) BT[3] (0) 11h Power Control 2 0 0 0 0 0 BT[2] (0) DC1[2] (1) BT[1] (0) DC1[1] (1) 12h Power Control 3 0 0 0 AP[1] (0) DC0[1] (1) PSON (0) 13h Power Control 4 0 0 0 14h-16h Setting inhibited Setting inhibited Setting inhibited Setting inhibited BT[0] (0) DC1[0] (0) VCMR[0] (0) VDV[0] (0) Setting inhibited Setting inhibited DM[0] (0) FMP[4] (0) Setting inhibited VSPL (0) AP[0] (0) DC0[0] (0) PON (0) 0 0 0 VDV[3] (0) Setting inhibited VDV[2] (0) Setting inhibited VDV[1] (0) Setting inhibited 0 0 FMP[7] (0) Setting inhibited FMP[6] (0) Setting inhibited 0 0 0 FMP[3] (0) Setting inhibited HSPL (0) FMP[2] (0) Setting inhibited 0 0 APE(0) 0 0 DC0[2] (1) VREG1R (0) 0 0 0 0 0 0 0 0 0 Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited 0 0 VRH[3] (0) Power Control 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited AD[7] (0) AD[15] (0) Setting inhibited AD[6] (0) AD[14] (0) Setting inhibited AD[5] (0) AD[13] (0) Setting inhibited AD[4] (0) AD[12] (0) Setting inhibited AD[3] (0) AD[11] (0) Setting inhibited AD[2] (0) AD[10] (0) Setting inhibited AD[1] (0) AD[9] (0) Setting inhibited UID[1] (0) VCM1[1] (0) VCM2[1] (0) Setting inhibited P0KP0[1] (0) P0KP2[1] (0) P0KP4[1] (0) P0FP0[1] (0) P0FP2[1] (0) P0RP0[1] (0) V0RP0[1] (0) P0KN0[1] (0) P0KN2[1] (0) P0KN4[1] (0) P0FN0[1] (0) P0FN2[1] (0) P0RN0[1] (0) V0RN0[1] (0) Setting inhibited HSA[1] (0) HEA[1] (1) VSA[1] (0) VEA[1] (1) Setting inhibited SCN[1] (0) VLE (0) Setting inhibited VL[1] (0) Setting inhibited PTDP0[1] (0) PTSA0[1] (0) PTEA0[1] (0) PTDP1[1] (0) PTSA1[1] (0) PTEA1[1] (0) Setting inhibited RTNI[1] (0) Setting inhibited Setting inhibited UID[0] (0) VCM1[0] (0) VCM2[0] (0) Setting inhibited P0KP0[0] (0) P0KP2[0] (0) P0KP4[0] (0) P0FP0[0] (0) P0FP2[0] (0) P0RP0[0] (0) V0RP0[0] (0) P0KN0[0] (0) P0KN2[0] (0) P0KN4[0] (0) P0FN0[0] (0) P0FN2[0] (0) P0RN0[0] (0) V0RN0[0] (0) Setting inhibited HSA[0] (0) HEA[0] (1) VSA[0] (0) VEA[0] (1) Setting inhibited SCN[0] (0) REV (0) Setting inhibited VL[0] (0) Setting inhibited PTDP0[0] (0) PTSA0[0] (0) PTEA0[0] (0) PTDP1[0] (0) PTSA1[0] (0) PTEA1[0] (0) Setting inhibited RTNI[0] (0) Setting inhibited RAM Adddress Set (Horizontal) 0 0 0 0 0 0 0 0 RAM Adddress Set (Vertical) 0 0 0 0 0 0 0 AD[16] (0) Write Data to / Read Data from GRAM Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited 28h NVM Data Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting inhibited Setting inhibited 29h VCOM High Voltage 0 0 0 0 0 0 0 0 2Ah VCOM High Voltage 0 0 0 0 0 0 0 0 2Bh-2Fh Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited 30h Gamma Control 1 0 0 0 0 0 31h Gamma Control 2 0 0 0 0 0 Setting inhibited P0KP1[2] (0) P0KP3[2] (0) P0KP5[2] (0) Setting inhibited P0KP1[1] (0) P0KP3[1] (0) P0KP5[1] (0) P0FP1[1] (0) P0FP3[1] (0) P0RP1[1] (0) V0RP1[1] (0) P0KN1[1] (0) P0KN3[1] (0) P0KN5[1] (0) P0FN1[1] (0) P0FN3[1] (0) P0RN1[1] (0) V0RN1[1] (0) Setting inhibited Setting inhibited P0KP1[0] (0) P0KP3[0] (0) P0KP5[0] (0) P0FP1[0] (0) P0FP3[0] (0) P0RP1[0] (0) V0RP1[0] (0) P0KN1[0] (0) P0KN3[0] (0) P0KN5[0] (0) P0FN1[0] (0) P0FN3[0] (0) P0RN1[0] (0) V0RN1[0] (0) Setting inhibited 32h Gamma Control 3 0 0 0 0 0 33h Gamma Control 4 0 0 0 0 0 0 34h Gamma Control 5 0 0 0 0 0 0 35h Gamma Control 6 0 0 0 0 0 V0RP1[3] (0) 36h Gamma Control 7 0 0 0 V0RP1[4] (0) 37h Gamma Control 8 0 0 0 0 0 38h Gamma Control 7 0 0 0 0 0 P0RP1[2] (0) V0RP1[2] (0) P0KN1[2] (0) P0KN3[2] (0) P0KN5[2] (0) 39h Gamma Control 7 0 0 0 0 0 3Ah Gamma Control 11 0 0 0 0 0 0 3Bh Gamma Control 12 0 0 0 0 0 0 3Ch Gamma Control 13 0 0 0 0 0 V0RN1[4] (0) Setting inhibited V0RN1[3] (0) Setting inhibited 3Dh Gamma Control 14 0 0 0 3Eh-3Fh Setting inhibited Setting inhibited Setting inhibited Setting inhibited P0RN1[2] (0) V0RN1[2] (0) Setting inhibited 5* Coordinates Control 50h Window Horizontal RAM Address (Start Address) 0 0 0 0 0 0 0 0 51h Window Horizontal RAM Address (End Address) 0 0 0 0 0 0 0 0 52h Window Vertical RAM Address (Start Address) 0 0 0 0 0 0 0 53h Window Vertical RAM Address (End Address) 54h-5Fh Setting inhibited 0 0 0 0 0 0 0 Setting inhibited GS (0) Setting inhibited Setting inhibited NL[5] (0) Setting inhibited NL[4] (0) Setting inhibited NL[3] (0) Setting inhibited NL[2] (0) Setting inhibited NL[1] (0) VSA[8] (0) VEA[8] (1) Setting inhibited NL[0] (0) VCMSEL (0) Setting inhibited VCM1[4] (0) VCM2[4] (0) Setting inhibited Setting inhibited UID[3] (0) VCM1[3] (0) VCM2[3] (0) Setting inhibited 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V0RP0[4] (0) V0RP0[3] (0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V0RN0[4] (0) Setting inhibited HSA[4] (0) HEA[4] (0) VSA[4] (0) VEA[4] (1) Setting inhibited SCN[4] (0) V0RN0[3] (0) Setting inhibited HSA[3] (0) HEA[3] (1) VSA[3] (0) VEA[3] (1) Setting inhibited SCN[3] (0) 0 0 0 Setting inhibited HSA[7] (0) HEA[7] (1) VSA[7] (0) VEA[7] (0) Setting inhibited Setting inhibited HSA[6] (0) HEA[6] (1) VSA[6] (0) VEA[6] (0) Setting inhibited 0 0 Setting inhibited HSA[5] (0) HEA[5] (1) VSA[5] (0) VEA[5] (1) Setting inhibited SCN[5] (0) Panel Image Control 60h Driver Output Control 61h Base Image Display Control 0 0 0 0 0 0 0 0 0 0 0 0 0 62h-69h Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited VL[7] (0) Setting inhibited PTDP0[7] (0) PTSA0[7] (0) PTEA0[7] (0) PTDP1[7] (0) PTSA1[7] (0) PTEA1[7] (0) Setting inhibited Setting inhibited VL[6] (0) Setting inhibited PTDP0[6] (0) PTSA0[6] (0) PTEA0[6] (0) PTDP1[6] (0) PTSA1[6] (0) PTEA1[6] (0) Setting inhibited Setting inhibited VL[5] (0) Setting inhibited PTDP0[5] (0) PTSA0[5] (0) PTEA0[5] (0) PTDP1[5] (0) PTSA1[5] (0) PTEA1[5] (0) Setting inhibited Setting inhibited VL[3] (0) Setting inhibited PTDP0[3] (0) PTSA0[3] (0) PTEA0[3] (0) PTDP1[3] (0) PTSA1[3] (0) PTEA1[3] (0) Setting inhibited RTNI[3] (0) Setting inhibited 6Ah Vertical Scroll Control 0 0 0 0 0 0 0 6Bh-6Fh Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited 80h Partial Image 1 Display Position 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited VL[8] (0) Setting inhibited PTDP0[8] (0) PTSA0[8] (0) PTEA0[8] (0) PTDP1[8] (0) PTSA1[8] (0) PTEA1[8] (0) Setting inhibited DIVI[0] (0) Setting inhibited NOWI[0] (0) 82h 83h 84h 85h A* B*-F* Panel Interface Control NVM Control Setting inhibited 0 Partial Image 2 Display Position Partial Image 2 RAM Address (Start Line Address) Partial Image 2 RAM Address (End Line Address) 86h-8Fh Setting inhibited 90h Panel Interface Control 1 0 0 0 0 0 0 91h Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited NOWI[2] (0) Setting inhibited DIVI[1] (0) Setting inhibited NOWI[1] (0) Setting inhibited UID[2] (0) VCM1[2] (0) VCM2[2] (0) Setting inhibited P0KP0[2] (0) P0KP2[2] (0) P0KP4[2] (0) 0 6* Partial Image 1 RAM Address (Start Line Address) Partial Image 1 RAM Address (End Line Address) Device Code "1505" RAM write data (WD17-0) / RAM read data (RD17-0) bits are allocated to different data bus according to the format of selected interface. 22h 23h-27h 81h Notes 0 Setting inhibited 21h Index - VC[0] (0) VRH[0] (0) 17h 20h 9* 0 DSTB (0) VC[2] (0) VRH[2] (0) 18h-1Fh Partial Image Control 0 BP[2] (0) ISC[2] (0) FMI[2] (0) Setting inhibited Setting inhibited PSE (0) Setting inhibited AD[0] (0) AD[8] (0) RAM Access 8* IB0 ID0 0 Display Control 3 0 IB1 ID1 0 Display Control 4 VDV[4] (0) Setting inhibited IB2 ID2 0 09h Gamma Control IB6 ID6 0Ah 2* 3* IB7 ID7 0 0 0 Setting inhibited Setting inhibited Setting inhibited Setting inhibited VL[4] (0) Setting inhibited PTDP0[4] (0) PTSA0[4] (0) PTEA0[4] (0) PTDP1[4] (0) PTSA1[4] (0) PTEA1[4] (0) Setting inhibited RTNI[4] (1) Setting inhibited 92h Panel Interface Control 2 0 0 0 0 0 0 0 0 0 0 93h Panel Interface Control 3 0 0 0 0 0 0 0 0 0 0 0 0 0 94h Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Panel Interface Control 4 0 0 0 0 0 0 96h Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited NOWE[3] (0) Setting inhibited NOWE[2] (0) Setting inhibited DIVE[0] (0) Setting inhibited NOWE[0] (0) Setting inhibited 95h Setting inhibited DIVE[1] (1) Setting inhibited NOWE[1] (0) Setting inhibited RTNE[4] (1) Setting inhibited Setting inhibited RTNE[3] (1) Setting inhibited 0 0 Setting inhibited Setting inhibited Setting inhibited RTNE[5] (0) Setting inhibited 97h Panel Interface Control 5 0 0 0 0 0 0 0 0 0 98h Panel Interface Control 6 0 0 0 0 0 0 0 0 0 0 0 0 0 99h-9Fh Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited NVM Access Control 1 0 0 0 0 0 0 0 0 Setting inhibited EOP[1] (0) A1h NVM Access Control 2 0 0 0 0 0 0 0 0 A2h-A3h Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited TE (0) ED7 (0) Setting inhibited Setting inhibited A0h Setting inhibited EOP[0] (0) ED4 (0) Setting inhibited A4h Calibration Control A5h-AFh Setting inhibited B*h-F*h Setting inhibited 0 0 0 Setting inhibited Setting inhibited P0RP0[2] (0) V0RP0[2] (0) P0KN0[2] (0) P0KN2[2] (0) P0KN4[2] (0) 0 0 P0RN0[2] (0) V0RN0[2] (0) Setting inhibited HSA[2] (0) HEA[2] (1) VSA[2] (0) VEA[2] (1) Setting inhibited SCN[2] (0) NDL (0) Setting inhibited VL[2] (0) Setting inhibited PTDP0[2] (0) PTSA0[2] (0) PTEA0[2] (0) PTDP1[2] (0) PTSA1[2] (0) PTEA1[2] (0) Setting inhibited RTNI[2] (0) Setting inhibited 0 0 0 MCPI[2] (0) Setting inhibited RTNE[2] (1) Setting inhibited MCPI[1] (0) Setting inhibited RTNE[1] (1) Setting inhibited MCPI[0] (0) Setting inhibited RTNE[0] (0) Setting inhibited 0 0 0 Setting inhibited MCPE[2] (0) Setting inhibited 0 0 ED3 (0) Setting inhibited ED2 (0) Setting inhibited MCPE[1] (0) Setting inhibited EAD[1] (0) ED1 (0) Setting inhibited MCPE[0] (0) Setting inhibited EAD[0] (0) ED0 (0) Setting inhibited CALB (0) Setting inhibited Setting inhibited 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited R61505U Reset Function The R61505U is initialized by the RESET input. During reset period, the R61505U is in a busy state and instruction from the MPU and GRAM access are not accepted. The R61505U’s internal power supply circuit unit is initialized also by the RESET input. The RESET period must be secured for at least 1ms. In case of power-on reset, wait until the RC oscillation frequency stabilizes (for 1 ms). During this period, GRAM access and initial instruction setting are prohibited. 1. Initial state of instruction bits (default) See the instruction list of p.90. The default value is shown in the parenthesis of each instruction bit cell. 2. RAM Data initialization The RAM data is not automatically initialized by the RESET input. It must be initialized by software in display-off period (D1-0 = “00”). 3. Output pin initial state * see Note 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. LCD driver S1~S720 G1~G320 VCOM VCOMH VCOML VREG1OUT VCIOUT VLOUT1 (DDVDH) VLOUT2 (VGH) VLOUT3 (VGL) VCL VCI1 FMARK SDO 4. Initial state of input/output pins* see Note 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. C11+ C11C12+ C12C13+ C13C21+ C21C22+ C22C23+ C23VDD : GND : VGL (= GND) : Halt (GND output) : DDVDH : Halt (GND output) : VGS : Hi-z : VCI clamp : DDVDH clamp : GND : GND : Hi-z : Halt (GND output ) : High level (IOVCC) when IM = “010*”(serial interface) : Hi-z when IM ≠ “010*”(other than serial interface) Rev.1.0 September 13, 2006, page 91 of 199 : Hi-z : Hi-z : Hi-z : Hi-z : VCI1 (= Hi-z) : GND : DDVDH : GND : DDVDH : GND : DDVDH : GND : VDD R61505U Note: The above mentioned initial states of output and input pins are those of when the R61505U’s power supply circuit is connected as exemplified in “Connection example”. 5. Note on Reset function (1) When a RESET input is entered into the R61505U while it is in deep standby mode, the R61505U starts up the inside logic regulator and makes a transition to the initial state. During this period, the state of the interface pins may become unstable. For this reason, do not enter a RESET input in deep standby mode. (2) When transferring instruction in either two or three transfers via 8-/9-/16-bit interface, make sure to execute data transfer synchronization after reset operation. Rev.1.0 September 13, 2006, page 92 of 199 R61505U Basic mode operation of the R61505U The basic operation modes of the R61505U are shown in the following diagram. When making a transition from one mode to another, refer to instruction setting sequence. Sleep mode Sleep set Exit Sleep Initial setting Display OFF Display ON sequence (Power ON sequence) Display OFF sequence (Power OFF sequence) moving picture display VSYNC interface VSYNC i/F sequence 2 (DM=10, RM=0) VSYNC i/F sequence 1 (DM=00, RM=0) DSTB = 1 Deep standby set Internal clock display operation Partial display sequence 2 Display color control 262k-color mode 262k 8 color display sequence 8-color mode Figure 8 Rev.1.0 September 13, 2006, page 93 of 199 Deep standby mode RGB i/F (1) sequence 2 (DM=00, RM=0) Partial display Reset Exit deep standby RGB i/F (1) sequence 1 (DM=01, RM=1) Partial display sequence 1 8 262k color display sequence Reset state moving picture display RGB interface (1) RAM access via system i/F while displaying moving picture RGB i/F (2) sequence 1 (DM=01, RM=0) RGB interface (2) RGB i/F (2) sequence 2 (DM=01, RM=1) R61505U Interface and data format The R61505U supports system interface for making instruction and other settings, and external display interface for displaying a moving picture. The R61505U can select the optimum interface for the display (moving or still picture) in order to transfer data efficiently. As external display interface, the R61505U supports RGB interface and VSYNC interface, which enables data rewrite operation without flickering the moving picture on display. In RGB interface operation, the display operation is executed in synchronization with synchronous signals VSYNC, HSYNC, and DOTCLK. In synchronization with these signals, the R61505U writes display data according to data enable signal (ENABLE) via RGB data signal bus (DB17-0). The display data is stored in the R61505U’s GRAM so that data is transferred only when rewriting the frames of moving picture and the data transfer required for moving picture display can be minimized. The window address function specifies the RAM area to write data for moving picture display, which enables displaying a moving picture and RAM data in other than the moving picture area simultaneously. To access the R61505U’s internal RAM in high speed with low power consumption, use high-speed write function (HWM = 1) in RGB or VSYNC interface operation. In VSYNC interface operation, the internal display operation is synchronized with the frame synchronization signal (VSYNC). The VSYNC interface enables a moving picture display via system interface by writing the data to the GRAM at faster than the minimum calculated speed in synchronization with the falling edge of VSYNC. In this case, there are restrictions in setting the frequency and the method to write data to the internal RAM. The R61505U operates in either one of the following four modes according to the state of the display. The operation mode is set in the external display interface control register (R0Ch). When switching from one mode to another, make sure to follow the relevant sequence in setting instruction bits. Table 65 Operation Modes Operation Mode RAM Access Setting (RM) Display Operation Mode (DM) Internal clock operation (displaying still pictures) System interface (RM = 0) Internal clock operation (DM1-0 = 00) RGB interface (1) (displaying moving pictures) RGB interface (RM = 1) RGB interface (DM1-0 = 01) RGB interface (2) (rewriting still pictures while displaying moving pictures) System interface (RM = 0) RGB interface (DM1-0 = 01) VSYNC interface (displaying moving pictures) System interface (RM = 0) VSYNC interface (DM1-0 = 10) Notes: 1. Instructions are set only via system interface. 2. 3. The RGB and VSYNC interfaces cannot be used simultaneously. Do not make changes to the RGB interface operation setting (RIM1-0) while RGB interface is in operation. 4. See the “External Display Interface” section for the sequences when switching from one mode to another. 5. Use high-speed write function (HWM = 1) when writing data via RGB or VSYNC interface. Rev.1.0 September 13, 2006, page 94 of 199 R61505U CS* System interface RS WR* (RD*) System interface 18/16/9/8 System DB17-0 RGB interface 18/16/6 R61505U ENABLE RGB interface VSYNC HSYNC DOTCLK Figure 9 Internal clock operation The display operation is synchronized with signals generated from internal oscillator’s clock (OSC) in this mode. All input via external display interface is disabled in this operation. The internal RAM can be accessed only via system interface. RGB interface operation (1) The display operation is synchronized with frame synchronous signal (VSYNC), line synchronous signal (HSYNC), and dot clock signal (DOTCLK) in RGB interface operation. These signals must be supplied during the display operation via RGB interface. The R61505U transfers display data in units of pixels via DB17-0 pins. The display data is stored in the internal RAM. The combined use of high-speed RAM write mode and window address function can minimize the total number of data transfer for moving picture display by transferring only the data to be written in the moving picture RAM area when it is written and enables the R61505U to display a moving picture and the data in other than the moving picture RAM area simultaneously. The front porch (FP), back porch (BP), and the display (NL) periods are automatically calculated inside the R61505U by counting the number of clocks of line synchronous signal (HSYNC) from the falling edge of the frame synchronous signal (VSYNC). Make sure to transfer pixel data via DB17-0 pins in accordance with the setting of these periods. Rev.1.0 September 13, 2006, page 95 of 199 R61505U RGB interface operation (2) This mode enables the R61505U to rewrite RAM data via system interface while using RGB interface for display operation. To rewrite RAM data via system interface, make sure that display data is not transferred via RGB interface (ENABLE = high). To return to the RGB interface operation, change the ENABLE setting first. Then set an address in the RAM address set register and R22h in the index register. VSYNC interface operation The internal display operation is synchronized with the frame synchronous signal (VSYNC) in this mode. This mode enables the R61505U to display a moving picture via system interface by writing data in the internal RAM at faster than the calculated minimum speed via system interface from the falling edge of frame synchronous (VSYNC). In this case, there are restrictions in speed and method of writing RAM data. For details, see the “VSYNC Interface” section. As external input, only VSYNC signal input is valid in this mode. Other input via external display interface becomes disabled. The front porch (FP), back porch (BP), and the display (NL) periods are automatically calculated from the frame synchronous signal (VSYNC) inside the R61505U according to the instruction settings for these periods. Rev.1.0 September 13, 2006, page 96 of 199 R61505U System Interface The following are the kinds of system interfaces available with the R61505U. The interface operation is selected by setting the IM3/2/1/0 pins. The system interface is used for instruction setting and RAM access. Table 66 IM Bit Settings and System Interface IM3 IM2 IM1 IM0 Interfacing Mode with MPU DB Pins Colors 0 0 0 0 Setting inhibited - - 0 0 0 1 Setting inhibited - - 0 0 1 0 80-system 16-bit interface DB17-10, DB8-1 262,144 *see Note1 0 0 1 1 80-system 8-bit interface DB17-10 262,144 *see Note2 0 1 0 * Clock synchronous serial interface - 65,536 0 1 1 0 Setting inhibited - - 0 1 1 1 Setting inhibited - - 1 0 0 0 Setting inhibited - - 1 0 0 1 Setting inhibited - - 1 0 1 0 80-system 18-bit interface DB17-0 262,144 1 0 1 1 80-system 9-bit interface DB17-9 262,144 1 1 0 0 Setting inhibited - - 1 1 0 1 Setting inhibited - - 1 1 1 0 Setting inhibited - - 1 1 1 1 Setting inhibited - - Notes: 1. 65,536 colors in 16-bit single transfer mode. 2. 65,536 colors in 8-bit 2-transfer mode. Rev.1.0 September 13, 2006, page 97 of 199 R61505U 80-system 18-bit Bus Interface IM[3:0] = 1010 MPU CSn* CS* A1 RS HWR WR* (RD*) (RD*) R61505U DB17-0 D31-0 18 Figure 10 18-bit interface Instruction write Input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 Instruction IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 Instruction code Device code read Device code IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 Output DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 0 Instruction code Figure 11 18-bit Interface Data Format (Instruction Write / Device Code Read) RAM data write Input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 GRAM write data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 1 pixel Note: Normal display in 262,144 colors RAM data read GRAM data Read data Output pins R5 R4 R3 R2 RD RD [17] [16] RD [15] RD RD RD RD [14] [13] [12] [11] RD [10] RD [9] RD [8] RD [7] DB 17 DB 15 DB 14 DB 10 DB 9 DB 8 DB 7 DB 16 R1 DB 13 R0 DB 12 G5 DB 11 G4 G3 G2 G1 B5 B4 B3 B2 B1 B0 RD [6] RD [5] RD [4] RD [3] RD [2] RD [1] RD [0] DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 G0 Figure 12 18-bit Interface Data Format (RAM Data Write / RAM Data Read) Rev.1.0 September 13, 2006, page 98 of 199 R61505U 80-system 16-bit Bus Interface IM[3:0] = 0010 MPU CSn* CS* A1 RS HWR WR* (RD*) (RD*) R61505U DB17-10, 8-1 D15-0 16 Figure 13 16-bit interface Instruction Input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 Instruction IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 Instruction code Device code read Device code IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 Output DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 Instruction code Note: Device code cannot be read in 2 transfer mode. Figure 14 16-bit Interface Data Format (Instruction Write / Device Code Read) Rev.1.0 September 13, 2006, page 99 of 199 DB 0 R61505U RAM data write (single transfer mode: TRIREG = 0) Input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 R5 R4 R3 R2 R1 R0 G5 G4 G3 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 G2 G1 G0 B5 B4 B3 B2 B1 B0 Note: Normal display in 65,536 colors RAM data write (2 transfer mode: TRIREG = 1, DFM =0) First transfer Second transfer Input pins DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 17 DB 16 GRAM write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] RGB assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 1 pixel Note: Normal display in 262,144 colors RAM data write (2 transfer mode: TRIREG = 1, DFM =1) First transfer Second transfer DB DB DB 10 8 7 Input pins DB 2 DB 1 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 GRAM write data WD [17] WD [16] WD [15] WD [14] WD [13] WD [12] WD [11] WD [10] WD [9] WD [8] WD [7] RGB assignment R5 R4 R3 R2 R1 B0 G5 G4 G3 G2 G1 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 WD [6] WD [5] WD [4] WD [3] WD [2] WD [1] WD [0] G0 B5 B4 B3 B2 B1 B0 1 pixel Note: Normal display in 262,144 colors Figure 15 16-bit Interface Data Format (RAM data write) RAM data read (one transfer: TRIREG = 0) GRAM data R5 R4 R3 R2 R1 R0 G5 G4 Read data RD [17] RD [16] RD [15] RD [14] RD [13] RD [12] RD [11] RD [10] Output pins DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 G3 RD [9] G2 G1 G0 B5 B4 B3 B2 B1 B0 RD [0] RD [8] RD [7] RD [6] RD [5] RD [4] RD [3] RD [2] RD [1] DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 Note: Data cannot be transferred in twice in read operation via 16-bit interface. Figure 16 16-bit Interface Data Format (RAM data read) Rev.1.0 September 13, 2006, page 100 of 199 R61505U Data Transfer Synchronization in 16-bit Bus Interface operation The R61505U supports data transfer synchronization function to reset the counters for upper 16-/2-bit and lower 2-/16-bit transfers in 16-bit 2-transfer mode. When a mismatch occurs in upper and lower data transfers due to noise and so on, the 000H instruction is written four times consecutively to reset the upper and lower counters in order to restart the data transfer from upper 2/16 bits. The data transfer synchronization, when executed periodically, can help the display system recover from runaway. Make sure to execute data transfer synchronization after reset operation before transferring instruction. RS RD WR DB17 ~ DB10, DB8 ~ DB1 Upper Lower "000"H "000"H "000"H "000"H Upper Lower Upper (16-bit transfer synchronization) Figure 17 16-bit Data Transfer Synchronization Rev.1.0 September 13, 2006, page 101 of 199 R61505U 80-system 9-bit Bus Interface When transferring 16-bit instruction, it is divided into upper and lower 8 bits, and the upper 8 bits are transferred first (the LSB is not used). The RAM write data is also divided into upper and lower 9 bits, and the upper 9 bits are transferred first. The unused DB pins must be fixed at either IOVCC or IOGND level. When transferring the index register setting, make sure to write upper byte (8 bits). IM[3:0] = 1011 H8/2245 CSn* CS* A1 RS HWR WR* (RD*) (RD*) DB17-9 DB8-0 D15-0 9 R61505U 9 Figure 18 9-bit interface Instruction write First transfer Second transfer Input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 Instruction IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 DB 9 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 DB 17 DB 16 DB 15 DB 14 DB 11 DB 10 DB 9 Instruction code Device code read Instruction IB 15 IB 14 IB 13 IB 12 Output DB 17 DB 16 DB 15 DB 14 IB 11 IB 10 IB 9 IB 8 DB 11 DB 10 First transfer DB 13 DB 12 Second transfer DB 9 DB 13 DB 12 instruction code Figure 19 9-bit Interface Data Format (Instruction Write / Device Code Read) Rev.1.0 September 13, 2006, page 102 of 199 DB 9 R61505U RAM data write 2nd transfer 1st transfer Input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 GRAM write data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 1 pixel Note:Normal display in 262,144 colors RAM data read GRAM data R5 R4 R3 R2 Read data RD RD [17] [16] RD [15] RD RD RD RD [14] [13] [12] [11] RD [10] RD [9] RD [8] RD [7] Output pins DB 17 DB 15 DB 14 DB 10 DB 9 DB 17 DB 16 DB 16 R1 DB 13 R0 DB 12 G5 DB 11 G4 G3 G2 G1 B5 B4 B3 B2 B1 B0 RD [6] RD [5] RD [4] RD [3] RD [2] RD [1] RD [0] DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 G0 2nd transfer 1st transfer Figure 20 9-bit Interface Data Format (RAM Data Write/ RAM Data Read) Data Transfer Synchronization in 9-bit Bus Interface operation The R61505U supports data transfer synchronization function to reset the counters for upper and lower 9bit transfers in 9-bit bus transfer mode. When a mismatch occurs in upper and lower data transfers due to noise and so on, the 00H instruction is written four times consecutively to reset the upper and lower counters in order to restart the data transfer from upper 9 bits. The data transfer synchronization, when executed periodically, can help the display system recover from runaway. Make sure to execute data transfer synchronization after reset operation before transferring instruction. RS RD WR DB17 ~ DB9 Upper Lower "00"H "00"H "00"H "00"H Upper Lower Upper (9-bit transfer synchronization) Figure 21 9-bit Data Transfer Synchronization Rev.1.0 September 13, 2006, page 103 of 199 R61505U 80-system 8-bit Bus Interface When transferring 16-bit instruction, it is divided into upper and lower 8 bits, and the upper 8 bits are transferred first. The RAM write data is also divided into upper and lower 8 bits, and the upper 8 bits are transferred first. The RAM write data is expanded into 18 bits internally as shown below. The unused DB pins must be fixed at either IOVCC or IOGND level. When transferring the index register setting, make sure to write upper byte (8 bits). IM[3:0] = 0011 H8/2245 CSn* CS* A1 RS HWR WR* (RD*) (RD*) R61505U DB17-10 DB9-0 D15-0 8 10 Figure 22 8-bit interface Instruction write Second transfer First transfer Input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 Instruction IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 Instruction code Device code read Instruction IB 15 IB 14 IB 13 Input DB 17 DB 16 DB 15 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 First transfer DB 14 DB 13 IB 3 IB 2 IB 1 IB 0 DB 11 DB 10 Second transfer DB 13 DB 12 Figure 23 8-bit Interface Data Format (Instruction Write / Device Code Read) Rev.1.0 September 13, 2006, page 104 of 199 R61505U RAM data write (2-transfer mode: TRIREG = 0) First transfer Input Second transfer DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 R5 R4 R3 R2 R1 R0 G5 G4 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 G2 G1 G0 B5 B4 B3 B2 B1 G3 B0 Note: 65,536-color display RAM data write (3-transfer mode: TRIREG = 1, DFM =0) DB 10 DB 17 DB 16 Second transfer DB DB DB DB 15 14 13 12 R4 R3 R2 R1 First transfer DB 11 Input GRAM data write R5 R0 G5 G4 DB 11 DB 10 DB 17 DB 16 DB 15 Third transfer DB DB DB 14 13 12 DB 11 DB 10 G3 G2 G1 G0 B5 B4 B1 B0 1 pixel B3 B2 Note: Normal display in 262,144 colors RAM data write (3-transfer mode: TRIREG = 1, DFM = 1) DB 17 First transfer DB DB DB 16 15 14 DB 13 DB 12 DB 17 Second transfer DB DB DB DB 16 15 14 13 DB 12 DB 17 R5 R4 R1 R0 G5 G4 G0 B5 Input GRAM data write R3 R2 G3 G2 G1 1 pixel Third transfer DB DB DB 16 15 14 B4 B3 B2 DB 13 DB 12 B1 B0 Note: Normal display in 262,144 colors Figure 24 8-bit Interface Data Format (RAM Data Write) RAM data read GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Read data RD [17] RD [16] RD [15] RD [14] RD [13] RD [12] RD [11] RD [10] RD [9] RD [8] RD [7] RD [6] RD [5] RD [4] RD [3] RD [2] RD [1] RD [0] DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 14 DB 13 DB 11 DB 10 Output pins 1st transfer DB 17 DB 16 DB 15 DB 12 2nd transfer Note: Data cannot be transferred in 3 times in read operation via 8-bit interface. Figure 25 8-bit Interface Data Format (RAM Data Read) Rev.1.0 September 13, 2006, page 105 of 199 R61505U Data Transfer Synchronization in 8-bit Bus Interface operation The R61505U supports data transfer synchronization function to reset the counters for upper and lower 8bit transfers in 8-bit bus transfer mode. When a mismatch occurs in upper and lower data transfers due to noise and so on, the 00H instruction is written four times consecutively to reset the upper and lower counters in order to restart the data transfer from upper 8 bits. The data transfer synchronization, when executed periodically, can help the display system recover from runaway. Make sure to execute data transfer synchronization after reset operation before transferring instruction. RS RD WR DB17 ~ DB10 Upper Lower "00"H "00"H "00"H "00"H Upper Lower Upper (8-bit transfer synchronization) Figure 26 8-bit Data Transfer Synchronization Rev.1.0 September 13, 2006, page 106 of 199 R61505U Serial Interface The serial interface is selected by setting the IM3/2/1 pins to the IOGND/IOVCC/IOGND levels, respectively. The data is transferred via chip select line (CS), serial transfer clock line (SCL), serial data input line (SDI), and serial data output line (SDO). In serial interface operation, the IM0/ID pin functions as the ID pin, and the DB17-0 pins, not used in this mode, must be fixed at either IOVCC or GND level. The R61505U recognizes the start of data transfer on the falling edge of CS input and starts transferring the start byte. It recognizes the end of data transfer on the rising edge of CS input. The R61505U is selected when the 6-bit chip address in the start byte transferred from the transmission unit and the 6-bit device identification code assigned to the R61505U are compared and both 6-bit data match. Then, the R61505U starts taking in subsequent data. The least significant bit of the device identification code is determined by setting the ID pin. Send “01110” to the five upper bits of the device identification code. Two different chip addresses must be assigned to the R61505U because the seventh bit of the start byte is register select bit (RS). When RS = 0, index register write operation is executed. When RS = 1, either instruction write operation or RAM read/write operation is executed. The eighth bit of the start byte is R/W bit, which selects either read or write operation. The R61505U receives data when the R/W = 0, and transfers data when the R/W = 1. When writing data to the GRAM via serial interface, the data is written to the GRAM after it is transferred in two bytes. The R61505U writes data to the GRAM in units of 18 bits by adding the same bits as the MSBs to the LSB of R and B dot data. After receiving the start byte, the R61505U starts transferring or receiving data in units of bytes. The R61505U transfers data from the MSB. The R61505U’s instruction consists of 16 bits and it is executed inside the R61505U after it is transferred in two bytes (16 bits: DB15-0) from the MSB. The R61505U expands RAM write data into 18 bits when writing them to the internal GRAM. The first byte received by the R61505U following the start byte is recognized as the upper eight bits of instruction and the second byte is recognized as the lower 8 bits of instruction. When reading data from the GRAM, valid data is not transferred to the data bus until first five bytes of data are read from the GRAM following the start byte. The R61505U sends valid data to the data bus when it reads the sixth and subsequent byte data. Table 67 Start Byte Format Transferred Bits S 1 Start byte format Transfer start Device ID code 0 Note: 2 1 The ID bit is determined by setting the IM0/ID pin. Rev.1.0 September 13, 2006, page 107 of 199 3 1 4 1 5 0 6 ID 7 8 RS R/W R61505U Table 68 Functions of RS, R/W bits RS R/W Function 0 0 Set index register 0 1 Setting inhibited 1 0 Write instruction or RAM data 1 1 Read register settings or RAM data Instruction Input D 15 D 14 D 13 Instruction IB 15 IB 14 IB 13 First transfer (upper) D D D 12 11 10 IB 12 IB 11 IB 10 Second transfer (Lower) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 D 7 D 6 D 5 D 4 G2 G1 G0 B5 Instruction code RAM data write Input D 15 D 14 D 13 GRAM write data R5 R4 R3 First transfer (upper) D D D 12 11 10 R2 R1 R0 Second transfer (Lower) D 9 D 8 G5 G4 G3 1 pixel Figure 27 Serial interface Data Format Rev.1.0 September 13, 2006, page 108 of 199 D 3 D 2 D 1 D 0 B4 B3 B2 B1 B0 Note: 65,536-color display in SPI R61505U (a) Clock synchronization serial data transfer (basic mode) End of transfer Transfer start CS input 1 2 3 4 5 6 7 “0” “1” “1” “1” “0” ID RS SCL input 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 D9 D8 D7 D6 D5 D4 D3 D2 D1 MSB SDI input Device ID code LSB RW D15 D14 D13 D12 D11 D10 D0 RS RW Start byte SDO output 24 Set IR (index register), instruction, write RAM data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Read instruction, RAM data (b) Clock synchronization serial consecutive data transfer CS input SCL input SDI input Start byte Instruction (1) Upper 8 bits Instruction (1) Lower 8 bits Instruction (2) Upper 8 bits Instruction (2) Lower 8 bits Start Note: The eight bits read after start byte input is recognized as the upper byte of instruction. Instruction execution time (1) End (c) RAM read data transfer CS input SCL input SDI input Start byte RS = 1 R/W = 1 SDO output Dummy read Dummy read Dummy read Dummy read Dummy read RAM read Upper 8 bits 5 1 2 3 4 Start RAM read Lower 8 bits Note: Valid data is not sent until the R61505U reads five bytes from the GRAM after start byte input . The R61505 sends valid data when it reads the sixth and subsequent bytes. Figure 28 Data Transfer in Serial interface Rev.1.0 September 13, 2006, page 109 of 199 End R61505U VSYNC Interface The R61505U supports VSYNC interface, which enables displaying a moving picture via system interface by synchronizing the display operation with the VSYNC signal. VSYNC interface can realize moving picture display with minimum modification to the conventional system operation. VSYNC CS* LCDC/MPU RS R61505U WR* DB17-0, 8-1 16 Figure 29 VSYNC Interface The VSYNC interface is selected by setting DM1-0 = 10 and RM = 0. In VSYNC interface operation, the internal display operation is synchronized with the VSYNC signal. By writing data to the internal RAM at faster than the calculated minimum speed (internal display operation speed + margin), it becomes possible to rewrite the moving picture data without flickering the display and display a moving picture via system interface. The display operation is performed in synchronization with the internal clock signal generated from the internal oscillator and the VSYNC signal. The display data is written in the internal RAM so that the R61505U rewrites the data only within the moving picture area and minimize the number of data transfer required for moving picture display. By writing data using high-speed write function (HWM =1), the R61505U can write data via VSYNC interface in high speed with low power consumption. VSYNC RAM data write via system interface Display operation synchronized with internal clock Note: Use high-speed write function (HWM=1) when writing data via VSYNC interface. Figure 30 Moving Picture Data Transfers via VSYNC Interface Rev.1.0 September 13, 2006, page 110 of 199 R61505U The VSYNC interface has the minimum for RAM data write speed and internal clock frequency, which must be more than the values calculated from the following formulas, respectively. Internal clock frequency (fosc) [Hz] = FrameFrequency × ( DisplayLin es ( NL ) + FrontPorch ( FP ) + BackPorch( BP )) × 16(clocks ) × var iance 240 × DisplayLines ( NL) RAMWriteSpeed (min .)[ Hz ] > ( BackPorch( BP) + DisplayLines( NL) − m arg ins ) × 16(clocks) × 1 fosc Note: When RAM write operation is not started right after the falling edge of VSYNC, the time from the falling edge of VSYNC until the start of RAM write operation must also be taken into account. An example of calculating minimum RAM writing speed and internal clock frequency in VSYNC interface operation is as follows. [Example] Panel size Total number of lines (NL) Back/front porch Frame frequency 240 RGB × 320 lines (NL = 6’h27: 320 lines) 320 lines 14/2 lines (BP = 4h’E, FP = 4’h2) 60 Hz Internal clock frequency (fosc) [Hz] = 60 Hz × (320 + 2 + 14) lines × 16 clocks × 1.1 / 0.9 = 394 kHz Notes: 1. When setting the internal clock frequency, possible causes of fluctuation must also be taken into consideration. In this example, the internal clock frequency allows for a margin of ±10% for variances and guarantee that display operation is completed within one VSYNC cycle. 2. This example includes variances attributed to LSI fabrication process and room temperature. Other possible causes of variances, such as differences in external resistors and voltage change are not considered in this example. It is necessary to include a margin for these factors. Minimum speed for RAM writing [Hz] > 240 × 320 / {((14 + 320 – 2) lines × 16 clocks) × 1/394 kHz} = 5.7 MHz Notes: 1. 2. In this example, it is assumed that the R61505U starts writing data in the internal RAM on the falling edge of VSYNC. There must be at least a margin of 2 lines between the line to which the R61505U has just written data and the line where display operation on the LCD is performed. In this example, the RAM write operation at a speed of 5.7MHz or more, which starts on the falling edge of VSYNC, guarantees the completion of data write operation in a certain line address before the R61505U starts the display operation of the data written in that line and can write moving picture data without causing flicker on the display. Rev.1.0 September 13, 2006, page 111 of 199 R61505U RAM write VSYNC RC oscillation ±10% [line] Display operation Back porch (14 lines) 320 Line processing FP = 2H Main panel Moving picture display (320 lines) RAM write 5.7 MHz Display operation 16.67 [ms] 0 Front porch (2 lines) (60 Hz) BP = 14H VSYNC Blank period Figure 31 Write/Display Operation Timing via VSYNC Interface Notes to VSYNC Interface operation 1. The above example of calculation gives a theoretical value. Possible causes of variances of internal oscillator should be taken into consideration. Make enough margin in setting RAM write speed for VSYNC interface operation. 2. The above example shows the values when writing over the full screen. Extra margin will be created if the moving picture display area is smaller than that. RAM write Back porch (14 lines) RC oscillation ±10% [line] 320 Display operation FP = 2H (16 lines) 316 Line processing Base image Moving picture display (320 lines) (24 lines) RAM write 5.7MHz Display operation 16 0 Front porch (2 lines) BP = 14H VSYNC Figure 32 RAM Write Speed Margins Rev.1.0 September 13, 2006, page 112 of 199 [ms] 16.67 (60 Hz) R61505U 3. The front porch period continues from the end of one frame period to the next VSYNC input. 4. The instructions to switch from internal clock operation (DM1-0 = 00) to VSYNC interface operation modes and vice versa are enabled from the next frame period. 5. The partial display and vertical scroll functions are not available in VSYNC interface operation. 6. In VSYNC interface operation, set AM = 0 to transfer display data correctly. 7. In VSYNC interface operation, use high-speed write function (HWM = 1) when writing display data to the internal RAM. Internal Clock Operation to VSYNC Interface VSYNC Interface to Internal Clock Operation Internal clock operation HWM = 1 and AM = 0 Operation via VSYNC interface Set DM1-0=00 and RM=0 for internal clock operation RAM address set Set DM1-0 = 10 and RM = 0 for VSYNC interface Display operation in synchronizaion with VSYNC Display operation in synchronization with internal clocks *Instruction setting to VSYNC interface is enabled from the next frame period. *Instruction setting to internal clock operation mode is enabled from the next frame. Wait one frame period or more Display operation in synchronization with internal clock Set index register to R22h Internal clock operation Wait one frame period or more Note: Continue VSYNC signal for at least one frame period after setting DM1-0 and RM bits to internal clock operation mode. Write data to RAM via VSYNC interface Sequences to Switch between VSYNC Display operation in synchronizaion with VSYNC Operation via VSYNC interface Internal Clock Operation Mode Setting (DM1-0=00, RM=0) ernal Clock Operation Modes Wait More Than One Frame Internal Clock Operation Note: Input the VSYNC signal before setting the DM1-0 and RM bits to VSYNC interface mode. Figure 33 Sequences to Switch between VSYNC and Internal Clock Operation Modes Rev.1.0 September 13, 2006, page 113 of 199 R61505U External Display Interface The R61505U supports the RGB interface. The interface format is set by RM[1:0] bits. The internal RAM is accessible via RGB interface. Table 69 RGB interface RIM1 RIM0 RGB Interface DB Pin 0 0 18-bit RGB interface DB17-0 0 1 16-bit RGB interface DB17-13, DB11-1 1 0 6-bit RGB interface DB17-12 1 1 Setting inhibited - Note: Using multiple interface at a time is prohibited. Rev.1.0 September 13, 2006, page 114 of 199 R61505U RGB Interface The display operation via RGB interface is synchronized with VSYNC, HSYNC, and DOTCLK. The data can be written only within the specified area with low power consumption by using window address function and high-speed write mode (HWM = 1). In RGB interface operation, front and back porch periods must be made before and after the display period. VSYNC ENABLE (V) Back porch period (BP) Moving picture display area Display period (NL) Front porch period (FP) HSYNC DOTCLK ENABLE (H) DB17-0 VSYNC: Frame synchronization signal HSYNC: Line synchronization signal DOTCLK: Dot clock ENABLE: Data enable signal DB 17-0: RGB (6:6:6) display data Back porch period (BPP): Front porch period (FPP): Display period: The number of lines for one frame: 14H ҈ BP ҈ 2H 14H ҈ FP ҈ 2H FPP + BPP ҇ 16H NL ҇ 320H FPP + NL + BPP Notes: 1. The front porch period continues until next VSYNC input is detected. 2. Make sure to match the VSYNC, HSYNC, and DOTCLK frequencies to the resolution of liquid crystal panel. Figure 34 Display Operation via RGB Interface Polarities of VSYNC, HSYNC, ENABLE, and DOTCLK Signals The polarities of VSYNC, HSYNC, ENABLE, and DOTCLK signals can be changed by setting the DPL, EPL, HSPL, and VSPL bits, respectively for convenience of system configuration. Rev.1.0 September 13, 2006, page 115 of 199 R61505U RGB Interface Timing The timing relationship of signals in RGB interface operation is as follows. 16-/18-bit RGB Interface Timing One frame Back porch period Front porch period VSYNC HSYNC DOTCLK ENABLE DB17-0 VLW = 1H or more VSYNC 1H HLW ҈ 1CLK HSYNC 1 clock DOTCLK DTST ҈ 1CLK ENABLE DB17-0 Valid data Figure 35 Notes: 1. VLW: VSYNC Low period HLW: HSYNC Low period DTST: data transfer setup time 2. Use high-speed write function (HWM = 1) when writing data via RGB interface. Rev.1.0 September 13, 2006, page 116 of 199 R61505U 6-bit RGB Interface Timing One frame Front porch period Back porch period VSYNC HSYNC DOTCLK ENABLE DB17-12 (DB5-0) VLW = 1H or more VSYNC 1H HLW ҈ 3CLK HSYNC 1CLK DOTCLK DTST ҈ 3CLK ENABLE RGBRGBRGBRGBRGBRGBRGB DB17-12 (DB5-0) Valid data Figure 36 Notes: 1. VLW: VSYNC Low period HLW: HSYNC Low period DTST: Data transfer setup time 2. Use high-speed write function (HWM = 1) when writing data via RGB interface. 3. In 6-bit RGB interface operation, set the VSYNC, HSYNC, ENABLE, DOTCLK cycles so that one pixel is transferred in units of three DOTCLKs via DB17-12 (DB5-0). Rev.1.0 September 13, 2006, page 117 of 199 R61505U Moving Picture Display via RGB Interface The R61505U supports RGB interface for moving picture display and incorporates RAM for storing display data, which provides the following advantages in displaying a moving picture. 1. The window address function enables transferring data only within the moving picture area 2. The high-speed write function enables RAM access in high speed with low power consumption 3. It becomes possible to transfer only the data written over the moving picture area 4. By reducing data transfer, it can contribute to lowering the power consumption of the whole system 5. The data in still picture area (icons etc.) can be written over via system interface while displaying a moving picture via RGB interface RAM access via system interface in RGB interface operation The R61505U allows RAM access via system interface in RGB interface operation. In RGB interface operation, data is written to the internal RAM in synchronization with DOTCLK while ENABLE is “Low”. When writing data to the RAM via system interface, set ENABLE “High” to stop writing data via RGB interface. Then set RM = “0” to enable RAM access via system interface. When reverting to the RGB interface operation, wait for the read/write bus cycle time. Then, set RM = “1” and the index register to R22h to start accessing RAM via RGB interface. If there is a conflict between RAM accesses via two interfaces, there is no guarantee that the data is written in the RAM. The following is an example of rewriting still picture data via system interface while displaying a moving picture via RGB interface. Rev.1.0 September 13, 2006, page 118 of 199 R61505U updating frame data updating frame data VSYNC ENABLE DOTCLK DB17-0 Note 4) Note 4) System interface Index R22 RM = 0 RAM address set Index R22 writing moving picture area Notes: Update data in the area other than moving picture area RAM address set RM = 1 Index R22 writing moving picture area writing still picture area 1. In RGB interface operation, RAM address AD16-0 is set in the address counter on the falling edge of VSYNC. 2. Set AD16-0 bits and the index R22h before starting RAM access via RGB interface. 3. Use high-speed write function when writing via RGB interface. 4. When switching to the system interface operation after writing data via RGB interface, wait at least one write cycle (tcycw). 6/25 00: 6/2 00:00 00 Moving picture area 6/25 00: 6/2 00:00 00 Moving picture area Figure 37 Updating the Still Picture Area while Displaying Moving Picture Rev.1.0 September 13, 2006, page 119 of 199 R61505U 6-bit RGB interface The 6-bit RGB interface is selected by setting RIM1-0 = 10. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. The display data is transferred to the internal RAM in synchronization with the display operation via 6-bit port while data enable signal (ENABLE) allows RAM access via RGB interface. Unused pins DB11-0 (DB17-6) must be fixed at either IOVCC or IOGND level. Instruction bits can be transferred only via system interface. RIM = 10 VSYNC HSYNC LCDC /MPU DOTCLK R61505 ENABLE DB17-12 (DB5-0) DB11-0 (DB17-6) 6 12 Data format for the 6-bit RGB interface (RIM = 10) Input GRAM write data Second transfer DB 17 DB 5 DB 16 DB 4 First transfer DB DB DB 15 14 13 DB DB DB 3 2 1 DB 12 DB 0 DB 17 DB 5 DB 16 DB 4 DB 15 DB 3 DB 14 DB 2 DB 13 DB 1 DB 12 R5 R4 R3 R0 G5 G4 G3 G2 G1 R2 R1 DB 0 DB 17 DB 5 DB 16 DB 4 G0 B5 B4 Third transfer DB DB DB 15 14 13 DB DB DB 3 2 1 B3 B2 B1 1 pixel Note: 262,144 colors Figure 38 Example of 6-bit RGB Interface and Data Format Rev.1.0 September 13, 2006, page 120 of 199 DB 12 DB 0 B0 R61505U Data Transfer Synchronization in 6-bit Bus Interface operation The R61505U has the counters, which count the first, second, third 6 bit transfers via 6-bit RBG interface. The counters are reset on the falling edge of VSYNC so that the data transfer will start from the first 6 bits of 18-bit RGB data from the next frame period. Accordingly, the data transfer via 6-bit interface can restart in correct order from the next frame period even if a mismatch occurs in transferring 6-bit data. This function can minimizes the effect from data transfer mismatch and help the display system return to normal display operation when data is transferred consecutively in moving picture operation. VSYNC ENABLE DOTCLK DB17-12 (DB5-0) Second transfer Transfer synchronization Second Third First First Second Third transfer transfer transfer transfer transfer transfer Figure 39 6-bit Transfer Synchronization Rev.1.0 September 13, 2006, page 121 of 199 R61505U 16-bit RGB interface The 16-bit RGB interface is selected by setting RIM1-0 = 01. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. The display data is transferred to the internal RAM in synchronization with the display operation via 16-bit ports while data enable signal (ENABLE) allows RAM access via RGB interface. Instruction bits can be transferred only via system interface. RIM = 001 VSYNC HSYNC DOTCLK LCDC/MPU R61505U ENABLE DB17-13, 11-1 16 DB12,0 2 Data format for the16-bit interface (RIM = 01) Input GRAM data DB 17 R5 DB 16 R4 DB 15 DB 14 DB 13 R3 R2 R1 R0 DB 11 DB 10 DB 9 DB 8 G5 G4 G3 G2 1 pixel DB 7 G1 DB 6 G0 DB 5 B5 DB 4 B4 DB 3 B3 B2 DB 1 B1 B0 Note: 65,536-color display Figure 40 Example of 16-Bit RGB Interface and Data Format Rev.1.0 September 13, 2006, page 122 of 199 DB 2 R61505U 18-bit RGB interface The 18-bit RGB interface is selected by setting RIM1-0 = 00. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. The display data is transferred to the internal RAM in synchronization with the display operation via 18-bit ports (DB17-0) while data enable signal (ENABLE) allows RAM access via RGB interface. Instruction bits can be transferred only via system interface. RIM = 00 VSYNC HSYNC DOTCLK LCDC/MPU R61505U ENABLE DB17-0 18 Data format for the 18-bit interface (RIM = 00) Input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 GRAM write data R5 R4 R3 R2 R1 R0 G5 G4 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 1 pixel Note: Normal display in 262,144 colors Figure 41 Example of 18-bit RGB Interface and Data Format Rev.1.0 September 13, 2006, page 123 of 199 R61505U Notes to external display interface operation a. The following functions are not available in external display interface operation. Table 70 Functions Not Available in External Display Interface operation Function External Display Interface Internal Display Operation Partial display Not available Available Scroll function Not available Available b. The VSYNC, HSYNC, and DOTCLK signals must be supplied during display period. c. The reference clock to generate liquid crystal panel controlling signals in RGB interface operation is DOTCLK, not the internal clock generated from the internal oscillator. d. In 6-bit RGB interface operation, 6-bit dot data (R, G, and B) is transferred in synchronization with DOTCLK. In other words, it takes three DOTCLKs to transfer one pixel data. e. In 6-bit RGB interface operation, make sure to set the cycles of VSYNC, HSYNC, DOTCLK, ENABLE signals so that the data transfer is completed in units of pixels. f. When switching between the internal operation mode and the external display interface operation mode, follow the sequences below in setting instruction. g. In RGB interface operation, front porch period continues after the end of frame period until next VSYNC input is detected. h. In RGB interface operation, use high-speed write function (HWM = 1) when writing data to the internal RAM. i. In RGB interface operation, RAM address AD16-0 is set in the address counter every frame on the falling edge of VSYNC. Rev.1.0 September 13, 2006, page 124 of 199 R61505U Internal Clock Operation to RGB Interface (1) RGB Interface (1) to Internal Clock Operation Internal clock operation RGB interface operation Set internal clock operation mode* (DM1-0 = 00 and RM = 0) HWM = 1 and AM = 0 RAM address set Set DM1-0 = 01 and RM = 1 for RGB interface Display operation in synchronization with internal clocks Wait one frame period or more *Instruction setting for the RGB interface operation is enebled from the next frame period. Internal clock operation Set index register to R22h *Instruction setting to the internal clock operation is enebled from the next frame period. Display operation in synchronization with internal clocks Note: Continue RGB interface signals at least for one frame period after setting DM1-0, RM bits to internal clock operation. Wait one frame period or more Write data to RAM via RGB interface Display operation in synchronization with VSYNC, HSYNC, and DOTCLK Display operation in synchronization with VSYNC, HSYNC, and DOTCLK Operation via RGB interface Note: Input the RGB interface signals before setting the DM1-0 and RM bits to the RGB interface operation. Figure 42 RGB and Internal Clock Operation Mode switching sequences Rev.1.0 September 13, 2006, page 125 of 199 R61505U RAM Address and Display Position on the Panel The R61505U has memory to store display data of 240RGB x 320 lines. The R61505U incorporates a circuit to control partial display, which allows switching driving method between full-screen display mode and partial display mode. The R61505U makes display arrangement setting and panel driving position control setting separately and specifies RAM area for each image displayed on the panel. For this reason, there is no need to take the mounting position of the panel into consideration when designing a display on the panel. The following is the sequence of setting full-screen and partial display. 1. 2. 3. 4. Set (PTSAx, PTEAx) to specify the RAM area for each partial image Set the display position of each partial image on the base image by setting PTDPx. Set NL to specify the number of lines to drive the liquid crystal panel to display the base image After display ON, set display enable bits (BASEE, PTDE0/1) to display respective images Normal display Partial display 1/2 5. BASEE = 1 BASEE = 0, PTDE0/1 = 1 Changes BASEE, PTDE0/1 settings when turning on and off the full and partial displays 1/2. In driving the liquid crystal panel, the clock signal for gate line scan is supplied consecutively via interface in accordance with the number of lines to drive the liquid crystal panel (NL setting). When switching the display position in horizontal direction, set SS bit when writing RAM data. Table 71 Base image Display ENABLE Numbers of lines RAM area BASEE NL (BSA, BEA) = (9’h000, 9’h13F) Notes 1: The base image is displayed from the first line of the screen. 2: Make sure NL ≤ 320 (lines) = BEA – BSA when setting a base image RAM area. BSA and BEA are fixed to 9’h000, 9’h13F, respectively. Table 72 Display ENABLE Display position RAM area Partial image 1 PTDE0 PTDP0 (PTSA0, PTEA0) Partial image 2 PTDE1 PTDP1 (PTSA1, PTEA1) Rev.1.0 September 13, 2006, page 126 of 199 R61505U Display data output position Panel display position Base image RAM Address RAM Write Address Partial image RAM Address 1 (HSA,HEA) BSA = 9'h000 LCD PTDP0 PTSA0 Base image Scan direction Partial image 1 PTEA0 Window Address PTDP1 PTSA1 (VSA,VEA) Partial image 2 PTEA1 NL BEA = 9'h13F Figure 43 RAM Address, display position and drive position Restrictions in setting display control instruction There are restrictions in coordinates setting for display data, display position and partial display. Screen setting In setting the number of lines to drive the liquid crystal panel, make sure that the total number of lines is 320 lines or less (NL ≤ 320 lines). Base image display 1. The base image is displayed from the first line of the screen: BSA = 1st line (of the display panel) 2. The base image RAM area (specified by BSA = 000, BEA = 13F) must include the same or more number of lines set by NL bits (liquid crystal panel drive lines): BEA – BSA = 320 lines ≥ NL Partial image display Set the partial image RAM area setting registers (PTSAx, PTEAx bits) and the partial position setting registers (PTDPx bits) so that the RAM areas and the display positions of partial images do not overlap one another. 0 ≤ PTDP0 ≤ PTDP0+ (PTEA0 – PTSA0) < PTDP1 ≤ PTDP1+ (PTEA1 – PTSA1) ≤ NL Rev.1.0 September 13, 2006, page 127 of 199 R61505U The following figure shows the relationship among the RAM address, display position, and the lines driven for the display. Display data output order LCD panel physical line address 0 RAM line address Partial display Display screen 0 (1st line) 1 (2nd line) 2 (3rd line) 1 2 3 4 5 BSA0 = 9'h000 PTDP0 PTSD image 1 Display area BASE image RAM area PTDP1 NL (n lines) NL PTSD image 2 Display area n-1 NL PTSA0 Partial image 1 RAM area PTEA0 PTSA1 Partial image 2 RAM area PTEA1 BEA = 9’h13F Figure 44 Display RAM address and panel display position Note: This figure shows the relationship between RAM line address and the display position on the panel. In the R61505U’s internal operation, the data is written in the RAM area specified by the window address setting (R50h~R53h). Rev.1.0 September 13, 2006, page 128 of 199 R61505U Instruction setting example The followings are examples of settings for 240(RGB) x 320(lines) panel. 1. Full screen display (no partial display) The following is an example of settings for full screen display. Table 73 Base image display instruction BASEE 1 NL[5:0] 6’h27 PTDE0 PTDE1 0 0 Display data output order LCD panel physical line address 0 (1st line) 1 (2nd line) 2 (3rd line) 1 2 3 4 5 NL (320 lines) RAM line address BSA=9'h000 9’h000 Base image BASE image RAM area 320 319 (320th line) BEA = 9’h13F Figure 45 Full screen display (no partial) Rev.1.0 September 13, 2006, page 129 of 199 R61505U 2. Partial Display The following is an example of settings for displaying partial image 1 only and turning off the base image. The partial image 1 is displayed at the position specified by PTDP0 bit. Table 74 Base image display instruction BASEE 0 NL[5:0] 6’h27 partial image 1 display instruction PTDE0 1 PTSA0[8:0] 9’h000 PTEA0[8:0] 9’h00F PTDP0[8:0] 9’h080 partial image 2 display instruction PTDE1 0 PTSA1[8:0] 9’h000 PTEA1[8:0] 9’h000 PTDP1[8:0] 9’h000 LCD panel physical line address Display data output order RAM line address PTSA0 = 9'000 0 (1st line) 1 (2nd line) 2 (3rd line) 1 2 3 4 5 Partial image 1 RAM area PTEA0 = 9'h00F PTDP0 Partial image display area BASE image RAM area NL (320 lines) Base image (non-lit display) 320 319 (320th line) BEA = 9’h13F Figure 46 Partial Display Rev.1.0 September 13, 2006, page 130 of 199 R61505U Resizing function The R61505U supports resizing function (x 1/2, x 1/4), which is performed when writing image data. The resizing function is enabled by setting a window address area and the RSZ bit representing the contraction factor (x1/2 or x1/4) of the image. This function enables the R61505U to write the resized image data directly to the internal RAM, while allowing the system to transfer the original-sized image data. The resizing function allows the system to transfer data as usual even when resizing of the image is required. This feature makes image resizing easily available with various applications such as camera display, sub panel display, thumbnail display and so on. The R61505U processes the contraction of an image simply by selecting pixels. For this reason, the resized image may appear distorted when compared with the original image. Check the resized image before use. Original image data RAM data 0 1 2 3 4 5 6 (0,0) (0,1) (0,2) (0,3) (0,4) (0,5) (0,6) 1 (1,0) (1,1) (1,2) (1,3) (1,4) (1,5) 2 (2,0) (2,1) (2,2) (2,3) (2,4) (2,5) 3 (3,0) (3,1) (3,2) (3,3) (3,4) 4 (4,0) (4,1) (4,2) (4,3) 5 (5,0) (5,1) (5,2) 6 (6,0) (6,1) (6,2) 0 0 1 2 3 0 (0,0) (0,2) (0,4) (0,6) (1,6) 1 (2,0) (2,2) (2,4) (2,6) (2,6) 2 (4,0) (4,2) (4,4) (4,6) (3,5) (3,6) 3 (6,0) (6,2) (6,4) (6,6) (4,4) (4,5) (4,6) (5,3) (5,4) (5,5) (5,6) (6,3) (6,4) (6,5) (6,6) 1/2 resizing Figure 47 Data transfer in resizing Panel Display R61505U RAM data Original data 240 RSZ=2’h1 120 320 RAM Write 160 Figure 48 Data transfer, display example in resizing Table 75 Original image size (X x Y) 640x480(VGA) 352x288 (CIF) 320x240 (QVGA) 176x144 (QCIF) 120x160 132x176 Rev.1.0 September 13, 2006, page 131 of 199 Resized image size 1/2 (RSZ = 2’h1) 320x240 176x144 160x120 88x72 60x80 66x88 1/4 (RSZ = 2’h3) 160x120 88x72 80x60 44x36 30x40 33x44 R61505U Resizing setting The RSZ bit sets the resizing (contraction) factor of an image. When setting a window address area in the internal RAM, the window address area must fit the size of the resized picture. If there are surplus pixels as a result of resizing, which are calculated from the following equations, set RCV, RCH bits to the number of surplus pixels before writing data to the internal RAM. R61505U GRAM Address X Formulas for calculating the number of surplus pixels Rx (X0,Y0) The number of surplus pixels in horizontal direction L = X mod N Ry Orizinal image data size Y RAM write data (1/N resizing) The number of surplus pixels in vertical direction M = Y mod N (X0+Rx-1,Y0+Ry-1) Resized picture size in horizontal direction Rx = (X-L)/N Resized picture size in vertical direction Ry = (Y-M)/N Figure 49 Resizing Setting, surplus pixel calculation Table 76 Image (before resizing) Register setting in the R61505U Number of data in horizontal direction X Resizing setting RSZ N-1 Number of data in vertical direction Y Number of data in horizontal direction RCV L Resizing ratio 1/N Number of data in vertical direction RCH M Rev.1.0 September 13, 2006, page 132 of 199 RAM writing start address AD RAM window address HSA X0 (X0, Y0) HEA X0+Rx – 1 VSA Y0 VEA Y0+Ry – 1 R61505U Example of 1/2 resizing Rx=120 (0,0) X=240 RAM write data (1/2 resizing) 120 x 160 Ry=160 Y=320 Original Image R61505U GRAM address (119, 159) 240 x 320 Figure 50 Resizing setting example (x 1/2) Table 77 Original image (before resizing) Register setting in the R61505U Number of data in horizontal direction X 240 Resizing setting RSZ 2’h1 Number of data in vertical direction Y 320 Number of data in horizontal direction RCV 2’h0 Resizing ratio 1/N 1/2 Number of data in vertical direction RCH 2’h0 RAM writing start address AD RAM window address HSA 8’h00 HEA 8’h77 VSA 8’h00 VEA 8’h9F Resizing instruction Table 78 Resizing factor RSZ[1:0] 2h’0 2h’1 2h’2 2h’3 2h’4 No resizing (x 1) 1/2 resizing (x 1/2) Setting disabled 1/4 resizing (x 1/4) Setting disabled Table 79 Surplus pixels Contraction factor Vertical direction horizontal direction RCV[1:0] 2h’0 2h’1 2h’2 2h’3 RCH[1:0] 2h’0 2h’1 2h’2 2h’3 Surplus pixels 0 1 pixel 2 pixels 3 pixels 1 pixel = 1 RGB Rev.1.0 September 13, 2006, page 133 of 199 Surplus pixels 0 1 pixel 2 pixels 3 pixels 1 pixel = 1 RGB 17’h00000 R61505U Notes to Resizing function 1. 2. 3. 4. 5. Set the resizing instruction bits (RSZ, RCV, and RCH) before writing data to the internal RAM. When writing data to the internal RAM using resizing function, make sure to start writing data from the first address of the window address area in units of lines. Set the window address area in the internal RAM to fit the size of the resized image. Set AD16-0 (R20h, R21h) before start transferring and writing data to the internal RAM. Set the RCH, RCV bits only when using resizing function and there are surplus pixels. Otherwise (if RSZ = 2’h0), set RCH = RCV = 2’h0. Resizing instruction (RSZ, RCH, RCV) Set a window address area (HSA, HEA, VSA, VEA) Set the size of the window address area to fit the size of the resized image RAM address set (AD16-0) Write data to RAM Figure 51 RAM write operation sequence in resizing Rev.1.0 September 13, 2006, page 134 of 199 R61505U FMARK function The R61505U outputs an FMARK pulse when the R61505U is driving the line specified by FMP[8:0] bits. The FMARK signal can be used as a trigger signal to write display data in synchronization with display operation by detecting the address where data is read out for display operation. The FMARK output interval is set by FMI[2:0] bits. Set FMI[2:0] bits in accordance with display data rewrite cycle and data transfer rate. Set FMARKOE = 1 when outputting FMARK pulse from the FMARK pin. Table 80 Table 81 FMP[8:0] FMARK output position FMI[2] FMI[1] FMI[0] FMARK Output interval 9’h000 0 0 0 0 One frame period 0 0 1 2 frame periods 9’h001 st 1 line nd 9’h002 2 : : line rd 9’h14D 333 line 9’h14E th 334 line 9’h14F 335th line 9’h150 ~ 1FF Setting disabled Rev.1.0 September 13, 2006, page 135 of 199 0 1 1 4 frame periods 1 0 1 6 frame periods Other setting Setting disabled R61505U FMP setting example FMARK output position FMP = 9'h008 FMP=9’h008 NL=6’h27 320th line FP=4’h8 BP=4’h8 VL=8'h00 Line address 0 (1st line) 1 (2nd line) 2 (3rd line) 3 (4th line) 4 (5th line) 5 (6th line) 6 (7th line) 7 (8th line) 8 (1st line) 9 (2nd line) 10 (3rd line) Base image Back porch RAM physical line address AD[16:8] = 9'h000 AD[16:8] = 9'h001 AD[16:8] = 9'h002 Display area NL = 6'h27 327 (320th line) 328 (1st line) 329 (2nd line) 330 (3rd line) 331 (4th line) 332 (5th line) 333 (6th line) 334 (7th line) 335 (8th line) AD[16:8] = 9'h13F Front porch Figure 52 Rev.1.0 September 13, 2006, page 136 of 199 R61505U Display operation synchronous data transfer using FMARK The R61505U uses FMARK signal as a trigger signal to start writing data to the internal GRAM in synchronization with display scan operation. FMARK CS* LCDC/MPU RS R61505U WR* DB17-10, 8-1 16 Figure 53 Display synchronous data transfer interface In this operation, moving picture display is enabled via system interface by writing data at higher than the internal display operation frequency to a certain degree, which guarantees rewriting the moving picture RAM area without causing flicker on the display. The data is written in the internal RAM in order to transfer only the data written over the moving picture display area and minimize the data transfer required for moving picture display. High-speed write function (HWM = 1) enables writing data in high speed with low power consumption. FMARK RAM data write via system interface Display operation synchronized with internal clock Note: Use high-speed write function (HWM=1) when writing data via FMARK interface. Figure 54 Moving Picture Data Transfers via FMARK function Rev.1.0 September 13, 2006, page 137 of 199 R61505U When transferring data in synchronization with FMARK signal, minimum RAM data write speed and internal clock frequency must be taken into consideration. They must be more than the values calculated from the following equations. Internal clock frequency (fosc) [Hz] = FrameFrequency × ( DisplayLin es ( NL ) + FrontPorch ( FP ) + BackPorch ( BP )) × 16(clocks ) × var iance 240 × DisplayLines( NL) RAMWriteSpeed (min .)[ Hz ] > ( FrontPorch( FP ) + BackPorch( BP) + DisplayLines( NL) − m arg ins ) × 16(clocks) × 1 fosc Note: When RAM write operation is not started immediately following the rising edge of FMARK, the time from the rising edge of FMARK until the start of RAM write operation must also be taken into account. Examples of calculating minimum RAM data write speed and internal clock frequency is as follows. [Example] Panel size Total number of lines (NL) Back/front porch Frame marker position (FMP) Frame frequency 240 RGB × 320 lines (NL = 6’h13) 320 lines 14/2 lines (BP = 4h’E, FP = 4’h2) Display end line: 320th (FMP = 9’h14E) 60 Hz Internal clock frequency (fosc) [Hz] = 60 Hz × (320 + 2 + 14) lines × 16 clocks × 1.1 / 0.9 = 394 kHz Notes: 1.When setting the internal clock frequency, possible causes of fluctuation must also be taken into consideration. In this example, the internal clock frequency allows for a margin of ±10% for variances and guarantee that display operation is completed within one FMARK cycle. 2.This example includes variances attributed to LSI fabrication process and room temperature. Other possible causes of variances, such as differences in external resistors and voltage change are not considered in this example. It is necessary to include a margin for these factors. Minimum speed for RAM writing [Hz] > 240 × 320 / {((2+14 + 320 – 2) lines × 16 clocks) × 1/394 kHz} = 5.67 MHz Notes: 1. In this example, it is assumed that the R61505U starts writing data in the internal RAM on the rising edge of FMARK. 2.There must be at least a margin of 2 lines between the line to which the R61505U has just written data and the line where display operation on the LCD is performed. 3.The FMARK signal output position is set to the line specified by FMP[8:0] bits. Rev.1.0 September 13, 2006, page 138 of 199 R61505U In this example, RAM write operation at a speed of 5.67MHz or more, when starting on the rising edge of FMARK, guarantees the completion of data write operation in a certain line address before the R61505U starts the display operation of the data written in that line and can write moving picture data without causing flicker on the display. RAM write FMARK [line] 320 Front porch (2 lines) RC oscillation ±10% Display operation RAM write 5.67MHz Line processing Back porch (14 lines) RAM write (10MHz) 76,800 times Main panel Moving picture display (320 lines) Display operation 0 1+FP+BP=17H 7.68 13.54 13.64 [ms] 16.67 (60Hz) FMARK Front porch (2 lines) Back porch (14 lines) Figure 55 Write/Display Operation Timing Notes to display operation synchronous data transfer using FMARK signal 1. The above example of calculation gives a theoretical value. Possible causes of variances of internal oscillator should be taken into consideration. Make enough margin in setting RAM write speed for this operation. 2. Use high-speed write function (HWM = 1). Rev.1.0 September 13, 2006, page 139 of 199 R61505U High-speed RAM Write Function The R61505U supports high-speed RAM write function to write data to each line of window address area at a time. This function makes the R61505U available with the applications, which require high-speed, low-power-consumption data write operation such as color moving picture display. When enabling high-speed RAM write function (HWM = “1”), the data is first stored in the internal register of the R61505U in order to rewrite the RAM data in each horizontal line of the window address area at a time. Also, when transferring the data from the internal register to the internal RAM, the data written in the next line of the window address area can be transferred to the internal register of the R61505U. The high-speed write function minimizes the number of RAM access in write operation and enables high-speed consecutive RAM write operation required for moving picture display with low power consumption. Microcomputer Latch circuit 18 Address counter (AC) Register 1 Register 2 ............... Register n 18 x n 17 17'h0-0000 17'h0-0001 ........... 17'h0-0003 GRAM Figure 56 High-speed Consecutive RAM Write Operation CS input 1 2 ... n 1 (1) (2) ... (n) (1) 2 ... n 1 2 ... n (n) (1) (2) ... (n) WR input RAM data DB17-0 input Index (R22) (2) ... RAM write execution time RAM write data (18 x n bits) RAM address (AD16-0) RAM write execution time Index (R22) RAM write execution time x 2* RAM data RAM data RAM data (1) - (n) (n + 1) - (2n) (2n + 1) - (3n) 17'h00000 – 17'h0000n 17'h00100 – 17'h0010n 17'h00200 – 17'h0020n Figure 57 Example of High-speed RAM Write Operation (HWM = 1) Note: When switching from high-speed RAM write operation to index write operation, wait at least for two normal RAM write bus cycle periods (2 x tcycw) before executing a next instruction. Rev.1.0 September 13, 2006, page 140 of 199 R61505U CS input 1 2 WR 3 4 5 6 .......... 7 8 .......... input DB17-0 input Index (R202) RAM data upper (1) RAM data lower (1) .... RAM data upper (n) RAM data lower (n) RAM data upper (1) RAM write execution time RAM write dat a (18 x n bits) RAM address (AD16-0) 17'h00000 – 17'h0000n RAM data lower (1) .... RAM data upper (n) RAM data lower (n) RAM write execution time RAM data RAM data (1) - (n) (n + 1) - (2n) 17'h00100 – 17'h0010n Figure 58 Example of High-speed RAM Write Operation via 9-bit Interface Note: In high-speed RAM write operation, the R61505U writes data in units of n words. When using 9bit interface, the R61505U performs write operation 2 x n times in the internal register before writing the data in each line of the window address area. Notes to high-speed RAM write function 1. In high-speed RAM write mode, the R61505U performs write operation to the internal RAM in units of lines. If the data inputted to the internal write register is not enough to rewrite the data in the horizontal line of the window address area, the data is not written correctly in that line address. 2. If the IR is set to 22h when HWM = “1”, the R61505U always performs RAM write operation. With this setting, the R61505U does not perform RAM read operation. Make sure to set HWM = 0, when performing RAM read operation. 3. The high-speed RAM write function cannot be used when writing data in normal RAM write function mode. When switching form one write mode to the other, change modes first and set AD16-0 (RAM address set) before starting write operation. Rev.1.0 September 13, 2006, page 141 of 199 R61505U Table 82 RAM Write Operation Normal RAM Write (HWM = 0) High-speed RAM Write (HWM = 1) BGR function Available Available RAM address set In units of words In units of words RAM read In units of words Not available RAM write In units of words In units of words Window address In units of words (minimum window address area: 1 word x 1 line) In units of words (minimum window address area: 8 words x 1 line) External display interface Available Available AM AM = 1/0 AM = 0 High-speed RAM data write in a window address area The R61505U can perform consecutive high-speed data rewrite operation within a rectangular area (minimum: 8 words x 1 line) made in the internal RAM with the following settings. When writing data to the internal RAM using high-speed RAM write function, make sure each line of the window address area is overwritten at a time. If the data buffered in the internal register of the R61505U is not enough to overwrite the horizontal line in the window address area, the data is not written correctly in that line. The following is an example of writing data in the window address area using high-speed write function when a window address area is made by setting HSA = 8’h12, HEA = 8’hA7, VSA = 9’h020, and VEA = 9’h05B. Write in horizontal direction AM = 0, I/D0 = 1 Window address setting area HSA = 8'h12, HEA = 8'hA7 VSA = 9'h020, VEA = 9'h05B Enable High speed RAM write HW M = 1 RAM address set AD = 17'h02012* see Note 17'h00000 GRAM addr ess map 17h'02012 Window address area (data rewrite area) 17'h05BA7 17'h13FEF RAM write x 150 times x 60 times Note: Set a RAM address within the window address area. Window address area HSA = 8'h12, HEA = 8'hA7 VSA = 9'h020,VEA = 9'h05B Figure 59 High-speed RAM Write Operation in the Window Address Area Rev.1.0 September 13, 2006, page 142 of 199 R61505U Window Address Function The window address function enables writing display data consecutively in a rectangular area (a window address area) made in the internal RAM. The window address area is made by setting the horizontal address register (start: HSA7-0, end: HEA 7-0 bits) and the vertical address register (start: VSA8-0, end: VEA8-0 bits). The AM and I/D bits set the transition direction of RAM address (either increment or decrement, horizontal or vertical, respectively). Setting these bits enables the R61505U to write data including image data consecutively without taking the data wrap position into account. The window address area must be made within the GRAM address map area. Also, the AD16-0 bits (RAM address set register) must be set to an address within the window address area. [Window address area setting range] (Horizontal direction) (Vertical direction) [RAM Address setting range] (RAM address) 8’h00 ≤ HSA ≤ HEA ≤ 8’hEF 9’h000 ≤ VSA ≤ VEA ≤ 9’h13F HSA ≤ AD7-0 ≤ HEA VSA ≤ AD16-8 ≤ VEA GRAM address map 17'h00000 17'h000EF Window address area 17'h02010 17'h02110 17'h0202F 17'h05F10 17'h05F2F 17'h0212F 17'h13F00 17'h13FEF Window address area HSA = 8'h10, HEA = 8'h2F VSA = 9'h020, VEA = 9'h05F I/D = 2'h3 (increment) AM = 1'h0 (horizontal writing) ORG = 0 RAM address set = 17'02010 (arbitrary) ORG = 1 RAM address set = 17'00000 Both are set to the same RAM address. Figure 60 Automatic address update within a Window Address Area Rev.1.0 September 13, 2006, page 143 of 199 R61505U Scan Mode Setting The R61505U can set the gate pin assignment and the scan direction in the following 4 different ways by setting SM and GS bits to realize various connections between the R61505U and the LCD panel. Scan direction SM Interchanging forward direction (GS=0) Interchanging backward direction (GS=1) main Panel (GS0) 320 319 317 320 318 2 4 1 3 320 main Panel (GS1) 0 317 176 319 240 318 4 320 2 176 240 3 1 R61505U R61505U (Non-bump view) (Non-bump view) Scan order (Gate line No.) Scan order (Gate line No.) G1ЈG2ЈG3ЈG4.... G317ЈG318ЈG319ЈG320 G320ЈG319ЈG318ЈG317 .... G4ЈG3ЈG2ЈG1 Left/right forward direction (GS=0) Left/right backward direction (GS=1) 1 2 159 160 320 318 320 main Panel (GS0) 162 161 161 320 main Panel (GS1) 162 160 159 1 240 319 320 240 R61505U 2 1 R61505U (Non-bump view) (Non-bump view) Scan order (Gate line No.) Scan order (Gate line No.) G1ЈG3.... G317ЈG319Ј G2ЈG4.... G318ЈG320 G320ЈG318 .... G4ЈG2ЈG319ЈG317 .... G3ЈG1 Note: the numbers in the circles in the figure shows the order of scan. Figure 61 Rev.1.0 September 13, 2006, page 144 of 199 R61505U 8-color Display Mode The R61505U has a function to display in eight colors. In this display mode, only V0 and V31 are used and power supplies to other grayscales (V1 to V30) are turned off to reduce power consumption. In 8-color display mode, the γ-adjustment registers P0KP0-P0KP5, P0KN0-P0KN5, P0RP0, P0RP1, P0RN0, P0RN1, P0FP0-P0FP3, and P0FN0-P0FN3, are disabled and the power supplies to V1 to V30 are halted. The R61505U does not require GRAM data rewrite for 8-color display by writing the MSB to the rest in each dot data to display in 8 colors. GRAM MSB Grayscale amplifier Display data R5 R4 R3 R2 R1 R0 LSB G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 V0 R5 Two-level grayscale control 2 G5 Two-level grayscale control <R> V31 LCD driver <G> LCD driver B5 Two-level grayscale control <B> LCD driver R G B LCD Figure 62 8-color Display Mode Rev.1.0 September 13, 2006, page 145 of 199 R61505U Line Inversion AC Drive The R61505U supports n-line inversion alternating current drive in addition to frame-inversion liquid crystal alternating current drive. The timing to invert the electric current can be set to either every line or every two lines. Set line number of inversion timing checking display quality on liquid crystal display. Note that less number of line leads to higher inversion frequency of liquid crystal and more charge/discharge battery in liquid crystal display. One frame One frame Back porch 1 2 3 Front porch 4 321322 Back porch 336 1 2 3 Front porch 4 321 322 Frame-inversion AC drive · 320 line drive Line inversion AC drive · 320 line drive Figure 63 Example of Alternating Signals for n-line Inversion Rev.1.0 September 13, 2006, page 146 of 199 336 R61505U Alternating Timing The following figure illustrates the liquid crystal polarity inversion timing in different LCD driving methods. In case of frame-inversion AC drive, the polarity is inverted as the R61505U draws one frame, which is followed by a blank period lasting for (BP+FP) periods. In case of line inversion AC drive, polarity is inverted as the R61505U draws one line, and a blank period lasting for (BP+FP) periods is inserted when the R61505U draws one frame. Flame-inversion AC drive Line-inversion AC drive Alternating timing Alternating timing Alternating timing Frame 1 One-frame period Alternating timing Alternating timing Alternating timing 1 line 1 line 1 line 1 line Alternating timing 1 line Alternating timing 1 line Alternating timing 1 line Alternating timing Alternating timing Front porch 1 line Alternating timing Alternating timing Alternating timing Back porch One-frame period Back porch 1 line 1 line Front porch Figure 64 Alternating Timing Note: Frame inversion AC drive is available only in 8-color display mode. Check the quality of display on the panel. Rev.1.0 September 13, 2006, page 147 of 199 R61505U Frame-Frequency Adjustment Function The R61505U supports a function to adjust frame frequency. The frame frequency for driving liquid crystal can be adjusted by setting the DIV, RTN bits without changing the oscillation frequency. The R61505U allows changing the frame frequency depending on whether moving picture or still picture is displayed on the screen. In this case, set a high oscillation frequency. By changing the DIV and RTN settings, the R61505U can operate at high frame frequency when displaying a moving picture, which requires the R61505U to rewrite data in high speed, and it can operate at low frame frequency when displaying a still picture. Relationship between liquid crystal drive duty and frame frequency The following equation represent the relationship between liquid crystal drive duty and frame frequency. The frame frequency can be changed by setting the 1H period adjustment bit (RTN) and the operation clock frequency division ratio setting bit (DIV). Equation for calculating frame frequency FrameFrequency = fosc [ Hz ] NumberofClocks / line × DivisionRatio × ( Line + FP + BP) fosc: RC oscillation frequency Number of clocks per line: RTN bit Division ratio: DIV bit Line: number of lines to drive the LCD panel (NL bit) Number of lines for front porch: FP Number of lines for back porch: BP Example of Calculation: when maximum frame frequency = 70 Hz Fosc: 376KHz Number of lines: 320 lines 1H period: 16 clock cycles (RTNI/E[4:0] = “10000”) Division ratio of operating clock: 1/1 Front porch: 2 lines Back porch: 14 lines FFLM=376KHz/(16 clocks x 1/1 x (320 + 2 + 14) (lines) = 70Hz Rev.1.0 September 13, 2006, page 148 of 199 R61505U Partial Display Function The partial display function allows the R61505U to drive lines selectively to display partial images by setting partial display control registers. The lines not used for displaying partial images are driven at nonlit display level to reduce power consumption. The power efficiency can be enhanced in combination with 8-color display mode. Check the display quality when using low power consumption functions. Non-display area G41 Partial image 1 19 lines G59 Non-display area Number of lines to drive LCD Base picture display ENABLE Partial image 1 display RAM area Partial image 1 display position Parital image 1 display ENABLE : NL = 6’h1D (320 lines) : BASEE = 0 : (PTSA0, PTEA0) = (9'h000, 9'h013) : PTDP0 = 9'h028 : PTDE0 = 1 Figure 65 Partial display Note: See the “RAM Address and Display Position on the Panel” (p.126) for details on the relationship between the display positions of partial images and respective RAM area setting. Rev.1.0 September 13, 2006, page 149 of 199 R61505U Liquid crystal panel interface timing The relationships between RGB interface signals and liquid crystal panel control signals in internal operation and RGB interface operations are as follows Internal clock operation 1 Frame reference point reference point reference point reference point reference point reference point 1H FMARK (FMP = BP - 1) NOWI G1 G2 G320 MCPI S(3n+1) S(3n+2) S(3n+3) R, G, B R, G, B R, G, B n=0 ~ 239 1st line 2nd line VCOM Figure 66 Rev.1.0 September 13, 2006, page 150 of 199 320th line reference point reference point R61505U RGB interface operation 1 Frame BP FP VSYNC 1H HSYNC DOTCLK ENABLE DB 1 2 3 4 5 6 318 319 320 1 2 3 5DOTCLK see Note reference point reference point 1H FMARK (FMP = BP = 1) NOWE G1 G2 G3 G320 MCPE S(3n+1) S(3n+2) S(3n+3) RGB RGB RGB 320 n= 0 ~ 239 1st line 2nd line 320th line 3rd line VCOM Note: Transfer RGB data in one transfer via 16-bit port Figure 67 Rev.1.0 September 13, 2006, page 151 of 199 1 R61505U Oscillator The R61505U incorporates necessary RC elements for oscillator, eliminating the need to connect external elements for RC oscillation. The R61505U has two versions, each with different oscillation frequency: Typ. 376kHZ (R61505U0) and Typ. 600kHz (R61505U). See “Electrical Characteristics” for details. Select either suitable for display system. Connecting external resistance to adjust frequency is impossible. See “Frame-Frequency Adjustment Function” to adjust frame frequency. External resistance is not needed. Open OSC1 Open OSC2 R61505U Figure 68 Note 1: OSC frequency is set at Typ.376kHz (R61505U0) or 600Khz (R61505U1) when using RC element (See Electrical Characteristics). Rev.1.0 September 13, 2006, page 152 of 199 R61505U γ Correction function The R61505U supports γ-correction function to display in 262,144 colors simultaneously using gradientadjustment, amplitude-adjustment, fine-adjustment, tap-adjustment, and voltage division ratio adjustment registers. Each register consists of positive-polarity register and negative-polarity register to allow optimal gamma correction setting for the characteristics of the panel by enabling different settings for positive and negative polarities. γ Correction registers Grayscale voltage Grayscale voltage Grayscale voltage The γ-correction registers of the R61505U consists of gradient-adjustment, amplitude-adjustment, fineadjustment, tap-adjustment, and voltage division ratio adjustment registers to correct grayscale voltage levels according to the gamma characteristics of the liquid crystal panel. These register settings make adjustments to the relationship between grayscale number and grayscale voltage and the setting can be made differently for positive and negative polarities (the reference level and the register settings are the same for all RGB dots). The function of each register is as follows. Grayscale number (Vx) Grayscale number (Vx) Fine adjustment Grayscale voltage Amplitude adjustment Grayscale voltage Gradient adjustment Grayscale number (Vx) Grayscale number (Vx) Tap adjustment Grayscale number (Vx) Voltage division ratio adjustment Figure 69 Rev.1.0 September 13, 2006, page 153 of 199 R61505U Gradient adjustment registers The gradient adjustment registers are used to adjust the gradient, which represents the relationship between grayscale and voltage, without changing the dynamic range. The grayscale voltages for middle grayscale number can be adjusted by this register setting. Amplitude adjustment registers The amplitude adjustment registers are used to adjust the amplitude of the grayscale voltage. Fine adjustment registers The fine adjustment registers are used for minute adjustment of grayscale voltage levels. Tap adjustment registers The tap adjustment registers are for selecting two tap voltage supply points from V3 to V6 and from V25 to V28 by using selector. Voltage division ratio adjustment registers The voltage division ratio adjustment registers are used to change the division ratios between V0 and V1 and between V30 and V31. Table 83 γ correction registers Register Gradient Amplitude Fine adjustment Positive Negative Function P0RP0 [2:0] P0RN1 [2:0] Grayscale V4 variable resistance P0RP1 [2:0] P0RN0 [2:0] Grayscale V27 variable resistance V0RP0 [4:0] V0RN1 [4:0] Voltage level for grayscale V0 V0RP1 [4:0] V0RN0 [4:0] Voltage level for grayscale V31 P0KP0 [2:0] P0KN5 [2:0] Voltage level for grayscale V1 P0KP1 [2:0] P0KN4 [2:0] Voltage level for grayscales V3, V4, V5, V6 P0KP2 [2:0] P0KN3 [2:0] Voltage level for grayscale V10 P0KP3 [2:0] P0KN2 [2:0] Voltage level for grayscale V21 P0KP4 [2:0] P0KN1 [2:0] Voltage level for grayscales V28, V27, V26, V25 P0KP5 [2:0] P0KN0 [2:0] Voltage level for grayscales V30 P0FP0 [1:0] P0FN3 [1:0] Division ratio between V0 and V1 P0FP1 [1:0] P0FN2 [1:0] P0FP2 [1:0] P0FN1 [1:0] P0FP3 [1:0] P0FN0 [1:0] Rev.1.0 September 13, 2006, page 154 of 199 P0FP1[1:0]: specify either one of grayscales V3, V4, V5, V6 for the P0KP1[2:0] level P0FN2[1:0]: specify either one of grayscales V3, V4, V5, V6 for the P0KN4[2:0] level P0FP2[1:0]: specify either one of grayscales V28, V27, V26, V25 for the P0KP4[2:0] level P0FN1[1:0]: specify either one of grayscales V28, V27, V26, V25 for the P0KN1[2:0] level Division ratio between V30 and V31 R61505U γ Correction register settings and γ curve relationship Gamma Correction Registers㩷Function㩷 䋨REV = 0䋩 V0 5’h00 V0RN1 V0RP0 V2 5’h1F 2’h0 3’h0 P0FN3 4 5’h00 V6 2’h3 2’h3 2’h0 P0RN1 P0FN2 P0KN5 V0 3’h0 V10 3’h7 3’h7 P0KP0 3’h7 3’h7 3’h0 P0KN4 P0FP0 3’h7 V21 P0KN3 3 3’h0 2’h3 3’h0 V1 3’h0 2’h0 3’h7 P0KN2 Grayscale voltage [V] 5’h1F P0FN1 P0KN1 2’h3 3’h7 3’h7 3’h7 P0KP2 3’h7 P0KP3 V3 2’h0 P0RP0 3’h0 2 P0KP1 P0FP1 2’h3 V10 3’h0 3’h0 2’h3 3’h7 P0FN0 P0KP4 P0KP5 3’h7 3’h7 3’h0 3’h7 3’h7 2’h3 2’h3 P0KN0 V21 P0FP2 2’h0 P0RP1 V25 V31 3’h0 Positive polarity 5’h00 Negative polarity 5’h1F 3’h0 1 2’h0 V0RN0 5’h1F 5’h00 V31 0 6’d0 6’d8 6’d16 6’d24 6’d32 6’d40 6’d48 6’d56 6’d63 RAM Data [dec] Figure 70 Sn Negative polarity VCOM Positive polarity Figure 71 Source output waveform and VCOM polarity relationship Rev.1.0 September 13, 2006, page 155 of 199 R61505U Power-supply Generating Circuit The following figures show the configurations of liquid crystal drive voltage generating circuit of the R61505U. Power supply circuit connection example 1 (VCI1 = VCIOUT) In the following example, the VCIOUT level is adjusted internally in the VCIOUT output circuit. (1) VREG1OUT (2) VCILVL VCIOUT VcomR VCIOUT output circuit Grayscalevoltage generation circuit VREG 1 regulator Internal reference voltage generation circuit Source driver S1-S720 (3) VCI1 VcomH (17) C11(4) C11+ C12- (5) Step-up circuit 1 VcomH, VcomL output circuit Vcom level adjustment circuit C12+ (6) Vcom VcomL (18) VLOUT1 VCI (7) 47 DDVDH C13(8) G1-G320 C13+ C21- (9) Step-up circuit 2 C21+ C22- (10) C22+ C23- (11) VCI VCC C23+ (12) GND/RGND VLOUT2 (13) VGH see Note (14) VCILVL R63400A0 VCI AGND VLOUT3 VGL IOVCC (15) see Note IOGND VCL VDD (19) (16) Figure 72 Note: The wiring resistances between the schottky diode and GND/VGL must be 10Ω or less. Rev.1.0 September 13, 2006, page 156 of 199 R61505U Power supply circuit connection example 2 (VCI1 = VCI direct input) In the following example, the electrical potential VCI is directly applied to VCI1. In this case, the VCIOUT level cannot be adjusted internally but step-up operation becomes more effective. (1) VREG1OUT (2) VCILVL VCIOUT VcomR VCIOUT output circuit Grayscalevoltage generation circuit VREG 1 regulator Internal reference voltage generation circuit Source driver S1-S720 see Note 2 VCI1 Vci VcomH (17) C11(4) VcomH, VcomL output circuit Vcom level adjustment circuit C11+ C12- (5) C12+ (6) Vcom VcomL (18) VLOUT1 VCI (7) DDVDH R61505U C13(8) G1-G320 C13+ C21- (9) Step-up circuit 2 C21+ C22- (10) C22+ C23- (11) VCI VCC C23+ (12) GND/RGND VLOUT2 (13) VGH see Note (14) VCILVL R63400A0 VCI AGND VLOUT3 VGL IOVCC (15) IOGND see Note VCL VDD (19) (16) Figure 73 Notes: 1. The wiring resistances between the schottky diode and GND/VGL must be 10Ω or less. 2. When directly applying the VCI level to VCI1, set VC = 3’h7. Capacitor connection to VCIOUT is not necessary. Rev.1.0 September 13, 2006, page 157 of 199 R61505U Specifications of Power-supply Circuit External Elements The specifications of external elements connected to the power-supply circuit of the R61505U are as follows. Table 84 Capacitor Capacitance 1µF (B characteristics) Notes: Voltage proof Pin Connection 6V (1) VREG1OUT, (3) VCIOUT, (4) C11-/+, (5) C12-/+, (8) C13-/+, (16) VCL, (17) VCOMH, (18) VCOML, (19) VDD 10 V (6) VLOUT1, (9) C21-/+, (10) C22-/+, (11) C23-/+ 25 V (11) VLOUT2, (13) VLOUT3 1. Check with the LC module. 2. The numbers in the parentheses corresponds to the numbers of the elements in Figure 72, Figure 73. Table 85 Schottky Diode Specification Pin Connection VF < 0.4 V/20 mA@25 °C, VR ≥ 25 V (15) GND–VGL, (13) VCI–VGH, (7) VCI–DDVDH (Recommended diode: HSC226) Table 86 Variable Resistor Specification Pin Connection > 200 kΩ (2) VCOMR Table 87 Internal logic power supply Capacitance Voltage proof (recommended) Pin Connection 1µF (B characteristics) 3V VDD Rev.1.0 September 13, 2006, page 158 of 199 R61505U Voltage Setting Pattern Diagram The following are the diagrams of voltage generation in the R61505U and the TFT display application voltage waveforms and electrical potential relationship. VLOUT2 VGH BT VLOUT1 BT VCILVL(2.5 ~ 3.3V) VCC(2.5 ~ 3.3V) DDVDH VREG1OUT VRH VREG1OUT VCM/VCOMR VC VCI1 VCOMH VDV IOVCC(1.65 ~ 3.3V) GND(0V) VCOML VCL BT VLOUT3 VGL Figure 74 Notes: 1. The DDVDH, VGH, VGL, and VCL output voltages will become lower than their theoretical levels (ideal voltages) due to current consumption at each output level. Make sure that output voltage level in operation maintains the following relationship: (DDVDH – VREG1OUT) ≥ 0.5V, (VCOML – VCL) > 0.5V. Also make sure VGH-VGL ≤ 28V, VCI-VCL ≤ 6V. When the alternating cycle of VCOM is high (e.g. polarity inverts every line cycle), current consumption will increase. In this case, check the voltage before use. 2. In operation, setting voltages within the respective voltage ranges are recommended. Rev.1.0 September 13, 2006, page 159 of 199 R61505U Liquid crystal application voltage waveform and electrical potential VGH VREG1OUT VCOMH VCOM VCOML Sn (source driver output) Gn (panel interface output) Figure 75 Rev.1.0 September 13, 2006, page 160 of 199 R61505U VCOMH voltage adjustment sequence When adjusting the VCOMH voltage by setting VCM1 [5:0] in the R29’h register (internal VCOMH level adjustment circuit), follow the sequence below. The R61505U can retain the VCOMH level adjustment setting values in NVM, which allows writing twice (only one setting value can be written in NVM at one time). In writing the setting value in NVM, write the VCOMH adjustment setting value VCM1 [4:0] in ED[4:0] and ED[7] = 0 when writing in NVM for the first time or ED[7] = 1 when writing for the second time. When writing the setting value in NVM, follow the NVM control sequence and NVM write sequence in the following pages. Rev.1.0 September 13, 2006, page 161 of 199 R61505U Display ON sequence VcomH adjustment R29h: VCM1[4:0] Write the setting value to adjust the VcomH level in VCM1[4:0] Write the setting value in VCM1[4:0] The display on the panle will flicker when the VcomH level is adjusted internally Check the display quality Complete the VcomH level adjustment When writing the VCOMH adjsutment setting value in NVM for the first time VCM1[4:0] (R29h) Index IB15 IB14 IB13 IB12 IB11 IB10 IB9 29'h 0 0 0 0 0 0 0 IB8 IB7 IB6 IB5 0 0 0 0 IB4 IB3 IB2 IB1 IB0 VCM1 VCM1 VCM1 VCM1 VCM1 [4] [3] [2] [1] [0] Write the setting value in VCM1[4:0] in ED[4:0] NVM write register(A1'h) Index IB15 IB14 IB13 IB12 IB11 IB10 IB9 A1'h 0 0 0 0 0 0 0 IB8 IB7 IB6 ED[7] 0 =0 0 IB5 0 IB4 ED [4] IB3 ED [3] IB2 ED [2] IB1 ED [1] IB0 ED [0] When writing the VCOMH adjustment setting value in NVM for the second time VCM2[4:0] (R2Ah) Index IB15 IB14 IB13 IB12 IB11 IB10 IB9 2A'h 0 0 0 0 0 0 0 IB8 0 IB7 VCM SEL IB6 IB5 0 0 IB6 IB5 0 0 IB4 IB3 IB2 IB1 IB0 VCM2 VCM2 VCM2 VCM2 VCM2 [4] [3] [2] [1] [0] Write the setting value in VCM2[4:0] in ED[4:0] and VCMSEL = 1 in ED[7] at the same time NVM write register(A1'h) Index IB15 IB14 IB13 IB12 IB11 IB10 IB9 A1'h 0 0 0 0 0 0 0 IB8 0 IB7 ED [7] Figure 76 Rev.1.0 September 13, 2006, page 162 of 199 IB4 ED [4] IB3 ED [3] IB2 ED [2] IB1 ED [1] IB0 ED [0] R61505U NVM control sequence NVM load (register setting value rewrite) sequence NVM write sequence (VCC,VCI,IOVCC) ON VCI IOVCC1,2 VCC NVM dummy read RA0 (invalid data) GND VCC ψ IOVCC ψ VCI or VCC IOVCC VCI simultaneously NVM Load RA4h: 16'h0001 (CALB = 1) 1ms or more VPP1 = 9.0 r 0.1V 8x 1/osc or more VPP2 = 7.5 r 0.1V VPP3=GND NVM Load end GND (CALB = 0 automatically) 1ms or more 1ms or more Power ON reset NVM data read out R28: instruction read R29: instruction read R2A: instruction read 2ms or more Data transfer synchronization RS=0, DB=16’h0000 RS=0, DB=16’h0000 RS=0, DB=16’h0000 RS=0, DB=16’h0000 NVM dummy read Instruction read (select one from RA0, RA1, or RA2) (Read data is invalid) NVM write data setting RA1: 16'h00** ED = 8'hXX (arbitrary) NVM data write start RA0:16’h0010 (TE=0,EOP=2’h1,EAD=2’h0) NVM data write start RA0:16’h0090 (TE=1,EOP=2’h1,EAD=2’h0) 100~200ms NVM data write end RA0:16’h0000 (TE=0,EOP=2’h0,EAD=2’h0) 1 μs or more NVM Write data in another address? YES NO VPP1 = 9.0 r0.1V VPP2 = 7.5 r0.1V VPP3 = GND GND 1ms or more Figure 77 Rev.1.0 September 13, 2006, page 163 of 199 R61505U NVM Write In Sequence NVM write-in Sequence Power ON reset NVM data write start EAD[2:0] setting EOP[1:0]=2'h1 TE=1 NVM write data setting ED7, ED[4:0]=0/1 NVM data write end EOP[1:0]=2'h0 TE=0 WR DB INDEX ED [7:0] INDEX TE, EOP, EAD [2:0] INDEX TE, EOP RESET* GND Vcc/IOVcc GND ψ open GND VPP/1 (9.0V +/- 0.1V) GND VPP2 (7.5V+/- 0.1V) GND ψ open NVM write in period 1 ms or more each 100~200 ms 2 ms or more Figure 78 NVM Read Out Sequence NVM read out Sequence Power ON reset NVM data read out CALB=1 NVM read out Read Instruction WR RD DB INDEX CALB INDEX RESET* Vcc/IOVcc GND VPP1 (OPEN) VPP2 (OPEN) 1ms or more 2ms or more 8 x 1/ osc Figure 79 Rev.1.0 September 13, 2006, page 164 of 199 read NVM data 1䎃μs or more 1 ms or more R61505U Written data on NVM can be confirmed by reading instruction registers. The write-in area is R28’h to R2A’h. Following table shows example of the reading out. Do not concern about ID7-5 (R29h) and ID6-5 (R2Ah) bits as individual die have different data. Check only the bits marked “user setting”. Table 88 Index ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 To write in user ID 28'h 0 0 0 0 User User User User setting setting setting setting To write in VCOM setting 29'h * * * User User User User User setting setting setting setting setting * User User User User User setting setting setting setting setting To write in VCOM setting 2A'h VCMSEL * Rev.1.0 September 13, 2006, page 165 of 199 R61505U NVM instruction dummy read sequence NVM dummy read RA0 (Invalid data) NVM data read out 1 R28: Read instruction Dummy access is not required NVM data read out 2 R29: Read instruction Dummy access is not required NVM data read out 3 R2A: Read instruction Read data bits in NVM (other than instruction data bits) Rxx: Read instruction Dummy access is required NVM dummy read RA0 (Invalid data) NVM data read out 1 R28: Read instruction Figure 80 Rev.1.0 September 13, 2006, page 166 of 199 R61505U Power supply Instruction Setting The following are the sequences for setting power supply ON/OFF instructions. Set power supply ON/OFF instructions according to the following sequences in Display ON/OFF, Sleep set/exit sequences. Power supply OFF sequence Power ON sequence Power supply (Vcc, Vci, IOVcc) ON Normal display Vci IOVcc Vcc DTE = 1, D=2'h3, GON=1, VON = 1 GND Display OFF sequence Vcc㩷 㸢㩷 IOVcc㩷 㸢 Vci or Vcc, IOVcc, Vci simultaneously When registers are set: Powr supply OFF setting Power ON reset 2ms or more DTE = 0, D=2'h0, GON=0 PON=0, VON=0 Power supply Halt setting 1) Source output: GND 2) Gate output: VCI 3) VCOM =GND R10h: AP = 2'h0, SAP=0 R11h: DC0=3'h6 R12h: PON = 0 1 frame or more Transfer synchronization Power supply Halt setting RS=0, DB=16'h0000 RS=0, DB=16'h0000 RS=0, DB=16'h0000 RS=0, DB=16'h0000 RA4h: CALB=1 Wait 1/fosc x 8 Power supply (Vcc, Vci, IOVcc) OFF User setting (1) Initial instruction setting LCD Power supply ON sequence NL, BP, FP, Gamma setting, others Vci IOVcc Vcc GND Vci㩷 㸢㩷 IOVcc㩷 㸢 Vcc or Vcc, IOVcc, Vci simultaneously R07h: D=2'h1 R17h: PSE=1'h1 Power supply user setting R10h: APE = 1, AP, BT, SAP=1 R11h: VC, DC0, DC1 R12h: VRH, PON=1, VCMR=1(Note 1) R13h: VDV R29h: VCM1 (Note2) R12h: PSON=1'h1 When registers are set: 1) Source output: GND 2) Gate output: VGH (all pins are ON) 3) VCOM =GND Power supply startup time (8 frames x 1/OSC) 1) Source output: GND 2) Gate output: GND 3) VCOM =GND R10h: APE=0 Other mode setting instruction Display ON sequence Note1: Set VCMR=1 when using internal electronic volume. Note2: When EPROM is in use, setting VCM1 and VCM2 (R29 and R2A) is not required. Figure 81 Rev.1.0 September 13, 2006, page 167 of 199 R61505U Notes to Power Supply ON sequence 1. When voltages do not rise in the order of VCC, IOVCC and then VCI, changing the order to IOVCC, VCC and then VCI will not lead to trouble such as latchup or the die go broken. Please read below carefully in operating the R61505U. 2. Notes If there is a time lag between IOVCC and VCC inputs when inputting them in IOVCC-first order, the R61505U’s bus is unstable until VCC is inputted. The die may become “output” status in this case. Do not send or receive data before power supply input is completed. 3. Command input timing Following flow chart shows power supply input to command input. Wait 1ms or more as power on reset and display off period after inputting IOVCC, VCC and VCI. Then wait another 10ms or more until internal operation stabilizes. And then, start inputting commands. (Waiting time: 11ms or more altogether). Input power supply (IOVCC, VCC, VCI) IOVCCψVCCψVCI or VCC, IOVCC, VCI simultanaeously 1ms or more Power ON reset, Display OFF 10ms or more (internal operation stabilizes during this period) Start inputting command Figure 82 (when power supply input sequence is changed) Rev.1.0 September 13, 2006, page 168 of 199 R61505U Instruction setting The following are the sequences for various instruction settings. When setting instruction in the R61505U, follow the relevant sequence below. Display ON/OFF sequences Display OFF sequence Display OFF sequence LCD Power supply ON sequence* see Note R07h: 16'h0072 (BASEE = 0, VON=1, GON=1, DTE=1, D=2'h2 ) Display OFF When registers are set: When registers are set: 15) Source output: non-lit display 16) Gate output:VGH/ VGL 17) VCOM =VCOMH / VCOML 2 frame periods or more Display ON R07h: 16'h0021 (BASEE = 0, VON=0, GON=1, DTE = 0, D=2'h1) 7) Source output: GND 8) Gate output: VGH (all pins are ON) 9) VCOM =GND 8H periods or more Display OFF R07h: 16'h0001 (BASEE = 0, VON=0, GON=0, DTE=0, D=2'h1) 10) Source output: GND 11) Gate output: VGH (all pins are ON) 12) VCOM =GND 8H periods or more Display ON R07h: 16'h0061 (BASEE = 0, VON=1, GON=1, DTE = 0, D=2'h1) 4) Source output: GND 5) Gate output: VGL (all pins are OFF) 6) VCOM =VCOMH / VCOML Display OFF R07h: 16'h0000 (BASEE = 0 , VON=0, GON=0, DTE=0, D=2'h0) 2 frame periods or more Display ON R07h: 16'h0173 (BASEE = 1, VON=1, GON=1, DTE = 1, D=2'h3) 1) Source output: V0-V31 2) Gate output:VGH/ VGL 3) VCOM =VCOMH / VCOML Display ON Display OFF Note: See power supply ON/OFF setting sequences Figure 83 Rev.1.0 September 13, 2006, page 169 of 199 LCD Power supply ON sequence* see Note Internal display operation halts. 13) Source output: GND 14) Gate output: VGH (all pins are ON) 3) VCOM =GND R61505U Sleep mode SET/EXIT sequences Sleep mode sequence Display OFF sequence* see Note Set Sleep mode Sleep SET R10h: SLP=1 Sleep EXIT R10h: SLP=0 Exit Sleep mode 1clock or more Display ON sequence* see Note Figure 84 Rev.1.0 September 13, 2006, page 170 of 199 R61505U Deep standby mode IN/EXIT sequences 18-/ 16-/ 9-/ 8 bit interface Deep standby mode Display off sequence Set deep standby mode Set deep standby mode R10h: DSTB = 1 CS = low (1) CS = low (2) VDD startup oscillator stabilizing period 1 ms or more CS = low (3) Initialize the R61505U Exit deep standby mode input CS = Low 6 times CS = low (4) CS = low (5) CS = low (6) RA4h: CALB = 1 1/fosc x 8 wait Initial instruction setting RAM data setting Notes: 1. See AC characteristics in "Electrical Characteristics" for details on low width (PWLW), high width (PWHW), and cycle (tCYCW) periods. 2. Leave at least 1 ms between the 2nd and 3rd inputs of CS = Low. 3. This sequence must be completed before writing GRAM data. Display on sequence CS 1 WR Wait 1ms or more 3 4 5 6 Any data Any data Any data "High" RD RS 2 "High" "Low" or "High" Data Any data Any data Any data Figure 85 Cancel standby mode by inputting CS=”Low” (18-/ 16-/ 9-/ 8- bit interface) Rev.1.0 September 13, 2006, page 171 of 199 R61505U 18bit/16bit interface Display off sequence Set deep standby mode Set deep standby mode R10h : DSTB=1 Index Write (Data=16'h0000) Index Write (Data=16'h0000) VDD startup oscillator stabilizing period 1ms Exit deep standby mode Initialize the R61505U Index Write (Data=16'h0000) Index Write (Data=16'h0000) Index Write (Data=16'h0000) Index Write (Data=16'h0000) R4Ah: CALB=1 1/fosc x 8 wait Initial instruction setting RAM data setting Notes: 1. See AC characteristics in "Electrical Characteristics" for details on low width (PWLW), high width (PWHW), and cycle (tCYCW) periods. 2. Leave at least 1 ms between the 2nd and 3rd inputs of Index Write. 3. This sequence must be completed before writing GRAM data. Display on sequence 1 CS 2 3 4 5 6 16'h0000 16'h0000 Wait 1ms or more WR RD RS Data "High" "Low" 16'h0000 16'h0000 16'h0000 16'h0000 Figure 86 Cancel deep standby mode by inputting CS=”Low” and WR=”Low” (18-/ 16 bit interface) Rev.1.0 September 13, 2006, page 172 of 199 R61505U 9- /8- bit interface Display off sequence Set deep standby mode Set deep standby mode R10h : DSTB=1 Index Write (Data=8'h00) Index Write (Data=8'h00) VDD startup oscillator stabilizing period 1ms Exit deep standby mode Initialize the R61505U Index Write (Data=8'h00) Index Write (Data=8'h00) Index Write (Data=8'h00) Index Write (Data=8'hF0) Index Write (Data=8'h00) Index Write (Data=8'h00) Transfer synchronization command Note 4 Index Write (Data=8'h00) Index Write (Data=8'h00) R4Ah: CALB=1 1/fosc x 8 wait Initial instruction setting RAM data setting Notes: 1. See AC characteristics in "Electrical Characteristics" for details on low width (PWLW), high width (PWHW), and cycle (tCYCW) periods. 2. Leave at least 1 ms between the 2nd and 3rd inputs of Index Write. 3. This sequence must be completed before writing GRAM data. 4. Transfer synchronization command is 8'h00 when 8 bit interface is used and 9'h000 when 9 bit interface is used. Display on sequence 1 CS 2 3 4 5 6 2 1 3 4 Wait 1ms or more WR RD "High" "Low" RS Data IW upper IW lower 00h 00h IW upper IW lower IW upper IW lower 00h 00h 00h F0h IW upper IW lower IW upper IW lower 00h 00h 00h 00h transfer synchronization Execute transfer synchronization command after canceling deep standby mode by inputting RS=Low and Index write. Figure 87 Cancel deep standby mode by inputting CS=”Low” and WR=”Low” (9-/ 8- bit interface) Rev.1.0 September 13, 2006, page 173 of 199 R61505U 8-color mode setting 262,144 color to 8 color mode 8 color to 262,144 color mode 262,144-color mode display 8-color mode display R07h: COL= 1'h1 R07h: COL= 1'h0 8-color mode display 262,144-color mode display Figure 88 Partial display setting Partial display setting sequence Full-screen display Partial display setting R80h: PTDP0 R81h: PTSA0 R82h: PTEA0 R83h: PTDP1 R84h: PTSA1 R85h: PTEA1 Base image display OFF Partial display ON R07h: BASEE=0, PTDEx=1 8-color display, low power consumption settings R07h: COL=1, R09h: PTS Partial display Base image display ON Partial display OFF R07h: BASEE=1, PTDEx=0 Full-screen display Figure 89 Rev.1.0 September 13, 2006, page 174 of 199 Set as required R61505U Absolute Maximum Ratings Table 89 Item Symbol Unit Value Note Power Supply Voltage1 VCC, IOVCC V -0.3 ~ +4.6 1, 2 Power Supply Voltage 2 VCI – AGND V -0.3 ~ +4.6 1, 3 Power Supply Voltage 3 DDVDH – AGND V -0.3 ~ +6.5 1, 4 Power Supply Voltage4 AGND – VCL V -0.3 ~ +4.6 1 Power Supply Voltage 5 DDVDH – VCL V -0.3 ~ +9.0 1, 5 Power Supply Voltage7 AGND – VGL V -0.3 ~ +13.0 1, 6 Power Supply Voltage 8 VGH– VGL V -0.3 ~ +30.0 1 Power Supply Voltage 9 VPP1 V -0.3 ~ +10.0 1 Power Supply Voltage 10 VPP2 V -0.3 ~ +10.0 1 Power Supply Voltage 11 VPP3 V 0 1 Input Voltage Vt V -0.3 ~ IOVCC + 0.3 1 Operating Temperature Topr ℃ -40 ~ +85 1, 7 NVM Write Temperature Twep ℃ +25 ~ +35 1 Storage Temperature Tstg ℃ -55 ~ +110 1 Notes 1.If the R61505U is used beyond the absolute maximum ratings, the LSI may be permanently damaged. It is strongly recommended to use the LSI under the condition within the electrical characteristics in normal operation. If exposed to the condition not within the electrical characteristics, it may affect the reliability of the device. 2. Make sure VCC(high)≥GND(low), IOVCC(high)≥IOGND(low) . 3. Make sure VCI(high)≥AGND(low) . 4. Make sure DDVDH(high)≥AGND(low). 5. Make sure DDVDH(high) ≥VCL(low). 6. Make sure AGND(high)≥VGL(low). 7. The DC/AC characteristics of die and wafer products are guaranteed at 85℃. Rev.1.0 September 13, 2006, page 175 of 199 R61505U Electrical Characteristics DC characteristics (VCC= 2.50V~3.30V,IOVCC=1.65V~3.30V,Ta=-40C~+85C See note 1) Table 90 Item Symbol Unit Test Condition Min. Typ. Max. Note - IOVCC 2,3 Input ”High” level voltage VIH V IOVCC=1.65V~3.30V 0.80× IOVCC Input ”Low” level voltage VIL V IOVCC=1.65V~3.30V -0.3 - 0.20× IOVCC VOH V IOVCC=1.65V~3.30V, IOH=-0.1mA 0.8× IOVCC - - 2 VOL V IOVCC=1.65V~3.30V, IOL=0.1mA - - 0.20× IOVCC 2 ILI µA Vin=0~IOVCC -1 - 1 4 - 175 (376KHz) 295 µA fosc=376/600kHz (320 line drive), IOVCC=VCC=3.00V, fFLM=70Hz, Ta=25C, RAM data: 18’h000000, See below for other data 190 (600Khz) 310 (600KHz) Iop2 µA fosc=376/600kHz (64 line partial display), IOVCC=VCC=3.00V, fFLM=40Hz, Ta=25C, RAM data: 18h’000000, See below for other data - 140 - 5, 6 IDST µA IOVCC=VCC=3.00V, Ta=25C - 0.1 1.0 5 mA IOVCC=2.40V, VCC=3.00V, tCYCW=125ns, Ta=25C, I80-8bit-I/F, TRIREG=1’h1, Consecutive RAM access during display operation, VCM1=5’h1D, AP=2’h3, BC0=0, FP=5, BP=8, γ register; 0(default), COL=0 (8-color mode) - 2.0 - 6 Output ”High” level voltage 1 (DB0-17, FMARK) Output ”Low” level voltage 1 (DB0-17, FMARK) Input / Output leagage current Current Consumption ((IOVCCIOGND) + (VCC-GND)) Normal operation mode (260kcolor, display operation) Current Consumption ((IOVCCIOGND) + (VCC-GND)) 8-color mode, 64-line partial display operation Current Consumption ((IOVCCIOGND) + (VCC-GND)) IOP1 Deep Standby mode Current Consumption ((IOVCCIOGND) + (VCC-GND)) RAM access mode 1 (Normal write operation, HWM=0) IRAM1 Rev.1.0 September 13, 2006, page 176 of 199 (376KHz) 2,3 5, 6 R61505U Current Consumption ((IOVCCIOGND) + (VCC-GND)) RAM access mode 2, High-speed write function (HWM=1) IRAM2 mA IOVCC=2.40V, VCC=3.00V, tCYCW=70ns, Ta=25C, I80-8bit-I/F, TRIREG=1’h1, Consecutive RAM access during display operation, VCM1=5’h1D, AP=2’h3, BC0=0, FP=5, BP=8, γ register; 0(default), COL=0 (8-color mode) - 1.7 - 1.4 3.0 (376KHz) (376KHz) 1.9 (600KHz) 3.5 (600KHz) 6 IOVCC=VCC=3.00V, VCI=3.00V, LCD Power Supply Current (VCIGND) Ici1 mA 260-k color display operation fosc=376/600kHz (320 line), fFLM=70Hz, Ta=25C, RAM data: 18’h00000, REV=”0”, BC0=0, FP=5, BP=8, VxRPx=”0”, VxRNx=”0”, PxKPx=”0”, PxKNx=”0”, PxRPx=”0”, PxRNx=”0”, PxFPx=”0”, PxFNx=”0”, BT=4’h6, VC=3’h7, AP=2’h3, DC0=3’h1, DC1=3’h2, VRH=4’hA, VCM1=5’h1D, VDV=5’h8, VCMR=1’h1, COL=1’h0, GON=1, No load on the panel. - Ici2 mA IOVCC=VCC= 3.00V, VCI=3.00V, fosc=376/600kHz (64 line partial), fFLM=40Hz, Ta=25C, RAM data: 18’h00000, REV=”0”, BC0=0, FP=5, BP=8, VxRPx=”0”, VxRNx=”0”, PxKPx=”0”, PxKNx=”0”, PxRPx=”0”, PxRNx=”0”, PxFPx=”0”, PxFNx=”0”, BT=4’h6, VC=3’h7, AP=2’h3, DC0=3’h1, DC1=3’h2, VRH=4’hA, VCM1=5’h1D, VDV=5’h8, VCMR=1’h1, COL=1’h1, GON=1, No load on the panel. Output voltage dispersion ΔVO mV - - Average output voltage variance ΔVΔ mV - -35 LCD Power Supply Current (VCIGND) 8-color (64-line partial) display operation Rev.1.0 September 13, 2006, page 177 of 199 5, 6 0.5 - - 5, 6 5 - 7 - 35 8 (376KHz) 0.8 (600KHz) R61505U Step-Up Circuit Characteristics Table 91 Item Unit Step-up Output Voltage Test Condition Min. Typ. Max. Note 4.57 4.84 - - 13.72 14.40 - - -6.86 -7.13 - - -2.25 -2.30 - - 2.5 - 3.3 - IOVCC=VCC=3.00[V],VCI=VCI1=2.5[V], fosc=376/600[kHz],Ta=25C, VC=3’h7, AP=2’h3, BT=3’h7, DC0=3’h4(div. 1/16), DC1=3’h4 (div. 1/ 256), COL=0, VLOUT1 V D=2’h0, VON=0, DIVI=2’h0, RTNI=5’h10, FP=4’h8, BP=4’h8, C11=C12=C13=C21=C22=C23=1[uF]/B Characteristics, VLOUT1=VLOUT2=VLOUT3=VCL=1[uF]/B Characteristics, No load on the panel, Iload1= -3 [mA] IOVCC=VCC=3.00[V],VCI=VCI1=2.5[V], fosc=376/600[kHz],Ta=25C, VC=3’h7, AP=2’h3, BT=3’h7, IOVCC=VCC=3.00[V],VCI=VCI1=2.5[V], fosc=376/600[kHz], Ta=25C, VC=3’h7, AP=2’h3, BT=3’h7, DC0=3’h4 (div. 1/16), VLOUT2 V DC1=3’h4 (div. 1/256), COL=0, D=2’h0, VON=0, DIVI=2’h0, RTNI=5’h10, FP=4’h8, BP=4’h8, C11=C12=C13=C21=C22=C23=1[uF]/B Characteristics, VLOUT1=VLOUT2=VLOUT3=VCL=1[uF]/B Characteristics, Iload2=-100[uA], No load on the panel. IOVCC=VCC=3.00[V],VCI=VCI1=2.5[V], fosc=376/600[kHz], Ta=25C, VC=3’h7, AP=2’h3, BT=3’h7, DC0=3’h4 (div. 1/ 16), DC1=3’h4 (div. 1/ 256), COL=0, D=2’h0, VON=0, VLOUT3 V DIVI=2’h0, RTNI=5’h10, FP=4’h8, BP=4’h8, C11=C12=C13=C21=C22=C23=1[uF]/B Characteristics, VLOUT1=VLOUT2=VLOUT3=VCL=1[uF]/B Characteristics, Iload3=+100[uA], No load on the panel. IOVCC=VCC=3.00[V], VCI=VCI1=2.5[V], fosc=376/600[kHz], Ta=25C, VC=3’h7, AP=2’h3, BT=3’h7, DC0=3’h4 (div. 1/16), DC1=3’h4 (div. 1/ 256), COL=0, VCL V D=2’h0, VON=0, DIVI=2’h0, RTNI=5’h10, FP=4’h8, BP=4’h8, C11=C12=C13=C21=C22=C23=1[uF]/B Characteristics, VLOUT1=VLOUT2=VLOUT3=VCL=1[uF]/B Characteristics, Iload4=+200[uA], No load on the panel. Input Voltage VCI V Internal Reference Voltage (Condition: VCC= 2.50V~3.30V, Ta=-40℃~+85℃) Table 92 Item Internal Reference Voltage Symbol VCIR Rev.1.0 September 13, 2006, page 178 of 199 Unit Min. Typ. Max. Note V 2.45 2.50 2.55 12 R61505U AC Characteristics (VCC= 2.50V~3.30V,IOVCC=1.65V~3.30V,Ta=-40C~+85C See Note 1) 1. Clock Characteristics Table 93 Item Symb ol Unit Test Condition Min. Typ. Max. Note RC oscillation clock (R61505U0) fosc kHz IOVCC=VCC=3.0V 25℃ 349 376 402 9 RC oscillation clock (R61505U1) fosc kHz IOVCC=VCC=3.0V 25℃ 558 600 642 9 2. 80-System Bus Interface Timing Characteristics (18-/ 16- bit interface) Table 94 Normal write operation (HWM=0), IOVCC=1.65V~3.30V Symbol Unit Timing Diagram Min. Typ. Max. Write tCYCW ns Figure 98 125 - - Read tCYCR ns Figure 98 450 - - Write low-level pulse width PWLW ns Figure 98 45 - - Read low-level pulse width PWLR ns Figure 98 170 - - Write high-level pulse width PWHW ns Figure 98 70 - - Read high-level pulse width PWHR ns Figure 98 250 - - ns Figure 98 - - 25 ns Figure 98 0 - - ns Figure 98 10 - - ns Figure 98 2 - - Item Bus cycle time Write / Read rise/ fall time tWRr, WRf Setup time Write (RS to CS*, WR*) tAS Read (RS to CS*,RD*) Address hold time tAH Write data setup time tDSW ns Figure 98 25 - - Write data hold time tH ns Figure 98 10 - - Read data delay time tDDR ns Figure 98 - - 150 Read data hold time tDHR ns Figure 98 5 - - Rev.1.0 September 13, 2006, page 179 of 199 R61505U Table 95 High-speed write Function (HWM=1), IOVCC=1.65~3.30V Symbol Unit Timing Diagram Min. Typ. Max. Write tCYCW ns Figure 98 75 - - Read Item Bus cycle time tCYCR ns Figure 98 450 - - Write low-level pulse width PWLW ns Figure 98 40 - - Read low-level pulse width PWLR ns Figure 98 170 - - Write high-level pulse width PWHW ns Figure 98 25 - - Read high-level pulse width PWHR ns Figure 98 250 - - ns Figure 98 - - 25 ns Figure 98 0 - - ns Figure 98 10 - - Write / Read rise/ fall time Setup time Write (RS to CS*, WR*) tWRr, WRf tAS Read (RS to CS*,RD*) Address hold time tAH ns Figure 98 2 - - Write data setup time tDSW ns Figure 98 25 - - Write data hold time tH ns Figure 98 10 - - Read data delay time tDDR ns Figure 98 - - 150 Read data hold time tDHR ns Figure 98 5 - - Rev.1.0 September 13, 2006, page 180 of 199 R61505U 3. 80-System Bus Interface Timing Characteristics (9-/ 8- bit interface) Table 96 Normal Write Function (HWM=0)/ High-speed Write Function (HWM=1), IOVCC=1.65~3.30V) Symbol Unit Timing Diagram Min. Typ. Max. Write tCYCW ns Figure 98 70 - - Read Item Bus cycle time tCYCR ns Figure 98 450 - - Write low-level pulse width PWLW ns Figure 98 30 - - Read low-level pulse width PWLR ns Figure 98 170 - - Write high-level pulse width PWHW ns Figure 98 25 - - Read high-level pulse width PWHR ns Figure 98 250 - - ns Figure 98 - - 25 ns Figure 98 0 - - ns Figure 98 10 - - Write / Read rise/ fall time Setup time Write (RS to CS*, WR*) tWRr, WRf tAS Read (RS to CS*,RD*) Address hold time tAH ns Figure 98 2 - - Write data setup time tDSW ns Figure 98 25 - - Write data hold time tH ns Figure 98 10 - - Read data delay time tDDR ns Figure 98 - - 150 Read data hold time tDHR ns Figure 98 5 - - Rev.1.0 September 13, 2006, page 181 of 199 R61505U 4. Clock-synchronized Serial Interface Timing Characteristics Table 97 Normal Write Function (HWM=0), High-speed Write Function (HWM=1), IOVCC=1.65~3.30V) Symbol Unit Timign Diagram Min. Typ. Max. Write (receive) tSCYC ns Figure 99 100 - 20,000 Read (transmitted) tSCYC ns Figure 99 350 - 20,000 Write (receive) tSCH ns Figure 99 40 - - Read (transmitted) tSCH ns Figure 99 150 - - Write (receive) tSCL ns Figure 99 40 - - Read (transmitted) tSCL ns Figure 99 150 - - tSCr,tSCf ns Figure 99 - - 20 Chip select setup time tCSU ns Figure 99 20 - - Chip select hold time tCH ns Figure 99 60 - - Serial input data setup time tSISU ns Figure 99 30 - - Serial input data hold time tSIH ns Figure 99 30 - - Serial output data delay time tSOD ns Figure 99 - - 130 Serial output data hold time tSOH ns Figure 99 5 - - Item Serial clock cycle time Serial clock highlevel width Serial clock lowlevel width Serial clock rise/fall time 5. Reset Timing Characteristics (IOVCC=1.65~3.30V) Table 98 Item Symbol Unit Timign Diagram Min. Typ. Max. Reset low-level width tRES ms Figure 100 1 - - Reset rise time trRES µs Figure 100 - - 10 Rev.1.0 September 13, 2006, page 182 of 199 R61505U 6. RGB Interface Timing Characteristics Table 99 18-/ 16- bit RGB interface (HWM=1), IOVCC=1.65~3.30V Item Symbol Unit Timign Diagram Min. Typ. Max. VSYNC/HSYNC setup time tSYNCS clock Figure 101 0 - 1 ENABLE setup time tENS ns Figure 101 10 - - ENABLE hold time tENH ns Figure 101 20 - - DOTCLK low-level pulse width PWDL ns Figure 101 40 - - DOTCLK high-level pulse width PWDH ns Figure 101 40 - - DOTCLK cycle time tCYCD ns Figure 101 100 - - Data setup time tPDS ns Figure 101 10 - - Data hold time tPDH ns Figure 101 40 - - DOTCLK, VSYNC and HSYNC rise/fall time trgbr, trgbf ns Figure 101 - - 25 Table 100 6-bit RGB interface (HWM=1), IOVCC=1.65~3.30V Item Symbol Unit Timign Diagram Min. Typ. Max. VSYNC/HSYNC setup time tSYNCS clock Figure 101 0 - 1 ENABLE setup time tENS ns Figure 101 10 - - ENABLE hold time tENH ns Figure 101 25 - - DOTCLK low-level pulse width PWDL ns Figure 101 25 - - DOTCLK high-level pulse width PWDH ns Figure 101 25 - - DOTCLK cycle time tCYCD ns Figure 101 60 - - Data setup time tPDS ns Figure 101 10 - - Data hold time tPDH ns Figure 101 25 - - DOTCLK, VSYNC and HSYNC rise/fall time trgbr, trgbf ns Figure 101 - - 25 Rev.1.0 September 13, 2006, page 183 of 199 R61505U 7. LCD driver Output Characteristics Table 101 Item Symbol Unit Timing Diagram Min. Typ. Max. Note - - 17 10 - - 17 11 VCC=IOVCC=3.00V, DDVDH=5.50V, VREG1OUT=5.00V, fosc=376/600kHz (320-line drive), Ta=25C, REV=0, AP=2’h3, VRH=4’h0, PxKPx=3’h0, PxKNx=3’h0, Source driver output delay time PxRNx=3’h0, PxRPx=3’h0, tdds µs VxRNx=5’h0, VxRPx=5’h0, PxFPx=2’h0, PxFNx=2’h0 Same change from same grayscale at all time-division source output pins. Time to reach +/- 35mV from VCOM polarity inversion timing.. R=10kohm, C=20pF VCC=IOVCC=3.00V, DDVDH=5.50V, VREG1OUT=5.00V, fosc=376/600kHz (320 line drive), Ta=25C, REV=0, AP=2’h3, VRH=4’h0, VCOM output delay time PxKPx=3’h0, PxKNx=3’h0, tddv µs PxRNx=3’h0, PxRPx=3’h0, VxRNx=5’h0, VxRPx=5’h0, PxFPx=2’h0, PxFNx=2’h0 Time to reach +/- 35mV when voltage on V0-V31 pins changes. R=100ohm, C=10nF Rev.1.0 September 13, 2006, page 184 of 199 R61505U Notes on Electrical Characteristics 1. DC/AC electrical characteristics of bare die and wafer products are guaranteed at +85℃. 2. The followings illustrate the configurations of input, I/O, and output pins. Pins: FMARK, SDO Pins: RESET* IM3-1 IM0/ID VSYNC HSYNC DOTCLK ENABLE CS, RS, SDI IOVCC IOVCC PMOS PMOS Input circuit Input data NMOS NMOS IOGND IOGND Pins: WR/SCL RD IOVCC PMOS PMOS Input enable (CS) Input circuit NMOS NMOS IOGND Pins: DB17 – DB0 IOVCC PMOS PMOS Input enable(CS) Input circuit NMOS NMOS IOGND Output circle; Three states IOVCC Output enable PMOS Output data NMOS IOGND Figure 90 Rev.1.0 September 13, 2006, page 185 of 199 R61505U 3. Fix pins as follows; TEST1/2/5 pins to IOGND, TEST3/4 pins to IOVCC, VDDTEST and VREFC to ground (AGND), and IM0/ID pins to IOVCC or IOGND. 4. This excludes the current in the output-drive MOS. 5. This excludes the current in the input/output units. Make sure that the input level is fixed because through current will increase in the input circuit when the CMOS input level takes a middle range level. The current consumption is unaffected by whether the CS* pin is “high” or “low” while not accessing via interface pins. 6. The relation between voltage and current consumption is as follows. Rev.1.0 September 13, 2006, page 186 of 199 R61505U Current consumption in normal display operation (262k-color display mode) 262k color-mode 320 line Ta=25͠, fosc=376/600 kHz, fHLM=70Hz, RAM data=18'h00000 COL=0 fosc=600KHz 200 Typ. Iop1 uA fosc=376KHz 150 100 2.5 3.0 3.5 IOVCC/VCC V Current Consumption in normal display operation (8-color-mode, 64 line partial display) 320 line Ta=25͠, fosc=376/600kHz, RAM data =18'h00000 COL=1, 8-color-mode, 64 line partial display 200 Iop2 uA 8color-mode 64line partial display 150 Typ. 100 2.5 3.0 3.5 IOVCC/VCC V Dynamic current consumption (RAM write during display RAM access) 8.0 IRAM1, IRAM2 mA IOVCC=2.4V, VCC=3.0V Ta=25͠, fosc=376/600kHz IRAM1 18/16bitI/F HWM=0 5.0 8bitI/F HWM=0 Typ. Typ. 18/16bitI/F HWM=1 Typ. 8bitI/F HWM=1 IRAM2 Typ. 0.0 5.0 10.0 15.0 Write cycle fequency[MHz] Figure 91 Rev.1.0 September 13, 2006, page 187 of 199 R61505U Liquid crystal power supply current consumption in 262k-color-mode (Ici1) 262k color mode 2.0 Ici1 mA IOVCC=VCC=3V, 320line, Ta=25C, fosc=376/600kHz, fFLM=70Hz, RAM data=18'00000, BC0=1'h0, REV=1'h0, COL=2'h0, AP=3'h3, BT=4'h5, DC0=3'h1, DC1=3'h2, VCMR=1'h1, VC=3'h7, VRH=4'hA, VCM=5'h1D, VDV=5'h8, GON=1 fosc=600KHz 1.5 PxKPx=3'h0, PxKNx=3'h0, PxRNx=3'h0, PxRPx=3'h0, VxRNx=3'h0, VxRPx=3'h0, PxFNx=2'h0, PxFPx=2'h0, No load on the panel. fosc=376KHz Typ. 1.0 2.5 3.0 3.5 VCI V Liiquid crystal power supply current consumption (Ici2) in 8-color, 64-line partial, display IOVCC=VCC=3V, 320line, Ta=25C, fosc=376/600kHz, fFLM=40Hz, RAM data=18'00000, BC0=1'h0, REV=1'h0, COL=2'h1, AP=3'h3, BT=4'h5, DC0=3'h1, DC1=3'h2, VCMR=1'h1, VC=3'h7, VRH=4'hA, VCM=5'h1D, VDV=5'h8, GON=1 fosc=600KHz Ici2 mA 0.7 0.5 Typ. fosc=376KHz 8 color mode 64line partial display 0.3 2.5 3.0 PxKPx=3'h0, PxKNx=3'h0, PxRNx=3'h0, PxRPx=3'h0, VxRNx=3'h0, VxRPx=3'h0, PxFNx=2'h0, PxFPx=2'h0, No load on the panel. 3.5 VCI V Figure 92 Rev.1.0 September 13, 2006, page 188 of 199 R61505U 7. The output voltage deviation is the difference in the voltages between output pins that are placed side by side in same display mode. The output voltage deviation is reference value. 8 The average output voltage dispersion is the variance of average source-output voltage of different chips of the same product. The average source output voltage is measured for one chip with same display data. 9 This applies to internal oscillators when using an internal RC oscillator. 10 The liquid crystal driver output delay time depends on the load on the liquid crystal panel. Adjust the frame frequency and the cycle per line by checking the quality on the actual panel in use. LCD driver output delay time tDD (μs) Reference data VCC=IOVCC=3.00V, DDVDH=5.50V, VREG1OUT=5.00V, fosc=376/600kHz (320 line drive) Ta=25͠, REV=0, AP=2'h3, VRH=4'h0, PxKPx=3'h0, PxKNx=3'h0, PxRNx=3'h0, PxRPx=3'h0, VxRNx=3'h0, VxRPx=3'h0, PxFNx=3'h0, PxFPx=3'h0, 28 24 20 16 Same change from the same grayscale at all time-division source output pins. 12 Typ. 8 Time to reach the target voltage r5mV from Vcom polarity inversion timing. 4 R=10kΩ, C=20pF 15 25 35 Load capacitance C (pF) Figure 93 Rev.1.0 September 13, 2006, page 189 of 199 R61505U 11 VCOM output delay time depends on the load on the liquid crystal panel. Adjust the frame frequency and the cycle per line checking the quality on the actual panel in use. Vcom output delay time: tDDv (μs) Reference data VCC=IOVCC=3.00V, DDVH=5.50V, VREG1OUT=5.00V, fosc=376/600kHz(320 line drive) Ta=25͠, REV=0, AP=2'h3, VRH=4'h0, PxKPx=3'h0, PxKNx=3'h0, PxRNx=3'h0, PxRPx=3'h0, VxRNx=5'h0, VxRPx=5'h0, PxFPx=2'h0, PxFNx=2'h0, Time to reach r35mV when voltage on Vo=V31 pin changes. R=100Ω, C=10nF 40 35 30 25 Typ. 20 15 10 10 30 50 Load capacitance C(nF) Figure 94 12 Internal reference voltage VCIR depends on temperature as shown in following graph. Internal reference voltage VCIR (V) Reference Voltage 2.60 VCC=IOVCC=VCI=3.00V AP=2'h3 2.55 Typ. 2.50 2.45 2.40 -50 -30 -10 10 30 50 70 Temperature (C) Figure 95 Rev.1.0 September 13, 2006, page 190 of 199 90 R61505U Test Circuits ٨ ٨ Test circuit for AC characteristics Test circuit for LCD output characteristics [LCD output: S1-S720] Load resistance R: 10kΩ Test Point [Data bus: DB17-DB0] Test Point Load capacitance C:20pF 50pF Figure 96 Test circuit for Vcom output characteristics [Vcom output] Load Resictance R: 100Ω Test Point Load Capacitance C 10nF Figure 97 Rev.1.0 September 13, 2006, page 191 of 199 R61505U Test Characteristics 80-System Bus Interface RS VIH VIH VIL VIL tAS tAH VIH VIL CS* VIH VIL See Note 1) PWLW,PWLR RD* RD VIH VIH WR* PWHW,PWHR VIH VIL VIL tWRf tWRr tCYCW, tCYCR tDSW See Note 2) DB17-0 VIH VIL Write data tH VIH VIL tDDR tDHR See Note 2) VOH DB17-0 VOL Read data VOH VOL Note 1) PWLW and PWLR are defined by the overlap period when CS* is "Low" and WR* or RD* is "Low". Note 2) Unused DB pins must be fixed at "IOVcc 1" or "IOGND 1". Figure 98 80-System Bus Interface Rev.1.0 September 13, 2006, page 192 of 199 R61505U Clock Synchronous Serial Interface End: P Start: S VIH CS* VIL tSCYC tscr tCSU tSCH VIH SCL tscf VIH VIL VIH VIL VIL tSISH VIH SDI tCH VIH VIL tSISU tSCL VIH Input data VIL Input data VIL tSOD tSOH VOH VOH Output data SDO Output data VOL VOL Figure 99 Clock Synchronous Serial Interface Reset Operation trRES tRES RESET* VIH VIL VIL Figure 100 Reset Operation Rev.1.0 September 13, 2006, page 193 of 199 R61505U RGB Interface trgbf trgbr tSYNCS VSYNC VIH VIH HSYNC VIL VIL tENS ENABLE tENH VIH VIH VIL VIL trgbr trgbf PWDL DOTCLK PWDH VIH VIH VIL VIH VIL VIL tCYCD tPDS tPDH VIH DB17-0 VIL VIH Write data Figure 101 RGB Interface LCD Driver Output tDDv Target Voltage r35mV VCOM Target Voltage r35mV tDDs Target Voltage r35mV S1-720 Target Voltage r35mV Figure 102 LCD Driver Outputs Rev.1.0 September 13, 2006, page 194 of 199 VIL R61505U Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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Renesas Technology Corporation, All rights reserved. Printed in Japan. Colophon 0.0 Rev.1.0 September 13, 2006, page 195 of 199 R61505U Revision Record Rev. Date Contents of Modification 0.04 2005.01.26 First issue 0.1.0 2006.02.20 Change PAD Arrangement, add Instruction List. 0.10 2006.04. 03 p.44 NW bit added (R02h) p. 53 PTG[1:0] 2’h1 changed to setting inhibited. p.59 VCL added to note 2 and 3. p.61 Setting of VREG1OUT added to Table 40. p.62 Description of VREG1 bit added. p.63 “5.5V or less” changed to “6.0V or less”. (Note1 to Table 42) p.76 Table 51 6’h15 of NL[5:0] bits changed to 176 lines. p.81 VEQWI[1:0] bit added. p.85 EAD[1:0] bits added. p.86 Description of RA4h added. p.143 Description of line inversion AC drive added. p.149 (TBD)kHz changed to 376kHz. p.155 Table to Internal Oscillator deleted. p.161 Figure 78 added. p.163 “RF9h” deleted from Figure 80. p.166 “RF9h” deleted from Figure 83. pp.168-187 added. 0.11 2006. 05. 12 p.169, pp.172-177 Target speculation value filled in (except Step-up circuit output characteristics) 0.12 2006.05.31 p.7 Change VCOM adjustment bits (11 bits → 5 bits x 2 sets). p.8 Add VPP and delete note. p.15 Change the description of OSC1 and OSC2. p.17 Change the description of capacitor connection pins (C23±). p.18 3.0V →4.0V (VREG1OUT) p.50 Change the table about VON. p.59 Add C13± (4’h1, 4’h4, 4’h6, 4’h9, 4’hC, and 4’hE) ,and delete C23± (4’h0 and 4’h8). p.62 VCM bits → VCM1 and VCM2 bits p.88 Delete Status Read. p.89 Change the initial state of VLOUT1 and VLOUT2, add VCI1, and delete the initial state of C21+, C22+, and C23 p.157 2.5V → 4.0V (VREG1OUT), (DDVDH – Rev.1.0 September 13, 2006, page 196 of 199 Drawn by Approved by R61505U Rev. Date Contents of Modification VREG1OUT) > 0.5V → (DDVDH – VREG1OUT) ≥ 0.5V p.161 Change VPP1 and VPP2, and the description of dummy data read and write data setting. p.164 Add notes. p.169 Delete Power Supply Voltage 6, and add Power Supply Voltage 8 to 11, and NVM write temperature. p.173 Change timing diagram of clock characteristics. p.175 80ns → 70ns (tCYCW), 50ns → 38ns (PWLW) p.178 Delete Typ., and add Max (tdds and tddv). 0.13 2006.06.01 p.9 Delete C23± from R61505U’s capacitor connection pins. p.16 Change note 2, VPP2 value, “When not in use” of VPP1, VPP2, and VPP3. 0.14 2006.06.02 p.9 Add VCL in R61505’s capacitor connection pins, and change the description of R61505U’s capacitor connection pins. p.18 Add “(VCILVL or VCIR)” in VREG1OUT. p.60 Change capacitor connection pins and VGL (max.), and add note 4. 0.15 2006.07.18 p.7 Gate drive power supply: VGH-GND=10.0V~15.0V → VGH-GND=10.0V~20.0V, VGL-GND= -4.5V ~ -12.5V → VGL-GND= -4.5V ~ -13.5V p.8 Add “Internal reference voltage: to generate VREG1OUT (VCIR)”. p.9 Table 1: NVM_FUSE → NVM, VGH 10.0V~15.0V → 10.0V ~ 20.0V VGL –4.5V~ -12.5V → -4.5V ~ -13.5V p.14 Change description to oscillator (8). VDH → DDVDH (liquid crystal drive circuit power supply circuit, 9) p.17 Open → Open or GND (VPP3: “When not in use” and NVM read) p.18 Add “Make sure to connect to stabilizing capacitor” to VCIOUT, VLOUT1, VLOUT2, VLOUT3 and VCL. p.19 Delete VDH from description of VREG1OUT. Add “Make sure to connect to stabilizing capacitor.” to VCOMH and VCOML. p.21 TEST5 Delete “ To stop the NVM operation, set the TEST5 pin to IOVCC level. p.61 VGH =15.0V (max.) → 20.0V (max) VGL = -12.5V (max) → -13.5V(max) p. 65 Error correction. (Description to VDV and Table 43) p.115 FPP + BPP = 16 → FPP + BPP ≤ 16 p.159 Figure 74: VGH 10.0V~15.0V → 10.0V ~ 20.0V, Rev.1.0 September 13, 2006, page 197 of 199 Drawn by Approved by R61505U Rev. Date Contents of Modification VGL –4.5V~ -12.5V → -4.5V ~ -13.5V p.162 29’h → 2A’h p.165 Figure 79: Error correction (Dummy access required → Dummy access is not required.) p.166 Figure 80: Add CALB=1. p.167 Figure 81: Error correction. p.171 Table 88: -0.3 ~ +13.0 → -0.3 → 14.0 (Power supply voltage 7) p.172 Table 89: Delete “”(Other than OSC1 pin)” (Input High level voltage, Input Low level voltage). VOH1 → VOH, VOL1 → VOL. p. 175 Change AC characteristics (Table 93: tcycw 150ns → 125ns, PWLW 50ns → 45ns. p.176 Change AC characteristics (Table 94: tcycw 80ns → 75ns, PWLW 50ns → 40ns). p.177 Change AC characteristics (Table 95: PWLW 38ns → 30ns). p.181 Figure 86: Delete “DB17-0 (RGB interface (RM=1)) and “(80-system interface (RM=0))” p.187 Figure 91: “Data bus DB15-DB0” → “Data bus DB17-DB0” p.188 Figure 93: tWRr → tWRf, VIH → VOH, VIL → VOL. p.189 Figure 94: VOH1, VOL1 → VOH, VOL p.190 Figure 97: S1-240 → S1-720 0.1.6 2006.07.26 p.11 Figure 1: Change direction of arrow (VREG1OUT). p. 21 AGND → IOGND (TSC) p.44 Delete row of “W” (R00h) p.50 Table 20: Source Output (S1-240) → Source Output (S1-720). p.51 Table 23: VCOML → GND p.57 9’h175 → 9’h15A, 9’h176 → 9’h15B, 9’h177 → 9’h1FF, 373rd line → 346 line, 374th line → 347th line, 375th line → Setting disabled. p.91 Delete “Oscillator: Oscillate”. p.142 Table 82: Delete row of “Write mask function”. p.149 Figure 65: 8’h000, 8’h013 → 9’h000, 9’h013 (Partial image 1 display RAM area), PTDP0=8’h028 → PTDP0=9’h028. p.152 Description changed. p.159 Figure 74: Delete voltage ranges. p. 170 Figure 84: R07h: COL=2’h1 → COL=1’h1, COL=2’h0 → COL=1’h0 Rev.1.0 September 13, 2006, page 198 of 199 Drawn by Approved by R61505U Rev. Date Contents of Modification p. 172 Table 89: AP=3’h3 → AP=2’h3 (Current consumption, RAM access mode 1) p.173 AP=3’h3 → AP=2’h3 (Current consumption, RAM access mode 2). AP=3’h3 → AP=2’h3, COL=2’h0 → COL=1’h0 (LCD Power Supply Current, 262-k color display operation). AP=3’h3 → AP=2’h3, COL=2’h1 → COL=1’h1 (LCD Power Supply Current, 8 color display operation). p.181 Figure 86: Change wiring. p.185 Figure 89: AP=3’h1 → AP=2’h3 p.186 Figure 90: AP=3’h1 → AP=2’h3 p.187 Figure 90: Load capacitance C25pF → 20pF 1.0 2006.09.13. p.8 Add product numbers. p.17 Delete Note 1 to VPP. p. 18 Error correction (VLOUT2= max, 15.0 → 20.0V, VLOUT3=min. -12.5 → -13.5V) p.50 Revise description of COL. p. 53 Table 26 Error correction. p. 57 Table 33 Error correction (FMP). p. 83 Delete VEQWI (R93h). p. 84 Error correction (Instruction List, R95h). p. 88 Change description of CALB. p. 90 Change Instruction List (Delete VEQWI, R93h). p. 108 Table 68 “11” Read instruction or RAM data → Read register settings or RAM data. p. 109 Figure 28 Delete “(d) Instruction Read”. p. 120 Figure 38 Error correction. p. 152 Revise description of “Oscillator”. p. 163 Revise Figure 77. p. 165 Inserted. p. 166 Figure 80: Error correction (NVM dummy read). p. 167 Revise Figure 81. p. 168 Insert “Notes on Power Supply ON sequence”. p. 169 Revise Figure 83 (Display ON/OFF sequence). p. 171 Revise Figure 85 (Deep standby mode). p.172 Insert Figure 86 (Deep standby mode). p. 173 Insert Figure 87 (Deep standby mode). pp. 176-184 Revise Electrical characteristics. pp. 187-190 Graphs inserted. p. 190 Add Note 12 Rev.1.0 September 13, 2006, page 199 of 199 Drawn by Approved by