CSD16407Q5C

CSD16407Q5C
www.ti.com
SLPS227D – DECEMBER 2009 – REVISED SEPTEMBER 2010
DualCool™ N-Channel NexFET™ Power MOSFET
Check for Samples: CSD16407Q5C
FEATURES
1
•
•
•
•
•
•
•
•
2
PRODUCT SUMMARY
Ultralow Qg and Qgd
DualCool™ Package
Optimized for Two Sided Cooling
Avalanche Rated
Pb Free Terminal Plating
RoHS Compliant
Halogen Free
SON 5-mm × 6-mm Plastic Package
•
Point-of-Load Synchronous Buck Converter
for Applications in Networking, Telecom and
Computing Systems
Optimized for Synchronous FET Applications
DESCRIPTION
The NexFET™ power MOSFET has been designed
to minimize losses in power conversion applications.
Drain
Gate
Source
Top View
D
D
D
D
D
S
G
G
Bottom View
D
D
D
S
S
S
Qg
Gate Charge Total (4.5V)
Qgd
Gate Charge Gate to Drain
RDS(on)
Drain to Source On Resistance
V(th)
Threshold Voltage
V
nC
3.5
nC
VGS = 4.5V
2.5
mΩ
VGS = 10V
1.8
mΩ
1.6
Device
Package
Media
CSD16407Q5C
SON 5-mm × 6-mm
Plastic Package
13-Inch
Reel
V
Qty
Ship
2500
Tape and
Reel
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise stated
VALUE
UNIT
VDS
Drain to Source Voltage
25
V
VGS
Gate to Source Voltage
+16 / –12
V
Continuous Drain Current, TC = 25°C
100
A
Continuous Drain Current(1)
31
A
IDM
Pulsed Drain Current, TA = 25°C(2)
200
A
PD
Power Dissipation(1)
3.1
W
TJ,
TSTG
Operating Junction and Storage
Temperature Range
–55 to 150
°C
EAS
Avalanche Energy, single pulse
ID = 66A, L = 0.1mH, RG = 25Ω
218
mJ
ID
S
RDS(on) vs VGS
GATE CHARGE
7
12
ID = 25A
6
ID = 25A
VDS = 12.5V
10
VG − Gate Voltage − V
RDS(on) − On-State Resistance − mW
25
13.3
(1) Typical RqJA = 40°C/W on 1-inch2 (6.45-cm2), 2-oz.
(0.071-mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4
PCB.
(2) Pulse duration ≤300ms, duty cycle ≤2%
S
S
Drain to Source Voltage
ORDERING INFORMATION
APPLICATIONS
•
VDS
5
TC = 125°C
C
4
3
2
TC = 25°C
8
6
4
2
1
0
0
0
2
4
6
8
VGS − Gate to Source Voltage − V
10
12
G006
0
5
10
15
20
25
30
35
Qg − Gate Charge − nC
G003
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DualCool, NexFET are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
CSD16407Q5C
SLPS227D – DECEMBER 2009 – REVISED SEPTEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
TA = 25°C, unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static Characteristics
BVDSS
Drain to Source Voltage
VGS = 0V, ID = 250mA
IDSS
Drain to Source Leakage Current
VGS = 0V, VDS = 20V
IGSS
Gate to Source Leakage Current
VDS = 0V, VGS = +16V / –12V
VGS(th)
Gate to Source Threshold Voltage
VDS = VGS, ID = 250mA
RDS(on)
Drain to Source On Resistance
gfs
Transconductance
25
1.3
V
1
mA
100
nA
1.6
1.9
V
VGS = 4.5V, ID = 25A
2.5
3.3
mΩ
VGS = 10V, ID = 25A
1.8
2.4
mΩ
VDS = 15V, ID = 25A
111
S
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
2040
2660
pF
1600
2080
pF
CRSS
Rg
Reverse Transfer Capacitance
115
160
pF
Series Gate Resistance
1.2
2.4
Qg
Gate Charge Total (4.5V)
Ω
13.3
18
nC
Qgd
Gate Charge Gate to Drain
Qgs
Gate Charge Gate to Source
Qg(th)
Gate Charge at Vth
QOSS
Output Charge
td(on)
Turn On Delay Time
tr
Rise Time
18.4
ns
td(off)
Turn Off Delay Time
16
ns
tf
Fall Time
9
ns
VGS = 0V, VDS = 12.5V , f = 1MHz
VDS = 12.5V, ID = 25A
VDS = 13.5V, VGS = 0V
VDS = 12.5V, VGS = 4.5V,
ID = 25A, RG = 2Ω
3.5
nC
5.3
nC
3.1
nC
33
nC
11.9
ns
Diode Characteristics
VSD
Diode Forward Voltage
IS = 25A, VGS = 0V
0.8
1
V
Qrr
Reverse Recovery Charge
VDD = 13.5V, IF = 25A, di/dt = 300A/ms
42
nC
trr
Reverse Recovery Time
VDD = 13.5V, IF = 25A, di/dt = 300A/ms
34
ns
THERMAL CHARACTERISTICS
TA = 25°C, unless otherwise specified
PARAMETER
MIN
(1)
TYP
MAX
UNIT
RqJC
Thermal Resistance Junction to Case (Top Source)
1.2
°C/W
RqJC
Thermal Resistance Junction to Case (Bottom Drain) (1)
1.1
°C/W
RqJA
Thermal Resistance Junction to Ambient (1)
51
°C/W
(1)
(2)
2
(2)
RqJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RqJC is specified by design, whereas RqJA is determined by the user’s board design.
Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
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Product Folder Link(s): CSD16407Q5C
CSD16407Q5C
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SLPS227D – DECEMBER 2009 – REVISED SEPTEMBER 2010
GATE
GATE
Source
N-Chan 5x6 QFN TTA MIN Rev3
N-Chan 5x6 QFN TTA MAX Rev3
Max RqJA = 51°C/W
when mounted on
1 inch2 (6.45 cm2) of
2-oz. (0.071-mm thick)
Cu.
Source
Max RqJA = 121°C/W
when mounted on
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
TYPICAL MOSFET CHARACTERISTICS
TA = 25°C, unless otherwise specified
ZθJA − Normalized Thermal Impedance
10
1
0.5
0.3
0.1
0.1
Duty Cycle = t1/t2
0.05
P
0.01
0.02
0.01
t1
t2
Single Pulse
0.001
0.001
0.01
o
Typical RqJA = 94 C/W (min Cu)
TJ = P x ZqJA x RqJA
0.1
1
10
100
t P − Pulse Duration − s
1k
G012
Figure 1. Transient Thermal Impedance
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CSD16407Q5C
SLPS227D – DECEMBER 2009 – REVISED SEPTEMBER 2010
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
TA = 25°C, unless otherwise specified
80
80
60
VGS = 4.5V
50
VGS = 3V
40
VGS = 3.5V
30
VGS = 2.5V
20
10
0.5
1.0
1.5
2.0
2.5
40
TC = 25°C
30
20
TC = −55°C
1.5
2.0
2.5
3.0
3.5
VGS − Gate to Source Voltage − V
G001
4.0
G002
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
12
6
ID = 25A
VDS = 12.5V
10
f = 1MHz
VGS = 0V
5
C − Capacitance − nF
VGS − Gate Voltage − V
TC = 125°C
50
0
1.0
3.0
VDS − Drain to Source Voltage − V
8
6
4
2
4
COSS = CDS + CGD
CISS = CGD + CGS
3
2
CRSS = CGD
1
0
0
0
5
10
15
20
25
30
35
Qg − Gate Charge − nC
0
10
15
20
VDS − Drain to Source Voltage − V
25
G004
Figure 4. Gate Charge
Figure 5. Capacitance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
7
RDS(on) − On-State Resistance − mW
ID = 250µA
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
−75
5
G003
2.00
VGS(th) − Threshold Voltage − V
60
10
0
0.0
−25
25
75
125
175
TC − Case Temperature − °C
ID = 25A
6
5
TC = 125°C
C
4
3
2
TC = 25°C
1
0
0
2
4
6
8
VGS − Gate to Source Voltage − V
G005
Figure 6. Threshold Voltage vs. Temperature
4
VDS = 5V
70
VGS = 10V
ID − Drain Current − A
ID − Drain Current − A
70
10
12
G006
Figure 7. On-State Resistance vs. Gate to Source Voltage
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Product Folder Link(s): CSD16407Q5C
CSD16407Q5C
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SLPS227D – DECEMBER 2009 – REVISED SEPTEMBER 2010
TYPICAL MOSFET CHARACTERISTICS (continued)
TA = 25°C, unless otherwise specified
100
ID = 25A
VGS = 10V
1.6
ISD − Source to Drain Current − A
Normalized On-State Resistance
1.8
1.4
1.2
1.0
0.8
0.6
0.4
−75
10
1
0.1
TC = 25°C
0.01
0.001
0.0001
−25
25
75
125
175
TC − Case Temperature − °C
0.0
0.2
0.4
0.6
0.8
1.0
Figure 8. Normalized On-State Resistance vs. Temperature
Figure 9. Typical Diode Forward Voltage
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
G008
I(AV) − Peak Avalanche Current − A
1k
100
100mS
10
1ms
10ms
1
0.1
1.2
VSD − Source to Drain Voltage − V
G007
1k
ID − Drain Current − A
TC = 125°C
Area Limited
by RDS(on)
100ms
Single Pulse
o
Typical RqJA = 94 C/W (min Cu)
0.01
0.01
0.1
DC
1
10
10
TC = 125°C
1
0.01
100
VD − Drain Voltage − V
TC = 25°C
100
0.1
1
10
100
t(AV) − Time in Avalanche − ms
G009
Figure 10. Maximum Safe Operating Area
G010
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
120
ID − Drain Current − A
100
80
60
40
20
0
−50
−25
0
25
50
75
100
125
TC − Case Temperature − °C
150
175
G011
Figure 12. Maximum Drain Current vs. Temperature
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Product Folder Link(s): CSD16407Q5C
5
CSD16407Q5C
SLPS227D – DECEMBER 2009 – REVISED SEPTEMBER 2010
www.ti.com
MECHANICAL DATA
Q5C Package Dimensions
E1
K
L
E2
8
8
7
7
4
4
5
5
e
3
6
3
6
D2
D1
E
2
N
1
Pin 9
1
q
Exposed
Heat Slug
L
c1
2
N1
b
M1
M
Top View
Bottom View
Side View
TM
DualCool Pinout
c
E1
A
q
Pin#
Label
1, 2, 3, 9
Source
4
Gate
5, 6, 7, 8
Drain
Front View
M0162-01
DIM
MILLIMETERS
MAX
MIN
MAX
A
0.950
1.050
0.037
0.039
b
0.360
0.460
0.014
0.018
c
0.150
0.250
0.006
0.010
c1
0.150
0.250
0.006
0.010
D1
4.900
5.100
0.193
0.201
D2
4.320
4.520
0.170
0.178
E
4.900
5.100
0.193
0.201
E1
5.900
6.100
0.232
0.240
E2
3.920
4.12
0.154
e
6
INCHES
MIN
1.27 TYP
0.162
0.050
K
0.760
–
0.030
–
L
0.510
0.710
0.020
0.028
q
–
–
–
–
M
3.260
3.460
0.128
0.136
M1
0.520
0.720
0.020
0.028
N
2.720
2.920
0.107
0.115
N1
1.227
1.427
0.048
0.056
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Product Folder Link(s): CSD16407Q5C
CSD16407Q5C
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SLPS227D – DECEMBER 2009 – REVISED SEPTEMBER 2010
DIM
Recommended PCB Pattern
F1
F7
F3
8
1
F2
F11
F5
F9
5
4
F6
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
F1
6.205
6.305
0.244
0.248
F2
4.460
4.560
0.176
0.180
F3
4.460
4.560
0.176
0.180
F4
0.650
0.700
0.026
0.028
F5
0.620
0.670
0.024
0.026
F6
0.630
0.680
0.025
0.027
F7
0.700
0.800
0.028
0.031
F8
0.650
0.700
0.026
0.028
F9
0.620
0.670
0.024
0.026
F10
4.900
5.000
0.193
0.197
F11
4.460
4.560
0.176
0.180
F8
F4
F10
M0139-01
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
K0
4.00 ±0.10 (See Note 1)
0.30 ±0.05
2.00 ±0.05
+0.10
–0.00
12.00 ±0.30
Ø 1.50
1.75 ±0.10
Q5C Tape and Reel Information
5.50 ±0.05
B0
R 0.30 MAX
A0
8.00 ±0.10
Ø 1.50 MIN
A0 = 6.50 ±0.10
B0 = 5.30 ±0.10
K0 = 1.40 ±0.10
R 0.30 TYP
M0138-01
Notes:
1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.30 ± 0.05 mm
6. MSL1 260°C (IR and convection) PbF reflow compatible
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CSD16407Q5C
SLPS227D – DECEMBER 2009 – REVISED SEPTEMBER 2010
www.ti.com
REVISION HISTORY
Changes from Original (October 2009) to Revision A
Page
•
Changed the device From: Procuct Preview To: Production ................................................................................................ 1
•
Changed Application - From: Optimized for Control FET ApplicationsTo: Optimized for Synchronous FET
Applications ........................................................................................................................................................................... 1
•
Changed the pinout illustration. ............................................................................................................................................ 1
•
Changed the Q5C Package Dimensions illustration ............................................................................................................. 6
Changes from Revision A (December 2009) to Revision B
Page
•
Changed the ABSOLUTE MAXIMUM RATINGS table, ID - Continuous Drain Current value From: 30A To: 31A .............. 1
•
Changed Note 1 of the ABSOLUTE MAXIMUM RATINGS table From: Typical RqJA = 41°C To: Typical RqJA = 40°C ....... 1
•
Changed Figure 1 - From: Typical RqJA = 98°C/W To: Typical RqJA = 94°C/W .................................................................... 3
•
Changed Figure 10 - From: Typical RqJA = 98°C/W To: Typical RqJA = 94°C/W .................................................................. 5
•
Changed Figure 11 - X axis values ...................................................................................................................................... 5
Changes from Revision B (January 2010) to Revision C
•
Changed the labels on the Bottom View pinout image ......................................................................................................... 1
Changes from Revision C (February 2010) to Revision D
•
8
Page
Page
Deleted the Package Marking Information section ............................................................................................................... 7
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PACKAGE MATERIALS INFORMATION
www.ti.com
15-Apr-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CSD16407Q5C
Package Package Pins
Type Drawing
VSONCLIP
DQU
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.8
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
5.3
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Apr-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD16407Q5C
VSON-CLIP
DQU
8
2500
335.0
335.0
32.0
Pack Materials-Page 2
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