CSD16325Q5C www.ti.com SLPS237B – DECEMBER 2009 – REVISED APRIL 2010 DualCool™ N-Channel NexFET™ Power MOSFETs Check for Samples: CSD16325Q5C FEATURES 1 • • • • • • • • 2 PRODUCT SUMMARY DualCool™ Package SON 5×6mm Optimized for 2-Sided Cooling Optimized for 5V Gate Drive Ultralow Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant and Halogen Free VDS Drain to Source Voltage 25 V Qg Gate Charge Total (4.5V) 18 nC Qgd Gate Charge Gate to Drain RDS(on) VGS(th) • The NexFET™ power MOSFET has been designed to minimize losses in power conversion applications and optimized for 5V gate drive applications. Drain Gate Source Top View D D D D Bottom View D D D 1.7 mΩ VGS = 8V 1.5 mΩ Threshold Voltage 1.1 S V Package Media CSD16325Q5C SON 5×6-mm Plastic Package 13-Inch Reel Qty Ship 2500 Tape and Reel ABSOLUTE MAXIMUM RATINGS VALUE UNIT VDS Drain to Source Voltage 25 V VGS Gate to Source Voltage +10 / –8 V Continuous Drain Current, TC = 25°C 100 A Continuous Drain Current(1) 33 A IDM Pulsed Drain Current, TA = 25°C(2) 200 A PD Power Dissipation(1) 3.1 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 100A, L = 0.1mH, RG = 25Ω 500 mJ ID (1) Typical RqJA = 38°C/W on 1-in2 Cu, (2-oz.) on a 0.060" thick FR4 PCB. (2) Pulse duration ≤300ms, duty cycle ≤2% S S G G S S S RDS(on) vs VGS Gate Charge 10 5.0 9 4.5 ID = 30A 4.0 VG − Gate Voltage − V RDS(on) − On-State Resistance − mW VGS = 4.5V TA = 25°C unless otherwise stated DESCRIPTION S mΩ ORDERING INFORMATION Point-of-Load Synchronous Buck in Networking, Telecom and Computing Systems Optimized for Synchronous FET Applications D Drain to Source On Resistance nC 2.1 Device APPLICATIONS • 3.5 VGS = 3V 3.5 TC = 125°C 3.0 2.5 2.0 1.5 TC = 25°C 1.0 ID = 30A VDS = 12.5V 8 7 6 5 4 3 2 1 0.5 0 0.0 0 1 2 3 4 5 6 7 8 VGS − Gate to Source Voltage − V 9 10 G006 0 5 10 15 20 25 Qg − Gate Charge − nC 30 35 40 G003 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DualCool, NexFET are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2010, Texas Instruments Incorporated CSD16325Q5C SLPS237B – DECEMBER 2009 – REVISED APRIL 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250mA IDSS Drain to Source Leakage VGS = 0V, VDS = 20V IGSS Gate to Source Leakage VDS = 0V, VGS = +10/–8V VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID = 250mA RDS(on) Drain to Source On Resistance gfs Transconductance 25 V 1 mA 100 nA 1.1 1.4 V VGS = 3V, ID = 30A 2.1 2.9 mΩ VGS = 4.5V, ID = 30A 1.7 2.2 mΩ VGS = 8V, ID = 30A 1.5 2 mΩ VDS = 15V, ID = 30A 159 0.9 S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance 120 150 RG Series Gate Resistance 1.6 3.2 Ω Qg Gate Charge Total (4.5V) 18 25 nC Qgd Gate Charge – Gate to Drain Qgs Gate Charge – Gate to Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0V, VDS = 12.5V, f = 1MHz VDS = 12.5V, IDS = 30A VDS = 13V, VGS = 0V VDS = 12.5V, VGS = 4.5V, IDS = 30A , RG = 2Ω 3070 4000 pF 2190 2850 pF pF 3.5 nC 6.6 nC 3.1 nC 43 nC 10.5 ns 16 ns 32 ns 12 ns Diode Characteristics VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time IDS = 30A, VGS = 0V 0.8 VDD = 13V, IF = 30A, di/dt = 300A/ms 1 V 63 nC 47 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER MIN (1) RqJC Thermal Resistance Junction to Case (Top Source) RqJC Thermal Resistance Junction to Case (Bottom drain) (1) RqJA Thermal Resistance Junction to Ambient (1) (2) (1) (2) 2 TYP MAX UNIT 1.4 °C/W 1 °C/W 50 °C/W RqJC is determined with the device mounted on a 1-inch2 2-oz. Cu pad on a 1.5 × 1.5-inch 0.060-inch thick FR4 board. RqJC is specified by design, whereas RqCA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 of 2-oz. Cu. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): CSD16325Q5C CSD16325Q5C www.ti.com SLPS237B – DECEMBER 2009 – REVISED APRIL 2010 GATE GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RqJA = 50°C/W when mounted on 1 inch2 of 2-oz. Cu. Source Max RqJA = 126°C/W when mounted on minimum pad area of 2-oz.Cu. DRAIN DRAIN M0137-02 M0137-01 Text and Text and Text and Text and br Added for Spacing br br br Added Added Added for for for Spacing Spacing Spacing TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) ZqJA – NormalizedThermal Impedance 10 1 0.5 0.3 0.1 Duty Cycle = t1/t2 0.1 0.05 0.01 P 0.02 0.01 t1 t2 o Typical R qJA = 101 C/W (min Cu) TJ = P x ZqJA x R qJA Single Pulse 0.001 0.001 0.01 0.1 1 10 100 1k tP – Pulse Duration–s G012 Figure 1. Transient Thermal Impedance Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): CSD16325Q5C 3 CSD16325Q5C SLPS237B – DECEMBER 2009 – REVISED APRIL 2010 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 100 90 VGS = 8V 70 ID − Drain Current − A ID − Drain Current − A 90 80 VGS = 4.5V 60 VGS = 3V 50 40 VGS = 2.5V 30 20 0 0.0 0.2 0.4 TC = 25°C 60 50 40 TC = 125°C 30 TC = −55°C 10 0.8 0.6 70 20 VGS = 2V 10 VDS = 5V 80 1 1.2 0 1.25 1.4 VDS − Drain to Source Voltage − V 1.5 TEXT ADDED FOR SPACING 2.5 G002 TEXT ADDED FOR SPACING 8 9 8 f = 1MHz VGS = 0V 7 ID = 30A VDS = 12.5V C − Capacitance − nF VG − Gate Voltage − V 2.25 Figure 3. Transfer Characteristics 10 7 6 5 4 3 2 Coss = Cds + Cgd 6 5 Ciss = Cgd + Cgs 4 3 2 Crss = Cgd 1 1 0 0 0 5 10 15 20 25 30 40 35 Qg − Gate Charge − nC 0 5 10 20 25 G004 Figure 5. Capacitance TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 5.0 1.4 RDS(on) − On-State Resistance − mW 1.6 ID = 250mA 1.2 1.0 0.8 0.6 0.4 0.2 0.0 −75 15 VDS − Drain to Source Voltage − V G003 Figure 4. Gate Charge VGS(th) − Threshold Voltage − V 2 VGS − Gate to Source Voltage − V G001 Figure 2. Saturation Characteristics 4.5 ID = 30A 4.0 3.5 TC = 125°C 3.0 2.5 2.0 1.5 TC = 25°C 1.0 0.5 0.0 −25 25 75 125 175 TC − Case Temperature − °C 0 1 2 3 4 5 6 7 8 9 VGS − Gate to Source Voltage − V G005 Figure 6. Threshold Voltage vs. Temperature 4 1.75 10 G006 Figure 7. On Resistance vs. Gate Voltage Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): CSD16325Q5C CSD16325Q5C www.ti.com SLPS237B – DECEMBER 2009 – REVISED APRIL 2010 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 ID = 30A VGS = 4.5V 1.4 ISD − Source to Drain Current − A Normalized On-State Resistance 1.6 1.2 1.0 0.8 0.6 0.4 0.2 0.0 −75 10 1 0.1 TC = 25°C 0.01 0.001 0.0001 −25 25 75 125 175 TC − Case Temperature − °C 0.0 G007 0.8 TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1.0 G008 1k I(AV) − Peak Avalanche Current − A ID − Drain Current − A 0.6 Figure 9. Typical Diode Forward Voltage 1ms 10 10ms 100ms 0.01 0.01 0.4 Figure 8. On Resistance vs. Temperature 100 0.1 0.2 VSD − Source to Drain Voltage − V 1k 1 TC = 125°C Area Limited by RDS(on) 1s Single Pulse Typical RqJA = 101°C/W (min Cu) 0.1 DC 1 10 TC = 125°C 10 1 0.01 100 VD − Drain Voltage − V TC = 25°C 100 0.1 1 10 t(AV) − Time in Avalanche − ms G009 Figure 10. Maximum Safe Operating Area 100 G010 Figure 11. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING 120 ID − Drain Current − A 100 80 60 40 20 0 −50 −25 0 25 50 75 100 125 TC − Case Temperature − °C 150 175 G011 Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): CSD16325Q5C 5 CSD16325Q5C SLPS237B – DECEMBER 2009 – REVISED APRIL 2010 www.ti.com MECHANICAL DATA Q5C Package Dimensions E1 K L E2 8 8 7 7 6 4 4 5 5 e 3 6 3 Pin 9 D2 D1 E 2 N 1 Exposed Heat Slug 1 c1 q 2 N1 L b M1 M Top View Bottom View Side View TM DualCool Pinout c E1 A q Pin# Label 1, 2, 3, 9 Source 4 Gate 5, 6, 7, 8 Drain Front View M0162-01 DIM MILLIMETERS MAX MIN MAX A 0.950 1.050 0.037 0.039 b 0.360 0.460 0.014 0.018 c 0.150 0.250 0.006 0.010 c1 0.150 0.250 0.006 0.010 D1 4.900 5.100 0.193 0.201 D2 4.320 4.520 0.170 0.178 E 4.900 5.100 0.193 0.201 E1 5.900 6.100 0.232 0.240 E2 3.920 4.12 0.154 e 6 INCHES MIN 1.27 TYP 0.162 0.050 L 0.510 0.710 0.020 0.028 q – – – – K 0.760 – 0.030 – M 3.260 3.460 0.128 0.136 M1 0.520 0.720 0.020 0.028 N 2.720 2.920 0.107 0.115 N1 1.227 1.427 0.048 0.056 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): CSD16325Q5C CSD16325Q5C www.ti.com SLPS237B – DECEMBER 2009 – REVISED APRIL 2010 Recommended PCB Pattern DIM F1 F7 F3 8 1 F2 F11 F5 F9 5 4 F6 MILLIMETERS INCHES MIN MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.46 4.56 0.176 0.18 F3 4.46 4.56 0.176 0.18 F4 0.65 0.7 0.026 0.028 F5 0.62 0.67 0.024 0.026 F6 0.63 0.68 0.025 0.027 F7 0.7 0.8 0.028 0.031 F8 0.65 0.7 0.026 0.028 F9 0.62 0.67 0.024 0.026 F10 4.9 5 0.193 0.197 F11 4.46 4.56 0.176 0.18 F8 F4 F10 M0139-01 K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 Q5C Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm, unless otherwise specified. 5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket 6. MSL1 260°C (IR and convection) PbF reflow compatible Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): CSD16325Q5C 7 CSD16325Q5C SLPS237B – DECEMBER 2009 – REVISED APRIL 2010 www.ti.com REVISION HISTORY Changes from Original (December 2009) to Revision A Page • Changed the labels on the Bottom View pinout image ......................................................................................................... 1 • Changed the Mechanical Data dimensions table. Added dimensions for M, M1, N and N1 ................................................ 6 Changes from Revision A (April 2010) to Revision B Page • Changed RDS(on) - VGS = 3V in the Electrical Characteristics table From: 2.7 To: 2.9 in the max column ............................ 2 • Deleted the Package Marking Information section ............................................................................................................... 7 8 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): CSD16325Q5C PACKAGE OPTION ADDENDUM www.ti.com 27-Apr-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing CSD16325Q5C ACTIVE SON DQU Pins Package Eco Plan (2) Qty 8 2500 Pb-Free (RoHS Exempt) Lead/Ball Finish Call TI MSL Peak Temp (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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