Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CSD18540Q5B SLPS488 – JUNE 2014 CSD18540Q5B 60V N-Channel NexFET™ Power MOSFETs 1 Features • • • • • • • 1 Product Summary Ultra-Low Qg and Qgd Low Thermal Resistance Avalanche Rated Pb-Free Terminal Plating RoHS Compliant Halogen Free SON 5-mm × 6-mm Plastic Package TA = 25°C TYPICAL VALUE Drain-to-Source Voltage 60 V Qg Gate Charge Total (10 V) 41 nC Qgd Gate Charge Gate-to-Drain RDS(on) Drain-to-Source On Resistance VGS(th) Threshold Voltage DC-DC Conversion Secondary Side Synchronous Rectifier Isolated Converter Primary Side Switch Motor Control 7 2 4 D Media Package Ship 13-Inch Reel CSD18540Q5BT 250 7-Inch Reel SON 5 × 6 mm Plastic Package Tape and Reel TA = 25°C VALUE UNIT VDS Drain-to-Source Voltage 60 V VGS Gate-to-Source Voltage ±20 V Continuous Drain Current (Package limited) 100 Continuous Drain Current (Silicon limited), TC = 25°C 221 6 D 5 D A Continuous Drain Current(1) 28 Pulsed Drain Current, TA = 25°C(2) 400 Power Dissipation(1) 3.1 Power Dissipation, TC = 25°C 195 TJ, Tstg Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 80 A, L = 0.1 mH, RG = 25 Ω 320 mJ PD A W (1) Typical RθJA = 40°C/W on a 1-inch2 , 2-oz. Cu pad on a 0.06inch thick FR4 PCB. (2) Max RθJC = 0.8°C/W, Pulse duration ≤100 μs, duty cycle ≤1% P0093-01 RDS(on) vs VGS Gate Charge 5 10 TC = 25°C, I D = 28A TC = 125°C, I D = 28A 4.5 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (mΩ) V Qty D D 4 3.5 3 2.5 2 1.5 1 0.5 0 mΩ 2500 IDM G 1.8 1.9 Device ID 8 1 3 VGS = 10 V Absolute Maximum Ratings Top View S mΩ (1) For all available packages, see the orderable addendum at the end of the data sheet. This 1.8 mΩ, 60 V, SON5x6 NexFET™ power MOSFET is designed to minimize losses in power conversion applications. S nC 2.6 CSD18540Q5B 3 Description S 6.7 VGS = 4.5 V Ordering Information(1) 2 Applications • • • • UNIT VDS 0 2 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 ID = 28A VDS = 30V 9 8 7 6 5 4 3 2 1 0 0 5 10 15 20 25 30 Qg - Gate Charge (nC) 35 40 45 G001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD18540Q5B SLPS488 – JUNE 2014 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 6.1 Trademarks ............................................................... 7 6.2 Electrostatic Discharge Caution ................................ 7 6.3 Glossary .................................................................... 7 1 1 1 2 3 7 7.1 7.2 7.3 7.4 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Mechanical, Packaging, and Orderable Information ............................................................. 8 Device and Documentation Support.................... 7 Q5B Package Dimensions ........................................ 8 Recommended PCB Pattern..................................... 9 Recommended Stencil Pattern ................................. 9 Q5B Tape and Reel Information ............................. 10 4 Revision History 2 DATE REVISION NOTES June 2014 * Initial release. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD18540Q5B CSD18540Q5B www.ti.com SLPS488 – JUNE 2014 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 48 V 1 μA IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, ID = 250 μA RDS(on) Drain-to-Source On Resistance gfs Transconductance 60 1.5 V 1.9 2.3 V VGS = 4.5 V, ID = 28 A 2.6 3.3 mΩ VGS = 10 V, ID = 28 A 1.8 2.2 mΩ VDS = 6 V, ID = 28 A 116 S DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Series Gate Resistance Qg Gate Charge Total (4.5 V) Qg Gate Charge Total (10 V) Qgd Gate Charge Gate-to-Drain Qgs Gate Charge Gate-to-Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) VGS = 0 V, VDS = 30 V, ƒ = 1 MHz VDS = 30 V, ID = 28 A 3250 4230 pF 622 808 pF 15 20 pF 0.8 1.6 Ω 20 26 nC 41 53 nC 6.7 nC 8.8 nC 6.3 nC 83 nC Turn On Delay Time 6 ns tr Rise Time 9 ns td(off) Turn Off Delay Time 20 ns tf Fall Time 3 ns VDS = 30 V, VGS = 0 V VDS = 30 V, VGS = 10 V, IDS = 28 A, RG = 0 Ω DIODE CHARACTERISTICS VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time ISD = 28 A, VGS = 0 V 0.8 VDS= 30 V, IF = 28 A, di/dt = 300 A/μs 145 1 nC V 82 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) THERMAL METRIC MIN TYP MAX RθJC Junction-to-Case Thermal Resistance (1) 0.8 RθJA Junction-to-Ambient Thermal Resistance (1) (2) 50 (1) (2) UNIT °C/W RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inches × 1.5-inches (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD18540Q5B 3 CSD18540Q5B SLPS488 – JUNE 2014 GATE www.ti.com GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Source Max RθJA = 125°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD18540Q5B CSD18540Q5B www.ti.com SLPS488 – JUNE 2014 Typical MOSFET Characteristics (continued) 200 200 180 180 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) (TA = 25°C unless otherwise stated) 160 140 120 100 80 60 VGS = 10V VGS = 6V VGS = 4.5V 40 20 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VDS - Drain-to-Source Voltage (V) 1.8 160 140 120 100 80 60 20 0 2 TC = 125°C TC = 25°C TC = −55°C 40 0 0.5 1 1.5 2 2.5 3 VGS - Gate-to-Source Voltage (V) G001 3.5 4 G001 VDS = 5 V Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics 100000 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 9 8 C − Capacitance (pF) VGS - Gate-to-Source Voltage (V) 10 7 6 5 4 3 10000 1000 100 2 10 1 0 0 5 10 15 20 25 30 Qg - Gate Charge (nC) ID = 28 A 35 40 1 45 0 10 20 30 40 50 VDS - Drain-to-Source Voltage (V) G001 G001 VDS = 30 V Figure 4. Gate Charge Figure 5. Capacitance 2.5 5 RDS(on) - On-State Resistance (mΩ) VGS(th) - Threshold Voltage (V) 60 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 −75 −25 25 75 125 TC - Case Temperature (ºC) 175 TC = 25°C, I D = 28A TC = 125°C, I D = 28A 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 2 G001 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 ID = 250 µA Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD18540Q5B 5 CSD18540Q5B SLPS488 – JUNE 2014 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 100 VGS = 4.5V VGS = 10V ISD − Source-to-Drain Current (A) Normalized On-State Resistance 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 −75 −25 25 75 125 TC - Case Temperature (ºC) 175 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) G001 1 G001 ID = 28 A Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage 1000 100 10us 100us 1ms 10ms DC IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 5000 100 10 1 0.1 0.1 1 10 VDS - Drain-to-Source Voltage (V) 100 TC = 25ºC TC = 125ºC 10 0.01 0.1 TAV - Time in Avalanche (mS) G001 1 G001 Single Pulse, Max RθJC = 0.8°C/W Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain- to- Source Current (A) 120 100 80 60 40 20 0 −50 −25 0 25 50 75 100 125 TC - Case Temperature (ºC) 150 175 G001 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD18540Q5B CSD18540Q5B www.ti.com SLPS488 – JUNE 2014 6 Device and Documentation Support 6.1 Trademarks NexFET is a trademark of Texas Instruments. 6.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD18540Q5B 7 CSD18540Q5B SLPS488 – JUNE 2014 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Q5B Package Dimensions K H D3 6 D1 4 5 e 6 4 3 3 5 D2 7 2 E 2 7 ө 1 8 1 8 L b (8x) c1 E1 d1 Top View d2 Bottom View Side View ө Front View DIM MILLIMETERS MIN NOM MAX A 0.80 1.00 1.05 b 0.36 0.41 0.46 c 0.15 0.20 0.25 c1 0.15 0.20 0.25 c2 0.20 0.25 0.30 D1 4.90 5.00 5.10 D2 4.12 4.22 4.32 D3 3.90 4.00 4.10 d 0.20 0.25 0.30 d1 0.085 TYP d2 0.319 0.369 0.419 E 4.90 5.00 5.10 E1 5.90 6.00 6.10 E2 3.48 3.58 3.68 e H 0.36 0.46 0.56 L 0.46 0.56 0.66 L1 0.57 0.67 0.77 θ 0° — — K 8 1.27 TYP 1.40 TYP Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD18540Q5B CSD18540Q5B www.ti.com SLPS488 – JUNE 2014 7.2 Recommended PCB Pattern (0.175) 4.440 5 (0.028) 0.710 (0.043) 1.100 C L 4 (0.023) 0.590 1.270 (0.028) SYM C L (0.178) 4.520 1 8 0.560 (0.022) (0.136) 3.456 0.710 (0.028) (0.054) (0.039) 0.984 1.372 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. 7.3 Recommended Stencil Pattern (0.020) 0.508 x4 (0.011) 0.286 (0.014) 0.350 (0.022) 0.562 x 4 (0.029) 0.746 x 8 2.186 (0.086) 4.318 (0.170) 0.300 (0.012) 1.270 (0.050) (0.030) 0.766 (0.051) 1.294 x8 (0.060) 1.525 1.270 (0.050) (0.042) 1.072 (0.259) 6.586 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD18540Q5B 9 CSD18540Q5B SLPS488 – JUNE 2014 www.ti.com K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 7.4 Q5B Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified). 5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket 10 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD18540Q5B PACKAGE OPTION ADDENDUM www.ti.com 6-Apr-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CSD18540Q5B ACTIVE VSON-CLIP DNK 8 2500 Pb-Free (RoHS Exempt) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 150 CSD18540 CSD18540Q5BT ACTIVE VSON-CLIP DNK 8 250 Pb-Free (RoHS Exempt) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 150 CSD18540 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 12-May-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CSD18540Q5B VSONCLIP DNK 8 2500 330.0 12.4 6.3 5.3 1.2 8.0 12.0 Q1 CSD18540Q5BT VSONCLIP DNK 8 250 180.0 12.4 6.3 5.3 1.2 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 12-May-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD18540Q5B VSON-CLIP DNK 8 2500 367.0 367.0 35.0 CSD18540Q5BT VSON-CLIP DNK 8 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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