M62420SP/ FP/ AFP 2ch Electronic Volume with Tone by I2C Bus System REJ03F0051-0100Z Rev.1.0 Sep.17.2003 Description M62420SP/FP/AFP is the tone and volume controller which is controlled by I2C bus. This IC can apply the broad application because of low noise and distortion. M62420AFP changes the slave address from M62420FP. Features • TONE(Bass/Treble) control and 1 dB step volume control are enabled. • Low noise and low distortion . VNO = 4.5 µVrms, CTHD=0.1% max • Controlling by serial data in conformity to the I2C bus format . Applications • TV, Mini-Stereo, etc Recommended Operating Condition • Supply voltage range: 8.5 to 9.5 V (analog) 4.5 to 5.5 V (digital) • Rated supply voltage: 9 V (analog) 5 V (digital) System Block Diagram M62420SP/FP Lch IN Lch OUT BASS TREBLE TONE CONTROL VOLUME Rch OUT Rch IN VOLUME BASS TREBLE 2 I C BUS INTERFACE SCL Rev.1.0, Sep.17.2003, page 1 of 16 SDA TONE CONTROL M62420SP/ FP/ AFP RESET AGND 16 15 14 13 12 11 DVDD OUT2 BASS2 SIMOUT2 18 17 TRE2 20 19 SIMIN 2 CH2 IN AVDD Block diagram and Pin Configuration 1.8K VR4 VR6 SIMAMP2 136K ref S2 S4 S6 S8 TONE AMP2 6.5K VR2 ref ref 6.5K VOLAMP2 CONTROL LOGIC VOLAMP1 6.5K VR1 6.5K TONE AMP1 ref ref S1 S3S5 S7 2 136KSIMAMP1 VR3 I C BUS INTER FACE VR5 1 2 3 4 5 6 7 8 9 10 REF CH1 IN SIMIN 1 SIMOUT 1 BASS1 TRE1 OUT1 DGND SDA SCL 1.8K Rev.1.0, Sep.17.2003, page 2 of 16 M62420SP/ FP/ AFP Pin Description Pin No. Pin Name I/O Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 REF CH1 IN SIMIN1 SIMOUT 1 BASS1 TRE1 VOL OUT1 DGND SDA SCL RESET DVDD AGND VOL OUT2 TRE2 BASS2 SIMOUT2 SIMIN 2 CH2 IN AVDD I I I O I I O I I/O I I I I O I I O I I I Reference voltage terminal for analog Input terminal (ch1) Pin for capacitor of simulated inductor 1 Pin for capacitor of simulated inductor 1 Pin for capacitor of ch1-side bass setting Pin for capacitor of ch1-side treble setting Output terminal (ch1) Digital GND I/O terminal of DATA I2C bus format Input terminal of CLOCK I2C bus format RESET terminal of built-in logic circuit VDD for digital circuit GND for analog circuit Output terminal (ch2) Pin for capacitor of ch2-side treble setting Pin for capacitor of ch2-side bass setting Pin for capacitor of simulated inductor 2 Pin for capacitor of simulated inductor 2 Input terminal (ch2) VCC for analog circuit Absolute Maximum Ratings (Ta = 25°C) Symbol Parameter AVdd DVdd Pd Kθ Topr Tstg Analog supply voltage Digital supply voltage Power dissipation Thermal Derating ratio Operating temperature Storage temperature Rev.1.0, Sep.17.2003, page 3 of 16 Condition Limits Unit Ta ≤ 25°C Ta > 25°C 10.0 7.0 750 7.5 –20 to +75 –40 to +125 V V mW mW / °C °C °C M62420SP/ FP/ AFP Power dissipation pd [mW] Thermal Derating Curves 1000 SP 800 750mW 600 550mW FP 400 375mW 275mW 200 0 25 0 50 75 100 125 150 Ambient temperature Ta [˚C] Recommended Operating Condition (Ta = 25°C unless otherwise noted) Item Symbol Analog supply voltage Digital supply voltage H level input voltage (logic circuit) H level input voltage (logic circuit) AVDD DVDD VIH VIL Rev.1.0, Sep.17.2003, page 4 of 16 Condition MIN TYP MAX Unit 8.5 4.5 0.7DVDD 0 9.0 5.0 — — 9.5 5.5 VDD 0.3DVDD V V V V M62420SP/ FP/ AFP Electrical Characteristics (DC) ( Ta = 25°C, AVDD = 9 V, DVDD = 5 V and tone, bassboost = 0 dB unless otherwise noted ) (1) Supply voltage Item Symbol Conditions Limit Unit Min. Typ. Max. Analog supply current Icc — 10 20 mA Digital supply current Idd AVdd = 9.0 V Measure terminal = 20 pin No signal input DVdd = 5 V Measure terminal = 12 pin No signal input – 0 2 µA Limit (2) I/O CHARACTERISTICS Item Symbol Conditions Unit Min. Typ. Max. Maximum input voltage VIM 2.0 3.2 — Vrms Output voltage Vodc 2,19 pin input, 7,14 pin output RL = 10 K, THD = 1%, f = 1 kHz ATT = -6dB 7 pin, 14 pin, no signal 4.35 4.5 4.65 V Gain Gv Vin = 0dBm, FLAT, f = 1 kHz 2-7PIN 19-14PIN gain –2 0 2 dB Output noise voltage Vono JIS-A filter, no signal, Rg =10 KΩ 7,14 pin — 4.5 30 µVrms Total harmonic distortion THD — 0.05 0.1 % Channel separation CT 7 pin, 14 pin f=1kHz Vo = 0.5 Vrms, RL = 10KΩ LPF = 30 kHz RL = 10 K S:Vin = 1 Vrms,f=1kHz M:Rg = 10 kΩ, JIS-A filter — –100 –70 dB Min. Typ. Max. 9 –15 9 12 –12 12 15 –9 15 dB dB dB –15 –12 –9 dB Min. Typ. Max. –108 –100 –80 dB –1.5 0 1.5 dB (3) Tone Characteristics Item Tone control gain (bass) Tone control gain (treble) Symbol Gbassb Gbassc Gtrebb Conditions f = 100 Hz f = 10 Hz Gtrebc Limit Unit (4) Volume Characteristics Item Symbol Maximum attenuation ATTmax Minimum attenuation ATTmin Rev.1.0, Sep.17.2003, page 5 of 16 Conditions f = 1KHz, Vin = 0dBm 2 pin to 7 pin 19 pin to 14pin gain JIS-A filter Limit Unit M62420SP/ FP/ AFP Function Explanation (1) Equivaration Circuit of Tone Control The resonance circuit is able to construct by using built-in amplifier for simulated inductor. (Shows the constant as follow) Incide IC Center frequency f0 = 1 / 2π R3 C1 Q= R1 (=1.8KΩ) C2 C1 • C2 • R1 • R2 [Hz] ( C2 • R2 ) / ( C1 • R1 ) ( EX ) BASS band ( f=100Hz ) R1=1.8KΩ , R2=136KΩ C1=0.47µF , C2=0.022µF SIMAMP R2 (=136KΩ) ref FIG1. The circuit used simurated inductor. FIG1 is equal to FIG2. The following relation is concluded. L=C2 • ER1 • ER2 ref L C1 R3 FIG2. The equivalent circuit used L. Rev.1.0, Sep.17.2003, page 6 of 16 M62420SP/ FP/ AFP I2C BUS Input Data Format Input direction ( 1 ) slave address S ( 2 ) sub address A acknowledge bit starting term ( 3 ) data A A P ending term acknowledge bit ( 1 ) Slave address M62420SP / FP A6 A5 A4 A3 A2 A1 A0 R/W 1 0 0 0 0 0 0 0 M62420AFP A6 A5 A4 A3 A2 A1 A0 R/W 1 0 0 0 0 0 1 0 ( 2 ) sub address subA7 subA6 The following sub address is defined at this IC. subA5 subA4 subA2 subA1 subA0 MUTE mode TREBLE level mode BASS level mode channel2 volume mode channel1 volume mode 1: ON 0: OFF 1: ON 0: OFF 1: ON 0: OFF 1: ON 0: OFF 1: ON 0: OFF empty slot Rev.1.0, Sep.17.2003, page 7 of 16 subA3 M62420SP/ FP/ AFP ( 3 ) -1: volume control The volume control is enabled at following condition. subA0 : subA1 : subA2 : 0 subA3 : 0 0 , 1 , 1 (either bit is 1) 1 , 0 , 1 (both bits are 0) volume code ATT D4 D3 D2 D1 D0 ATT D6 D5 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 16dB 18dB 20dB 22dB 24dB 26dB 28dB 30dB 32dB 34dB H H H H H H H H H H H H H H H H L L L L L L L L L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H L L L L L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L 0dB 1dB * 2dB * 3dB H H L L H L H L 36dB 38dB 40dB 42dB 46dB 50dB 54dB 58dB 62dB 66dB 70dB 74dB 78dB ∞dB Rev.1.0, Sep.17.2003, page 8 of 16 * 2dB,3dB setting is enabled at less than 42dB step. M62420SP/ FP/ AFP ( 3 ) -2 : tone level control The tone level controlling is enabled at following condition. subA0 : 0 subA1 : 0 subA2 : subA3 : (both bits are 0) 0 , 1 , 1 (either bit is 1) 1 , 0 , 1 tone code BASS 12dB 10dB 8dB 6dB 4dB 2dB 0dB -2dB -4dB -6dB -8dB -10dB -12dB TREBLE D7 D6 D5 D4 D3 D2 D1 D0 L L L L L L L H H H H H H H H H L L L L L L L H H H H L L H H L L L H H L L H L H L H L H L H L H L H L L L L L L L L H H H H H H H H H L L L L L L L H H H H L L H H L L L H H L L H L H L H L H L H L H L H L non-used code HHHH LHHH HLLL ( 3 ) -3 : Mute mode The mute mode is enabled at following condition. subA0 : no definition subA1 : no definition Rev.1.0, Sep.17.2003, page 9 of 16 subA2 : no definition subA3 : no definition subA4 : 1 M62420SP/ FP/ AFP DATA and CLOCK S D A (IN) 1 SCL 2~7 8 9 S D A (OUT) S ACK start acknowledge P stop start This term is defined by SDA(in) falling edge at SCL H . stop This term is defined by SDA(in) rising edge at SCL H . CAUTION The SDA(IN) level never change at SCK=H except start and stop . data transmisson The SDA(IN) is enabled at SCL rising edge and H . acknowledge Transmitter must send H during ninth clock pulse of SCL . The case of finished receiving , the receiver replies L synchronized to falling edge of eighth pulse . And restart receiving the transmitted data synchronized to falling edge of ninth pulse . Rev.1.0, Sep.17.2003, page 10 of 16 M62420SP/ FP/ AFP BUS Line Timing Specification tR, tF tBUF VIL SDA VIH tHD:STA tSU:DAT tHD:DAT tSU:STA tSU:STO VIL SCL VIH tLOW S tHIGH S Parameter Min. input low voltage Max. input high voltage SCL clock frequency Time the bus must be free before a new transmission can start Hold time start condition. After this period the first clock pulse is generated The LOW period of the clock The HIGH period of the clock Set up time for start condition (Only relevant for a repeated start condition) Hold time DATA Set-up time DATA Rise time of both SDA and SCL lines Fall time of both SDA and SCL lines Set-up time for stop condition Rev.1.0, Sep.17.2003, page 11 of 16 P Symbol VIL VIH fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO MIN –0.5 3.0 0 4.7 4.0 4.7 4.0 4.7 0 250 S MAX 1.5 5.5 100 1000 300 4.0 Units V V kHz µs µs µs µs µs µs ns ns ns µs M62420SP/ FP/ AFP Level Diagram G1 6.5KΩ 6.5KΩ -12dB to +12dB G2 CH1 IN VOLAMP1 ref TONEAMP1 G1 CH1 OUT 0dB to ∞ -dB 136K ref 1.8K same to CH1 CH2 IN Rev.1.0, Sep.17.2003, page 12 of 16 CH2 OUT M62420SP/ FP/ AFP Logic Circuit ANALOG BLOCK ref VOLAMP1 TONE AMP1 Level shifter Decoder, latch for volume control Decoder, latch for tone control <D1> <D0> <D3> <D2> <D6> <D5> <D4> <D7> <D7> <D6> <D5> <D4> <D3> <D2> <D1> <D0> <D0> <D1> <D2> <D4> <D3> Sub-address latch circuit Slave address compare circuit Acknowledge generator SDA SCL Bi-direct control Rev.1.0, Sep.17.2003, page 13 of 16 Shift register <D0> <D1> <D2> <D3> <D4> <D5> <D6> <D7> Timing generator M62420SP/ FP/ AFP Application Example OUT2 DVDD 2.2µF ref 0.033µ F 10K 430 2.2µ F 0.47µ F 0.022µ F IN2 100K AGND 1.8K VCC 10K 20 19 18 17 16 15 14 13 12 11 1.8K VR4 VR6 SIMAMP2 136K ref S2 S4S6 S8 TONE AMP2 6.5K VR2 ref ref 6.5K VOLAMP2 CONTROL LOGIC VOLAMP1 6.5K VR1 6.5K TONE AMP1 ref 136KSIMAMP1 ref VR3 I2C BUS INTER FACE VR5 1.8K 1 470µ F 4.7K 2 3 0.022µ F Reference voltage 4 5 0.47µ F 6 7 8 9 10 1.8K 0.033µ F ref 2.2µ F Reference circuit example 4.7K S1 S3 S5 S7 DGND 430 10K IN1 MPU 2.2µ F 10K Rev.1.0, Sep.17.2003, page 14 of 16 OUT1 1000pF Rev.1.0, Sep.17.2003, page 15 of 16 G Z1 E HE 1 20 EIAJ Package Code SOP20-P-300-1.27 z Detail G e D JEDEC Code — y b x Weight(g) 0.26 M 10 11 F A Detail F A2 Lead Material Cu Alloy L1 MMP c A1 A A1 A2 b c D E e HE L L1 z Z1 x y Symbol e1 b2 e1 I2 b2 Dimension in Millimeters Min Nom Max — 2.1 — 0.1 0.2 0 1.8 — — 0.5 0.35 0.4 0.2 0.18 0.25 12.6 12.7 12.5 5.3 5.4 5.2 1.27 — — 7.8 8.1 7.5 0.8 0.6 0.4 — 1.25 — — 0.585 — — — 0.735 — — 0.25 — 0.1 — — 0° 8° — — 0.76 — 7.62 — 1.27 — — Recommended Mount Pad e Plastic 20pin 300mil SOP I2 20P2N-A M62420SP/ FP/ AFP Package Dimensions L SEATING PLANE EIAJ Package Code SDIP20-P-300-1.78 e b D b1 10 1 Lead Material Alloy 42/Cu Alloy 11 Weight(g) 1.0 20 JEDEC Code — A A1 A2 b b1 c D E e e1 L Symbol Plastic 20pin 300mil SDIP Dimension in Millimeters Min Nom Max — — 4.5 0.51 — — — 3.3 — 0.38 0.48 0.58 0.9 1.0 1.3 0.22 0.27 0.34 18.8 19.0 19.2 6.15 6.3 6.45 — 1.778 — — 7.62 — 3.0 — — 0° 15° — c MMP A L E A2 Rev.1.0, Sep.17.2003, page 16 of 16 A1 e1 20P4B M62420SP/ FP/ AFP Sales Strategic Planning Div. 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