TI CCBTLV3257MPWREP

SN74CBTLV3257-EP
www.ti.com ....................................................................................................................................................................................................... SCDS271 – MAY 2008
LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
FEATURES
1
•
•
•
•
•
(1)
Controlled Baseline
– One Assembly Site
– One Test Site
– One Fabrication Site
Extended Temperature Performance of
–55°C to 125°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
•
•
•
•
•
5-Ω Switch Connection Between Two Ports
Rail-to-Rail Switching on Data I/O Ports
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
PW PACKAGE
(TOP VIEW)
S
1B1
1B2
1A
2B1
2B2
2A
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
OE
4B1
4B2
4A
3B1
3B2
3A
DESCRIPTION/ORDERING INFORMATION
The SN74CBTLV3257 is a 4-bit 1-of-2 high-speed FET multiplexer/demultiplexer. The low on-state resistance of
the switch allows connections to be made with minimal propagation delay.
The select (S) input controls the data flow. The FET multiplexers/demultiplexers are disabled when the
output-enable (OE) input is high.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging
current does not backflow through the device when it is powered down. The device has isolation during power
off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN74CBTLV3257-EP
SCDS271 – MAY 2008 ....................................................................................................................................................................................................... www.ti.com
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–55°C to 125°C
(1)
(2)
TSSOP – PW
ORDERABLE PART NUMBER
Tape and reel
CCBTLV3257MPWREP
TOP-SIDE MARKING
C3257EP
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
FUNCTION TABLE
INPUTS
OE
FUNCTION
S
L
L
A port = B1 port
L
H
A port = B2 port
H
X
Disconnect
LOGIC DIAGRAM (POSITIVE LOGIC)
4
1A
2
1B1
SW
3
1B2
SW
7
2A
5
2B1
SW
6
2B2
SW
3A
9
11
SW
3B1
10
SW
12
4A
3B2
14
4B1
SW
13
SW
4B2
1
S
15
OE
2
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Product Folder Link(s): SN74CBTLV3257-EP
SN74CBTLV3257-EP
www.ti.com ....................................................................................................................................................................................................... SCDS271 – MAY 2008
SIMPLIFIED SCHEMATIC, EACH FET SWITCH
A
B
(OE)
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
VI
Input voltage range (2)
–0.5
4.6
V
128
mA
Continuous channel current
UNIT
V
IIK
Input clamp current
VIO < 0)
–50
mA
θJA
Package thermal impedance
PW package (3)
108
°C/W
Tstg
Storage temperature range
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
VCC
Supply voltage
VIH
High-level control input voltage
VIL
Low-level control input voltage
TA
Operating free-air temperature
(1)
MIN
MAX
2.3
3.6
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
V
V
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
–55
UNIT
125
V
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
VIK
VCC = 3 V,
II = –18 mA
–1.2
V
II
VCC = 3.6 V,
VI = VCC or GND
±1
µA
Ioff
VCC = 0,
VI or VO = 0 to 3.6 V
15
µA
ICC
VCC = 3.6 V,
IO = 0,
10
µA
(1)
VI = VCC or GND
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
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SN74CBTLV3257-EP
SCDS271 – MAY 2008 ....................................................................................................................................................................................................... www.ti.com
Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
ΔICC
(2)
Ci
Cio(OFF)
TEST CONDITIONS
Control inputs
VCC = 3.6 V,
Control inputs
VI = 3 V or 0
A port
B port
One input at 3 V,
OE = VCC
VCC = 2.3 V,
TYP at VCC = 2.5 V
VI = 0
VI = 1.7 V,
VI = 0
VCC = 3 V
VI = 2.4 V,
(2)
(3)
TYP (1)
Other inputs at VCC or
GND
MAX
UNIT
300
µA
3
VO = 3 V or 0,
ron (3)
MIN
pF
10.5
pF
5.5
II = 64 mA
5
8
II = 24 mA
5
8
II = 15 mA
27
40
II = 64 mA
5
7
II = 24 mA
5
7
II = 15 mA
10
15
Ω
This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND.
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
(1)
4
FROM
(INPUT)
TO
(OUTPUT)
A or B (1)
B or A
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
0.15
UNIT
MAX
0.25
ns
S
A or B
1.8
8.1
1.8
7.3
ten
S
A or B
1.7
7.5
1.7
6.5
ns
tdis
S
A or B
1
6.3
1
6.0
ns
ten
OE
A or B
1.9
7.1
2
6.2
ns
tdis
OE
A or B
1
7.0
1.6
6.5
ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
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SN74CBTLV3257-EP
www.ti.com ....................................................................................................................................................................................................... SCDS271 – MAY 2008
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
RL
LOAD CIRCUIT
VCC
CL
RL
V∆
2.5 V ± 0.2 V
3.3 V ± 0.3 V
30 pF
50 pF
500 Ω
500 Ω
0.15 V
0.3 V
VCC
Timing Input
VCC/2
0V
tw
tsu
th
VCC
VCC/2
Input
VCC/2
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VOH
Output
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VCC/2
0V
tPZL
tPLZ
VCC
VCC/2
tPZH
VOL + V∆
VOL
tPHZ
VCC/2
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CCBTLV3257MPWREP
Package Package Pins
Type Drawing
TSSOP
PW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CCBTLV3257MPWREP
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
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