LT3430/LT3430-1 - High Voltage, 3A, 200kHz/100kHz Step-Down Switching Regulators

LT3430/LT3430-1
High Voltage, 3A,
200kHz/100kHz Step-Down
Switching Regulators
DESCRIPTION
FEATURES
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Wide Input Range: 5.5V to 60V
3A Peak Switch Current over All Duty Cycles
Constant Switching Frequency:
200kHz (LT3430)
100kHz (LT3430-1)
0.1Ω Switch Resistance
Current Mode
Effective Supply Current: 2.5mA
Shutdown Current: 30µA
1.2V Feedback Reference Voltage
Easily Synchronizable
Cycle-by-Cycle Current Limiting
Small, 16-Pin Thermally Enhanced TSSOP Package
The LT®3430/LT3430-1 are monolithic buck switching
regulators that accept input voltages up to 60V. A high efﬁciency 3A, 0.1Ω switch is included on the die along with
all the necessary oscillator, control and logic circuitry. A
current mode architecture provides fast transient response
and excellent loop stability.
Special design techniques and a new high voltage process
achieve high efﬁciency over a wide input range. Efﬁciency
is maintained over a wide output current range by using
the output to bias the circuitry and by utilizing a supply
boost capacitor to saturate the power switch. Patented
circuitry* maintains peak switch current over the full duty
cycle range. A shutdown pin reduces supply current to
30µA and a SYNC pin can be externally synchronized with
a logic level input from 228kHz to 700kHz for the LT3430
or from 125kHz to 250kHz for the LT3430-1.
APPLICATIONS
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Industrial and Automotive Power Supplies
Portable Computers
Battery Chargers
Distributed Power Systems
The LT3430/LT3430-1 are available in a thermally enhanced
16-pin TSSOP package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
*US Patent # 6498466
TYPICAL APPLICATION
5V, 2A Buck Converter
Efﬁciency vs Load Current
100
MMSD914TI
VOUT = 5V
VIN = 12V
BOOST
22µH
VIN
4.7µF
100V
OFF ON
VOUT
5V
2A
SW
30BQ060
LT3430**
+
SHDN
BIAS
SYNC
FB
100µF 10V
SOLID
TANTALUM
EFFICIENCY (%)
VIN
5.5V*
TO 60V
90
0.68µF
80
VIN = 42V
70
15.4k
GND
60
LT3430-1 L = 68µH
LT3430 L =27µH
4.99k
VC
50
220pF
3.3k
0
0.5
1.5
2.0
1.0
LOAD CURRENT (A)
2.5
3430 TA02
0.022µF
3430 TA01
*FOR INPUT VOLTAGES BELOW 7.5V, SOME RESTRICTIONS MAY APPLY
** SEE LT3430-1 CIRCUIT IN APPLICATIONS INFORMATION SECTION
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LT3430/LT3430-1
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
TOP VIEW
Input Voltage (VIN) .................................................. 60V
BOOST Pin Above SW (Note 11) .............................. 35V
BOOST Pin Voltage ................................................. 68V
SYNC Voltage ............................................................. 7V
⎯S⎯H⎯D⎯N Voltage ............................................................ 6V
BIAS Pin Voltage ..................................................... 30V
FB Pin Voltage/Current .................................. 3.5V/2mA
Operating Junction Temperature Range
LT3430EFE (Notes 8, 10) .................. –40°C to 125°C
LT3430IFE (Notes 8, 10) .................. –40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................ 300°C
GND
1
16 GND
SW
2
15 SHDN
VIN
3
14 SYNC
VIN
4
SW
5
12 FB
BOOST
6
11 VC
NC
7
10 BIAS
GND
8
9
17
13 NC
GND
FE PACKAGE
16-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER PART NUMBER
FE PART MARKING
LT3430EFE
LT3430IFE
LT3430EFE-1
LT3430IFE-1
3430EFE
3430IFE
3430EFE-1
3430IFE-1
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TJ = 25°C. VIN = 15V, VC = 1.5V, ⎯S⎯H⎯D⎯N = 1V, BOOST = Open Circuit,
SW = Open Circuit, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Voltage (VREF)
VOL + 0.2 ≤ VC ≤ VOH – 0.2
5.5V ≤ VIN ≤ 60V
1.204
1.195
1.219
1.234
1.243
V
–0.2
–1.5
µA
●
●
FB Input Bias Current
Error Amp Voltage Gain
(Note 2)
Error Amp gm
dl (VC) = ±10µA
●
200
400
1650
1000
2200
VC to Switch gm
V/V
3300
4200
3.4
µMho
µMho
A/V
EA Source Current
FB = 1V
●
125
225
450
µA
EA Sink Current
FB = 1.4V
●
100
225
500
µA
VC Switching Threshold
Duty Cycle = 0
0.9
V
VC High Clamp
⎯S⎯H⎯D⎯N = 1V
2.1
V
Switch Current Limit
VC Open, Boost = VIN + 5V, FB = 1V
–40°C ≤ TJ ≤ 25°C
TJ = 125°C (Note 9)
Switch On Resistance
ISW = 2.5A, Boost = VIN + 5V (Note 7)
Maximum Switch Duty Cycle (LT3430)
FB = 1V
3
2.5
●
93
90
5
4
6.5
5.5
A
A
0.1
0.14
0.18
Ω
Ω
96
%
%
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LT3430/LT3430-1
ELECTRICAL CHARACTERISTICS
The ● denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TJ = 25°C. VIN = 15V, VC = 1.5V, ⎯S⎯H⎯D⎯N = 1V, BOOST = Open Circuit,
SW = Open Circuit, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
96
94
98
●
●
184
172
200
200
216
228
kHz
kHz
●
88
85
100
100
115
120
kHz
kHz
0.05
0.15
%/V
Maximum Switch Duty Cycle (LT3430-1)
Switch Frequency (LT3430)
VC Set to Give DC = 50%
Switch Frequency (LT3430-1)
●
MAX
UNITS
%
%
fSW Line Regulation
5.5V ≤ VIN ≤ 60V
fSW Shifting Threshold
Df = 10kHz
Minimum Input Voltage
(Note 3)
●
4.6
5.5
V
Minimum Boost Voltage
(Note 4) ISW ≤ 2.5A
●
1.8
3
V
Boost = VIN + 5V, ISW = 0.75A
Boost = VIN + 5V, ISW = 2.5A
●
●
25
75
50
120
mA
mA
Boost Current (Note 5)
0.8
V
Input Supply Current (IVIN)
(Note 6) VBIAS = 5V
1.5
2.2
mA
Bias Supply Current (IBIAS)
(Note 6) VBIAS = 5V
3.1
4.2
mA
Shutdown Supply Current
⎯S⎯H⎯D⎯N = 0V, VIN ≤ 60V, SW = 0V, VC Open
30
100
200
µA
µA
●
Lockout Threshold
VC Open
●
2.3
2.42
2.53
V
Shutdown Threshold
VC Open, Shutting Down
VC Open, Starting Up
●
●
0.15
0.25
0.37
0.42
0.58
0.60
V
V
Minimum SYNC Amplitude
1.5
V
SYNC Frequency Range (LT3430)
228
700
kHz
SYNC Frequency Range (LT3430-1)
125
250
kHz
SYNC Input Resistance
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Gain is measured with a VC swing equal to 200mV above the low
clamp level to 200mV below the upper clamp level.
Note 3: Minimum input voltage is not measured directly, but is guaranteed
by other tests. It is deﬁned as the voltage where internal bias lines are still
regulated so that the reference voltage and oscillator remain constant.
Actual minimum input voltage to maintain a regulated output will depend
upon output voltage and load current. See Applications Information.
Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 5: Boost current is the current ﬂowing into the BOOST pin with the
pin held 5V above input voltage. It ﬂows only during switch on time.
Note 6: Input supply current is the quiescent current drawn by the input
pin when the BIAS pin is held at 5V with switching disabled. Bias supply
current is the current drawn by the BIAS pin when the BIAS pin is held
at 5V. Total input referred supply current is calculated by summing input
supply current (IVIN) with a fraction of bias supply current (IBIAS):
ITOTAL = IVIN + (IBIAS)(VOUT/VIN)
With VIN = 15V, VOUT = 5V, IVIN = 1.4mA, IBIAS = 2.9mA, ITOTAL = 2.4mA.
20
kΩ
Note 7: Switch on resistance is calculated by dividing VIN to SW voltage
by the forced current (3A). See Typical Performance Characteristics for the
graph of switch voltage at other currents.
Note 8: The LT3430EFE/LT3430EFE-1 are guaranteed to meet performance
speciﬁcations from 0°C to 125°C junction temperature. Speciﬁcations over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT3430IFE/LT3430IFE-1 are guaranteed over the full –40°C to 125°C
operating junction temperature range.
Note 9: See Peak Switch Current Limit vs Junction Temperature graph in
the Typical Performance Characteristics section.
Note 10: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the speciﬁed maximum operating junction
temperature may impair device reliability.
Note 11: The maximum operational Boost-SW voltage is limited by
thermal and load current constraints. See ‘Boost Pin’ and ‘Thermal
Calculations’ in the Applications Information section.
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LT3430/LT3430-1
TYPICAL PERFORMANCE CHARACTERISTICS
Switch Peak Current Limit
⎯S⎯H⎯D⎯N Pin Bias Current
FB Pin Voltage and Current
1.234
6
250
2.0
TJ = 25°C
4
GUARANTEED MINIMUM
3
1.5
1.224
VOLTAGE
1.219
1.0
CURRENT
1.214
CURRENT (µA)
FEEDBACK VOLTAGE (V)
TYPICAL
CURRENT (µA)
SWITCH PEAK CURRENT (A)
5
150
100
0
20
40
60
DUTY CYCLE (%)
80
Lockout and Shutdown Threshold
0
50
100
–50 –25
25
75
0
JUNCTION TEMPERATURE (°C)
Shutdown Supply Current
Shutdown Supply Current
300
INPUT SUPPLY CURRENT (µA)
1.6
1.2
0.8
START-UP
0.4
INPUT SUPPLY CURRENT (µA)
VSHDN = 0V
35 TA = 25°C
LOCKOUT
125
3430 G03
40
2.4
SHDN PIN VOLTAGE (V)
0
125
3430 G02
3430 G01
2.0
AT 2.38V STANDBY THRESHOLD
(CURRENT FLOWS OUT OF PIN)
6
1.204
50
100
–50 –25
25
75
0
JUNCTION TEMPERATURE (°C)
100
12
0.5
1.209
2
CURRENT REQUIRED TO FORCE SHUTDOWN
(FLOWS OUT OF PIN). AFTER SHUTDOWN,
CURRENT DROPS TO A FEW µA
200
1.229
30
25
20
15
10
5
TA = 25°C
250
VIN = 60V
200
VIN = 15V
150
100
50
SHUTDOWN
0
–25
0
25
50
75
100
0
10
0
125
JUNCTION TEMPERATURE (°C)
20
30
40
INPUT VOLTAGE (V)
50
Error Ampliﬁer Transconductance
Frequency Foldback
200
600
PHASE
2500
1000
GAIN
2000
100
(
1500
1000
500
150
VFB 2 • 10
–3
)
ROUT
200k
VC
COUT
12pF
ERROR AMPLIFIER EQUIVALENT CIRCUIT
RLOAD = 50Ω
TA = 25°C
0
–50
–25
0
25
50
75
100
125
JUNCTION TEMPERATURE (°C)
3430 G07
50
500
100
1k
10k
100k
FREQUENCY (Hz)
1M
0
–50
10M
PHASE (DEG)
GAIN (µMho)
2000
0.5
3430 G06
Error Ampliﬁer Transconductance
3000
2500
1500
0.1
0.2
0.3
0.4
SHUTDOWN VOLTAGE (V)
3430 G05
3430 G04
TRANSCONDUCTANCE (µmho)
0
60
SWITICHING FREQUENCY (kHz)
OR FB CURRENT (µA)
0
–50
TA = 25°C
500
400
FB PIN
CURRENT
300
3430
200
3430-1
100
0
SWITCHING
FREQUENCY
0
0.5
1.0
1.5
VFB (V)
3430 G08
3430 G09
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LT3430/LT3430-1
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Input Voltage with
5V Output
Switching Frequency
230
7.5
(LT3430)
BOOST Pin Current
90
TA = 25°C
TA = 25°C
80
210
200
190
6.5
MINIMUM INPUT
VOLTAGE TO START
6.0
MINIMUM INPUT
VOLTAGE TO RUN
5.5
180
–25
0
50
25
75
100
5.0
125
0
JUNCTION TEMPERATURE (°C)
70
60
50
40
30
20
10
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (A)
3430 G10
0
0
1
2
SWITCH CURRENT (A)
3430 G11
VC Pin Shutdown Threshold
3
3430 G12
Switch Voltage Drop
2.1
450
1.9
400
SWITCH VOLTAGE (mV)
THRESHOLD VOLTAGE (V)
1.7
1.5
1.3
1.1
TJ = 125°C
350
300
TJ = 25°C
250
200
150
TJ = –40°C
100
0.9
50
0.7
50
100
–50 –25
25
75
0
JUNCTION TEMPERATURE (°C)
0
125
0
1
2
SWITCH CURRENT (A)
3430 G13
Switch Minimum ON Time
vs Temperature
Switch Peak Current Limit
600
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
–50
3
3430 G14
SWITCH MINIMUM ON TIME (ns)
170
–50
BOOST PIN CURRENT (mA)
INPUT VOLTAGE (V)
7.0
SWITCH PEAK CURRENT LIMIT (A)
FREQUENCY (kHz)
220
–25
0
25
50
75
100
125
JUNCTION TEMPERATURE (°C)
3430 G16
500
400
300
200
100
0
50
100
–50 –25
25
75
0
JUNCTION TEMPERATURE (°C)
125
3430 G15
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LT3430/LT3430-1
PIN FUNCTIONS
GND (Pins 1, 8, 9, 16, 17): The GND pin connections act
as the reference for the regulated output, so load regulation
will suffer if the “ground” end of the load is not at the same
voltage as the GND pins of the IC. This condition will occur
when load current or other currents ﬂow through metal
paths between the GND pins and the load ground. Keep the
paths between the GND pins and the load ground short and
use a ground plane when possible. The FE package has an
exposed pad that is fused to the GND pins. The pad (Pin
17) should be soldered to the copper ground plane under
the device to reduce thermal resistance. (See Applications
Information—Layout Considerations.)
SW (Pins 2, 5): The switch pin is the emitter of the on-chip
power NPN switch. This pin is driven up to the input pin
voltage during switch on time. Inductor current drives the
switch pin voltage negative during switch off time. Negative
voltage is clamped with the external catch diode. Maximum
negative switch voltage allowed is –0.8V.
VIN (Pins 3, 4): This is the collector of the on-chip power
NPN switch. VIN powers the internal control circuitry when
a voltage on the BIAS pin is not present. High dI/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the VIN pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductance in this path creates voltage spikes at switch
off, adding to the VCE voltage across the internal NPN.
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal bipolar
NPN power switch. Without this added voltage, the typical
switch voltage loss would be about 1.5V. The additional
BOOST voltage allows the switch to saturate and voltage
loss approximates that of a 0.1Ω FET structure.
NC (Pins 7, 13): No Connection.
BIAS (Pin 10): The BIAS pin is used to improve efﬁciency
when operating at higher input voltages and light load current. Connecting this pin to the regulated output voltage
forces most of the internal circuitry to draw its operating
current from the output voltage rather than the input supply.
This architecture increases efﬁciency especially when the
input voltage is much higher than the output. Minimum
output voltage setting for this mode of operation is 3V.
VC (Pin 11): The VC pin is the output of the error ampliﬁer
and the input of the peak switch current comparator. It is
normally used for frequency compensation, but can also
serve as a current clamp or control loop override. VC sits
at about 0.9V for light loads and 2.1V at maximum load.
It can be driven to ground to shut off the regulator, but if
driven high, current must be limited to 4mA.
FB (Pin 12): The feedback pin is used to set the output
voltage using an external voltage divider that generates
1.22V at the pin for the desired output voltage. Three
additional functions are performed by the FB pin. When
the pin voltage drops below 0.6V, switch current limit is
reduced and the external SYNC function is disabled. Below
0.8V, switching frequency is also reduced. See Feedback
Pin Functions in Applications Information for details.
SYNC (Pin 14): The SYNC pin is used to synchronize the
internal oscillator to an external signal. It is directly logic
compatible and can be driven with any signal between 10%
and 90% duty cycle. The synchronizing range is 125kHz
to 250kHz for the LT3430-1 and 228kHz to 700kHz for the
LT3430. See Synchronizing in Applications Information
for details.
⎯S⎯H⎯D⎯N (Pin 15): The ⎯S⎯H⎯D⎯N pin is used to turn off the
regulator and to reduce input drain current to a few microamperes. This pin has two thresholds: one at 2.38V to
disable switching and a second at 0.4V to force complete
micropower shutdown. The 2.38V threshold functions
as an accurate undervoltage lockout (UVLO); sometimes
used to prevent the regulator from delivering power until
the input voltage has reached a predetermined level.
If the ⎯S⎯H⎯D⎯N pin functions are not required, the pin can
either be left open (to allow an internal bias current to lift
the pin to a default high state) or be forced high to a level
not to exceed 6V.
34301fa
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LT3430/LT3430-1
BLOCK DIAGRAM
it much easier to frequency compensate the feedback loop
and also gives much quicker transient response.
The LT3430/LT3430-1 are constant frequency, current
mode buck converters. This means that there is an internal clock and two feedback loops that control the duty
cycle of the power switch. In addition to the normal error
ampliﬁer, there is a current sense ampliﬁer that monitors
switch current on a cycle-by-cycle basis. A switch cycle
starts with an oscillator pulse which sets the RS ﬂip-ﬂop
to turn the switch on. When switch current reaches a level
set by the inverting input of the comparator, the ﬂip-ﬂop
is reset and the switch turns off. Output voltage control is
obtained by using the output of the error ampliﬁer to set
the switch current trip point. This technique means that the
error ampliﬁer commands current to be delivered to the
output rather than voltage. A voltage fed system will have
low phase shift up to the resonant frequency of the inductor
and output capacitor, then an abrupt 180° shift will occur.
The current fed system will have 90° phase shift at a much
lower frequency, but will not have the additional 90° shift
until well beyond the LC resonant frequency. This makes
Most of the circuitry of the LT3430/LT3430-1 operates
from an internal 2.9V bias line. The bias regulator normally
draws power from the regulator input pin, but if the BIAS
pin is connected to an external voltage equal to or higher
than 3V, bias power will be drawn from the external source
(typically the regulated output voltage). This will improve
efﬁciency if the BIAS pin voltage is lower than regulator
input voltage.
High switch efﬁciency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing switch to be saturated.
This boosted voltage is generated with an external capacitor and diode. Two comparators are connected to the
shutdown pin. One has a 2.38V threshold for undervoltage
lockout and the second has a 0.4V threshold for complete
shutdown.
VIN
3, 4
BIAS 10
RSENSE
RLIMIT
2.9V BIAS
REGULATOR
–
+
INTERNAL
VCC
CURRENT
COMPARATOR
Σ
SLOPE COMP
SYNC 14
BOOST
ANTISLOPE COMP
6
SHUTDOWN
COMPARATOR
200kHz: LT3430
100kHz: LT3430-1
OSCILLATOR
S
RS
FLIP-FLOP
Q1
POWER
SWITCH
DRIVER
CIRCUITRY
–
R
+
0.4V
5.5µA
SW
+
2, 5
FREQUENCY
FOLDBACK
–
LOCKOUT
COMPARATOR
×1
2.38V
Q2
FOLDBACK
CURRENT
LIMIT
CLAMP
Q3
ERROR
AMPLIFIER
gm = 2000µMho
11
VC
12 FB
+
VC(MAX)
CLAMP
–
SHDN 15
1.22V
GND
1, 8, 9, 16, 17
3430 F01
Figure 1. LT3430/LT3430-1 Block Diagram
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7
LT3430/LT3430-1
APPLICATIONS INFORMATION
FEEDBACK PIN FUNCTIONS
The feedback (FB) pin on the LT3430/LT3430-1 is used to
set output voltage and provide several overload protection
features. The ﬁrst part of this section deals with selecting
resistors to set output voltage and the second part talks
about foldback frequency and current limiting created by
the FB pin. Please read both parts before committing to
a ﬁnal design.
The suggested value for the LT3430 output divider resistor
(see Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. For the LT3430-1, choose
the resistors so that the Thevinin resistance of the divider
at the feedback pin is 7.5kΩ. The output voltage error
caused by ignoring the input bias current on the FB pin
is less than 0.25% with R2 = 5k. A table of standard 1%
values is shown in Table 1 for common output voltages.
Please read the following if divider resistors are increased
above the suggested values.
R1 =
R2(VOUT − 1.22)
1.22
Table 1. *LT3430, **LT3430-1
OUTPUT
VOLTAGE
(V)
R2
(kΩ)
R1
(NEAREST 1%)
(kΩ)
% ERROR AT OUTPUT
DUE TO DISCREET 1%
RESISTOR STEPS
3*
4.99
7.32
+0.32
3.3*
4.99
8.45
–0.43
5*
4.99
15.4
–0.30
12*
4.12
46.4
–0.27
3**
12.7
18.7
+0.54
3.3**
12.1
20.5
–0.40
5**
10
30.9
–0.20
12**
8.25
73.2
+0.37
More Than Just Voltage Feedback
The feedback pin is used for more than just output voltage
sensing. It also reduces switching frequency and current
limit when output voltage is very low (see the Frequency
Foldback graph in Typical Performance Characteristics).
This is done to control power dissipation in both the IC
and in the external diode and inductor during short-circuit conditions. A shorted output requires the switching
regulator to operate at very low duty cycles, and the
average current through the diode and inductor is equal
to the short-circuit current limit of the switch (typically
4A for the LT3430/LT3430-1, folding back to less than
2A). Minimum switch on time limitations would prevent
the switcher from attaining a sufﬁciently low duty cycle if
switching frequency were maintained at 200kHz (100kHz
LT3430-1), so frequency is reduced by about 5:1 (3:1
LT3430-1) when the feedback pin voltage drops below
0.8V (see Frequency Foldback graph). This does not affect
operation with normal load conditions; one simply sees
a gear shift in switching frequency during start-up as the
output voltage rises.
In addition to lower switching frequency, the LT3430/
LT3430-1 also operate at lower switch current limit when
the feedback pin voltage drops below 0.6V. Q2 in Figure 2
performs this function by clamping the VC pin to a voltage
less than its normal 2.1V upper clamp level. This foldback
current limit greatly reduces power dissipation in the IC,
diode and inductor during short-circuit conditions. External
synchronization is also disabled to prevent interference
with foldback operation. Again, it is nearly transparent to
the user under normal load conditions. The only loads that
may be affected are current source loads which maintain
full load current with output voltage less than 50% of
ﬁnal value. In these rare situations the feedback pin can
be clamped above 0.6V with an external diode to defeat
foldback current limit. Caution: clamping the feedback
pin means that frequency shifting will also be defeated,
so a combination of high input voltage and dead shorted
output may cause the LT3430/LT3430-1 to lose control
of current limit.
The internal circuitry which forces reduced switching
frequency also causes current to ﬂow out of the feedback
pin when output voltage is low. The equivalent circuitry
is shown in Figure 2. Q1 is completely off during normal
operation. If the FB pin falls below 0.8V, Q1 begins to
conduct current and LT3430 reduces frequency at the rate
of approximately 1.4kHz/µA. To ensure adequate frequency
foldback (under worst-case short-circuit conditions), the
external divider Thevinin resistance (RTHEV) must be low
enough to pull 115µA out of the FB pin with 0.44V on
the pin (RTHEV ≤ 3.8k)(LT3430-1 RTHEV ≈ 7.5k). The net
result is that reductions in frequency and current limit
are affected by output voltage divider impedance. Cau34301fa
8
LT3430/LT3430-1
APPLICATIONS INFORMATION
LT3430
VSW
TO FREQUENCY
SHIFTING
1.4V
–
OUTPUT
5V
Q1
ERROR
AMPLIFIER
+
L1
R1
1.2V
R4
2k
R3
1k
FB
+
C1
BUFFER
Q2
R2
TO SYNC CIRCUIT
VC
GND
3430 F02
Figure 2. Frequency and Current Limit Foldback
tion should be used if resistors are increased beyond the
suggested values and short-circuit conditions occur with
high input voltage. High frequency pickup will increase
and the protection accorded by frequency and current
foldback will decrease.
Choosing the Inductor
For most applications, the output inductor will fall into
the range of 5µH to 47µH (10µH to 100µH for LT3430-1).
Lower values are chosen to reduce physical size of the
inductor. Higher values allow more output current because
they reduce peak current seen by the LT3430/LT3430-1
switch, which has a 3A limit. Higher values also reduce
output ripple voltage.
When choosing an inductor you will need to consider
output ripple voltage, maximum load current, peak inductor current and fault current in the inductor. In addition,
other factors such as core and copper losses, allowable
component height, EMI, saturation and cost should also
be considered. The following procedure is suggested
as a way of handling these somewhat complicated and
conﬂicting requirements.
20mV/DIV
VOUT USING
100µF CERAMIC
OUTPUT
CAPACITOR
20mV/DIV
VOUT USING
100µF 0.08Ω
TANTALUM
OUTPUT
CAPACITOR
VIN = 40V
VOUT = 5V
L = 22µH
2µs/DIV
3430 F03
Figure 3. LT3430 Output Ripple Voltage Waveforms.
Ceramic vs Tantalum Output Capacitors
ceramic output capacitor; the signiﬁcant decrease in output ripple voltage is due to the very low ESR of ceramic
capacitors.
Output ripple voltage is determined by ripple current (ILP-P)
through the inductor and the high frequency impedance of
the output capacitor. At high frequencies, the impedance
of the tantalum capacitor is dominated by its effective
series resistance (ESR).
Output Ripple Voltage
Tantalum Output Capacitor
Figure 3 shows a comparison of output ripple voltage for
the LT3430/LT3430-1 using either a tantalum or ceramic
output capacitor. It can be seen from Figure 3 that output
ripple voltage can be signiﬁcantly reduced by using the
The typical method for reducing output ripple voltage
when using a tantalum output capacitor is to increase the
inductor value (to reduce the ripple current in the inductor).
The following equations will help in choosing the required
34301fa
9
LT3430/LT3430-1
APPLICATIONS INFORMATION
inductor value to achieve a desirable output ripple voltage level. If output ripple voltage is of less importance,
the subsequent suggestions in Peak Inductor and Fault
Current and EMI will additionally help in the selection of
the inductor value.
Peak-to-peak output ripple voltage is the sum of a triwave
(created by peak-to-peak ripple current (ILP-P) times ESR)
and a square wave (created by parasitic inductance (ESL)
and ripple current slew rate). Capacitive reactance is assumed to be small compared to ESR or ESL.
VRIPPLE = (ILP-P )(ESR) + (ESL)
dI
dt
where:
ESR = equivalent series resistance of the output capacitor
ESL = equivalent series inductance of the output capacitor
dI/dt = slew rate of inductor ripple current = VIN/L
Peak-to-peak ripple current (ILP-P) through the inductor
and into the output capacitor is typically chosen to be
between 20% and 40% of the maximum load current. It
is approximated by:
(VOUT )(VIN – VOUT )
ILP-P =
(VIN )( f)(L)
Example: with VIN = 40V, VOUT = 5V, L = 22µH, ESR =
0.080Ω and ESL = 10nH, output ripple voltage can be
approximated as follows:
IP-P =
(5)(40 − 5)
(40)(22 • 10−6 )(200 • 103 )
40
dI
=
= 10 6 • 1.8
dt 22 • 10 − 6
= 0.99 A
An alternative way to further reduce output ripple voltage
is to reduce the ESR of the output capacitor by using a
ceramic capacitor. Although this reduction of ESR removes
a useful zero in the overall loop response, this zero can
be replaced by inserting a resistor (RC) in series with the
VC pin and the compensation capacitor CC. (See Ceramic
Capacitors in Applications Information.)
Peak Inductor Current and Fault Current
To ensure that the inductor will not saturate, the peak
inductor current should be calculated knowing the
maximum load current. An appropriate inductor should
then be chosen. In addition, a decision should be made
whether or not the inductor must withstand continuous
fault conditions.
If maximum load current is 1A, for instance, a 1A inductor may not survive a continuous 4A overload condition.
Dead shorts will actually be more gentle on the inductor
because the LT3430/LT3430-1 have frequency and current
limit foldback.
Table 2
VENDOR/
PART NO.
VALUE
(µH)
IDC
(Amps)
DCR
(Ohms)
HEIGHT
(mm)
CDRH104R-150
15
3.6
0.050
4
CDRH104R-220
22
2.9
0.073
4
CDRH104R-330
33
2.3
0.093
4
CDRH124-220
22
2.9
0.066
4.5
CDRH124-330
33
2.7
0.097
4.5
CDRH127-330
33
3.0
0.065
8
CDRH127-470
47
2.5
0.100
8
CEI122-220
22
2.3
0.085
8
UP3B-330
33
3
0.069
6.8
UP3B-470
47
2.4
0.108
6.8
UP4B-680
68
4.3
0.120
7.9
DO3316P-153
15
3
0.046
5.2
DO5022p-683
68
3.5
0.130
7.1
Sumida
Coiltronics
(
)( )
VRIPPLE = (0.99 A )(0.08) + 10 • 10 − 9 10 6 (1.8 )
= 0.079 + 0.018 = 97mVP-P
To reduce output ripple voltage further requires an increase
in the inductor value with the trade-off being a physically
larger inductor with the possibility of increased component
height and cost.
10
Ceramic Output Capacitor
Coilcraft
34301fa
LT3430/LT3430-1
APPLICATIONS INFORMATION
Peak switch and inductor current can be signiﬁcantly higher
than output current, especially with smaller inductors
and lighter loads, so don’t omit this step. Powdered iron
cores are forgiving because they saturate softly, whereas
ferrite cores saturate abruptly. Other core materials fall
somewhere in between. The following formula assumes
continuous mode of operation, but errs only slightly on
the high side for discontinuous mode, so it can be used
for all conditions.
IPEAK = IOUT +
(VOUT )(VIN – VOUT )
ILP-P
= IOUT +
2
(2)(VIN )( f)(L)
EMI
Decide if the design can tolerate an “open” core geometry
like a rod or barrel, which have high magnetic ﬁeld radiation,
or whether it needs a closed core like a toroid to prevent
EMI problems. This is a tough decision because the rods
or barrels are temptingly cheap and small and there are
no helpful guidelines to calculate when the magnetic ﬁeld
radiation will be a problem.
Additional Considerations
After making an initial choice, consider additional factors
such as core losses and second sourcing, etc. Use the
experts in Linear Technology’s Applications department
if you feel uncertain about the ﬁnal choice. They have experience with a wide range of inductor types and can tell
you about the latest developments in low proﬁle, surface
mounting, etc.
Maximum Output Load Current
Maximum load current for a buck converter is limited by
the maximum switch current rating (IP). The current rating
for the LT3430/LT3430-1 is 3A. Unlike most current mode
converters, the LT3430/LT3430-1 maximum switch current
limit does not fall off at high duty cycles. Most current
mode converters suffer a drop off of peak switch current
for duty cycles above 50%. This is due to the effects of
slope compensation required to prevent subharmonic
oscillations in current mode converters. (For detailed
analysis, see Application Note 19.)
The LT3430/LT3430-1 are able to maintain peak switch
current limit over the full duty cycle range by using patented
circuitry* to cancel the effects of slope compensation
on peak switch current without affecting the frequency
compensation it provides.
Maximum load current would be equal to maximum switch
current for an inﬁnitely large inductor, but with ﬁnite
inductor size, maximum load current is reduced by onehalf peak-to-peak inductor current (ILP-P). The following
formula assumes continuous mode operation, implying
that the term on the right is less than one-half of IP.
IOUT(MAX) =
Continuous Mode
IP –
( V + V )( V − V – V )
ILP-P
=IP − OUT F IN OUT F
2 (L )( f ) ( VIN )
2
For VOUT = 5V, VIN = 12V, VF(D1) = 0.52V, f = 200kHz and
L = 15µH:
IOUT (MAX) = 3 −
(5 + 0.52)(12 − 5 – 0.52)
2(15 • 10− 6)(200 • 103 )(12 )
= 3 − 0.5 = 2.5A
Note that there is less load current available at the higher
input voltage because inductor ripple current increases.
At VIN = 24V, duty cycle is 23% and for the same set of
conditions:
IOUT (MAX) = 3 −
(5 + 0.52)(24 − 5 – 0.52)
2(15 • 10− 6)(200 • 103 )(24 )
= 3 − 0.71 = 2.29A
To calculate actual peak switch current with a given set
of conditions, use:
ILP-P
2
(VOUT + VF )(VIN − VOUT – VF )
= IOUT +
2(L)( f)(VIN )
ISW(PEAK) = IOUT +
*US Patent # 6,498,466
34301fa
11
LT3430/LT3430-1
APPLICATIONS INFORMATION
Reduced Inductor Value and Discontinuous Mode
If the smallest inductor value is of most importance to a
converter design, in order to reduce inductor size/cost,
discontinuous mode may yield the smallest inductor solution. The maximum output load current in discontinuous
mode, however, must be calculated and is deﬁned later
in this section.
Discontinuous mode is entered when the output load
current is less than one-half of the inductor ripple current
(ILP-P). In this mode, inductor current falls to zero before
the next switch turn on (see Figure 8). Buck converters
will be in discontinuous mode for output load current
given by:
IOUT
<
Discontinuous Mode
(VOUT + VF )(VIN – VOUT – VF )
(2)(VIN )(f)(L)
The inductor value in a buck converter is usually chosen
large enough to keep inductor ripple current (ILP-P) low;
this is done to minimize output ripple voltage and maximize
output load current. In the case of large inductor values,
as seen in the equation above, discontinuous mode will
be associated with “light loads.”
When choosing small inductor values, however, discontinuous mode will occur at much higher output load currents.
The limit to the smallest inductor value that can be chosen
is set by the LT3430/LT3430-1 peak switch current (IP) and
the maximum output load current required, given by:
IOUT(MAX)
Discontinuous Mode
=<
ILP-P
2
IP2
=
(2)(ILP-P )
=
2(VOUT
IP2 ( f • L • VIN )
+ VF )(VIN – VOUT – VF )
Example: For VIN = 15V, VOUT = 5V, VF = 0.52V, f = 200kHz
and L = 4.7µH.
IOUT(MAX)
32 • (200 • 10 3)(4.7 • 10 −6)(15)
Discontinuous =
2(5 + 0.52)(15 – 5 – 0.52)
Mode
IOUT(MAX)
= 1.21A
Discontinuous Mode
What has been shown here is that if high inductor ripple
current and discontinuous mode operation can be tolerated,
small inductor values can be used. If a higher output load
current is required, the inductor value must be increased.
If IOUT(MAX) no longer meets the discontinuous mode
criteria, use the IOUT(MAX) equation for continuous mode;
the LT3430/LT3430-1 are designed to operate well in both
modes of operation, allowing a large range of inductor
values to be used.
Short-Circuit Considerations
The LT3430/LT3430-1 are current mode controllers. They
use the VC node voltage as an input to a current comparator which turns off the output switch on a cycle-by-cycle
basis as this peak current is reached. The internal clamp on
the VC node, nominally 2V, then acts as an output switch
peak current limit. This action becomes the switch current
limit speciﬁcation. The maximum available output power
is then determined by the switch current limit.
A potential controllability problem could occur under
short-circuit conditions. If the power supply output is
short circuited, the feedback ampliﬁer responds to the
low output voltage by raising the control voltage, VC, to its
peak current limit value. Ideally, the output switch would
be turned on, and then turned off as its current exceeded
the value indicated by VC. However, there is ﬁnite response
time involved in both the current comparator and turnoff
of the output switch. These result in a minimum on time
tON(MIN). When combined with the large ratio of VIN to
(VF + I • R), the diode forward voltage plus inductor I • R
voltage drop, the potential exists for a loss of control.
Expressed mathematically the requirement to maintain
control is:
f • tON ≤
VF + I • R
VIN
34301fa
12
LT3430/LT3430-1
APPLICATIONS INFORMATION
where:
f = switching frequency
tON = switch minimum on time
VF = diode forward voltage
VIN = Input voltage
I • R = inductor I • R voltage drop
If this condition is not observed, the current will not be
limited at IPK, but will cycle-by-cycle ratchet up to some
higher value. Using the nominal LT3430/LT3430-1 clock
frequencies of 200KHz/100kHz, a VIN of 40V and a (VF +
I • R) of say 0.7V, the maximum tON to maintain control
would be approximately 90ns for the LT3430 and 180ns
for the LT3430-1, unacceptably short times.
The solution to this dilemma is to slow down the oscillator when the FB pin voltage is abnormally low thereby
indicating some sort of short-circuit condition. Oscillator
frequency is unaffected until FB voltage drops to about
2/3 of its normal value. Below this point the oscillator
frequency decreases roughly linearly down to a limit of
about 40kHz. (30kHz for LT3430-1) This lower oscillator
frequency during short-circuit conditions can then maintain
control with the effective minimum on time.
It is recommended that for [VIN/(VOUT + VF)] ratios >
10, a soft-start circuit should be used for the LT3430 to
control the output capacitor charge rate during start-up
or during recovery from an output short circuit, thereby
adding additional control over peak inductor current. See
Buck Converter with Adjustable Soft-Start later in this
data sheet.
OUTPUT CAPACITOR
The output capacitor is normally chosen by its effective
series resistance (ESR), because this is what determines
output ripple voltage. To get low ESR takes volume, so
physically smaller capacitors have high ESR. The ESR
range for typical LT3430 applications is 0.05Ω to 0.2Ω.
A typical output capacitor is an AVX type TPS, 100µF at
10V, with a guaranteed ESR less than 0.1Ω (The LT3430-1
will typically use two of these capacitors in parallel). This
is a “D” size surface mount solid tantalum capacitor. TPS
capacitors are specially constructed and tested for low
ESR, so they give the lowest ESR for a given volume. The
value in microfarads is not particularly critical, and values
Table 3. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current
E Case Size
AVX TPS, Sprague 593D
ESR (Max., Ω )
Ripple Current (A)
0.1 to 0.3
0.7 to 1.1
0.1 to 0.3
0.7 to 1.1
0.2 (typ)
0.5 (typ)
D Case Size
AVX TPS, Sprague 593D
C Case Size
AVX TPS
from 22µF to greater than 500µF work well, but you cannot
cheat mother nature on ESR. If you ﬁnd a tiny 22µF solid
tantalum capacitor, it will have high ESR, and output ripple
voltage will be terrible. Table 3 shows some typical solid
tantalum surface mount capacitors.
Many engineers have heard that solid tantalum capacitors
are prone to failure if they undergo high surge currents. This
is historically true, and type TPS capacitors are specially
tested for surge capability, but surge ruggedness is not
a critical issue with the output capacitor. Solid tantalum
capacitors fail during very high turn-on surges, which
do not occur at the output of regulators. High discharge
surges, such as when the regulator output is dead shorted,
do not harm the capacitors.
Unlike the input capacitor, RMS ripple current in the output
capacitor is normally low enough that ripple current rating
is not an issue. The current waveform is triangular with
a typical value of 250mARMS. The formula to calculate
this is:
Output capacitor ripple current (RMS):
IRIPPLE(RMS) =
0.29(VOUT )(VIN − VOUT )
(L)( f)(VIN)
Ceramic Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available. They are generally chosen for their
good high frequency operation, small size and very low
ESR (effective series resistance). Their low ESR reduces
output ripple voltage but also removes a useful zero in the
loop frequency response, common to tantalum capacitors. To compensate for this, a resistor RC can be placed
in series with the VC compensation capacitor CC. Care
must be taken however, since this resistor sets the high
34301fa
13
LT3430/LT3430-1
APPLICATIONS INFORMATION
frequency gain of the error ampliﬁer, including the gain at
the switching frequency. If the gain of the error ampliﬁer
is high enough at the switching frequency, output ripple
voltage (although smaller for a ceramic output capacitor)
may still affect the proper operation of the regulator. A
ﬁlter capacitor CF in parallel with the RC/CC network is
suggested to control possible ripple at the VC pin. An “All
Ceramic” solution is possible for the LT3430/LT3430-1
by choosing the correct compensation components for
the given application.
Example: For VIN = 8V to 40V, VOUT = 5V at 2A, the LT3430
can be stabilized, provide good transient response and
maintain very low output ripple voltage using the following component values: (refer to the ﬁrst page of this data
sheet for component references) CIN = 4.7µF, RC = 3.3k,
CC = 22nF, CF = 220pF and COUT = 100µF. See Application
Note 19 for further detail on techniques for proper loop
compensation.
INPUT CAPACITOR
Step-down regulators draw current from the input supply
in pulses. The rise and fall times of these pulses are very
fast. The input capacitor is required to reduce the voltage ripple this causes at the input of LT3430/LT3430-1
and force the switching current into a tight local loop,
thereby minimizing EMI. The RMS ripple current can be
calculated from:
IRIPPLE(RMS) = IOUT VOUT (VIN – VOUT ) / VIN2
Ceramic capacitors are ideal for input bypassing. At
200kHz (100kHz) switching frequency, the energy storage
requirement of the input capacitor suggests that values
in the range of 4.7µF to 20µF (10µF to 47µF) are suitable
for most applications. If operation is required close to the
minimum input required by the output of the LT3430, a
larger value may be required. This is to prevent excessive
ripple causing dips below the minimum operating voltage
resulting in erratic operation.
Depending on how the LT3430/LT3430-1 circuit is powered
up you may need to check for input voltage transients.
The input voltage transients may be caused by input voltage
steps or by connecting the LT3430/LT3430-1 converter to
an already powered up source such as a wall adapter. The
sudden application of input voltage will cause a large surge
of current in the input leads that will store energy in the
parasitic inductance of the leads. This energy will cause the
input voltage to swing above the DC level of input power
source and it may exceed the maximum voltage rating of
input capacitor and LT3430/LT3430-1.
The easiest way to suppress input voltage transients is
to add a small aluminum electrolytic capacitor in parallel
with the low ESR input capacitor. The selected capacitor
needs to have the right amount of ESR in order to critically dampen the resonant circuit formed by the input lead
inductance and the input capacitor. The typical values of
ESR will fall in the range of 0.5Ω to 2Ω and capacitance
will fall in the range of 5µF to 50µF.
If tantalum capacitors are used, values in the 22µF to
470µF range are generally needed to minimize ESR and
meet ripple current and surge ratings. Care should be taken
to ensure the ripple and surge ratings are not exceeded.
The AVX TPS and Kemet T495 series are surge rated. AVX
recommends derating capacitor operating voltage by 2:1
for high surge applications.
CATCH DIODE
Highest efﬁciency operation requires the use of a Schottky
type diode. DC switching losses are minimized due to its
low forward voltage drop, and AC behavior is benign due
to its lack of a signiﬁcant reverse recovery time.
The use of so-called “ultrafast” recovery diodes is generally
not recommended. When operating in continuous mode,
the reverse recovery time exhibited by “ultrafast” diodes
will result in a slingshot type effect. The power internal
switch will ramp up VIN current into the diode in an attempt to get it to recover. Then, when the diode has ﬁnally
turned off, some tens of nanoseconds later, the VSW node
voltage ramps up at an extremely high dV/dt, perhaps 5 to
even 10V/ns ! With real world lead inductances, the VSW
node can easily overshoot the VIN rail. This can result in
34301fa
14
LT3430/LT3430-1
APPLICATIONS INFORMATION
poor RFI behavior and if the overshoot is severe enough,
damage the IC itself.
The suggested catch diode (D1) is an International Rectiﬁer 30BQ060 Schottky. It is rated at 3A average forward
current and 60V reverse voltage. Typical forward voltage
is 0.52V at 3A. The diode conducts current only during
switch off time. Peak reverse voltage is equal to regulator
input voltage. Average forward current in normal operation
can be calculated from:
ID(AVG) =
IOUT (VIN – VOUT )
VIN
This formula will not yield values higher than 3A with
maximum load current of 3A.
BOOST PIN
For most LT 3430 applications, the boost components are
a 0.68µF capacitor and a MMSD914TI diode. The anode
is typically connected to the regulated output voltage to
generate a voltage approximately VOUT above VIN to drive
the output stage. However, the output stage discharges
the boost capacitor during the on time of the switch. The
output driver requires at least 3V of headroom throughout
this period to keep the switch fully saturated. If the output
voltage is less than 3.3V, it is recommended that an alternate
boost supply is used. For output voltages greater than 6V,
it is recommended to place a zener diode (D4; page 20)
in series with the Boost diode to set Boost-to-SW voltage
between 4V to 6V. This minimizes power loss within the
IC, improving maximum ambient temperature operation.
In addition, D4 minimizes Boost current overshoot during
power switch turn on to reduce noise within the regulator loop. For output voltages greater than the standard
demoboard 5V output, a location for D4 is provided.
A 0.68µF boost capacitor is recommended for most LT3430
applications. Almost any type of ﬁlm or ceramic capacitor is suitable, but the ESR should be <1Ω to ensure it
can be fully recharged during the off time of the switch.
The LT3430 capacitor value is derived from conditions of
4800ns on time, 75mA boost current and 0.7V discharge
ripple. The boost capacitor value could be reduced under
less demanding conditions, but this will not improve circuit operation or efﬁciency. Under low input voltage and
low load conditions, a higher value capacitor will reduce
discharge ripple and improve start-up operation. For the
LT3430-1 a 1.5µF boost capacitor is recommended.
SHUTDOWN FUNCTION AND UNDERVOLTAGE
LOCKOUT
Figure 4 shows how to add undervoltage lockout (UVLO)
to the LT3430/LT3430-1. Typically, UVLO is used in situations where the input supply is current limited, or has
a relatively high source resistance. A switching regulator
draws constant power from the source, so source current increases as source voltage drops. This looks like a
negative resistance load to the source and can cause the
source to current limit or latch low under low source voltage
conditions. UVLO prevents the regulator from operating at
source voltages where these problems might occur.
Threshold voltage for lockout is about 2.38V. A 5.5µA
bias current ﬂows out of the pin at this threshold. The
internally generated current is used to force a default high
state on the shutdown pin if the pin is left open. When
low shutdown current is not an issue, the error due to this
current can be minimized by making RLO 10k or less. If
shutdown current is an issue, RLO can be raised to 100k,
but the error due to initial bias current and changes with
temperature should be considered.
R LO = 10k to 100k (25k suggested)
R HI =
RLO (VIN − 2.38V )
2.38V − R LO(5.5µA)
VIN = Minimum input voltage
Keep the connections from the resistors to the shutdown
pin short and make sure that interplane or surface capacitance to the switching nodes are minimized. If high resistor
values are used, the shutdown pin should be bypassed with
a 1000pF capacitor to prevent coupling problems from the
switch node. If hysteresis is desired in the undervoltage
lockout point, a resistor RFB can be added to the output
node. Resistor values can be calculated from:
34301fa
15
LT3430/LT3430-1
APPLICATIONS INFORMATION
RFB
L1
LT3430/LTC3430-1
2.38V
IN
INPUT
OUTPUT
VSW
+
STANDBY
RHI
–
5.5µA
+
SHDN
C1
+
TOTAL
SHUTDOWN
RLO
C2
0.4V
–
GND
3430 F04
Figure 4. Undervoltage Lockout
R HI =
[
RLO VIN − 2.38( ∆V/VOUT + 1) + ∆V
(
2.38 − RLO (5 .5µA )
R FB = (RHI ) VOUT /∆V
]
)
25k suggested for RLO
VIN = Input voltage at which switching stops as input
voltage descends to trip level
∆V = Hysteresis in input voltage level
Example: output voltage is 5V, switching is to stop if
input voltage drops below 12V and should not restart
unless input rises back to 13.5V. ∆V is therefore 1.5V and
VIN = 12V. Let RLO = 25k.
25k 12 − 2.38(1.5/5 + 1) + 1.5
R HI =
2.38 – 25k(5.5µA )
[
]
25k (10.41)
= 116k
2.24
R FB = 116k (5/1.5) = 387 k
=
SYNCHRONIZING
The SYNC input must pass from a logic level low, through
the maximum synchronization threshold with a duty cycle
between 10% and 90%. The input can be driven directly
from a logic level output. The LT3430 synchronizing range
is equal to initial operating frequency up to 700kHz. This
means that minimum practical sync frequency is equal to
the worst-case high self-oscillating frequency (228kHz), not
the typical operating frequency of 200kHz. Caution should
be used when synchronizing above 265kHz because at
higher sync frequencies the amplitude of the internal slope
compensation used to prevent subharmonic switching is
reduced. This type of subharmonic switching only occurs
at input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufﬁcient slope compensation. Application Note 19 has more details on the theory
of slope compensation. The LT3430-1 synchronizing range
is from 125kHz to 250kHz (slope compensation loss occurs above 133kHz).
At power-up, when VC is being clamped by the FB pin (see
Figure 2, Q2), the sync function is disabled. This allows
the frequency foldback to operate in the shorted output
condition. During normal operation, switching frequency is
controlled by the internal oscillator until the FB pin reaches
0.6V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
to ground.
34301fa
16
LT3430/LT3430-1
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS
ing this path will also reduce the parasitic trace inductance
of approximately 25nH/inch. At switch off, this parasitic
inductance produces a ﬂyback spike across the LT3430/
LT3430-1 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT3430/LT3430-1 that may exceed its
absolute maximum rating. A ground plane should always
be used under the switcher circuitry to prevent interplane
coupling and overall noise.
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efﬁciency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. This is
implemented in the suggested layout of Figure 6. ShortenLT3430/
LT3430-1
L1
5V
VIN
C3
HIGH
FREQUENCY
CIRCULATING
PATH
D1
C1
LOAD
3430 F05
Figure 5. High Speed Switching Path
1 GND
2 SW
3 VIN LT3430/
4 VIN LT3430-1
CONNECT TO
GROUND PLANE
GND
5 SW
L1
6 BOOST
VIN PINS 3 AND 4
ARE SHORTED TOGETHER.
SW PINS 2 AND 5 ARE ALSO
SHORTED TOGETHER (USING
AVAILABLE SPACE UNDERNEATH
THE DEVICE BETWEEN PINS AND
GND PLANE)
MINIMIZE
LT3430/LT3430-1
C3-D1 LOOP
GND
C1
D2
D1
1 GND
C3
GND 16
2 SW
15
3 VIN
14
13
4 VIN LT3430/
LT3430-1
SW
FB 12
5
6 BOOST
VIN
VOUT
C2
SHDN
BIAS 10
8 GND
GND 9
KELVIN SENSE
VOUT
SYNC
VC 11
7
SOLDER THE EXPOSED PAD
(PIN 17) TO THE ENTIRE COPPER
GROUND PLANE UNDERNEATH
THE DEVICE. NOTE: THE BOOST
AND BIAS COPPER TRACES ARE
ON A SEPARATE LAYER FROM
THE GROUND PLANE
R2
R1 CFB
CF
RC
PLACE FEEDTHROUGH AROUND
GROUND PINS (4 CORNERS) FOR
GOOD THERMAL CONDUCTIVITY
CC
KEEP FB AND VC COMPONENTS
AWAY FROM HIGH FREQUENCY,
HIGH CURRENT COMPONENTS
3430 F06
Figure 6. Suggested Layout
34301fa
17
LT3430/LT3430-1
APPLICATIONS INFORMATION
The VC and FB components should be kept as far away as
possible from the switch and boost nodes. The LT3430/
LT3430-1 pinout has been designed to aid in this. The
ground for these components should be separated from
the switch current path. Failure to do so will result in poor
stability or subharmonic like oscillation.
Board layout also has a signiﬁcant effect on thermal
resistance. Pins 1, 8, 9 and 16, GND, should be soldered
to a continuous copper ground plane under the LT3430/
LT3430-1 die. The FE package has an exposed pad (Pin
17) which is the best thermal path for heat out of the
package. Soldering the exposed pad to the copper ground
plane under the device will reduce die temperature and
increase the power capability of the LT3430/LT3430-1. Adding multiple solder ﬁlled feedthroughs under and around
the four corner pins to the ground plane will also help.
Similar treatment to the catch diode and coil terminations
will reduce any additional heating effects.
PARASITIC RESONANCE
Resonance or “ringing” may sometimes be seen on the
switch node (see Figure 7). Very high frequency ringing
following switch rise time is caused by switch/diode/input
capacitor lead inductance and diode capacitance. Schottky
diodes have very high “Q” junction capacitance that can
ring for many cycles when excited at high frequency. If
total lead length for the input capacitor, diode and switch
path is 1 inch, the inductance will be approximately 25nH.
At switch off, this will produce a spike across the NPN
output device in addition to the input voltage. At higher
currents this spike can be in the order of 10V to 20V
or higher with a poor layout, potentially exceeding the
absolute max switch voltage. The path around switch,
catch diode and input capacitor must be kept as short as
possible to ensure reliable operation. When looking at this,
a >100MHz oscilloscope must be used, and waveforms
should be observed on the leads of the package. This
switch off spike will also cause the SW node to go below
ground. The LT3430/LT3430-1 have special circuitry inside
which mitigates this problem, but negative voltages over
0.8V lasting longer than 10ns should be avoided. Note that
100MHz oscilloscopes are barely fast enough to see the
details of the falling edge overshoot in Figure 7.
A second, much lower frequency ringing is seen during
switch off time if load current is low enough to allow the
inductor current to fall to zero during part of the switch off
time (see Figure 8). Switch and diode capacitance resonate with the inductor to form damped ringing at 1MHz
to 10MHz. This ringing is not harmful to the regulator
and it has not been shown to contribute signiﬁcantly to
EMI. Any attempt to damp it with a resistive snubber will
degrade efﬁciency.
LT3430
SWITCH NODE
VOLTAGE
10mV/DIV
SW RISE
SW FALL
2V/DIV
INDUCTOR
CURRENT AT
IOUT = 0.1A
0.2A/DIV
50ns/DIV
VIN = 40V
VOUT = 5V
L = 22µH
1µs/DIV
3430 F08
3430 F07
Figure 7. Switch Node Resonance
Figure 8. Discontinuous Mode Ringing
34301fa
18
LT3430/LT3430-1
APPLICATIONS INFORMATION
THERMAL CALCULATIONS
Power dissipation in the LT3430/LT3430-1 chip comes
from four sources: switch DC loss, switch AC loss, boost
circuit current, and input quiescent current. The following formulas show how to calculate each of these losses.
These formulas assume continuous mode operation, so
they should not be used for calculating efﬁciency at light
load currents.
Switch loss:
TSSOP (Exposed Pad) Package: With a full plane under
the TSSOP package, thermal resistance will be about
45°C/W.
To calculate die temperature, use the proper thermal
resistance number for the desired package and add in
worst-case ambient temperature:
TJ = TA + (θJA • PTOT)
RSW (IOUT ) (VOUT )
=
+ tEFF (1/2)(IOUT )(VIN)( f)
VIN
2
PSW
Thermal resistance for the LT3430/LT3430-1 package is inﬂuenced by the presence of internal or backside planes.
When estimating ambient, remember the nearby catch
diode and inductor will also be dissipating power:
(VF )(VIN – VOUT )(ILOAD )
VIN
(Note: Switching losses are less for the LT3430-1 operating at only 100kHz)
PDIODE =
Boost current loss:
VOUT 2 (IOUT /36)
PBOOST =
VIN
VF = Forward voltage of diode (assume 0.52V at 2A)
Quiescent current loss:
PINDUCTOR = (ILOAD)2(RIND)
PDIODE =
PQ = VIN (0.0015) + VOUT (0.003 )
RIND = Inductor DC resistance (assume 0.1Ω)
PINDUCTOR (2)2(0.1) = 0.4W
RSW = Switch resistance (≈ 0.15) hot
tEFF = Effective switch current/voltage overlap time
= (tr + tf + tIr + tIf)
tr = (VIN/1.2)ns
tf = (VIN/1.1)ns
tIr = tIf = (IOUT/0.2)ns
f = Switch frequency
Only a portion of the temperature rise in the external
inductor and diode is coupled to the junction of the
LT3430. Based on empirical measurements, the thermal
effect on the LT3430 junction temperature due to power
dissipation in the external inductor and catch diode can
be calculated as:
Example: with VIN = 40V, VOUT = 5V and IOUT = 2A:
PSW
2
0.15)(2) (5)
(
=
+
(
)
(
90 •10 −9 (1/ 2)(2)(40) 200 •10 3
40
= 0.08 + 0.72 = 0.8W
PBOOST
2
5) (2 / 36)
(
=
= 0.04W
40
PQ = 40(0.0015) + 5(0.003) = 0.08W
(0.52)(40 – 5)(2)
= 0.91W
40
)
∆TJ(LT3430) ≈ (PDIODE + PINDUCTOR)(5°C/W)
Using the example calculations for LT3430 dissipation, the
LT3430 die temperature will be estimated as:
TJ = TA + (θJA • PTOT) + [5 • (PDIODE + PINDUCTOR)]
With the TSSOP package (θJA = 45°C/W), at an ambient
temperature of 50°C:
TJ = 50 + (45 • 0.92) + (5 • 1.31) = 98°C
Total power dissipation in the IC is given by:
PTOT = PSW + PBOOST + PQ
= 0.8W + 0.04W + 0.08W = 0.92W
Die temperature can peak for certain combinations of VIN,
VOUT and load current. While higher VIN gives greater
switch AC losses, quiescent and catch diode losses, a
34301fa
19
LT3430/LT3430-1
APPLICATIONS INFORMATION
lower VIN may generate greater losses due to switch DC
losses. In general, the maximum and minimum VIN levels
should be checked with maximum typical load current for
calculation of the LT3430/LT3430-1 die temperature. If a
more accurate die temperature is required, a measurement of the SYNC pin resistance (to GND) can be used.
The SYNC pin resistance can be measured by forcing a
voltage no greater than 0.5V at the pin and monitoring the
pin current over temperature in an oven. This should be
done with minimal device power (low VIN and no switching
(VC = 0V)) in order to calibrate SYNC pin resistance with
ambient (oven) temperature.
Note: Some of the internal power dissipation in the IC,
due to BOOST pin voltage, can be transferred outside
of the IC to reduce junction temperature, by increasing
the voltage drop in the path of the boost diode D2 (see
Figure 9). This reduction of junction temperature inside
the IC will allow higher ambient temperature operation for
a given set of conditions. BOOST pin circuitry dissipates
power given by:
PDISS BOOST Pin =
VOUT • (ISW / 36) • VC2
VIN
Typically VC2 (the boost voltage across the capacitor C2)
equals VOUT. This is because diodes D1 and D2 can be
considered almost equal, where:
section, the value of C2 was designed for a 0.7V droop in
VC2 = VDROOP. Hence, an output voltage as low as 4V would
still allow the minimum 3.3V for the boost function using
the C2 capacitor calculated. If a target output voltage of
12V is required, however, an excess of 8V is placed across
the boost capacitor which is not required for the boost
function but still dissipates additional power.
What is required is a voltage drop in the path of D2 to
achieve minimal power dissipation while still maintaining
minimum boost voltage across C2. A zener, D4, placed in
series with D2 (see Figure 9), drops voltage to C2.
Example : the BOOST pin power dissipation for a 20V input
to 12V output conversion at 2A is given by:
PBOOST =
12 • (2 / 36) • 12
= 0.4 W
20
If a 7V zener D4 is placed in series with D2, then power
dissipation becomes :
PBOOST =
12 • (2 / 36) • 5
= 0.167 W
20
For an FE package with thermal resistance of 45°C/W,
ambient temperature savings would be, T(ambient) sav-
D2
D4
VC2 = VOUT – VFD2 – (–VFD1) = VOUT
Hence the equation used for boost circuitry power dissipation given in the previous Thermal Calculations section
is stated as:
PDISS(BOOST)
VOUT • (ISW / 36)
=
• VOUT
VIN
Here it can be seen that boost power dissipation increases
as the square of VOUT. It is possible, however, to reduce
VC2 below VOUT to save power dissipation by increasing the
voltage drop in the path of D2. Care should be taken that
VC2 does not fall below the minimum 3.3V boost voltage
required for full saturation of the internal power switch.
For output voltages of 5V, VC2 is approximately 5V. During
switch turn on, VC2 will fall as the boost capacitor C2 is
dicharged by the BOOST pin. In the previous BOOST Pin
D2
C2
BOOST
VIN
L1
VIN
C3
VOUT
SW
D1
LT3430/
LT3430-1
SHDN
BIAS
SYNC
FB
R1
GND
+
C1
R2
VC
CF
RC
CC
3430 F09
Figure 9. BOOST Pin, Diode Selection
34301fa
20
LT3430/LT3430-1
APPLICATIONS INFORMATION
ings = 0.233W • 45°C/W = 11°C. The 7V zener should be
sized for excess of 0.233W operaton. The tolerances of
the zener should be considered to ensure minimum VC2
exceeds 3.3V + VDROOP.
Input Voltage vs Operating Frequency Considerations
The absolute maximum input supply voltage for the LT3430/
LT3430-1 is speciﬁed at 60V. This is based solely on internal
semiconductor junction breakdown effects. Due to internal
power dissipation, the actual maximum VIN achievable in
a particular application may be less than this.
A detailed theoretical basis for estimating internal power
loss is given in the section, Thermal Considerations. Note
that AC switching loss is proportional to both operating
frequency and output current. The majority of AC switching
loss is also proportional to the square of input voltage.
For example, while the combination of VIN = 40V, VOUT
= 5V at 2A and fOSC = 200kHz may be easily achievable,
simultaneously raising VIN to 60V and fOSC to 700kHz is
not possible. Nevertheless, input voltage transients up to
60V can usually be accommodated, assuming the resulting increase in internal dissipation is of insufﬁcient time
duration to raise die temperature signiﬁcantly.
A second consideration is controllability. A potential limitation occurs with a high step-down ratio of VIN to VOUT, as
this requires a correspondingly narrow minimum switch
on time. An approximate expression for this (assuming
continuous mode operation) is given as follows:
V +V
min tON = OUT F
VIN fOSC
( )
where:
VIN = input voltage
VOUT = output voltage
VF = Schottky diode forward drop
fOSC = switching frequency
A potential controllability problem arises if the LT3430/
LT3430-1 are called upon to produce an on time shorter
than it is able to produce. Feedback loop action will lower
then reduce the VC control voltage to the point where
some sort of cycle-skipping or odd/even cycle behavior
is exhibited.
In summary:
1. Be aware that the simultaneous requirements of high
VIN, high IOUT and high fOSC may not be achievable in
practice due to internal dissipation. The Thermal Considerations section offers a basis to estimate internal
power. In questionable cases a prototype supply should
be built and exercised to verify acceptable operation.
2. The simultaneous requirements of high VIN, low VOUT and
high fOSC can result in an unacceptably short minimum
switch on time. Cycle skipping and/or odd/even cycle
behavior will result although correct output voltage is
usually maintained. The LT3430-1 100kHz switching
frequency will allow higher VIN/VOUT ratios without
pulse skipping.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered—the
worse the board layout, the more difﬁcult the circuit will
be to stabilize. This is true of almost all high frequency
analog circuits, read the Layout Considerations section
ﬁrst. Common layout errors that appear as stability problems are distant placement of input decoupling capacitor
and/or catch diode, and connecting the VC compensation
to a ground track carrying signiﬁcant switch current. In
addition, the theoretical analysis considers only ﬁrst
order non-ideal component behavior. For these reasons,
it is important that a ﬁnal stability check is made with
production layout and components.
The LT3430/LT3430-1 use current mode control. This alleviates many of the phase shift problems associated with
the inductor. The basic regulator loop is shown in Figure
10. The LT3430/LT3430-1 can be considered as two gm
blocks, the error ampliﬁer and the power stage.
Figure 11 shows the overall loop response. At the VC
pin, the frequency compensation components used are:
RC = 3.3k, CC = 0.022µF and CF = 220pF. The output
capacitor used is a 100µF, 10V tantalum capacitor with
typical ESR of 100mΩ. LT3430-1 uses two of these
capacitors in parallel.
The ESR of the tantalum output capacitor provides a useful zero in the loop frequency response for maintaining
34301fa
21
LT3430/LT3430-1
APPLICATIONS INFORMATION
stability. This ESR, however, contributes signiﬁcantly to
the ripple voltage at the output (see Output Ripple Voltage
in the Applications Information section). It is possible to
reduce capacitor size and output ripple voltage by replacing the tantalum output capacitor with a ceramic output
capacitor because of its very low ESR. The zero provided
by the tantalum output capacitor must now be reinserted
back into the loop. Alternatively, there may be cases where,
even with the tantalum output capacitor, an additional
zero is required in the loop to increase phase margin for
improved transient response.
A zero can be added into the loop by placing a resistor (RC)
at the VC pin in series with the compensation capacitor,
CC, or by placing a capacitor (CFB) between the output
and the FB pin.
When using RC, the maximum value has two limitations.
First, the combination of output capacitor ESR and RC
may stop the loop rolling off altogether. Second, if the
loop gain is not rolled off sufﬁciently at the switching
frequency, output ripple will perturb the VC pin enough to
cause unstable duty cycle switching similar to subharmonic
oscillations. If needed, an additional capacitor (CF) can be
added across the RC/CC network from the VC pin to ground
to further suppress VC ripple voltage.
With a tantalum output capacitor, the LT3430/LT3430-1
already includes a resistor (RC) and ﬁlter capacitor (CF)
at the VC pin (see Figures 10 and 11) to compensate the
loop over the entire VIN range (to allow for stable pulse
skipping for high VIN-to-VOUT ratios ≥ 10). A ceramic output
capacitor can still be used with a simple adjustment to the
resistor RC for stable operation (see Ceramic Capacitors
section for stabilizing LT3430). If additional phase margin
is required, a capacitor (CFB) can be inserted between the
output and FB pin but care must be taken for high output
voltage applications. Sudden shorts to the output can create
unacceptably large negative transients on the FB pin.
For VIN-to-VOUT ratios < 10, higher loop bandwidths are
possible by readjusting the frequency compensation
components at the VC pin.
When checking loop stability, the circuit should be operated
over the application’s full voltage, current and temperature range. Proper loop compensation may be obtained
by empirical methods as described in Application Notes
19 and 76.
CONVERTER WITH BACKUP OUTPUT REGULATOR
In systems with a primary and backup supply, for example,
a battery powered device with a wall adapter input, the
output of the LT3430/LT3430-1 can be held up by the
backup supply with the LT3430/LT3430-1 input disconnected. In this condition, the SW pin will source current
into the VIN pin. If the ⎯S⎯H⎯D⎯N pin is held at ground, only the
shut down current of 30µA will be pulled via the SW pin
from the second supply. With the ⎯S⎯H⎯D⎯N pin ﬂoating, the
80
180
LT3430/LTC3430-1
60
OUTPUT
CFB
FB
TANTALUM CERAMIC
–
gm =
2000µmho
+
RO
200k
GND
40
R1
1.22V
RLOAD
20
90
PHASE
ESR
ESL
0
60
C1
C1
–20
30
R2
–40
CF
CC
3430 F10
Figure 10. Model for Loop Response
120
+
VC
RC
GAIN (dB)
ERROR
AMPLIFIER
150
GAIN
VSW
PHASE (DEG)
CURRENT MODE
POWER STAGE
gm = 2mho
10
100
1k
10k
100k
FREQUENCY (Hz)
VIN = 42V
RC = 3.3k
VOUT = 5V
CC = 22nF
ILOAD = 1A
CF = 220pF
COUT = 100µF, 10V, 0.1Ω
0
1M
3430 F11
Figure 11. Overall Loop Response
34301fa
22
LT3430/LT3430-1
APPLICATIONS INFORMATION
LT3430/LT3430-1 will consume their quiescent operating
current of 1.5mA. The VIN pin will also source current to
any other components connected to the input line. If this
load is greater than 10mA or the input could be shorted to
ground, a series Schottky diode must be added, as shown
in Figure 12. With these safeguards, the output can be held
at voltages up to the VIN absolute maximum rating.
output. Output rise time is controlled by the current through
CSS deﬁned by R4 and Q1’s VBE. Once the output is in
regulation, Q1 turns off and the circuit operates normally.
R3 is transient protection for the base of Q1.
(R4)(C SS )(VOUT )
Rise Time =
VBE
BUCK CONVERTER WITH ADJUSTABLE SOFT-START
Using the values shown in Figure 10,
47 • 103 15 • 10–9 (5)
Rise Time =
= 5ms
0.7
(
Large capacitive loads or high input voltages can cause
high input currents at start-up. Figure 13 shows a circuit
that limits the dv/dt of the output at start-up, controlling
the capacitor charge rate. The buck converter is a typical
conﬁguration with the addition of R3, R4, CSS and Q1. As
the output starts to rise, Q1 turns on, regulating switch
current via the VC pin to maintain a constant dv/dt at the
)(
)
The ramp is linear and rise times in the order of 100ms are
possible. Since the circuit is voltage controlled, the ramp
rate is unaffected by load characteristics and maximum
output current is unchanged. Variants of this circuit can
be used for sequencing multiple regulator outputs.
D2
MMSD914TI
D3
30BQ060
C2
0.68µF
33µH
BOOST
REMOVABLE
INPUT
VIN
LT3430
54k
SW
5V, 2A
BIAS
R1
15.4k
SHDN
SYNC
FB
VC
GND
25k
RC
3.3k
CC
0.022µF
C3
4.7µF
R2
4.99k
D1
30BQ060
+
ALTERNATE
SUPPLY
C1
100µF
10V
CF
220pF
3430 F12
Figure 12. Dual Source Supply with 25µA Reverse Leakage
D2
MMSD914TI
BOOST
INPUT
40V
C3
4.7µF
50V
CER
C2
0.68µF
BIAS
VIN
L1
33µH
SW
D1
C1
30BQ060 100µF
OR B250A 10V
LT3430
SHDN
SYNC GND
RC
3.3k
CC
0.022µF
+
R1
15.4k
OUTPUT
5V
2A
FB
R2
4.99k
VC
CF
220pF Q1
R3
2k
CSS
15nF
3430 F13
R4
47k
L1: CDRH104R-220M
Figure 13. Buck Converter with Adjustable Soft-Start
34301fa
23
LT3430/LT3430-1
APPLICATIONS INFORMATION
DUAL OUTPUT SEPIC CONVERTER
POSITIVE-TO-NEGATIVE CONVERTER
The circuit in Figure 14 generates both positive and negative
5V outputs with a single piece of magnetics. The two inductors shown are actually just two windings on a standard
Coiltronics inductor. The topology for the 5V output is a
standard buck converter. The – 5V topology would be a
simple ﬂyback winding coupled to the buck converter if
C4 were not present. C4 creates a SEPIC (single-ended
primary inductance converter) topology which improves
regulation and reduces ripple current in L1. Without C4,
the voltage swing on L1B compared to L1A would vary
due to relative loading and coupling losses. C4 provides a
low impedance path to maintain an equal voltage swing in
L1B, improving regulation. In a ﬂyback converter, during
switch on time, all the converter’s energy is stored in L1A
only, since no current ﬂows in L1B. At switch off, energy
is transferred by magnetic coupling into L1B, powering
the –5V rail. C4 pulls L1B positive during switch on time,
causing current to ﬂow, and energy to build in L1B and
C4. At switch off, the energy stored in both L1B and C4
supply the –5V rail. This reduces the current in L1A and
changes L1B current waveform from square to triangular.
For details on this circuit, including maximum output currents, see Design Note 100.
The circuit in Figure 15 is a positive-to-negative topology
using a grounded inductor. It differs from the standard
approach in the way the IC chip derives its feedback
signal because the LT3430/LT3430-1 accepts only positive feedback signals. The ground pin must be tied to the
regulated negative output. A resistor divider to the FB pin
then provides the proper feedback voltage for the chip.
The following equation can be used to calculate maximum
load current for the positive-to-negative converter:
IMAX
⎡
(VIN )(VOUT ) ⎤
⎢IP – 2(V
⎥(VOUT )(VIN – 0.15)
OUT + VIN )(f)(L)⎦
⎣
=
(VOUT + VIN – 0.15)(VOUT + VF )
IP = Maximum rated switch current
VIN = Minimum input voltage
VOUT = Output voltage
VF = Catch diode forward voltage
0.15 = Switch voltage drop at 3A
Example: with VIN(MIN) = 5.5V, VOUT = 12V, L = 10µH,
VF = 0.52V, IP = 3A: IMAX = 0.6A.
D2
MMSD914TI
C2
0.68µF
L1A*
25µH
BOOST
VIN
7.5V TO 60V
C3
4.7µF
100V
CERAMIC
VIN
VOUT
5V
SW
LT3430
R1
15.4k
SHDN
SYNC
GND
RC
3.3k
CC
0.022µF
+
C1
100µF
10V TANT
FB
R2
4.99k
VC
CF
220pF
D1
GND
* L1 IS A SINGLE CORE WITH TWO WINDINGS
COILTRONICS #CTX25-4A
†
IF LOAD CAN GO TO ZERO, AN OPTIONAL
PRELOAD OF 1k TO 5k MAY BE USED TO
IMPROVE LOAD REGULATION
D1, D3: 30BQ060
C4
100µF
10V
TANT
+
L1B*
C5
100µF
10V TANT
+
3430 F14
VOUT
–5V†
D3
Figure 14. Dual Output SEPIC Converter
34301fa
24
LT3430/LT3430-1
APPLICATIONS INFORMATION
D2†
MMSD914TI
INPUT
5.5V TO
44V
C2
0.68µF
BOOST
L1*
10µH
VSW
VIN
R1
36.5k
LT3430
GND
C3
4.7µF
100V
CER
Minimum inductor continuous mode:
(VIN )(VOUT )
LMIN =
⎡
⎛ (V
+ VF )⎞ ⎤
2(f)(VIN + VOUT )⎢IP – IOUT ⎜ 1 + OUT
⎟⎥
⎝
⎠⎦
VIN
⎣
D4
7V
VC
FB
CC
CF
D1
30BQ060
RC
D3
30BQ015
+
R2
4.12k
C1
100µF
16V TANT
OUTPUT**
–12V, 0.5A
* INCREASE L1 FOR HIGHER CURRENT APPLICATIONS.
SEE APPLICATIONS INFORMATION
** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE
AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION
3430 F15
Figure 15. Positive-to-Negative Converter
INDUCTOR VALUE
The criteria for choosing the inductor is typically based on
ensuring that peak switch current rating is not exceeded.
This gives the lowest value of inductance that can be
used, but in some cases (lower output load currents) it
may give a value that creates unnecessarily high output
ripple voltage.
The difﬁculty in calculating the minimum inductor size
needed is that you must ﬁrst decide whether the switcher
will be in continuous or discontinuous mode at the critical
point where switch current reaches 3A. The ﬁrst step is to
use the following formula to calculate the load current above
which the switcher must use continuous mode. If your
load current is less than this, use the discontinuous mode
formula to calculate minimum inductor needed. If load
current is higher, use the continuous mode formula.
Output current where continuous mode is needed:
ICONT >
(VIN )2 (IP )2
4(VIN + VOUT )(VIN + VOUT + VF )
Minimum inductor discontinuous mode:
2(V )(I )
LMIN = OUT 2OUT
(f)(IP )
For a 40V to –12V converter using the LT3430/LT34301 with peak switch current of 3A and a catch diode of
0.52V:
ICONT =
(40)2 (3)2
= 1.148A
4(40 + 12)(40 + 12 + 0.52)
For a load current of 0.5A, this says that discontinuous
mode can be used and the minimum inductor needed is
found from:
2(12)(0.5)
LMIN =
= 6.7µH
(200 • 103 )(3)2
In practice, the inductor should be increased by about
30% over the calculated minimum to handle losses and
variations in value. This suggests a minimum inductor of
10µH for this application.
Ripple Current in the Input and Output Capacitors
Positive-to-negative converters have high ripple current in
the input capacitor. For long capacitor lifetime, the RMS
value of this current must be less than the high frequency
ripple current rating of the capacitor. The following formula
will give an approximate value for RMS ripple current. This
formula assumes continuous mode and large inductor
value. Small inductors will give somewhat higher ripple
current, especially in discontinuous mode. The exact formulas are very complex and appear in Application Note
44, pages 29 and 30. For our purposes here I have simply
added a fudge factor (ff). The value for ff is about 1.2 for
higher load currents and L ≥15µH. It increases to about
2.0 for smaller inductors at lower load currents.
V
Capacitor IRMS = (ff)(IOUT ) OUT
VIN
ff = 1.2 to 2.0
The output capacitor ripple current for the positive-tonegative converter is similar to that for a typical buck
regulator—it is a triangular waveform with peak-to-peak
34301fa
25
LT3430/LT3430-1
APPLICATIONS INFORMATION
value equal to the peak-to-peak triangular waveform of the
inductor. The low output ripple design in Figure 15 places
the input capacitor between VIN and the regulated negative
output. This placement of the input capacitor signiﬁcantly
reduces the size required for the output capacitor (versus
placing the input capacitor between VIN and ground).
ESR of the chosen capacitor (see Output Ripple Voltage
in Applications Information).
Diode Current
Average diode current is equal to load current. Peak diode
current will be considerably higher.
The peak-to-peak ripple current in both the inductor and
output capacitor (assuming continuous mode) is:
IP-P =
Peak diode current:
Continuous Mode =
(V + V )
(VIN )(VOUT )
IOUT IN OUT +
2(L)(f)(VIN + VOUT )
VIN
DC • VIN
f •L
DC = Duty Cycle =
ICOUT (RMS) =
VOUT + VF
VOUT + VIN + VF
Discontinuous Mode =
IP-P
12
2(IOUT )(VOUT )
(L)(f)
Keep in mind that during start-up and output overloads,
average diode current may be much higher than with normal loads. Care should be used if diodes rated less than
1A are used, especially if continuous overload conditions
must be tolerated.
The output ripple voltage for this conﬁguration is as low
as the typical buck regulator based predominantly on the
inductor’s triangular peak-to-peak ripple current and the
TYPICAL APPLICATION
3.3V, 2A Buck Converter
MMSD914TI
6
VIN
5.5V*
TO 60V
1.5µF
BOOST
3, 4
VIN
4.7µF
100V
SW
OFF ON
14
+
SHDN
BIAS
SYNC
FB
GND
1, 8, 9, 16
VOUT
3.3V
2A
30BQ060
LT3430-1
15
68µH
2, 5
10
12
20.5k
100µF 10V
SOLID
TANTALUM
2 IN PARALLEL
12.1k
VC
11
220pF
3.3k
0.022µF
3430 F16
*FOR INPUT VOLTAGES BELOW 7.5V, SOME RESTRICTIONS MAY APPLY
34301fa
26
LT3430/LT3430-1
PACKAGE DESCRIPTION
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BB
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
3.58
(.141)
16 1514 13 12 1110
6.60 ±0.10
9
2.94
(.116)
4.50 ±0.10
2.94 6.40
(.116) (.252)
BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
0.25
REF
1.10
(.0433)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE16 (BB) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
34301fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3430/LT3430-1
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1074/LT1074HV
4.4A (IOUT), 100kHz, High Efﬁciency Step-Down DC/DC
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VIN: 7.3V to 45V/64V, VOUT(MIN): 2.21V, IQ: 8.5mA, ISD: 10µA DD-5/7,
TO220-5/7
LT1076/LT1076HV
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VIN: 7.3V to 45V/64V, VOUT(MIN): 2.21V, IQ: 8.5mA, ISD: 10µA DD-5/7,
TO220-5/7
LT1676
60V, 440mA (IOUT), 100kHz, High Efﬁciency Step-Down
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VIN: 7.4V to 60V, VOUT(MIN): 1.24V, IQ: 3.2mA, ISD: 2.5µA, S8
LT1765
25V, 2.75A (IOUT), 1.25MHz, High Efﬁciency Step-Down
DC/DC Converter
VIN: 3V to 25V, VOUT(MIN): 1.20V, IQ: 1mA, ISD: 15µA, S8, TSSOP16E
LT1766
60V, 1.2A (IOUT), 200kHz, High Efﬁciency Step-Down
DC/DC Converter
VIN: 5.5V to 60V, VOUT(MIN): 1.20V, IQ: 2.5mA, ISD: 25µA, TSSOP16/E
LT1767
25V, 1.2A (IOUT), 1.25MHz, High Efﬁciency Step-Down
DC/DC Converter
VIN: 3V to 25V, VOUT(MIN): 1.20V, IQ: 1mA, ISD: 6µA, MS8/E
LT1776
40V, 550mA (IOUT), 200kHz, High Efﬁciency Step-Down
DC/DC Converter
VIN: 7.4V to 40V, VOUT(MIN): 1.24V, IQ: 3.2mA, ISD: 30µA, N8, S8
LT1940
25V, Dual 1.2A (IOUT), 1.1MHz, High Efﬁciency
Step-Down DC/DC Converter
VIN: 3V to 25V, VOUT(MIN): 1.2V, IQ: 3.8mA, ISD: <1µA, TSSOP16E
LT1956
60V, 1.2A (IOUT), 500kHz, High Efﬁciency Step-Down
DC/DC Converter
VIN: 5.5V to 60V, VOUT(MIN): 1.20V, IQ: 2.5mA, ISD: 25µA, TSSOP16/E
LT1976
60V, 1.2A (IOUT), 200kHz, High Efﬁciency Step-Down
DC/DC Converter with Burst Mode® Operation
VIN: 3.3V to 60V, VOUT(MIN): 1.20V, IQ: 100µA, ISD: <1µA, TSSOP16/E
LT3010
80V, 50mA Low Noise Linear Regulator
VIN: 1.5V to 80V, VOUT(MIN): 1.28V, IQ: 30µA, ISD: <1µA, MSE8
LTC3407
Dual 600mA (IOUT), 1.5MHz, Synchronous Step-Down
DC/DC Converter
VIN: 2.5V to 5.5V, VOUT(MIN): 0.6V, IQ: 40µA, ISD: <1µA, MS10E
LTC3412
2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC
Converter
VIN: 2.5V to 5.5V, VOUT(MIN): 0.8V, IQ: 60µA, ISD: <1µA, TSSOP16E
LTC3414
4A (IOUT), 4MHz, Synchronous Step-Down DC/DC
Converter
VIN: 2.3V to 5.5V, VOUT(MIN): 0.8V, IQ: 64µA, ISD: <1µA, TSSOP20E
LT3430/LT3431
60V, 2.75A (IOUT), 200kHz/500kHz, High Efﬁciency
Step-Down DC/DC Converters
VIN: 5.5V to 60V, VOUT(MIN): 1.20V, IQ: 2.5mA, ISD: 30µA, TSSOP16E
LT3433
60V, 400mA (IOUT), 200kHz, High Efﬁciency
Step-Up Step-Down DC/DC Converter with Burst Mode
Operation
VIN: 4V to 60V, VOUT(MIN): 3.3V to 20V, IQ: 100µA, ISD: <1µA, TSSOP16E
LTC3727/LTC3727-1 36V, 500kHz, High Efﬁciency Step-Down DC/DC
Controllers
VIN: 4V to 36V, VOUT(MIN): 0.8V, IQ: 670µA, ISD: 20µA, QFN-32, SSOP-28
Burst Mode is a registered trademark of Linear Technology Corporation.
34301fa
28 Linear Technology Corporation
LT 0107 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006

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