DS90UR903Q,DS90UR904Q DS90UR903Q/DS90UR904Q 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer Literature Number: SNLS346A DS90UR903Q/DS90UR904Q 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer General Description The DS90UR903Q/DS90UR904Q chipset offers a FPD-Link II interface with a high-speed forward channel for data transmission over a single differential pair. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE). The serializer converts 21 bit data over a single high-speed serial stream. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. The Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support ACCoupled interconnects. The Serializer is offered in a 40-pin lead in LLP and Deserializer is offered in a 48-pin LLP packages. Capable to drive up to 10 meters shielded twisted-pair I2C compatible serial interface for device configuration Single hardware device addressing pin LOCK output reporting pin to validate link integrity Integrated termination resistors 1.8V- or 3.3V-compatible parallel bus interface Single power supply at 1.8V ISO 10605 ESD and IEC 61000-4-2 ESD compliant Automotive grade product: AEC-Q100 Grade 2 qualified Temperature range −40°C to +105°C No reference clock required on Deserializer Programmable Receive Equalization EMI/EMC Mitigation — DES Programmable Spread Spectrum (SSCG) outputs — DES Receiver staggered outputs Applications ■ Automotive Display Systems Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 10 MHz to 43 MHz input PCLK support 210 Mbps to 903 Mbps data throughput Single differential pair interconnect Embedded clock with DC Balanced coding to support ACcoupled interconnects — Central Information Displays — Navigation Displays — Rear Seat Entertainment Typical Application Diagram 30164627 FIGURE 1. Typical Application Circuit TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation 301646 www.national.com DS90UR903Q/DS90UR904Q 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer September 22, 2011 DS90UR903Q/DS90UR904Q Block Diagrams 30164628 FIGURE 2. Block Diagram 30164629 FIGURE 3. Application Block Diagram www.national.com 2 NSID Quantity SPEC Package ID DS90UR903QSQE Package Description 40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch 250 NOPB SQA40A DS90UR903QSQ 40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch 1000 NOPB SQA40A DS90UR903QSQX 40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch 4500 NOPB SQA40A DS90UR904QSQE 48-pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch 250 NOPB SQA48A DS90UR904QSQ 48-pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch 1000 NOPB SQA48A DS90UR904QSQX 48-pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch 4500 NOPB SQA48A Note: Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies. Reliability qualification is compliant with the requirements and temperature grades defined in the AEC Q100 standard. Automotive Grade products are identified with the letter Q. For more information go to http://www.national.com/automotive. DS90UR903Q Pin Diagram 30164619 Serializer - DS90UR903Q — Top View 3 www.national.com DS90UR903Q/DS90UR904Q Ordering Information DS90UR903Q/DS90UR904Q DS90UR903Q Serializer Pin Descriptions Pin Name Pin No. I/O, Type Description LVCMOS PARALLEL INTERFACE DIN[20:0] PCLK 5, 4, 3, 2, 1, Inputs, LVCMOS Parallel data inputs. 40, 39, 38, 37, w/ pull down 36, 35, 33, 32, 30, 29, 28, 27, 26, 25, 24, 23 6 Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register. w/ pull down SERIAL CONTROL BUS - I2C COMPATIBLE SCL 7 Input, Open Drain Clock line for the serial control bus communication SCL requires an external pull-up resistor to VDDIO. SDA 8 Input/Output, Open Drain Data line for the serial control bus communication SDA requires an external pull-up resistor to VDDIO. MODE 12 ID[x] 9 I2C Mode select Input, LVCMOS MODE = H,- REQUIRED. The MODE pin must be set HIGH to allow I2C w/ pull down configuration of the serializer. Input, analog Device ID Address Select Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 3 CONTROL AND CONFIGURATION Power down Mode Input Pin. PDB = H, Serializer is enabled and is ON. Input, LVCMOS PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down, w/ pull down the PLL is shutdown, and IDD is minimized. Programmed control register data are NOT retained and reset to default values PDB 13 RES 10, 11 Input, LVCMOS Reserved. w/ pull down This pin MUST be tied LOW. 22, 21, 20, 19 No Connect NC FPD-LINK II INTERFACE DOUT+ 17 DOUT- 16 Output, CML Non-inverting differential output. The interconnect must be AC Coupled with a 100 nF capacitor. Output, CML Inverting differential output. The interconnect must be AC Coupled with a 100 nF capacitor. POWER AND GROUND VDDPLL 14 Power, Analog PLL Power, 1.8V ±5% VDDT 15 Power, Analog Tx Analog Power, 1.8V ±5% VDDCML 18 Power, Analog CML Power, 1.8V ±5% VDDD 34 Power, Digital Digital Power, 1.8V ±5% Power, Digital Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10% Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at the center of the LLP package. Connected to the ground plane (GND) with at least 16 vias. VDDIO VSS www.national.com 31 DAP 4 DS90UR903Q/DS90UR904Q DS90UR904Q Pin Diagram 30164620 Deserializer - DS90UR904Q — Top View 5 www.national.com DS90UR903Q/DS90UR904Q DS90UR904Q Deserializer Pin Descriptions Pin Name Pin No. I/O, Type Description LVCMOS PARALLEL INTERFACE ROUT[20:0] PCLK 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 19, 21, 22, 23, 24, 25, 26, 27, 28 4 Outputs, LVCMOS Parallel data outputs. Output, LVCMOS Pixel Clock Output Pin. Strobe edge set by RRFB control register. SERIAL CONTROL BUS - I2C COMPATIBLE SCL 2 Input, Open Drain Clock line for the serial control bus communication SCL requires an external pull-up resistor to VDDIO. SDA 1 Input/Output, Open Drain Data line for the serial control bus communication SDA requires an external pull-up resistor to VDDIO. I2C Mode select MODE 47 ID[x] 48 Input, LVCMOS MODE = H -REQUIRED. The MODE pin must be set HIGH to allow I2C configuration w/ pull up of the deserializer. Input, analog Device ID Address Select Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 4 CONTROL AND CONFIGURATION PDB LOCK 35 34 RES 37, 38, 39, 43, 44, 46 NC 30, 31, 32, 33 Power down Mode Input Pin. PDB = H, Deserializer is enabled and is ON. Input, LVCMOS PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power w/ pull down Down. Programmed control register data are NOT retained and reset to default values. Output, LVCMOS - LOCK Status Output Pin. LOCK = H, PLL is Locked, outputs are active LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by OSS_SEL control register. May be used as Link Status. Reserved. Pin 46: This pin MUST be tied LOW. Pin 37, 43, 44: Leave pin open. Pins 38, 39: Route to test point or leave open if unused. No Connect FPD-LINK II INTERFACE RIN+ 41 Input, CML Noninverting differential input. The interconnect must be AC Coupled with a 100 nF capacitor. RIN- 42 Inputt, CML Inverting differential input. The interconnect must be AC Coupled with a 100 nF capacitor. www.national.com 6 Pin No. I/O, Type Description POWER AND GROUND VDDSSCG 3 Power, Digital SSCG Power, 1.8V ±5% Power supply must be connected regardless if SSCG function is in operation. VDDIO1/2/3 29, 20, 7 Power, Digital LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10% VDDD 17 Power, Digital Digital Core Power, 1.8V ±5% VDDR 36 Power, Analog Rx Analog Power, 1.8V ±5% VDDCML 40 Power, Analog 1.8V ±5% VDDPLL 45 Power, Analog PLL Power, 1.8V ±5% DAP Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at the center of the LLP package. Connected to the ground plane (GND) with at least 16 vias. VSS 7 www.national.com DS90UR903Q/DS90UR904Q Pin Name DS90UR903Q/DS90UR904Q ESD Rating (ISO10605) Absolute Maximum Ratings (Note 1) Air Discharge (DOUT+, DOUT-, RIN+, RIN-) Contact Discharge (DOUT+, DOUT-, RIN+, RIN-) ESD Rating (HBM) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage – VDDn (1.8V) Supply Voltage – VDDIO LVCMOS Input Voltage I/O Voltage CML Driver I/O Voltage (VDD) CML Receiver I/O Voltage (VDD) Junction Temperature Storage Temperature Maximum Package Power Dissipation Capacity Package Package Derating: DS90UR903Q 40L LLP −0.3V to +2.5V −0.3V to +4.0V 6.8 °C/W θJA (based on 16 thermal vias) 26.9 °C/W θJC (based on 16 thermal vias) ESD Rating (IEC 61000-4-2) 4.4 °C/W Air Discharge (DOUT+, DOUT-, RIN+, RIN-) Contact Discharge (DOUT+, DOUT-, RIN+, RIN-) ESD Rating (ISO10605) ≥±8 kV ≥±1 kV ≥±250 V For soldering specifications: see product folder at www.national.com and www.national.com/ms/MS/MS-SOLDERING.pdf Recommended Operating Conditions 1/θJA °C/W above +25° θJC (based on 16 thermal vias) DS90UR904Q 48L LLP ≥±10 kV ESD Rating (MM) −0.3V to (VDD + 0.3V) +150°C −65°C to +150°C 30.7 °C/W ≥±15 kV ESD Rating (CDM) −0.3V to + (VDDIO + 0.3V) −0.3V to +(VDD + 0.3V) θJA (based on 16 thermal vias) RD = 2KΩ, CS = 150/330pF Supply Voltage (VDDn) LVCMOS Supply Voltage (VDDIO) OR LVCMOS Supply Voltage (VDDIO) Supply Noise VDDn (1.8V) VDDIO (1.8V) VDDIO (3.3V) Operating Free Air Temperature (TA) PCLK Clock Frequency RD = 330Ω, CS = 150pF ≥±25 kV ≥±10 kV Min 1.71 Nom 1.8 Max 1.89 Units V 1.71 1.8 1.89 V 3.0 3.3 3.6 V 25 25 50 mVp-p mVp-p mVp-p +105 °C 43 MHz -40 +25 10 RD = 330Ω, CS = 150/330pF Electrical Characteristics (Note 2, Note 3, Note 4) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, CONTROL INPUTS AND OUTPUTS) VIH High Level Input Voltage VIN = 3.0V to 3.6V 2.0 VIN V VIL Low Level Input Voltage VIN = 3.0V to 3.6V GND 0.8 V IIN Input Current VIN = 0V or 3.6V VIN = 3.0V to 3.6V -20 +20 µA VOH High Level Output Voltage VDDIO = 3.0V to 3.6V IOH = -4 mA 2.4 VDDIO V VOL Low Level Output Voltage VDDIO = 3.0V to 3.6V IOL = +4 mA GND 0.4 V IOS Output Short Circuit Current VOUT = 0V IOZ PDB = 0V, TRI-STATE® Output Current VOUT = 0V or VDD ±1 -39 -20 ±1 mA +20 µA LVCMOS DC SPECIFICATIONS 1.8V I/O (SER INPUTS, DES OUTPUTS, CONTROL INPUTS AND OUTPUTS) VIH High Level Input Voltage VIN = 1.71V to 1.89V 0.65 VIN VIN +0.3 VIL Low Level Input Voltage VIN = 1.71V to 1.89V GND 0.35 VIN IIN Input Current VIN = 0V or 1.89V VIN = 1.71V to 1.89V -20 www.national.com 8 ±1 +20 V µA Parameter Conditions Min Typ Max Units VOH High Level Output Voltage VDDIO = 1.71V to 1.89V IOH = −4 mA VDDIO 0.45 VDDIO V VOL Low Level Output Voltage VDDIO = 1.71V to 1.89V IOL = +4 mA GND 0.45 V IOS Output Short Circuit Current VOUT = 0V IOZ TRI-STATE® Output Current PDB = 0V, VOUT = 0V or VDD -20 mA -20 ±1 +20 µA 268 340 412 mV 50 mV CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-) |VOD| Output Differential Voltage RT = 100Ω (Figure 7) ΔVOD Output Differential Voltage Unbalance RL = 100Ω 1 VOS Output Differential Offset Voltage RL = 100Ω (Figure 7) VDD (MIN) V VDD - VOD DD (MAX) VOD (MAX) VOD (MIN) V ΔVOS Offset Voltage Unbalance RL = 100Ω 1 mV IOS Output Short Circuit Current DOUT+/- = 0V RT Differential Internal Termination Resistance Differential across DOUT+ and DOUT- 50 -27 80 100 mA 120 Ω CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-) VTH Differential Threshold High Voltage (Figure 8) +90 mV VTL Differential Threshold Low Voltage VIN Differential Input Voltage Range RIN+ - RIN- Input Current VIN = VDD or 0V, VDD = 1.89V Differential Internal Termination Resistance Differential across RIN+ and RIN- IIN RT -90 180 mV -20 ±1 +20 µA 80 100 120 Ω 62 90 SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD IDDT Serializer (Tx) VDDn Supply Current (includes load current) RT = 100Ω WORST CASE pattern (Figure 5) VDDn = 1.89V PCLK = 43 MHz Default Registers RT = 100Ω RANDOM PRBS-7 pattern IDDIOT IDDTZ IDDIOTZ Serializer (Tx) VDDIO Supply Current (includes load current) RT = 100Ω WORST CASE pattern (Figure 5) Serializer (Tx) Supply Current PDB = 0V; All other Power-down LVCMOS Inputs = 0V 9 mA 55 VDDIO = 1.89V PCLK = 43 MHz Default Registers 2 VDDIO = 3.6V PCLK = 43 MHz Default Registers 7 15 VDDn = 1.89V 370 775 VDDIO = 1.89V 55 125 VDDIO = 3.6V 65 135 5 mA µA www.national.com DS90UR903Q/DS90UR904Q Symbol DS90UR903Q/DS90UR904Q Symbol IDDR Parameter Conditions Deserializer (Rx) VDDn VDDn = 1.89V Supply Current (includes load CL = 8 pF current) WORST CASE Pattern (Figure 5) Min Typ Max 60 96 PCLK = 43 MHz SSCG[3:0] = ON Default Registers VDDn = 1.89V PCLK = 43 MHz Default Registers CL = 8 pF RANDOM PRBS-7 Pattern IDDIOR IDDRZ IDDIORZ Deserializer (Rx) VDDIO VDDIO = 1.89V Supply Current (includes load CL = 8 pF current) WORST CASE Pattern (Figure 5) PCLK = 43 MHz Default Registers VDDIO = 3.6V CL = 8 pF WORST CASE Pattern PDB = 0V; All other LVCMOS Inputs = 0V Deserializer (Rx) Supply Current Power-down Units 53 mA 21 32 PCLK = 43 MHz Default Registers 49 83 VDDn = 1.89V 42 400 VDDIO = 1.89V 8 40 VDDIO = 3.6V 350 800 µA Recommended Serializer Timing for PCLK (Note 12) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min Typ Max Units 23.3 T 100 ns Transmit Clock Input High Time 0.4T 0.5T 0.6T ns tTCIL Transmit Clock Input Low Time 0.4T 0.5T 0.6T ns tCLKT PCLK Input Transition Time (Figure 9) 3 ns fOSC Internal oscillator clock source tTCP Transmit Clock Period tTCIH www.national.com Conditions 10 MHz – 43 MHz 0.5 25 10 MHz Over recommended operating supply and temperature ranges unless otherwise specified. Typ Max Units tLHT Symbol CML Low-to-High Transition Time Parameter RL = 100Ω (Figure 6) Conditions 150 330 ps tHLT CML High-to-Low Transition Time RL = 100Ω (Figure 6) 150 330 ps tDIS Data Input Setup to PCLK tDIH Serializer Data Inputs Data Input Hold from PCLK (Figure 10) tPLD Serializer PLL Lock Time RL = 100Ω (Note 5, Note 11) tSD Serializer Delay RT = 100Ω PCLK = 10–43 MHz Register 0x03h b[0] (TRFB = 1) (Figure 12) tJIND tJINR tJINT λSTXBW δSTX δSTXf Serializer Output Deterministic Jitter Min 2.0 ns 2.0 ns 6.386T +5 1 2 ms 6.386T + 12 6.386T + 19.7 ns Serializer output intrinsic deterministic jitter . Measured (cycle-cycle) with PRBS-7 test pattern PCLK = 43 MHz (Note 4, Note 13) 0.13 UI Serializer Output Random Jitter Serializer output intrinsic random jitter (cycle-cycle). Alternating-1,0 pattern. PCLK = 43 MHz (Note 4, Note 13) 0.04 UI Peak-to-peak Serializer Output Jitter Serializer output peak-to-peak jitter includes deterministic jitter, random jitter, and jitter transfer from serializer input. Measured (cycle-cycle) with PRBS-7 test pattern. PCLK = 43 MHz (Note 4, Note 13) 0.396 UI Serializer Jitter Transfer Function -3 dB Bandwidth PCLK = 43 MHz Default Registers (Figure 18) (Note 4) 1.90 MHz Serializer Jitter Transfer Function (Peaking) PCLK = 43 MHz Default Registers (Figure 18 ) (Note 4) 0.944 dB Serializer Jitter Transfer Function (Peaking Frequency) PCLK = 43 MHz Default Registers (Figure 18) (Note 4) 500 kHz 11 www.national.com DS90UR903Q/DS90UR904Q Serializer Switching Characteristics DS90UR903Q/DS90UR904Q Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. tRCP Receiver Output Clock Period tRCP = tTCP PCLK tPDC PCLK Duty Cycle Default Registers SSCG[3:0] = OFF PCLK tCLH tCHL tCLH tCHL LVCMOS Low-to-High Transition VDDIO: 1.71V to 1.89V or PCLK Time 3.0 to 3.6V, LVCMOS High-to-Low Transition CL = 8 pF (lumped load) Default Registers Time (Figure 14) (Note 10) LVCMOS Low-to-High Transition VDDIO: 1.71V to 1.89V or Deserializer ROUTn Time Data Outputs 3.0 to 3.6V, LVCMOS High-to-Low Transition CL = 8 pF (lumped load) Default Registers Time (Figure 14) (Note 10) tROS ROUT Setup Data to PCLK tROH ROUT Hold Data to PCLK VDDIO: 1.71V to 1.89V or Deserializer ROUTn Data Outputs 3.0V to 3.6V, CL = 8 pF (lumped load) Default Registers Typ Max Units T 100 ns 45 50 55 % 1.3 2.0 2.8 1.3 2.0 2.8 1.6 2.4 3.3 1.6 2.4 3.3 0.38T 0.5T 0.38T 0.5T 4.571T +8 4.571T + 12 ns ns ns tDD Deserializer Delay Default Registers Register 0x03h b[0] (RRFB = 1) (Figure 15) tDDLT Deserializer Data Lock Time (Figure 13) (Note 5) 10 MHz–43 MHz tRJIT Receiver Input Jitter Tolerance (Figure 17, Figure 19) (Note 13, Note 14) 43 MHz tRCJ Receiver Clock Jitter PCLK SSCG[3:0] = OFF (Note 6, Note 10) 10 MHz PCLK SSCG[3:0] = OFF (Note 7, Note 10) 10 MHz Deserializer Cycle-to-Cycle Clock PCLK Jitter SSCG[3:0] = OFF (Note 8, Note 10) 10 MHz fdev Spread Spectrum Clocking Deviation Frequency 20 MHz–43 MHz ±0.5% to ±2.0% % fmod Spread Spectrum Clocking Modulation Frequency 20 MHz–43 MHz 9 kHz to 66 kHz kHz tDPJ tDCCJ Deserializer Period Jitter www.national.com 10 MHz–43 MHz Min 23.3 43 MHz 43 MHz 43 MHz LVCMOS Output Bus SSC[3:0] = ON (Figure 20) 12 4.571T + 16 ns 10 ms 0.53 UI 300 550 120 250 425 600 320 480 320 500 300 500 ps ps ps Over recommended supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units 100 kHz RECOMMENDED INPUT TIMING REQUIREMENTS (Note 12) fSCL SCL Clock Frequency tLOW SCL Low Period tHIGH >0 fSCL = 100 kHz 4.7 µs SCL High Period 4.0 µs tHD:STA Hold time for a start or a repeated start condition 4.0 µs tSU:STA Set Up time for a start or a repeated start condition 4.7 µs tHD:DAT Data Hold Time tSU:DAT Data Set Up Time 250 tSU:STO Set Up Time for STOP Condition 4.0 tr SCL & SDA Rise Time 1000 tf SCL & SDA Fall Time 300 ns Cb Capacitive load for bus 400 pF 3.45 µs 0 3.45 µs ns µs ns SWITCHING CHARACTERISTICS (Note 11) tHD:DAT Data Hold Time tSU:DAT Data Set Up Time tf SCL & SDA Fall Time 0 250 ns 300 ns 30164636 FIGURE 4. Serial Control Bus Timing Serial Control Bus DC Characteristics (SCL, SDA) - I2C Compliant Over recommended supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions VIH Input High Level SDA and SCL VIL Input Low Level Voltage SDA and SCL VHY Input Hysteresis SDA and SCL IOZ TRI-STATE Output Current PDB = 0V VOUT = 0V or VDD IIN Input Current Max Units 0.7 x VDDIO Min Typ VDDIO V GND 0.3 x VDDIO V >50 SDA or SCL, Vin = VDDIO or GND 13 mV -20 ±1 +20 µA -20 ±1 +20 µA www.national.com DS90UR903Q/DS90UR904Q Serial Control Bus AC Timing Specifications (SCL, SDA) - I2C Compliant (Figure 4) DS90UR903Q/DS90UR904Q Symbol Parameter CIN Input Pin Capacitance VOL Low Level Output Voltage Conditions Min Typ Max <5 Units pF SCL and SDA VDDIO = 3.0V IOL = 1.5mA 0.36 V SCL and SDA VDDIO = 1.71V IOL = 1mA 0.36 V Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional; the device should not be operated beyond such conditions. Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 3: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Note 4: Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 5: tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK Note 6: tDCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE). Note 7: tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples. Note 8: tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples. Note 9: Supply noise testing was done with minimum capacitors (as shown on Figures 27, 28) on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 1 MHz. The Des on the other hand shows no error when the noise frequency is less than 750 kHz. Note 10: Specification is guaranteed by characterization and is not tested in production. Note 11: Specification is guaranteed by design. Note 12: Recommended Input Timing Requirements are input specifications and not tested in production. Note 13: UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency. Note 14: tRJIT max (0.61UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI. www.national.com 14 DS90UR903Q/DS90UR904Q AC Timing Diagrams and Test Circuits 30164652 FIGURE 5. “Worst Case” Test Pattern 30164646 30164647 FIGURE 6. Serializer CML Output Load and Transition Times 15 www.national.com DS90UR903Q/DS90UR904Q 30164648 30164630 FIGURE 7. Serializer VOD DC Diagram 30164634 FIGURE 8. Differential VTH/VTL Definition Diagram 30164616 FIGURE 9. Serializer Input Clock Transition Times www.national.com 16 DS90UR903Q/DS90UR904Q 30164649 FIGURE 10. Serializer Setup/Hold Times 30164632 FIGURE 11. Serializer Data Lock Time 30164650 FIGURE 12. Serializer Delay 30164613 FIGURE 13. Deserializer Data Lock Time 17 www.national.com DS90UR903Q/DS90UR904Q 30164614 FIGURE 14. Deserializer LVCMOS Output Load and Transition Times 30164611 FIGURE 15. Deserializer Delay 30164631 FIGURE 16. Deserializer Output Setup/Hold Times 30164658 FIGURE 17. Receiver Input Jitter Tolerance www.national.com 18 DS90UR903Q/DS90UR904Q 30164662 FIGURE 18. Typical Serializer Jitter Transfer Function Curve at 43 MHz 30164659 FIGURE 19. Typical Deserializer Input Jitter Tolerance Curve at 43 MHz 30164635 FIGURE 20. Spread Spectrum Clock Output Profile 19 www.national.com DS90UR903Q/DS90UR904Q TABLE 1. DS90UR903Q Control Registers Addr (Hex) 0 Name Reset R/W Default 7:1 DEVICE ID 0 SER ID SEL 7:3 RESERVED 2 RESERVED 1 DIGITAL RESET0 RW 1: Resets the device to default register values. Does not 0 self clear affect device I2C Bus or Device ID 0 DIGITAL RESET1 RW 0 1: Digital Reset, retains all register values self clear RW 0xB0'h RW Description 7-bit address of Serializer; 0x58'h (1011_000X'b) default 0: Device ID is from ID[x] 1: Register I2C Device ID overrides ID[x] 0x00'h Reserved 0 Reserved Reserved 7:0 RESERVED 0x20'h Reserved Reserved 7:6 RESERVED 11'b Reserved VDDIO Control 3 Field I2C Device ID 1 2 Bits 5 VDDIO CONTOL RW 1 Auto VDDIO detect Allows manual setting of VDDIO by register. 0: Disable 1: Enable (auto detect mode) VDDIO Mode 4 VDDIO MODE RW 1 VDDIO voltage set Only used when VDDIOCONTROL = 0 0: 1.8V 1: 3.3V RESERVED 3 RESERVED RW 1 Reserved RESERVED 2 RESERVED 0 Reserved 1 Switch over to internal 25 MHz Oscillator clock in the absence of PCLK 0: Disable 1: Enable 1 Pixel Clock Edge Select: 0: Parallel Interface Data is strobed on the Falling Clock Edge. 1: Parallel Interface Data is strobed on the Rising Clock Edge. PCLK_AUTO 1 PCLK_AUTO TRFB 0 4 Reserved 7:0 RESERVED 0x80'h Reserved 5 Reserved 7:0 RESERVED RW 0x40'h Reserved 6 Reserved 7:0 RESERVED RW 0xC0'h Reserved 7 Reserved 7:0 RESERVED RW 0x00'h Reserved 8 Reserved 7:0 RESERVED 0x00'h Reserved 9 Reserved 7:0 RESERVED 0x01'h Reserved A Reserved 7:0 RESERVED 0x00'h Reserved B Reserved 7:0 RESERVED 0x00'h Reserved Reserved 7:3 RESERVED 0x00'h Reserved PCLK Detect 2 PCLK DETECT Reserved 3 RESERVED Reserved 0 RESERVED D Reserved 7:0 E Reserved F Reserved 10 11 C TRFB RW RW 0 1: Valid PCLK detected 0: Valid PCLK not detected 0 Reserved 0 Reserved RESERVED 0x11'h Reserved 7:0 RESERVED 0x01'h Reserved 7:0 RESERVED 0x03'h Reserved Reserved 7:0 RESERVED 0x03'h Reserved Reserved 7:0 RESERVED 0x03'h Reserved www.national.com R R 20 Name Bits Field 12 Reserved 7:0 RESERVED 7:0 GPCR[7] GPCR[6] GPCR[5] GPCR[4] GPCR[3] GPCR[2] GPCR[1] GPCR[0] 13 General Purpose Control Reg R/W Default Description 0x03'h Reserved DS90UR903Q/DS90UR904Q Addr (Hex) 0: LOW 1: HIGH RW 0x00'h 21 www.national.com DS90UR903Q/DS90UR904Q TABLE 2. DS90UR904Q Control Registers Addr (Hex) 0 Name Bits Field R/W Default RW 0xC0'h 7:1 DEVICE ID 7-bit address of Deserializer; 0x60h (1100_000X) default 0 DES ID SEL 0: Device ID is from ID[x] 1: Register I2C Device ID overrides ID[x] 7:3 RESERVED 2 RESERVED I2C Device ID 1 Reset 0x00'h RW 0 Reserved Reserved 1 DIGITALRESET0 RW 1: Resets the device to default register values. Does not 0 self clear affect device I2C Bus or Device ID 0 DIGITALRESET1 RW 0 1: Digital Reset, retains all register values self clear RESERVED 7:6 RESERVED 00'b Auto Clock 5 AUTO_CLOCK RW 0 1: Output PCLK or Internal 25 MHz Oscillator clock 0: Only PCLK when valid PCLK present OSS Select 4 OSS_SEL RW 0 Output Sleep State Select 0: Outputs = TRI-STATE, when LOCK = L 1: Outputs = LOW , when LOCK = L 2 3 Description SSCG Select 0000: Normal Operation, SSCG OFF (default) 0001: fmod (kHz) PCLK/2168, fdev ±0.50% 0010: fmod (kHz) PCLK/2168, fdev ±1.00% 0011: fmod (kHz) PCLK/2168, fdev ±1.50% 0100: fmod (kHz) PCLK/2168, fdev ±2.00% 0101: fmod (kHz) PCLK/1300, fdev ±0.50% 0110: fmod (kHz) PCLK/1300, fdev ±1.00% 0111: fmod (kHz) PCLK/1300, fdev ±1.50% 1000: fmod (kHz) PCLK/1300, fdev ±2.00% 1001: fmod (kHz) PCLK/868, fdev ±0.50% 1010: fmod (kHz) PCLK/868, fdev ±1.00% 1011: fmod (kHz) PCLK/868, fdev ±1.50% 1100: fmod (kHz) PCLK/868, fdev ±2.00% 1101: fmod (kHz) PCLK/650, fdev ±0.50% 1110: fmod (kHz) PCLK/650, fdev ±1.00% 1111: fmod (kHz) PCLK/650, fdev ±1.50% SSCG 3:0 SSCG RESERVED 7:6 RESERVED VDDIO Control 5 VDDIO CONTROL RW 1 Auto voltage control 0: Disable 1: Enable (auto detect mode) VDDIO Mode 4 VDDIO MODE RW 0 VDDIO voltage set 0: 1.8V 1: 3.3V RESERVED 3 RESERVED RW 1 Reserved RESERVED 2 RESERVED RW 0 Reserved RESERVED 1 RESERVED 0 Reserved 1 Pixel Clock Edge Select 0: Parallel Interface Data is strobed on the Falling Clock Edge 1: Parallel Interface Data is strobed on the Rising Clock Edge. RRFB www.national.com 0 RRFB 0000'b Reserved 11'b RW 22 Reserved Name Bits Field R/W Description 0x00'h EQ Gain 00'h = ~0.0 dB 01'h = ~4.5 dB 03'h = ~6.5 dB 07'h = ~7.5 dB 0F'h = ~8.0 dB 1F'h = ~11.0 dB 3F'h = ~12.5 dB FF'h = ~14.0 dB RESERVED 0x00'h Reserved RESERVED 0 Reserved 000'b Reserved 4 EQ Control 7:0 EQ 5 RESERVED 7:0 RESERVED 7 RESERVED 6:4 RESERVED RW 6 Default RW RESERVED 3:0 RESERVED RW 1111'b Reserved 7 RESERVED 7:0 RESERVED RW 0xB0'h Reserved 8:17 RESERVED 7:0 RESERVED RW 0x00'h Reserved 18 RESERVED 7:0 RESERVED 0x00'h Reserved 19 RESERVED 7:0 RESERVED 0x01'h Reserved 1A RESERVED 7:0 RESERVED 0x00'h Reserved 1B RESERVED 7:0 RESERVED 0x00'h Reserved RESERVED 7:3 RESERVED 0x00'h Reserved RESERVED 2 RESERVED 0 Reserved Signal Detect Status 1 R 0 0: Active signal not detected 1: Active signal detected LOCK Pin Status 0 R 0 0: CDR/PLL Unlocked 1: CDR/PLL Locked 1D Reserved 7:0 RESERVED 0x17'h Reserved 1E Reserved 7:0 RESERVED 0x07'h Reserved 1F Reserved 7:0 RESERVED 0x01'h Reserved 20 Reserved 7:0 RESERVED 0x01'h Reserved 21 Reserved 7:0 RESERVED 0x01'h Reserved 22 Reserved 7:0 RESERVED 0x01'h Reserved 7:0 GPCR[7] GPCR[6] GPCR[5] GPCR[4] GPCR[3] GPCR[2] GPCR[1] GPCR[0] RW 1C DS90UR903Q/DS90UR904Q Addr (Hex) 0: LOW 1: HIGH 23 General Purpose Control Reg 24 RESERVED 0 RESERVED RW 0 Reserved 25 RESERVED 7:0 RESERVED R 0x00'h Reserved 26 RESERVED 7:6 RESERVED RW 00'b Reserved 5:0 RESERVED RW 0 Reserved 0x00'h 23 www.national.com DS90UR903Q/DS90UR904Q a 21 bit parallel video bus for 18-bit color depth (RGB666) display format. In a RGB666 configuration, 18 color bits (R [5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are supported across the serial link. The DS90UR903Q Serializer accepts a 21-bit parallel data bus. The parallel data is converted into a single differential link. The DS90UR904Q Deserializer extracts the clock/control information from the incoming data stream and reconstructs the 21-bit parallel data. Functional Description The DS90UR903Q/904Q FPD-Link II chipset is intended for video display applications. The Serializer/ Deserializer chipset operates from a 10 MHz to 43 MHz pixel clock frequency. The DS90UR903Q transforms a 21-bit wide parallel LVCMOS data bus into a single high-speed differential pair. The high-speed serial bit stream contains an embedded clock and DC-balance information which enhances signal quality to support AC coupling. The DS90UR904Q receives the single serial data stream and converts it back into a 21-bit wide parallel data bus. DISPLAY APPLICATION The DS90UR903Q/904Q chipset is intended for interface between a host (graphics processor) and a Display. It supports 30164606 FIGURE 21. Typical Display System Diagram is connected to the deserializer, while the CMOS image sensor provides data to the serializer. CAMERA APPLICATION Camera applications are also supported by the DS90UR903Q/904Q chipset. The host controller/processsor 30164640 FIGURE 22. Typical Camera System Diagram SERIAL FRAME FORMAT The DS90UR903Q/904Q chipset will transmit and receive a pixel of data in the following format: 30164661 FIGURE 23. Serial Bitstream for 28-bit Symbol www.national.com 24 six devices on the bus using only a single pin. The pin sets one of six possible addresses for each Serializer/Deserializer device. The pin must be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor and a pull down resistor (RID) of the recommended value to set the physical device address. The recommended maximum resistor tolerance is 0.1% worst case (0.2% total tolerance). DESCRIPTION OF SERIAL CONTROL BUS ID[X] ADDRESS DECODER The ID[x] pin is used to decode and set the physical slave address of the Serializer/Deserializer (I2C only) to allow up to 30164643 FIGURE 24. Serial Control Bus Connection TABLE 3. ID[x] Resistor Value – DS90UR903Q TABLE 4. ID[x] Resistor Value – DS90UR904Q ID[x] Resistor Value - DS90UR903Q Ser Resistor RID Ω (±0.1%) 0 GND Address 7'b (Note 11) ID[x] Resistor Value - DS90UR904Q Des Address 8'b 0 appended (WRITE) Resistor RID Ω (±0.1%) Address 7'b (Note 11) Address 8'b 0 appended (WRITE) 7b' 101 1000 (h'58) 8b' 1011 0000 (h'B0) 0 GND 7b' 110 0000 (h'60) 8b' 1100 0000 (h'C0) 2.0k 7b' 101 1001 (h'59) 8b' 1011 0010 (h'B2) 2.0k 7b' 110 0001 (h'61) 8b' 1100 0010 (h'C2) 4.7k 7b' 101 1010 (h'5A) 8b' 1011 0100 (h'B4) 4.7k 7b' 110 0010 (h'62) 8b' 1100 0100 (h'C4) 8.2k 7b' 101 1011 (h'5B) 8b' 1011 0110 (h'B6) 8.2k 7b' 110 0011 (h'63) 8b' 1101 0110 (h'C6) 12.1k 7b' 101 1100 (h'5C) 8b' 1011 1000 (h'B8) 12.1k 7b' 110 0100 (h'64) 8b' 1101 1000 (h'C8) 39.0k 7b' 101 1110 (h'5E) 8b' 1011 1100 (h'BC) 39.0k 7b' 110 0110 (h'66) 8b' 1100 1100 (h'CC) 25 www.national.com DS90UR903Q/DS90UR904Q The High Speed Serial Channel is a 28-bit symbol composed of 21 bits of data containing video data & control information transmitted from Serializer to Deserializer. CLK1 and CLK0 represent the embedded clock in the serial stream. CLK1 is always HIGH and CLK0 is always LOW. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized, balanced and scrambled. DS90UR903Q/DS90UR904Q PROGRAMMABLE CONTROLLER An integrated I2C slave controller is embedded in each of the DS90UR903Q Serializer and DS90UR904Q Deserializer. It must be used to access and program the extra features embedded within the configuration registers. Refer to Table 1 and Table 2 for details of control registers. EMI REDUCTION Des - Receiver Staggered Output The Receiver staggered outputs allows for outputs to switch in a random distribution of transitions within a defined window. Outputs transitions are distributed randomly. This minimizes the number of outputs switching simultaneously and helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall EMI. LVCMOS VDDIO OPTION 1.8V or 3.3V SER Inputs and DES Outputs are user selectable to provide compatibility with 1.8V and 3.3V system interfaces. Des Spread Spectrum Clocking The DS90UR904Q parallel data and clock outputs have programmable SSCG ranges from 9 kHz–66 kHz and ±0.5%– ±2% from 20 MHz to 43 MHz. The modulation rate and modulation frequency variation of output spread is controlled through the SSC control registers. POWERDOWN The SER has a PDB input pin to ENABLE or Powerdown the device. The modes can be controlled by the host and is used to disable the Link to save power when the remote device is not operational. An auto mode is also available. In this mode, the PDB pin is tied High and the SER switches over to an internal oscillator when the PCLK stops or not present. When a PCLK starts again, the SER will then lock to the valid input PCLK and transmits the data to the DES. In powerdown mode, the high-speed driver outputs are static (High). The DES has a PDB input pin to ENABLE or Powerdown the device. This pin can be controlled by the system and is used to disable the DES to save power. An auto mode is also available. In this mode, the PDB pin is tied High and the DES will enter powerdown when the serial stream stops. When the serial stream starts up again, the DES will lock to the input stream and assert the LOCK pin and output valid data. In powerdown mode, the Data and PCLK outputs are set by the OSS_SEL control register. PIXEL CLOCK EDGE SELECT (TRFB/RRFB) The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0, data is strobed on the Falling edge of the PCLK. POWER UP REQUIREMENTS AND PDB PIN It is required to delay and release the PDB input signal after VDD (VDDn and VDDIO) power supplies have settled to the recommended operating voltages. A external RC network can be connected to the PDB pin to ensure PDB arrives after all the VDD have stabilized. 30164651 FIGURE 25. Programmable PCLK Strobe Select SIGNAL QUALITY ENHANCERS Des - Receiver Input Equalization (EQ) The receiver inputs provided input equalization filter in order to compensate for loss from the media. The level of equalization is controlled via register setting. www.national.com 26 AC COUPLING The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme. Exter- 30164638 FIGURE 26. AC-Coupled Connection For high-speed FPD-Link II transmissions, the smallest available package should be used for the AC coupling capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require a 100 nF AC coupling capacitors to the line. TYPICAL APPLICATION CONNECTION Figure 27 shows a typical connection of the DS90UR903Q Serializer. 30164655 FIGURE 27. DS90UR903Q Typical Connection Diagram — Pin Control 27 www.national.com DS90UR903Q/DS90UR904Q nal AC coupling capacitors must be placed in series in the FPD-Link II signal path as illustrated in Figure 26. Applications Information DS90UR903Q/DS90UR904Q Figure 28 shows a typical connection of the DS90UR904Q Deserializer. 30164656 FIGURE 28. DS90UR904Q Typical Connection Diagram — Pin Control www.national.com 28 30164657 *Note: Equalization is enabled for cable lengths greater than 7 meters FIGURE 29. Rosenberger HSD & Leoni DACAR 538 Cable Performance A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency. Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs. Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential lines of 100 Ohms are typically recommended for differential interconnect. The closely coupled lines help to ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less. Information on the LLP style package is provided in National Application Note: AN-1187. PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the Ser/Des devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the tantalum capacitors should be at least 5X the power supply voltage being used. Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor will increase the inductance of the path. 29 www.national.com DS90UR903Q/DS90UR904Q Other cable parameters that may limit the cable's performance boundaries are: cable attenuation, near-end crosstalk and pair-to-pair skew. For obtaining optimal performance, we recommend: • Use Shielded Twisted Pair (STP) cable • 100Ω differential impedance and 24 AWG (or lower AWG) cable • Low skew, impedance matched • Ground and/or terminate unused conductors Figure 29 shows the Typical Performance Characteristics demonstrating various lengths and data rates using Rosenberger HSD and Leoni DACAR 538 Cable. TRANSMISSION MEDIA The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and signal quality requirements. The Ser/Des employ internal termination providing a clean signaling environment. The interconnect for FPD-Link II interface should present a differential impedance of 100 Ohms. Use of cables and connectors that have matched differential impedance will minimize impedance discontinuities. Shielded or un-shielded cables may be used depending upon the noise environment and application requirements. The chipset's optimum cable drive performance is achieved at 43 MHz at 10 meters length. The maximum signaling rate increases as the cable length decreases. Therefore, the chipset supports 50 MHz at shorter distances. DS90UR903Q/DS90UR904Q • Use differential connectors when operating above 500Mbps line speed • Maintain balance of the traces • Minimize skew within the pair Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the National web site at: www.national.com/lvds INTERCONNECT GUIDELINES See AN-1108 and AN-905 for full details. • Use 100Ω coupled differential pairs • Use the S/2S/3S rule in spacings – S = space between the pair – 2S = space between pairs – 3S = space to LVCMOS signal • Minimize the number of Vias www.national.com 30 DS90UR903Q/DS90UR904Q Physical Dimensions inches (millimeters) unless otherwise noted DS90UR903Q Serializer NS Package Number SQA40A DS90UR904Q Deserializer NS Package Number SQA48A 31 www.national.com DS90UR903Q/DS90UR904Q 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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