RT8881A

®
RT8881A
Dual-Channel, Multi-Phase PWM Controller with I2C Interface
for AMD SVI2 CPU Power Supply
General Description
Features
The RT8881A is a multi-phases PWM controller. Moreover,
it is compliant with AMD SVI2 Voltage Regulator
Specification to support both CPU core (VDD) and
Northbridge portion (VDDNB) of the CPU. The RT8881A
adopts the G-NAVPTM (Green-Native AVP), which is a
Richtek's proprietary topology. The G-NAVP makes it an
easy setting controller to meet all AMD AVP (Adaptive
Voltage Positioning) requirements. The droop is easily
programmed by setting the DC gain of the error amplifier.
With proper compensation, the load transient response
can achieve optimized AVP performance. The RT8881A
uses SVI2 interface to control 8-bit DAC to set output
voltage and operation mode, and support a dynamic
platform master. An I2C interface is available for advanced

power configuration and monitoring. The RT8881A also
features programmable power states with different sets of
operating phase number, over clocking offset, switching
frequency, load-line and protection setting. The platform
master can optimize the performance and efficiency of the
power according to different working scenarios via the I2C
interface. The RT8881A also provides power good
indication, over-current indication and dual OCP
mechanism for AMD SVI2 CPU core and NB. It also
features complete fault protection functions including overvoltage, under-voltage and negative-voltage protections.

















Dual Outputs :
 4/3/2/1-Phase for VDD
 2/1/0-Phase for VDDNB
G-NAVPTM Topology
Support Dynamic Load-Line and Zero Load-Line
Diode Emulation Mode at Light Load Condition
SVI2 Interface to Comply with AMD Power
Management Protocol
I2C Interface for Platform Configuration
Build-in ADC for VOUT and IOUT Reporting
Immediate OV, UV and NV Protections and UVLO
Programmable Dual OCP Mechanism
Accurate Current Balance
Fast Transient Response
Dynamic Phase Up/Down Control
Programmable Power State Control
Power Good Indicator
Over-Current Indicator
Over Clocking Offset Capabilities
52-Lead WQFN Package
RoHS Compliant and Halogen Free
Applications


AMD SVI2 CPU
Desktop Computer
Simplified Application Circuit
To CPU
To SMBUS
RT8881A
OCP_L
PHASE1
MOSFET
SVC
PHASE2
MOSFET
SVD
PWM3
RT9624A
MOSFET
SVT
PWM4
RT9624A
MOSFET
SCL
PWMA1
RT9624A
MOSFET
SDA
PWMA2
RT9624A
MOSFET
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8881A-01 January 2014
VVDD
VVDDNB
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT8881A
Ordering Information
Marking Information
RT8881A
RT8881AGQW : Product Number
RT8881A
GQW
YMDNN
Package Type
QW : WQFN-52L 6x6 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
YMDNN : Date Code
Note :
Richtek products are :

RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.
Pin Configurations
PWM3
BOOT2
UGATE2
PHASE2
LGATE2
PVCC
LGATE1
PHASE1
UGATE1
BOOT1
PWMA1
PWMA2
TONSETA
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
PWM4
TONSET
ISEN2P
ISEN2N
ISEN1N
ISEN1P
ISEN3P
ISEN3N
ISEN4N
ISEN4P
VSEN
FB
COMP
1
39
2
38
3
37
4
36
5
35
34
6
GND
7
33
8
32
9
31
10
53
30
11
29
12
28
13
27
PGOOD
PGOODA
EN
ISENA1P
ISENA1N
ISENA2N
ISENA2P
VSENA
FBA
COMPA
IBIAS
VCC
OCP_L
RGND
IMON
V064
IMONA
VDDIO
PWROK
SVC
SVD
SVT
SCL
SDA
SET1
SET2
14 15 16 17 18 19 20 21 22 23 24 25 26
WQFN-52L 6x6
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
2
is a registered trademark of Richtek Technology Corporation.
DS8881A-01 January 2014
RT8881A
Functional Pin Description
Pin No.
1, 52
Pin Name
Pin Function
PWM4, PWM3
PWM Outputs for Channel 3 and 4 of VDD Controller.
TONSET
VDD Controller On-Time Setting. Connect this pin to the converter input
voltage, Vin, through a resistor, RTON, to set the on-time of UGATE and
also the output voltage ripple of VDD controller.
5, 4, 8, 9
ISEN1N to ISEN4N
Negative Current Sense Input of Channel 1, 2, 3 and 4 for VDD Controller.
6, 3, 7, 10
ISEN1P to ISEN4P
Positive Current Sense Input of Channel 1, 2, 3 and 4 for VDD Controller.
11
VSEN
VDD Controller Voltage Sense Input. This pin is connected to the terminal
of VDD controller output voltage.
12
FB
Output Voltage Feedback Input of VDD Controller. This pin is the negative
input of the error amplifier for the VDD controller.
13
COMP
14
RGND
15
IMON
16
V064
Fixed 0.64V Reference Voltage Output. This voltage is only used to offset
the output voltage of IMON pin and IMONA pin. Connect a 0.47F
capacitor from this pin to GND.
17
IMONA
Current Monitor Output for the VDDNB Controller. This pin outputs a
voltage proportional to the output current.
18
VDDIO
Processor memory interface power rail and serves as the reference for
PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the
SVI pins.
19
PWROK
System Power Good Input. If PWROK is low, the SVI interface is disabled
and VR returns to BOOT-VID state with initial load line slope and initial
offset. If PWROK is high, the SVI interface is running and the DAC
decodes the received serial VID codes to determine the output voltage.
20
SVC
Serial VID Clock Input from Processor.
21
SVD
Serial VID Data input from Processor. This pin is a serial data line.
22
SVT
Serial VID Telemetry Input from VR. This pin is a push-pull output.
23
SCL
I C Clock Signal from Platform Master.
24
SDA
25
SET1
I C Data Signal. Bi-directional Data Signal from / to the Platform Master.
OCP_TDC threshold setting individually for VDD and VDDNB controllers
and also the internal ramp slew rate setting (RSET and RSETA)
individually for VDD and VDDNB controllers.
26
SET2
Quick response threshold (QRTH and QRTHA) setting individually for VDD
and VDDNB controllers and also the OCP_TDC trigger delay time setting
for both controllers and over clocking offset enable setting.
27
OCP_L
Over Current Indicator for Dual OCP Mechanism. This pin is an open-drain
output.
28
VCC
Controller Power Supply Input. Connect this pin to 5V with an 1F or
greater ceramic capacitor for decoupling.
2
Compensation Node of the VDD Controller.
Return Ground of VDD and VDDNB Controller. This pin is the common
negative input of output voltage differential remote sense for VDD and
VDDNB controllers.
Current Monitor Output for the VDD Controller. This pin outputs a voltage
proportional to the output current.
2
2
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8881A-01 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT8881A
Pin No.
Pin Name
Pin Function
29
IBIAS
Internal Bias Current Setting. Connect only a 100k resistor from this pin to
GND to generate bias current for internal circuit. Place this resistor as close to
the IBIAS pin as possible.
30
COMPA
Compensation Node of the VDDNB Controller.
31
FBA
Output Voltage Feedback Input of VDDNB Controller. This pin is the negative
input of the error amplifier for the VDDNB controller.
32
VSENA
VDDNB Controller Voltage Sense Input. This pin is connected to the terminal
of VDDNB controller output voltage.
33, 36
ISENA2P,
ISENA1P
Positive Current Sense Input of Channel 1 and 2 for VDDNB Controller.
34, 35
ISENA2N,
ISENA1N
Negative Current Sense Input of Channel 1 and 2 for VDDNB Controller.
37
EN
Controller Enable Control Input. A logic high signal enables the controller.
38
PGOODA
Power Good Indicator for the VDDNB Controller. This pin is an open-drain
output.
39
PGOOD
Power Good Indicator for the VDD Controller. This pin is an open-drain output.
40
TONSETA
VDDNB Controller On-Time Setting. Connect this pin to the converter input
voltage, Vin, through a resistor, RTONNB, to set the on-time of
UGATE_VDDNB and also the output voltage ripple of VDDNB controller.
41, 42
PWMA2,
PWMA1
PWM Output for Channel 1 and 2 of VDDNB Controller.
43, 51
BOOT1,
BOOT2
Bootstrap Supply for High-Side MOSFET Driver.
44, 50
UGATE1,
UGATE2
High-Side Gate Driver Outputs. Connect this pin to Gate of high-side
MOSFET.
45, 49
PHASE1,
PHASE2
Switch nodes of High-Side Driver. Connect this pin to high-side MOSFET
Source together with the low-side MOSFET Drain and the inductor.
46, 48
LGATE1,
LGATE2
Low-Side Driver Outputs. This pin drives the Gate of low-side MOSFET.
47
PVCC
Driver Power. Connect this pin to GND by ceramic capacitor larger than 1F.
53 (Exposed Pad)
GND
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
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is a registered trademark of Richtek Technology Corporation.
DS8881A-01 January 2014
RT8881A
QR
SEN
QR
SENA
QR
QRA
PGOODA
RSET/RSETA
TONSETA
OCP Threshold
VSETA
ERROR
AMP
+
x1
-
+
Offset
Cancellation
+
PWM
CMPA
PWMA1
QRA
-
TON
GENA
PWMA2
TONA
FBA
COMPA
Current mirror
ISENA1P
ISENA1N
+
x1
-
ISENA2P
ISENA2N
+
x1
-
IBA1
V064
+
1/3
-
RSETA
Current mirror
Average
IBA2
+
OCP_TDCA,
OCP_SPIKEA
From Control Logic
OCA
-
VSET
FB
ERROR
AMP
+
+
+
COMP
Current mirror
ISEN1P
ISEN1N
+
x1
-
ISEN2P
+
x1
-
-
PWM1
PWM
CMP
QR
TON
GEN
PWM2
2-PH
Driver
IB1
BOOTx
UGATEx
PHASEx
LGATEx
PWM3
TON
PWM4
+
1/3
-
RSET
Current mirror
IB2
Average
Current Balance
IMONI
Current mirror
+
x1
-
TONSET
OV/UV/NV
Offset
Cancellation
-
IBA2
To Protection Logic
VSENA
DAC
Soft-Start & Slew Rate
Control
Current Balance
IMONAI
IBA1
IMONA
ISEN3N
Loop Control
Protection Logic
Load Line
/Load Line A
DAC
Soft-Start & Slew
Rate Control
ISEN3P
OCP_L
OFS/OFSA
I C/SVI2 Interface
Configuration Registers
Control Logic
From Control Logic
ISEN2N
GND
ADC
2
RGND
PGOOD
UVLO
MUX
IBIAS
RGND
VCC
EN
PWROK
VDDIO
SVT
SVD
SVC
SDA
SCL
VSENA
VSEN
IMONAI
SET2
IMONI
SET1
Function Block Diagram
IB1
IB2
IB3
IB4
IB3
Current mirror
ISEN4P
ISEN4N
+
x1
-
IB4
OCP_TDC,
OCP_SPIKE
+
OC
-
VSEN
To Protection Logic
OV/UV/NV
IMON V064
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8881A-01 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT8881A
Operation
QRSEN/QRSENA
Error Amplifier
The QRSEN/QRSENA detects VSEN/VSENA and
generates QR/QRA signals.
The Error amplifier generates COMP/COMPA signal by
the difference between VSET/VSETA and FB/FBA.
MUX and ADC
Offset Cancellation
The MUX switches ADC input to SET1, SET2, IMON or
IMONA. ADC converts these analog signals to digital
codes for reporting or performance adjustment. (In
RT8881A, TSEN and TSENA are not connected to MUX)
This block cancels the output offset voltage due to voltage
and current ripples to achieve accurate output voltage.
I2C/SVI2 Interface
PWM CMP
PWM comparator compares COMP signal and current
feedback signal to initial PWM signal.
I2C/SVI2 interface uses the SVC, SVD, and SVT pins to
communicate with CPU, and uses the SCL and SDA pins
to communicate with platform. The RT8881A's performance
and behavior can be adjusted by commands sent by CPU
or platform.
TONGEN/TONGENA
UVLO
UVLO detects the VCC pin voltages to generate UVLO
signal.
Per-phase current is sensed and adjusted by adjusting
on-time of each phase to achieve current balance among
each phase.
Loop Control Protection Logic
OC/OV/UV/NV
Loop control protection logic detects the EN pin voltage
and UVLO signal to initiate soft-start, and generates opendrain PGOOD and PGOODA signals after soft-start is
finished. When OCP_L event occurs, the OCP_L pin
voltage will be pulled low.
VSEN/VSENA and output current are sensed for overcurrent, over-voltage, under-voltage, negative-voltage
protections.
DAC
This block generates PWM signal's high interval based
on on-time setting and current balance.
Current Balance
RSET
Ramp generator to improve noise immunity and reduce
jitter.
The DAC receives VID codes to generate internal reference
voltage (VSET/VSETA) for controller to regulate.
Soft-Start and Slew-Rate Control
This block controls the slew rate of internal reference
change to control the slew rate when output voltage
changes.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
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is a registered trademark of Richtek Technology Corporation.
DS8881A-01 January 2014
RT8881A
Table 1. Serial VID Codes
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
0000_0000
1.55000
0010_0111
1.30625
0100_1110
1.06250
0111_0101
0.81875
0000_0001
1.54375
0010_1000
1.30000
0100_1111
1.05625
0111_0110
0.81250
0000_0010
1.53750
0010_1001
1.29375
0101_0000
1.05000
0111_0111
0.80625
0000_0011
1.53125
0010_1010
1.28750
0101_0001
1.04375
0111_1000
0.80000
0000_0100
1.52500
0010_1011
1.28125
0101_0010
1.03750
0111_1001
0.79375
0000_0101
1.51875
0010_1100
1.27500
0101_0011
1.03125
0111_1010
0.78750
0000_0110
1.51250
0010_1101
1.26875
0101_0100
1.02500
0111_1011
0.78125
0000_0111
1.50625
0010_1110
1.26250
0101_0101
1.01875
0111_1100
0.77500
0000_1000
1.50000
0010_1111
1.25625
0101_0110
1.01250
0111_1101
0.76875
0000_1001
1.49375
0011_0000
1.25000
0101_0111
1.00625
0111_1110
0.76250
0000_1010
1.48750
0011_0001
1.24375
0101_1000
1.00000
0111_1111
0.75625
0000_1011
1.48125
0011_0010
1.23750
0101_1001
0.99375
1000_0000
0.75000
0000_1100
1.47500
0011_0011
1.23125
0101_1010
0.98750
1000_0001
0.74375
0000_1101
1.46875
0011_0100
1.22500
0101_1011
0.98125
1000_0010
0.73750
0000_1110
1.46250
0011_0101
1.21875
0101_1100
0.97500
1000_0011
0.73125
0000_1111
1.45625
0011_0110
1.21250
0101_1101
0.96875
1000_0100
0.72500
0001_0000
1.45000
0011_0111
1.20625
0101_1110
0.96250
1000_0101
0.71875
0001_0001
1.44375
0011_1000
1.20000
0101_1111
0.95625
1000_0110
0.71250
0001_0010
1.43750
0011_1001
1.19375
0110_0000
0.95000
1000_0111
0.70625
0001_0011
1.43125
0011_1010
1.18750
0110_0001
0.94375
1000_1000
0.70000
0001_0100
1.42500
0011_1011
1.18125
0110_0010
0.93750
1000_1001
0.69375
0001_0101
1.41875
0011_1100
1.17500
0110_0011
0.93125
1000_1010
0.68750
0001_0110
1.41250
0011_1101
1.16875
0110_0100
0.92500
1000_1011
0.68125
0001_0111
1.40625
0011_1110
1.16250
0110_0101
0.91875
1000_1100
0.67500
0001_1000
1.40000
0011_1111
1.15625
0110_0110
0.91250
1000_1101
0.66875
0001_1001
1.39375
0100_0000
1.15000
0110_0111
0.90625
1000_1110
0.66250
0001_1010
1.38750
0100_0001
1.14375
0110_1000
0.90000
1000_1111
0.65625
0001_1011
1.38125
0100_0010
1.13750
0110_1001
0.89375
1001_0000
0.65000
0001_1100
1.37500
0100_0011
1.13125
0110_1010
0.88750
1001_0001
0.64375
0001_1101
1.36875
0100_0100
1.12500
0110_1011
0.88125
1001_0010
0.63750
0001_1110
1.36250
0100_0101
1.11875
0110_1100
0.87500
1001_0011
0.63125
0001_1111
1.35625
0010_0110
1.11250
0110_1101
0.86875
1001_0100
0.62500
0010_0000
1.35000
0100_0111
1.10625
0110_1110
0.86250
1001_0101
0.61875
0010_0001
1.34375
0100_1000
1.10000
0110_1111
0.85625
1001_0110
0.61250
0010_0010
1.33750
0100_1001
1.09375
0111_0000
0.85000
1001_0111
0.60625
0010_0011
1.33125
0100_1010
1.08750
0111_0001
0.84375
1001_1000
0.60000
0010_0100
1.32500
0100_1011
1.08125
0111_0010
0.83750
1001_1001
0.59375
0010_0101
1.31875
0100_1100
1.07500
0111_0011
0.83125
1001_1010
0.58750
0010_0110
1.31250
0100_1101
1.06875
0111_0100
0.82500
1001_1011
0.58125
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8881A-01 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
7
RT8881A
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
1001_1100
0.57500
1011_0101 *
0.41875
1100_1110 *
0.26250
1110_0111*
0.10625
1001_1101
0.56875
1011_0110 *
0.41250
1100_1111 *
0.25625
1110_1000*
0.10000
1001_1110
0.56250
1011_0111 *
0.40625
1101_0000 *
0.25000
1110_1001*
0.09375
1001_1111
0.55625
1011_1000 *
0.40000
1101_0001 *
0.24375
1110_1010*
0.08750
1010_0000
0.55000
1011_1001 *
0.39375
1101_0010 *
0.23750
1110_1011*
0.08125
1010_0001
0.54375
1011_1010 *
0.38750
1101_0011 *
0.23125
1110_1100*
0.07500
1010_0010
0.53750
1011_1011 *
0.38125
1101_0100 *
0.22500
1110_1101*
0.06875
1010_0011
0.53125
1011_1100 *
0.37500
1101_0101 *
0.21875
1110_1110*
0.06250
1010_0100
0.52500
1011_1101 *
0.36875
1101_0110 *
0.21250
1110_1111*
0.05625
1010_0101
0.51875
1011_1110 *
0.36250
1101_0111 *
0.20625
1111_0000*
0.05000
1010_0110
0.51250
1011_1111 *
0.35625
1101_1000 *
0.20000
1111_0001*
0.04375
1010_0111
0.50625
1100_0000 *
0.35000
1101_1001 *
0.19375
1111_0010*
0.03750
1010_1000 *
0.50000
1100_0001 *
0.34375
1101_1010 *
0.18750
1111_0011*
0.03125
1010_1001 *
0.49375
1100_0010 *
0.33750
1101_1011 *
0.18125
1111_0100*
0.02500
1010_1010 *
0.48750
1100_0011 *
0.33125
1101_1100 *
0.17500
1111_0101*
0.01875
1010_1011 *
0.48125
1100_0100 *
0.32500
1101_1101 *
0.16875
1111_0110*
0.01250
1010_1100 *
0.47500
1100_0101 *
0.31875
1101_1110 *
0.16250
1111_0111*
0.00625
1010_1101 *
0.46875
1100_0110 *
0.31250
1101_1111 *
0.15625
1111_1000*
0.00000
1010_1110 *
0.46250
1100_0111 *
0.30625
1110_0000*
0.15000
1111_1001*
OFF
1010_1111 *
0.45625
1100_1000 *
0.30000
1110_0001*
0.14375
1111_1010*
OFF
1011_0000 *
0.45000
1100_1001 *
0.29375
1110_0010*
0.13750
1111_1011*
OFF
1011_0001 *
0.44375
1100_1010 *
0.28750
1110_0011*
0.13125
1111_1100*
OFF
1011_0010 *
0.43750
1100_1011 *
0.28125
1110_0100*
0.12500
1111_1101*
OFF
1011_0011 *
0.43125
1100_1100 *
0.27500
1110_0101*
0.11875
1111_1110*
OFF
1011_0100 *
0.42500
1100_1101 *
0.26875
1110_0110*
0.11250
1111_1111*
OFF
* Indicates TOB is 80mV for this VID code; unconditional VR controller stability required at all VID codes
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8881A-01 January 2014
RT8881A
Table 2. SET1 Pin Setting for VDD Controller
SET1 Pin Voltage
Before Current
Injection VSET1 (mV)
RSET
SET1 Pin Voltage
Before Current
Injection VSET1 (mV)
34
61%
836
61%
59
74%
861
74%
87%
886
100%
911
135
113%
936
113%
160
126%
961
126%
235
61%
1036
61%
260
74%
1061
74%
87%
1086
100%
1112
335
113%
1137
113%
360
126%
1162
126%
435
61%
1237
61%
460
74%
1262
74%
87%
1287
100%
1312
535
113%
1337
113%
560
126%
1362
126%
636
61%
1437
61%
661
74%
1462
74%
87%
1487
100%
1512
736
113%
1537
113%
761
126%
1562
126%
85
110
285
310
485
510
686
711
OCP_TDC
(Respect to
OCP_SPIKE)
70%
75%
80%
85%
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8881A-01 January 2014
OCP_TDC
(Respect to
OCP_SPIKE)
90%
95%
100%
Disable
OCPTDC
RSET
87%
100%
87%
100%
87%
100%
87%
100%
is a registered trademark of Richtek Technology Corporation.
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9
RT8881A
Table 3. SET1 Pin Setting for VDDNB Controller
SET1 Pin Voltage
OCP_TDCA
Difference VSET1
(Respect to
(Before and After
OCP_SPIKEA)
Current Injection) (mV)
RSETA
SET1 Pin Voltage
OCP_TDCA
Difference VSET1
(Respect to
(Before and After
OCP_SPIKEA)
Current Injection) (mV)
RSETA
34
61%
836
61%
59
74%
861
74%
87%
886
100%
911
135
113%
936
113%
160
126%
961
126%
235
61%
1036
61%
260
74%
1061
74%
87%
1086
100%
1112
335
113%
1137
113%
360
126%
1162
126%
435
61%
1237
61%
460
74%
1262
74%
87%
1287
100%
1312
535
113%
1337
113%
560
126%
1362
126%
636
61%
1437
61%
661
74%
1462
74%
87%
1487
100%
1512
736
113%
1537
113%
761
126%
1562
126%
85
110
285
310
485
510
686
711
70%
75%
80%
85%
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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10
90%
95%
100%
Disable
OCPTDC
87%
100%
87%
100%
87%
100%
87%
100%
is a registered trademark of Richtek Technology Corporation.
DS8881A-01 January 2014
RT8881A
Table 4. SET2 Pin Setting
SET2 Pin Voltage
Before Current Injection VSET2 (mV)
34 to 85
110 to 160
235 to 285
310 to 360
435 to 485
510 to 560
636 to 686
711 to 761
836 to 886
911 to 961
1036 to 1086
1112 to 1162
1237 to 1287
1312 to 1362
1437 to 1487
1512 to 1562
QRTH
(for VDD)
OCPTRGDELAY
(for VDD/VDDNB)
10ms
Disable
40ms
10ms
Disable
40ms
10ms
30mV
40ms
10ms
35mV
40ms
10ms
40mV
40ms
10ms
45mV
40ms
10ms
50mV
40ms
10ms
55mV
40ms
Table 5. Quick Response Threshold for VDDNB Controller
SET2 Pin Voltage Difference VSET2
(Before and After Current Injection) (mV)
QRTHA (for VDDNB)
19
Disable
72
Disable
122
30mV
172
35mV
222
40mV
272
45mV
323
50mV
373
55mV
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8881A-01 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11
RT8881A
Absolute Maximum Ratings
















(Note 1)
VCC to GND -------------------------------------------------------------------------------------------- −0.3V to 6.5V
PVCC to GND ------------------------------------------------------------------------------------------ −0.3V to 15V
RGND to GND ------------------------------------------------------------------------------------------ −0.3V to 0.3V
TONSET, TONSETA to GND ------------------------------------------------------------------------ −0.3V to 6.5V
BOOTx to PHASEx ----------------------------------------------------------------------------------- −0.3V to 15V
PHASEx to GND
DC --------------------------------------------------------------------------------------------------------- −0.3V to 30V
< 20ns --------------------------------------------------------------------------------------------------- −10V to 35V
LGATEx to GND
DC --------------------------------------------------------------------------------------------------------- −0.3V to (PVCC + 0.3V)
< 20ns --------------------------------------------------------------------------------------------------- −2V to (PVCC + 0.3V)
UGATEx to GND
DC --------------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V)
< 20ns --------------------------------------------------------------------------------------------------- (VPHASE − 2V) to (VBOOT + 0.3V)
VDDIO, PWROK, SVT, SVD and SVC ------------------------------------------------------------ −0.3V to 3.3V
Other Pins ----------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)
Power Dissipation, PD @ TA = 25°C
WQFN-52L 6x6 ---------------------------------------------------------------------------------------- 3.77W
Package Thermal Resistance (Note 2)
WQFN-52L 6x6, θJA ----------------------------------------------------------------------------------- 26.5°C/W
WQFN-52L 6x6, θJC ---------------------------------------------------------------------------------- 6.5°C/W
Junction Temperature --------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------- 260°C
Storage Temperature Range ------------------------------------------------------------------------ −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) -------------------------------------------------------------------------- 2kV
Recommended Operating Conditions





(Note 4)
Supply Voltage, VCC --------------------------------------------------------------------------------- 4.5V to 5.5V
Driver Supply Voltage, PVCC ----------------------------------------------------------------------- 4.5V to 13.2V
Junction Temperature Range ------------------------------------------------------------------------ −40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------ −40°C to 85°C
Input Voltage + Driver Supply Voltage, VIN + PVCC ------------------------------------------ <35V
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8881A-01 January 2014
RT8881A
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Power Supply
Supply Current
IVCC
EN = 3V, Not Switching
--
--
15
mA
Shutdown Current
ISHDN
EN = 0V
--
--
5
A
VFB = 1.0000  1.5500
(No Load, CCM Mode )
0.5
0
0.5
%SVID
VFB = 0.8000  1.0000
5
0
5
VFB = 0.3000  0.8000
8
0
8
VFB = 0.2500  0.3000
80
0
80
IRGND
EN = 3V, Not Switching
--
--
400
A
SR
SetVID Fast
7.5
12
--
mV/s
2
--
2
mV
Reference and DAC
DC Accuracy
VFB
mV
RGND Current
RGND Current
Slew Rate
Dynamic VID Slew Rate
Error Amplifier
Input Offset
VEAOFS
DC Gain
ADC
RL = 47k
70
80
--
dB
Gain-Bandwidth Product
GBW
CLOAD = 5pF
--
10
--
MHz
Output Voltage Range
VCOMP
0.3
--
3.6
V
Maximum Source Current
IEAsr
1
--
--
mA
Maximum Sink Current
IEAsk
1
--
--
mA
0.8
--
0.8
mV
97
--
103
%
97
--
103
%
Impedance at Negative Input RISENxN
1
--
--
M
Impedance at Positive Input
RISENxP
1
--
--
M
Internal Sum Current Sense
DC Gain for CORE
Ai, VDD
GBD
0.32
0.33
0.34
V/V
Internal Sum Current Sense
DC Gain for NB
Ai,
VDDNB
GBD
0.32
0.33
0.34
V/V
Maximum Source Current
ICSsr
0 < VFB < 2.35
100
--
--
A
Maximum Sink Current
ICSsk
0 < VFB < 2.35
10
--
--
A
VZCD_TH
VZCD_TH = GND  VPHASEx
--
10
--
mV
Current Sense Amplifier
Input Offset Voltage
VOSCS
Current Mirror Gain for
CORE
AMIRROR,
Current Mirror Gain for NB
VDD
AMIRROR,
VDDNB
Zero Current Detection
Zero Current Detection
Threshold
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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13
RT8881A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
0.5
--
V
Ton Setting
TONSETx Pin Minimum
Voltage
VTON(MIN)
TONSETx TON
TON
IRTON = 80A, VFB = 1.1V
270
305
340
ns
TONSETx Input Current
Range
IRTON
VFB = 1.1V
25
--
280
A
Minimum TOFF
TOFF
--
250
--
ns
1.95
2
2.05
V
--
0.64
--
V
800
--
--
A
A
IBIAS
IBIAS Pin Voltage
VIBIAS
RIBIAS = 100k
V064
Reference Voltage Output
V064
Sink Current Capability
IV064sk
Source Current Capability
IV064sr
--
--
100
Logic-High VIH_EN
2
--
--
VIL_EN
--
--
0.8
ILEK_IN
1
--
1
V064 = 0.64V
Logic Inputs
EN Input
Voltage
Logic-Low
Leakage Current of EN, SCL
SDA
SVC, SVD, SVT, Logic-High
PWROK Input
Logic-Low
Voltage
Hysteresis of SVC, SVD,
SVT, PWROK
SCL, SDA Input
Voltage
A
VIH_SVI
Respect to VDDIO
70
--
100
VIL_SVI
Respect to VDDIO
0
--
35
VHYS_SVI
Respect to VDDIO
10
--
--
2.4
--
--
--
--
0.8
3.9
4.1
4.3
V
--
200
--
mV
--
3
--
s
275
325
375
mV
--
1
--
s
350
425
500
mV
--
3
--
s
--
0
--
mV
Logic-High VIH_I2C
Logic-Low
V
VIL_I2C
%
%
V
Protection
Under-Voltage Lockout
Threshold
VUVLO
Under-Voltage Lockout
Hysteresis
VUVLO
VCC Falling edge
Under-Voltage Lockout Delay TUVLO
VCC Rising above UVLO
Threshold
Over-Voltage Protection
Threshold
VOVP
I C Default Setting
Over-Voltage Protection
Delay
TOVP
VSENx Rising above Threshold
Under-Voltage Protection
Threshold
VUVP
I C Default Setting
Under-Voltage Protection
Delay
TUVP
VSENx Falling below Threshold
Negative-Voltage Protection
Threshold
VNV
2
2
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8881A-01 January 2014
RT8881A
Parameter
Symbol
Per-Phase OCP
Threshold
IOCP_Per-Phase
Delay of Per-Phase OCP
TPHOCP
OCP_SPIKE Threshold
IOCP_SPIKE
OCP_SPIKE Action
Delay
TOCP_SPIKE
OCP_TDC Action Delay
Test Conditions
IISENxN Per-Phase OCP
Threshold, RSENSE = 680
DCR = 0.57m, RSENSE =
680, RIMON = 17.19k
_Action_Dly
TOCP_TDC
_Action_Dly
Min
Typ
Max
Unit
80
130
180
A
--
1
--
s
162
180
198
A
6
--
12
s
12
--
24
s
0
--
0.2
V
2
--
--
s
PGOOD, PGOODA and OCP_L
Output Low Voltage at
OCP_L
VOCP_L
OCP_L Assertion Time
TOCP_L
Output Low Voltage at
PGOOD, PGOODA
VPGOOD,
VPGOODA
IPGOOD = 4mA,
IPGOODA = 4mA
0
--
0.2
V
PGOOD and PGOODA
Threshold Voltage
VTH_PGOOD
VTH_PGOODA
Respect to VBOOT
--
300
--
mV
PGOOD and PGOODA
Delay Time
TPGOOD
TPGOODA
VSENx = VBOOTx to
PGOOD/PGOODA High
70
100
130
s
Maximum Reported
Current (FFh = OCP)
--
100
--
%SPIKE_
OCP
Minimum Reported
Current (00h)
--
0
--
%SPIKE_
OCP
IDDSpike Current
Accuracy
--
--
3
%
Maximum Reported
Voltage (0_00h)
--
3.15
--
V
Minimum Reported
Voltage (1_F8h)
--
0
--
V
800mV  VID  1.2V
1
--
1
VID < 800 mV, VID > 1.2V
2
--
2
Quick Response
Threshold Voltage Setting
Range Minimum Value
Refer to Table 4 and Table 5
--
35
--
mV
Quick Response
Threshold Voltage Setting VQRTH(MAXx)
Range Maximum Value
Refer to Table 4 and Table 5
--
60
--
mV
PWMx Source Resistance RPWMsr
--
20
--

PWMx Sink Resistance
--
10
--

IOCP_L = 4mA
Current Report
Voltage Report
Voltage Accuracy
LSB
QR Setting of VDD and VDDNB
PWM Driving Capability
RPWMsk
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8881A-01 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
15
RT8881A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Timing
UGATEx Rise Time
tUGATEr
3nF Load
--
25
--
ns
UGATEx Fall Time
tUGATEf
3nF Load
--
12
--
ns
LGATEx Rise Time
tLGATEr
3nF Load
--
24
--
ns
LGATEx Fall Time
tLGATEf
3nF Load
--
10
--
ns
tUGATEpdh
VBOOTx VPHASEx = 12V
See Timing Diagram
--
60
--
--
22
--
--
30
--
--
8
--
Propagation Delay
tUGATEpdl
tLGATEpdh
tLGATEpdl
See Timing Diagram
ns
ns
Output
UGATEx Drive Source
IUGATE_sr
VBOOTx VPHASEx = 12V,
ISource = 100mA
--
1.7
--

UGATEx Drive Sink
RUGATE_sk
VBOOTx VPHASEx = 12V,
ISink = 100mA
--
1.4
--

LGATEx Drive Source
ILGATE_sr
ISource = 100mA
--
1.6
--

LGATEx Drive Sink
RLGATE_sk
ISink = 100mA
--
1.1
--

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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16
is a registered trademark of Richtek Technology Corporation.
DS8881A-01 January 2014
RT8881A
Typical Application Circuit
VDDIO
2.2
12V/5V
47
10µF
2.2
5V
VCC
VCC
62k
28
1µF
499
187k
PVCC
VCC
VCC
25 SET1
22.1k
510
26
SET2
130
0
1
VIN
RTONNB
165k 40
1
37
RIBIAS
100k 29
16
EN
82p
V064
RNTC
100k
10k
RIMON
16k 15
2.2
0
5.1k
RIMONA
3.55k 17
27k
430
IMONA
30
COMPA
31
FBA
14 RGND
1
EN
LGATE
RT9624A
2.2
10µF
0
BOOT
VSS_SENSE
0.1µF
VIN
BOOT1
UGATE1
43
2.2
44
0
10µF
0.1µF
0.36µH/0.72m
45
0
46
1
VVDD
0.1µF
LOAD
3.3n
NC
ISEN1N 5
BOOT2 51
UGATE2 50
VIN
820µF/2.5V x 8 OSCON
22µF/6.3V x 30 MLCC
0.1µF
0.1µF
2.2
10µF
0
0.36µH/0.72m
PHASE2 49
48
LGATE2
0
1
5.1k
0.1µF
3.3n
NC
ISEN2P 3
RSENSE2
680
VIN
VCC
PGND
PWM3
52
5V
BOOT
PHASE
EN
LGATE
10µF
0
UGATE
PWM
0.1µF
2.2
0.36µH/0.72m
0
1
35 ISENA1N
ISEN3P
RSENSE3
680
ISEN3N 8
12V
NC
RSENSEA2
680
VCC
1µF
1µF
41
PWMA2
PWM4 1
5V
ISEN4P 10
34 ISENA2N
ISEN4N
9
PGND
PWM
BOOT
VIN
0.1µF
2.2
10µF
0
UGATE
0.36µH/0.72m
PHASE
0
LGATE
EN
RT9624A
5V
33 ISENA2P
0.1µF
NC
7
VCC
PWM
5.1k
3.3n
0.1µF
EN
LGATE
RT9624A
3.3n
5.1k
RSENSE1
680
1µF
36 ISENA1P
10µF
10µF
RT9624A
UGATE PGND
PHASE
0
VVDD_SENSE
10k
12
12V
0.36µH/0.72m
1
FB
13
0.1µF
0.1µF
5.1k
82p
39k
0.1µF
5V
RSENSEA1
680
VIN
To Platform Master
NC
12V
42 PWMA1
NC
0.1µF
NC
0
COMP
180
1µF
PWM
10k
0
VCC
UGATE PGND
PHASE
0
3.3n
820µF/2.5V x 3 OSCON
22µF/6.3V x 15 MLCC
BOOT
10k
0
23
24
ISEN2N 4
10µF
LOAD
22
12V
0.36µH/0.72m
0.1µF
To CPU
IMON
39p
VIN
0.1µF
VVDDNB
21
ISEN1P 6
RNTC
100k
0.1µF
100
3.3V
20
27p
LGATE1
NC
100
4.7k 10k 10k
GND 53 (Exposed Pad)
PHASE1
0
VSS_SENSE
SVD
IBIAS
32 VSENA
VVDDNB_SENSE
SVC
TONSETA
12k
14.5k
4.7k
19
VSEN 11
17.66k
8.86k
1µF
18
0.1µF
Chip Enable
0.47µF
3.3V
OCP_L 27
PGOOD 39
PGOODA 38
SVT
2 TONSET
VIN
PWROK
SDA
RTON
160k
0.1µF
VDDIO
SCL
240
VDDIO
2.2
RT8881A
1
5.1k
0.1µF
3.3n
NC
RSENSE4
680
0.1µF
0.1µF
Timing Diagram
PWMx
LGATEx
tLGATEpdl
90%
tUGATEpdl
1.5V
1.5V
1.5V
90%
1.5V
UGATEx
tUGATEpdh
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8881A-01 January 2014
tLGATEpdh
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
17
RT8881A
Typical Operating Characteristics
CORE VR Power On from EN
CORE VR Power Off from EN
VDD
(500mV/Div)
VDD
(500mV/Div)
EN
(5V/Div)
EN
(5V/Div)
PGOOD
(5V/Div)
PGOOD
(5V/Div)
UGATE1
(20V/Div)
Boot VID = 0.8V
UGATE1
(20V/Div)
Time (200μs/Div)
Time (200μs/Div)
CORE VR OCP_TDC
CORE VR OCP_SPIKE
I LOAD
(200A/Div)
I LOAD
(250A/Div)
PGOOD
(5V/Div)
PGOOD
(5V/Div)
OCP_L
(2V/Div)
OCP_L
(2V/Div)
UGATE1
(20V/Div)
UGATE1
(20V/Div)
ILOAD = 80A to 160A
ILOAD = 50A to 200A
Time (4ms/Div)
Time (8μs/Div)
CORE VR OVP and NVP
CORE VR UVP
VDD
(1V/Div)
VDD
(1V/Div)
PGOOD
(5V/Div)
PGOOD
(5V/Div)
UGATE1
(50V/Div)
UGATE1
(50V/Div)
LGATE1
(20V/Div)
VID = 1.1V
Time (20μs/Div)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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18
Boot VID = 0.8V
LGATE1
(20V/Div)
VID = 1.1V
Time (10μs/Div)
is a registered trademark of Richtek Technology Corporation.
DS8881A-01 January 2014
RT8881A
CORE VR Dynamic VID Up
CORE VR Dynamic VID Up
VDD
(1V/Div)
VDD
(1V/Div)
I LOAD
(22A/Div)
I LOAD
(55A/Div)
SVD
(2V/Div)
SVD
(2V/Div)
SVT
(2V/Div)
VID = 0.4V to 1V, ILOAD = 11A
SVT
(2V/Div)
VID = 1V to 1.06875V, ILOAD = 55A
Time (20μs/Div)
Time (20μs/Div)
CORE VR Dynamic VID Up
CORE VR Dynamic VID Up
VDD
(1V/Div)
VDD
(1V/Div)
I LOAD
(55A/Div)
I LOAD
(55A/Div)
SVD
(2V/Div)
SVD
(2V/Div)
SVT
(2V/Div)
SVT
(2V/Div)
VID = 1V to 1.1V, ILOAD = 55A
VID = 1V to 1.2V, ILOAD = 55A
Time (20μs/Div)
Time (20μs/Div)
CORE VR Dynamic VID Up
CORE VR Load Transient
VDD
(1V/Div)
VDD
(100mV/Div)
I LOAD
(55A/Div)
SVD
(2V/Div)
I LOAD
(120A/Div)
SVT
(2V/Div)
VID = 1V to 1.4V, ILOAD = 55A
Time (20μs/Div)
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DS8881A-01 January 2014
fLOAD = 10kHz, ILOAD = 55A to 150A
Time (4μs/Div)
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19
RT8881A
CORE VR Load Transient
NB VR Power On from EN
VDDNB
(500mV/Div)
VDD
(100mV/Div)
EN
(5V/Div)
PGOODA
(5V/Div)
I LOAD
(120A/Div)
fLOAD = 10kHz, ILOAD = 150A to 55A
UGATEA1
(20V/Div)
Time (4μs/Div)
Time (200μs/Div)
NB VR Power Off from EN
NB VR OCP_TDC
I LOAD
(100A/Div)
VDDNB
(500mV/Div)
PGOODA
(5V/Div)
EN
(5V/Div)
PGOODA
(5V/Div)
OCP_L
(2V/Div)
UGATEA1
(20V/Div)
UGATEA1
(20V/Div)
Boost VID = 0.8V
Time (4ms/Div)
NB VR OCP_SPIKE
NB VR OVP and NVP
VDDNB
(1V/Div)
PGOODA
(5V/Div)
PGOODA
(5V/Div)
OCP_L
(2V/Div)
UGATEA1
(50V/Div)
ILOAD = 20A to 80A
Time (8μs/Div)
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20
ILOAD = 30A to 60A
Time (200μs/Div)
I LOAD
(100A/Div)
UGATEA1
(20V/Div)
Boost VID = 0.8V
LGATEA1
(20V/Div)
VID = 1.1V
Time (20μs/Div)
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DS8881A-01 January 2014
RT8881A
NB VR UVP
NB VR Dynamic VID Up
VDDNB
(1V/Div)
VDD
(1V/Div)
PGOODA
(5V/Div)
I LOAD
(9A/Div)
SVD
(2V/Div)
UGATEA1
(50V/Div)
LGATEA1
(20V/Div)
VID = 1.1V
SVT
(2V/Div)
VID = 0.4V to 1V, ILOAD = 4.1A
Time (10μs/Div)
Time (20μs/Div)
NB VR Dynamic VID Up
NB VR Dynamic VID Up
VDD
(1V/Div)
VDD
(1V/Div)
I LOAD
(21A/Div)
I LOAD
(21A/Div)
SVD
(2V/Div)
SVD
(2V/Div)
SVT
(2V/Div)
SVT
(2V/Div)
VID = 1V to 1.06875V, ILOAD = 20.5A
VID = 1V to 1.1V, ILOAD = 20.5A
Time (20μs/Div)
Time (20μs/Div)
NB VR Dynamic VID Up
NB VR Dynamic VID Up
VDD
(1V/Div)
VDD
(1V/Div)
I LOAD
(21A/Div)
I LOAD
(21A/Div)
SVD
(2V/Div)
SVD
(2V/Div)
SVT
(2V/Div)
VID = 1V to 1.2V, ILOAD = 20.5A
Time (20μs/Div)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8881A-01 January 2014
SVT
(2V/Div)
VID = 1V to 1.4V, ILOAD = 20.5A
Time (20μs/Div)
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21
RT8881A
NB VR Load Transient
NB VR Load Transient
VDD
(100mV/Div)
VDD
(100mV/Div)
I LOAD
(45A/Div)
I LOAD
(45A/Div)
fLOAD = 10kHz, ILOAD = 20A to 60A
fLOAD = 10kHz, ILOAD = 60A to 20A
Time (4μs/Div)
Time (4μs/Div)
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22
is a registered trademark of Richtek Technology Corporation.
DS8881A-01 January 2014
RT8881A
Application Information
The RT8881A is a multi-phase PWM controller supporting
two outputs. It is compliant with AMD SVI2 Voltage
Regulator Specification and to support both core (VDD)
and Northbridge (VDDNB) portion of the CPU. Unless
otherwise described, the following functions are performed
on the RT8881A on each rail independently.
Current feedback signal,VCS
Comp signal,VCOMP
PWM1
PWM2
G-NAVPTM
The RT8881A adopts the G-NAVPTM controller, which is a
current-mode constant on-time control with DC offset
cancellation. The approach can not only improve DC offset
problem for increasing system accuracy but also provide
fast transient response. The control loop consists of PWM
modulators with power stages, current sense amplifiers
and an error amplifier as shown in Figure 1.
PWM3
PWM4
(a). G-NAVPTM Behavior Waveforms in CCM in Steady
State
In the RT8881A, when current feedback signal reaches
comp signal to generate an on-time width to achieve PWM
modulation. Figure 2 shows the basic G-NAVPTM behavior
waveforms in Continuous Conduction Mode (CCM).
Current feedback signal,VCS
Comp signal,VCOMP
VIN
HS_FET
CCRCOT
PWM
Logic
VCOMP
+
GM
-
ISENxP
ISENxN
IMON
+
EA
+
RX
CX
VREF
COMP
FB
RGND
PWM2
PWM3
COUT
RCSx
RIMON
C2
R2
PWM4
(b). G-NAVPTM Behavior Waveforms in CCM in Load
Transient
C1
R1
VVDD_SENSE
Figure 2
VSS_SENSE
VDAC
Figure 1. Simplified Schematic for Droop and Remote
Sense in CCM
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8881A-01 January 2014
PWM1
RESR
LS_FET
VCS
1/3
L RSENSE
Driver
+
-
CMP
PWMx
VOUT
Diode Emulation Mode (DEM)
As well-known, the dominate power loss is switching
related loss during light load, hence VR needs to be
operated in asynchronous mode (or called discontinuous
conduction mode, DCM) to reduce switching related loss
due to switching frequency is dependent on loading in
the asynchronous mode. The RT8881A can operate in
Diode Emulation Mode (DEM) in order to improve light
load efficiency. In DEM operation, the behavior of the lowside MOSFET(s) needs to work like a diode, that is, the
low-side MOSFET(s) will be turned on when the phase
voltage is a negative value, i.e. the inductor current follows
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RT8881A
from Source to Drain of low-side MOSFET(s). The lowside MOSFET(s) will be turned off when phase voltage is
a positive value, i.e. reversed current is not allowed. Figure
3 shows the control behavior in DEM. Figure 4 shows the
G-NAVPTM operation in DEM to illustrate the control
behaviors. When the load decreases, the discharge time
of output capacitors increases during UGATE and LGATE
are turned off. Hence, the switching frequency and
switching loss will be reduced to improve efficiency in
light load condition.
Inductor current
Phase node
The RT8881A is a multiphase controller, which has a phase
interleaving function in VDD and VDDNB rails, 90 degree
phase shift for 4-phase operation, 120 degree phase shift
for 3-phase operation and 180 degree phase shift for 2phase operation, which can help reduce output voltage
ripple and EMI problem.
Current Balance
The RT8881A implements internal current balance
mechanism in the current loop. The RT8881A senses and
compares per-phase current signal with average current.
If the sensed current of any particular phase is larger than
average current, the on-time of this phase will be adjusted
to be shorter.
Active Phase Determination : Before POR
UGATE
LGATE
Figure 3. Diode Emulation Mode (DEM) in Steady State
Inductor
current signal
Output capacitor
discharge slope
Phase Interleaving Function
The number of active phases is determined by the internal
circuitry that monitors the ISENxN voltages during startup. Pull ISEN ( N + 1 ) N + 1 pin to VCC to configure for N
phase operation. For example, setting the controller in a
3 + 1 configuration, pulling ISEN4N to VCC programs a 3phase operation of the VDD VR and pulling ISENA2N to
VCC programs a 1-phase operation of the VDDNB VR.
COMP signal
UGATE
LGATE
(a). Lighter Load Condition
Capacitor discharge slope is lower than Figure 4 (b)
Inductor
current signal
Before POR, the controller detects whether the voltages
of ISENxN are higher than “VCC − 1V” respectively to
decide how many phases should be active. When POR =
high, the number of active phases of each rail are
determined and latched. The unused ISENxP pins are
recommended to be connected to VCC and unused PWM
pins can be left floating.
Differential Remote Sense Setting
Output capacitor
discharge slope
COMP signal
UGATE
LGATE
(b). Load Increased Condition
Capacitor discharge slope is higher than Figure 4 (a)
Figure 4. G-NAVPTM Operation in DEM
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24
The RT8881A includes differential, remote-sense inputs
to eliminate the effects of voltage drops along the PC
board traces, CPU internal power routes and socket
contacts. Figure 5 shows the CORE VR differential remote
voltage sense connection. The CPU contains on-die sense
pins, V DD_SENSE and V SS_SENSE . Connect RGND to
VSS_SENSE. Connect FB to VDD_SENSE with a resistor to
build the negative input path of the error amplifier. The
VDAC and the precision voltage reference are referred to
RGND for accurate remote sensing.
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RT8881A
For better efficiency of the given load range, the maximum
switching frequency is suggested to be :
CPU VDD_SENSE
To
Compensation
R3
R1
C2
RGND
R4
VOUT_CAP
C1
R2
fSW(MAX)
GND

CPU VSS_SENSE
Figure 5. Differential Remote Voltage Sense Connection
Switching Frequency (TON) Setting
High frequency operation optimizes the application for the
smaller component size, trading off efficiency due to higher
switching losses. This may be acceptable in ultra portable
devices where the load currents are lower and the
controller is powered from a lower voltage supply. Low
frequency operation offers the best overall efficiency at
the expense of component size and board space. Figure
6 shows the on-time setting circuit. Connect a resistor
(RTON) between VIN and TONSET to set the on-time of
UGATE :
24.4  10 12  RTON
t ON (0.5V  VDAC  1.8V) =
VIN  VDAC
of the VR, and VDAC is the DAC voltage.
TONSET
VDAC
RTON
R1


DCR  RON _ LS-FET(MAX)  N  R LL 
IDDTDC  R
V
 ON _ LS-FET(MAX)  RON _ HS-FET(MAX) 
IN(MAX) 
N

(3)
where fSW(MAX) is the maximum switching frequency,
VDAC_PS0 is the test VID of application at normal full phase
operation, VIN(MAX) is the maximum application input
voltage, IDDTDC is the thermal design current of
application, N is the phase number, RON_HS-FET(MAX) is the
maximum equivalent high-side FET RDS(ON), RON_LS-FET(MAX)
is the maximum equivalent low-side FET RDS(ON), DCR is
the inductor DCR, and RLL is the load-line setting.
Current Sense Setting
(1)
where tON is the UGATE turn on period, VIN is input voltage
CCRCOT
On-Time
Computer

VDAC_PS0  IDDTDC
N
IDDTDC
 RON _ HS-FET(MAX)  50ns
 tON  60ns  
N
VIN
The current sense topology of the VR is continuous
inductor current sensing. Therefore, the controller has less
noise sensitive. Low offset amplifiers are used for current
balance, loop control and over current detection. The
ISENxP and ISENxN pins denote the positive and negative
input of the current sense amplifier of each phase.
Users can either use a current-sense resistor or the
inductor DCR for current sensing. Using the inductor's
DCR allows higher efficiency as shown in Figure 7.
C1
On-Time
VDD
IL
Figure 6. CORE VR : On-Time Setting with RC Filter
When VDAC is larger than 1.8V, the equivalent switching
frequency may be over 500kHz, and this fast switching
frequency is unacceptable. Therefore, the CORE VR
implements a pseudo constant frequency technology to
avoid this disadvantage of CCRCOT topology. When VDAC
is larger than 1.8V, the on-time equation will be modified
to :
t ON (VDAC  1.8V) =
13.55  10-12  RTON  VDAC
VIN  VDAC
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8881A-01 January 2014
L
DCR
CX
RX
ISENxN
+
-
ISENxP
ISENxN
RCSx
Figure 7. Lossless Inductor Sensing
(2)
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RT8881A
In order to optimum transient performance, RX and CX must
be set according to the equation below :
L = R C
(4)
X
X
DCR
Then the proportion between the phase current IL and the
sensed current ISENxN can be described as below :
ISENxN = IL  DCR
RCSx
(5)
where RCSx is sense resistor and it only with a exact 680Ω
resistor. The resistance accuracy of RCSx is recommended
to be 1% or higher.
In addition to consider the inductance tolerance, the
resistor RX has to be tuned on board by examining the
transient voltage. If the output voltage transient has an
initial dip below the minimum load-line requirement and
the recovery is too fast causing a ring back. Vice versa,
with a resistance too large the output voltage transient
has only a small initial dip with a slow recovery.
Using current sense resistor in series with the inductor
can have better accuracy, but the efficiency is a trade-off.
Considering the equivalent inductance (LESL) of the current
sense resistor, an RC filter is recommended. The RC filter
calculation method is similar to the inductor DCR sensing
method mentioned above.
Substitution of Equation 8 in to Equation 7 gives Equation
9:
(9)
VIMON = DCR  ILOAD  RIMON  0.64
RCSx
Rewriting Equation 9 and application of full load condition
gives Equation 10 :
RIMON =
RCSx (VIMON  0.64)

DCR
OCPSpike
(10)
For example, given RCSx = 680Ω, DCR = 0.82mΩ, VIMON
= 3.19375V at OCPSpike = 200A, Equation 10 gives RIMON
= 10.588kΩ.
In addition, Richtek provides a Microsoft Excel-based
spreadsheet to help design the IMON resistor network
with temperature compensation for VDD VR.
Load-Line (Droop) Setting
It's very easy to achieve Active Voltage Positioning (AVP)
by properly setting the error amplifier gain due to the native
droop characteristics. This target is to have
VOUT = VDAC  ILOAD  RLL
(11)
Then solving the switching condition VCOMP = VCS in Figure
1 yields the desired error amplifier gain as
AI
(12)
A V = R2 =
R1
RLL
OCPSpike Current Setting and Current Reporting
where RLL is the equivalent load line resistance as well as
the desired static output impedance.
The RT8881A provides the current monitor function for VR.
In VDD VR, IMON pin reports VDD VR inductor sum
current. The IMON pin outputs a high-speed analog current
source that is 1 times of the summed current. Thus IIMON
can be described as below :
The summed current sense gain AI is
AI = DCR  RIMON  1
RCSx
3
The load line equation is
IIMON =
 ISENxN
(6)
The RT8881A monitors the IMON pin voltage and considers
that VDD VR has reached the OCPSpike current when
the IMON pin voltage is 3.19375V.
As show in Figure 1, a resistor RIMON is connected between
the IMON and V064 pins. Through the RIMON to convert
the IMON pin current to voltage. The voltage of the IMON
pin is expressed in Equation 7 :
VIMON = IIMON  RIMON  0.64
(7)
Rewriting Equations 5 and 6 gives Equation 8 :
IIMON = DCR  ILOAD
RCSx
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26
(8)
RLL =
AI
= 1  R1  DCR  RIMON (m  )
AV
3 R2 RCSx
(13)
(14)
For example, given RLL = 1.3mΩ, RCSx = 680Ω, DCR =
0.82mΩ, RIMON = 10.588kΩ and R1 = 10kΩ, Equation 14
gives R2 = 32.738kΩ.
Loop Compensation
Optimized compensation of the VR allows for best
possible load step response of the regulator's output. A
type-I compensator with one pole and one zero is adequate
for proper compensation. Figure 1 shows the
compensation circuit. Prior design procedure shows how
to select the resistive feedback components for the error
amplifier gain. Next, C1 and C2 must be calculated for
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DS8881A-01 January 2014
RT8881A
the compensation. The target is to achieve constant
resistive output impedance over the widest possible
frequency range.
The pole frequency of the compensator must be set to
compensate the output capacitor ESR zero, where COUT
is the capacitance of output capacitor, and RESR is the
ESR of output capacitor.
fp =
1
2  COUT  RESR
(15)
The output voltage signal behavior needs to be detected
so that QR mechanism can be trigged. The output voltage
signal is via a remote sense line to connect at the VSEN
pin that is shown in Figure 9. The QR mechanism needs
to set QR width and QR threshold (In SVI mode, only QR
threshold can be set in SET2 pin, QR width is 1.1 x TON).
Both definitions are shown in Figure 8.The QR threshold
setting for VDD controller refers to Table 4 and Table 5.
C2 can be calculated as follows :
+
CMP
-
QR_TH
VSEN
+
COUT  RESR
(16)
R2
The zero of compensator has to be placed at half of the
switching frequency to filter the switching related noise.
Such that,
1
(17)
C1 =
R1   fSW
C2 =
QR Pulse
Generation
Circuit
VOUT
Figure 9. Quick Response Triggering Circuit
Ramp Compensation
Quick Response (QR) Mechanism
The G-NAVPTM topology is one type of ripple based control
When the transient load step-up becomes quite large, it
is difficult loop response to meet the energy transfer.
Hence, the output voltage generates undershoot to fail
specification.The RT8881A has Quick Response (QR)
mechanism which is able to improve this issue. It adopts
a nonlinear control mechanism which can disable
interleaving function and simultaneously turn on all UGATE
one pulse at instantaneous step-up transient load to
restrain the output voltage drooping, Figure 8 shows the
QR behavior.
that has fast transient response, no beat frequency issue
in high repetitive load frequency operation and low BOM
cost. However, ripple based control usually don't have good
noise immunity. The RT8881A provides a ramp
compensation to increase noise immunity and reduce jitter
at the switching node. Figure 10 shows the ramp
compensation.
Noise Margin
w/o ramp compensation
IMON-VREF
QR Width
VCORE
QR Threshold
VCOMP
Noise Margin
w/ ramp compensation
IMON-VREF
VCOMP
PWM1
PWM2
Figure 10. Ramp Compensation
PWM3
PWM4
Load
Figure 8. Quick Response Mechanism
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8881A-01 January 2014
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RT8881A
Multi-Function Pin Setting
The RT8881A provides the SET1 pin for platform users to
set the VDD and VDDNB VR OCP_TDC threshold and
internal ramp compensation amplitude (RSET & RSETA),
and the SET2 pin to set VDD and VDDNB VR OCP trigger
delay (OCPTRGDELAY) and quick response threshold
(QRTH & QRTHA). For more description for OCP_TDC
threshold and OCP trigger delay settings, please refer to
over-current protection section.
To set these pins, platform designers should use resistive
voltage divider on these pins, refer to Figure 11 and Figure
12. The voltage at the SET1 and SET2 pins are
VSET1 = VCC 
ROCPTDC,D
ROCPTDC,U  ROCPTDC,D
(18)
VSET2 = VCC 
RQRTH,D
RQRTH,U  RQRTH,D
(19)
The ADC monitors and decodes the voltage at this pin
only after power up. After ADC decoding (only once), a
80μA current will be generated at the SET1 and SET2
pins for internal use. The voltage at the SET1 and SET2
pins are
VSET1 = 80μA 
ROCPTDC,U  ROCPTDC,D
ROCPTDC,U  ROCPTDC,D
(20)
VSET2 = 80μA 
RQRTH,U  RQRTH,D
RQRTH,U  RQRTH,D
(21)
From equation (18) to equation (21) and Table 2 to Table
5, platform users can set the OCP_TDC threshold, OCP
trigger delay, internal ramp amplitude and quick response
threshold for VDD and VDDNB VR.
OCPTRGDELAY
QRTH
VCC
ADC
VQRTH,DIV
OCPTDC
VOCPTDC,DIV
VOCPTDC
Register
VOCPTDC,2
SET1
ROCPTDC,U
ROCPTDC,D
RT8881A
Figure 11. OCP_TDC/RSET Setting
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28
RQRTH,D
Figure 12. QRTH/OCPTRGDELAY Setting
Power Ready (POR) Detection
During start-up, the RT8881A will detect the voltage at
the voltage input pins : VCC, EN and PVCC. When VCC >
4.3V and PVCC > 4V, the IC will recognize the power
state of system to be ready (IC POR = high). After 50μs
delay, enable signal can be asserted at the EN pin. After
POR = high and VEN > 2V, the IC will enter start-up
sequence for both VDD VR and VDDNB VR. If the voltage
at any voltage input pin drops below low threshold (POR
= low), the IC will enter power down sequence and all the
functions will be disabled. Normally, connecting system
enable signal to the EN pin is recommended. The SVID
will be ready in 2ms (MAX) after the chip has been enabled.
All the protection latches (OVP, OCP, UVP) will be cleared
only after POR = low. The condition of VEN = low will not
clear these latches.
VCC
+
4.3V
CMP
POR
+
2V
CMP
+
EN Signal
VCC
ADC
RQRTH,U
RT8881A
4V
80µA
(VCC = 5V)
SET2
VQRTH
Register
VQRTH,2
PVCC
RSET
80µA
(VCC = 5V)
CMP
Chip EN
-
Figure 13. Power Ready (POR) Detection
Start-Up Sequence
The start-up sequence is initiated when all the following
conditions are satisfied. Figure 14 shows the simplified
sequence timing diagram of the RT8881A.
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RT8881A
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
VCC
PVCC
SVID
Send
Byte
SVC
SVID
Send
Byte
SVD
VOTF
Complete
VOTF
Complete
SVT
SDA
SCL
EN
PWROK
CCM
VDD/
VDDNB
Boot VID
CCM
VID
CCM
Boot VID
CCM CCM
VID
CCM
CCM
PGOOD/
PGOODA
Figure 14. Simplified Sequence Timing Diagram
The detailed operation is described in the following.
that can be adjusted through the I2C interface. If RT8881A
operates in SVI mode, the I2C interface is disabled.
T0 : The RT8881A waits for VCC and PVCC POR. The
number of active phases is determined and latched when
POR = high.
T5 : A valid SVID command transaction occurs between
the processor and the RT8881A.
T1 : The SVC and SVD pins set the Boot VID. The SCL
and SDA pins set the operating mode. Boot VID and
operating mode are latched at EN rising edge.
T6 : The RT8881A starts VID-on-the-fly transition according
to the received SVID command and send a VOTF
Complete if the VID reaches target VID.
T2 : The enable signal goes high and all output voltages
ramp up to the boot VID in CCM. The soft start slew rate
is 3mV/μs.
T7 : The PWROK pin goes low and the SVI2 interface and
I2C interface stop running. All output voltages go back to
the boot VID in CCM operating but the operating
parameters are not affected.
T3 : All output voltages are within the regulation limits and
the PGOOD and PGOODA signal goes high.
T4 : The PWROK pin goes high and the SVI2 interface
and I2C interface start running. The RT8881A waits for SVID
command from processor and the operating parameters
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8881A-01 January 2014
T8 : The PWROK pin goes high and the SVI2 interface
and I2C interface start running. The RT8881A waits for SVI
command from processor and the operating parameters
that can be adjusted through the I2C interface.
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RT8881A
Power-Down Sequence
If the voltage at the EN pin falls below the enable falling
threshold, the controller is disabled. The voltage at the
PGOOD and PGOODA pins will immediately go low when
the EN pin voltage is pulled low and the controller will
execute soft-shutdown operation. The internal digital
circuit ramps down the reference voltage at the same slew
rate in soft-start, making VDD and VDDNB output voltages
gradually decrease in CCM. Each channel stops switching
when the voltage at the VSEN/VSENA pin reaches about
0.2V. The Boot VID information stored in the internal
register is cleared at POR. This event forces the RT8881A
to check the SVC and SVD inputs for a new boot VID
when the EN voltage goes high again.
PWROK Operation
The PWROK pin is an input pin, which is connected to
the global power good signal from the platform. In SVI
mode, logic high at this pin enables the SVI2 interface,
allowing data transaction between processor and the
RT8881A. If the PWROK input goes low during normal
operation, the SVI2 protocol stops running. The RT8881A
immediately drives SVT high and modifies all output
voltages back to the boot VID, which is stored in the internal
register right after the controller is enabled. The controller
does not read SVD and SVC inputs after the loss of
PWROK. If the PWROK input goes high again, the SVI2
protocol resumes running. The RT8881A then waits for
decoding the SVID command from processor for a new
VID and acts as previously described. The SVI2 protocol
runs only when the PWROK input goes high after the
voltage at the EN pin goes high; otherwise, the RT8881A
will not soft-start due to incorrect signal sequence.
Also, this pin enables the I2C interface in I2C mode,
allowing data transaction between SMBUS and the
RT8881A. If the PWROK input goes low during normal
operation, the I2C protocol stops running and the I2C
register do not affected by SDA and SCL. If the PWROK
input goes high again, the I2C protocol resumes running.
PGOOD and PGOODA
The PGOOD and PGOODA are open-drain logic outputs.
The PGOOD and PGOODA pins provide the power good
signal when VDD and VDDNB output voltage are within
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30
the regulation limits and no protection is triggered. The
PGOOD and PGOODA pins are typically tied to 3.3V or
5V power source through a pull-high resistor. During
shutdown state (EN = low) and the soft-start period, the
PGOOD and PGOODA voltage are pulled low. After a
successful soft-start and VDD and VDDNB output voltages
are within the regulation limits, the PGOOD and PGOODA
are released high individually.
The voltage at the PGOOD and PGOODA pins are pulled
low individually during normal operation when any of the
following events occurs : over-voltage protection, undervoltage protection, over-current protection, and logic-low
EN voltage. If one rail triggers protection, another rail's
PGOOD will be pull low after 5μs delay.
VID on-the-Fly Transition
After the RT8881A has received a valid SVID code, it enters
CCM mode and executes the VID on-the-fly transition by
stepping up/down the reference voltage of the required
controller channel(s) in a controlled slew rate, hence
allowing the output voltage(s) to ramp up/down to the target
VID. The output voltage slew rate during the VID on-thefly transition is faster than that in a soft-start/soft-shutdown
operation. If the new VID level is higher than the current
VID level, the controller begins stepping up the reference
voltage with a typical slew rate of 12mV/μs upward to the
target VID level. If the new level is lower than the current
VID level, the controller begins stepping down the reference
voltage with a typical slew rate of −12mV/μs downward to
the target VID level.
During the VID on-the-fly transition, the RT8881A will force
the controller channel to operate in CCM mode. If the
controller channel operates in the power-saving mode prior
to the VID on-the-fly transition, it will be in CCM mode
during the transition and then back to the power saving
mode at the end of the transition. The voltage at the
PGOOD and PGOODA pins will keep high during the VID
on-the-fly transition. The RT8881A checks the output
voltage for voltage related protections and send a VOTF
Complete at the end of VID on-the-fly transition. In the
event of receiving a VID off code, the RT8881A steps the
reference voltage of required controller channel down to
zero, hence making the required output voltage decreases
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RT8881A
to zero. The voltage at the PGOOD and PGOODA pins
will remain high since the VID code is valid.
Precise Reference Current Generation
The RT8881A includes complicated analog circuits inside
the controller. These analog circuits need very precise
reference voltage/current to drive these analog devices.
The RT8881A will auto generate a 2V voltage source at
IBIAS pin, and a 100kΩ resistor is required to be
connected between IBAIS and analog ground, as shown
in Figure 15. Through this connection, the RT8881A will
generate a 20μA current from the IBIAS pin to analog
ground, and this 20μA current will be mirrored inside the
RT8881A for internal use. Note that other type of
connection or other values of resistance applied at the
IBIAS pin may cause failure of the RT8881A's functions,
such as slew rate control, OFS accuracy, etc. In other
words, the IBIAS pin can only be connected with a 100kΩ
resistor to GND. The resistance accuracy of this resistor
is recommended to be 1% or higher.
keep full-phase operation. When the VDD VR receives
PSI0_L = 0 and PSI1_L = 0, the VDD VR takes phase
shedding operation and enters diode emulation mode. In
reverse, the VDD VR goes back to full-phase operation in
CCM upon receiving PSI0_L = 1 and PSI1_L = 0 or 1, or
PSI0_L = 0 and PSI1_L = 1, see Table 6. When the VDDNB
VR receives PSI0_L = 0 and PSI1_L = 1, it enters singlephase CCM, when the VDDNB VR receives PSI0_L = 0
and PSI1_L = 0, it enters single-phase diode emulation
mode. When the VDDNB VR goes back to full-phase CCM
operation after receiving PSI0_L = 1 and PSI1_L = 0 or 1,
see Table 7.
Table 6. VDD VR Power State
Full Phase
Number
4
3
Current
Mirror
2V
+
-
+
2
-
IBIAS
100k
1
PSI0_L : PSI1_L
Mode
11
4 phase CCM
01
4 phase CCM
00
1 phase DEM
11
3 phase CCM
01
3 phase CCM
00
1 phase DEM
11
2 phase CCM
01
2 phase CCM
00
1 phase DEM
11
1 phase CCM
01
1 phase CCM
00
1 phase DEM
Figure 15. IBAIS Setting
Table 7. VDDNB VR Power State
Power State Transition
In SVI mode, the RT8881A supports power state transition
function in VDD and VDDNB VR for the PSI[x]_L and
command from AMD processor. The PSI[x]_L bit in the
SVI2 protocol controls the operating mode of the RT8881A
controller channels. The default operation mode of VDD
and VDDNB VR is CCM.
When the VDD VR is in full-phase configuration and
receives PSI0_L = 0 and PSI1_L = 1, the VDD VR will
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Full Phase
Number
2
1
PSI0_L : PSI1_L
Mode
11
2 phase CCM
01
1 phase CCM
00
1 phase DEM
11
1 phase CCM
01
1 phase CCM
00
1 phase DEM
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RT8881A
Operation Mode Decision (SVI mode or I2C mode)
Dynamic Phase Control Capability
(only in I2C mode)
In I2C mode, the RT8881A has the ability to automatically
shed its operating phase number according to the total
load current to improve medium to light load range. This
function can be enabled or disabled through a register
setting in I2C mode, and the power state change command
from AMD processor by SVI interface is ignored.
Because the IMON pin voltage (VIMON) represents the total
current, and maximum VIMON corresponds to OCPSpike
current, the controller compares VIMON with threshold1
(VTH1) and threshold2 (VTH2) to decide the number of
operating phase. The RT8881A hops to higher phase
number operation when VIMON higher than VTH1 or VTH2.
No hysteresis and extra delay exists during an up phase
decision. However, hysteresis (V HYS ) and delay
time (<100μs) exist during a down phase decision. The
RT8881A triggers a timer when VIMON is lower than (VTH1
− VHYS1) or (VTH2 −VHYS2). If VIMON is always lower than
(VTH1 − VHYS2) or (VTH2 − VHYS2) during a certain amount
of time (<100μs), the controller goes to lower phase
number operation. For example, the default threshold2 is
4% of OCPSpike and the hysteresis is 2% of OCPSpike.
If OCPSpike is designed as 200A, the down phase
operation can only take place when load current is
continuously lower than 4A for 100μs and increases phase
number when load current higher then 8A. When RT8881A
detected the inductor current is down to zero in PS2 state
by phase pins, the RT8881A enters diode emulation mode.
Furthermore, when a DVID up or a QR event is triggered,
the RT8881A jumps back to maximum-phase operation
immediately. See Figure 16 for the dynamic phase control
mechanism.
PS0
TH1/HYS1
The RT8881A supports three modes for operating, allowing
one chip to be used for multiple applications. This greatly
enhances the freedom of design for users. The designer
should use pin-strapped method with SCL and SDA pins
to decide which mode to operate before EN rising. After
those pins are configured, the EN signal is used to force
the RT8881A into either pure SIV mode or I2C mode. Table
8 shows the Mode Decision setting.
Table 8. Mode Decision Setting
SCL
SDA
Function
0
0
SVI Mode
1
1
I C Mode
2
SVI Mode
In SVI mode, the RT8881A configures its function to be
fully compliant with AMD SVI2 Specification. All the setting
of RT8881A is configured by the SET1 and SET2 pins.
I2C Mode
In I2C mode, control and communication with RT8881A
may occur either through the SVI interface where an AMD
SVI command is present or alternatively through the I2C
interface for any other performance registers setting.
Boot VID
When EN goes high, both VDD and VDDNB output begin
to soft-start to the boot VID in CCM. Table 9 shows the
boot VID setting. The boot VID is determined by the SVC
and SVD input states at EN rising edge and it is stored in
the internal register. The digital soft-start circuit ramps up
the reference voltage at a controlled slew rates to reduce
inrush current during start up. When all the output voltage
are above power good threshold (300mV below boot VID)
at the end of soft-start, the controller asserts power good
after a time delay.
Table 9. 2-Bit Boot VID Code
DVID
Up
Sequential
Up
QR
Up
PS1
TH2/HYS2
Loading
Tracking
Down
PS2
Figure 16. Dynamic Phase Control Mechanism
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32
Initial Startup VID Code
SVC
SVD
VDD/VDDNB Output Voltage (V)
0
0
1.1
0
1
1
1
0
0.9
1
1
0.8
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RT8881A
Protection Function
Over-Current Protection
The RT8881A has dual OCP and per phase OCP
mechanisms. The dual OCP mechanism has two types of
thresholds. The first type, referred to as OCPTDC, is a
time and current based threshold. OCPTDC should trip
when the average output current exceeds TDC by some
percentage and for a period of time. This period of time is
referred to as the trigger delay. The second type, referred
to as OCPSpike, is a current based threshold. OCPSpike
should trip when the cycle-by-cycle output current
exceeds spike current by some percentage. If either
mechanism trips, then the controller asserts OCP_L and
delays any further action. This delay is called an action
delay. Refer to action delay time. After the action delay
has expired and the controller has allowed its current sense
filter to settle out and the current has not decreased below
the threshold, then the controller will turn off both highside MOSFETs and low-side MOSFETs of all channels.
The PHOCP threshold is determined as equation 25 :
(25)
IL,PERPHASE(MAX) = 680  8  16μA
DCR
The controller will turn off all high-side/low-side MOSFETs
to protect CPU if the per-phase over-current protection is
triggered.
Over-Voltage Protection (OVP)
The over-voltage protection circuit of the controller monitors
the output voltage via the VSENx pin after POR. When
VID is lower than 0.9V, once VSENx exceeds “0.9V +
325mV”, OVP is triggered and latched. When VID is larger
than 0.9V, once VSENx exceeds the internal reference
by 325mV, OVP is triggered and latched. The controller
will try to turn on low-side MOSFETs and turn off highside MOSFETs of all active phases of the controller to
protect the CPU. When OVP is triggered by one rail, the
other rail will also enter soft shut down sequence. A 1μs
delay is used in OVP detection circuit to prevent false
trigger.
The controller determines OCP by comparing the IIMON
with OCPTDC threshold and OCPSpike threshold, which
setting refer to the IMON pin setting section. Users can set
OCPSpike threshold, IL(Spike), by the current monitor
resistor RIMON of the following equation :
R
IL,SUM (SPIKE) = 3.19375  0.64  CSx
DCR
RIMON
(24)
And set the OCPTDC threshold, IL(TDC), refer to some
percentage of OCPSpike through Table 2.
For per phase OCP mechanism, the controller provides
over-current protection in each phase. For controller in
four-phase configuration, each phase can trigger Per-Phase
Over-Current Protection (PHOCP). The controller senses
each phase inductor current IL, and PHOCP comparator
compares sensed current with PHOCP threshold current,
as shown in Figure 17.
Current Mirror
1 I
8 SENAxN
PHOCP trigger
16µA
ISENAxN
Negative-Voltage Protection (NVP)
During OVP latch state, the controller also monitors the
VSENx pin for negative-voltage protection. Since the OVP
latch continuously turns on all low-side MOSFETs of the
controller, the controller may suffer negative output voltage.
As a consequence, when the VSENx voltage drops below
0V after triggering OVP, the controller will trigger NVP to
turn off all low-side MOSFETs of the controller while the
high-side MOSFETs remains off. After triggering NVP, if
the output voltage rises above 0V, the OVP latch will restart
to turn on all low-side MOSFETs. The NVP function will
be active only after OVP is triggered.
Under-Voltage Protection (UVP)
The controller implements under-voltage protection of VOUT.
If VSENx is less than the internal reference by −425mV,
the controller will trigger UVP latch. The UVP latch will
turn off both high-side and low-side MOSFETs. When UVP
is triggered by one rail, the other rail will also enter soft
shutdown sequence. A 3μs delay is used in UVP detection
circuit to prevent false trigger.
Figure 17. Per-Phase OCP Setting
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RT8881A
Under-Voltage Lock Out (UVLO)
During normal operation, if the voltage at the VCC pin
drops below 4.1V or the voltage at PVCC pin drops below
3.5V, the VR will trigger UVLO. The UVLO protection
forces all high-side MOSFETs and low-side MOSFETs off
by shutting down internal PWM logic drivers. A 3μs delay
is used in UVLO detection circuit to prevent false trigger.
SVI2 Wire Protocol
The RT8881A complies with AMD's Voltage Regulator
Specification, which defines the Serial VID Interface 2
(SVI2) protocol. With SVI2 protocol, the processor directly
controls the reference voltage level of each individual
controller channel and determines which controller
operates in power saving mode.
START
SVC
2
3
4
5
6
7
8
VID
Bit [0]
VID Bits [7:1]
PSI0_L
1
The SVI2 interface is a three wire bus that connects a
single master to one or above slaves. The master initiates
and terminates SVI2 transactions and drives the clock,
SVC, and the data, SVD, during a transaction. The slave
drives the telemetry, SVT during a transaction. The AMD
processor is always the master. The RT8881A always is
the slave and do not driver the SVD during the ACK bit.
The RT8881A receives the SVID code and acts accordingly.
The SVI protocol of the RT8881A supports 20MHz high
speed mode I2C, which is based on SVD data packet and
is listed in Figure 18. Table 10 shows the SVD data packet
of the RT8881A. An SVD packet consists of a Start signal,
three data bytes after each byte, and a Stop signal. The
8-bit serial VID codes are listed in Table 1.
PSI1_L
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
SVD
Ack
Ack
Ack
Figure 18. SVD Bit Definition
Table 10. SVD Data Packet
Bit Time
Description
1:5
Always 11000b
VDD domain selector bit, if set then the following two data bytes contains the VID for VDD, the
PSI state for VDD, and the load-line slope trim and offset trim state for VDD
6
7
VDDNB domain selector bit, if set then the following two data bytes contains the VID for VDDNB,
the PSI state for VDDNB, and the load-line slope trim and offset trim state for VDDNB.
8
Always 0b
9
ACK bit
10
PSI0_L
11 : 17
VID Code bits [7:1]
19
VID Code bit [0]
20
PSI1_L
21
TFN (Telemetry Functionality)
22 : 24
Load Line Slope Trim [2:0]
25 : 26
Offset Trim [1:0]
27
ACK bit
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RT8881A
PSI[x]_L and TFN
SVI2 defines two PSI levels, showed as Table 10. It is
possible for the processor to assert or deassert PSI0_L
and PSI1_L out of order. PSI0_L takes priority over PSI1_L.
If PSI0_L is deasserted but PSI1_L is still asserted, the
VR must be ready to deliver full infrastructure current,
meaning IDDSpike current.
Table 11. PSI0_L, PSI1_L and TFN Definition
Bit
Define
Description
10
PSI0_L
Power State Indicate level 0. When this signal is asserted (active-low) the processor is in
a low enough power state for the VR to take some action to boost efficiency, such as drop
phases.
20
PSI1_L
Power State Indicate level 1. When this signal is asserted (active-low) the processor is in
a low enough power state for the VR to take some action, in additional to what it is doing
with PSI0_L asserted, to boost efficiency, such as pulse skip or diode emulation.
21
TFN
Telemetry Functionality. This is an active high signal that allows the processor to control
the telemetry functionality of the VR.
The TFN along with the VDD and VDDNB domain selector
bits are used by the processor to change the functionality
of telemetry, see Table 12 for more information.
Table 13. Load Line Slope Trim Definition
LL Slope
Trim [22 : 24]
Description
000
Remove all LL droop from output
001
Initial LL Slope 40%
Description
010
Initial LL Slope 20%
011
Initial LL Slope (Default)
100
Initial LL Slope +20%
101
Initial LL Slope +40%
110
Initial LL Slope +60%
111
Initial LL Slope +80%
101
Telemetry is in voltage only
mode. Only the voltage of VDD
and VDDNB domains are sent.
(Default)
Telemetry is in voltage and
current mode. V & I are sent for
VDD and VDDNB domains.
Telemetry is disabled.
111
Reserved
Table 12. TFN Truth Table
VDD, VDDNB
and TFN Bits
[6, 7, 21]
001
011
Dynamic Load-Line Slope Trim
The RT8881A have the ability for the processor to
manipulate the load-line slope of VDD and VDDNB
independently via the serial VID interface. The slope
manipulation applies to the initial load-line slope. A loadline slop trim will typically coincide with a VOTF change.
Refer to Table 13 for more information about the load-line
capabilities of the RT8881A.
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Dynamic Offset Trim
The RT8881A have ability for the processor to manipulate
the offset of VDD and VDDNB independently via the serial
VID interface. Refer to Table 14 for more information about
the offset capabilities of the RT8881A. For RT8881A, the
initial offset always be set to zero.
Table 14. Offset Trim Definition
Offset Trim
[25:26]
Description
00
Remove all Offset from output
01
Initial Offset 25mV
10
Use Initial Offset (Default)
11
Initial Offset +25mV
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RT8881A
SVC. A bit TFN at SVD packet along with the VDD and
VDDNB domain selector bits are used by the processor
to change the functionality of telemetry. The telemetry bit
definition is listed in Figure 19. The detailed SVI2
specification is outlined in the AMD Voltage Regulator and
Voltage Regulator Module (VRM) and Serial VID Interface
2 (SVI2) Specification.
Telemetry Format
After the RT8881A has received the stop sequence, it
decodes the received serial VID code and executes the
command. SVI2 VR Controller has the ability to sample
and report voltage and current for the VDD and VDDNB
domains. The Controller reports this telemetry serially over
the SVT wire which is clocked by the processor driven
Voltage and Current
Mode Selection
Bit Time…… START
1
2
3
VDDNB Voltage Bit in Voltage Only Mode;
Current Bit in Voltage and Current Mode
VDD Voltage Bits
4
5
6
7
8
10
9
11
12
13
14
15
16
17
18
19
STOP
20
SVC
SVT
Figure 19. Telemetry Bit Definition
I2C Interface
An I2C interface is used to communicate with the RT8881A
It is important to note that the I2C interface of the RT8881A
and the address for RT8881A is 0x40. Figure 20 shows
should write register I2C_LOCK_IND to 0x5A before any
online register update and write back to 0xff after update
done.
2
the I C format employed by the RT8881A.
The bus provides read and write access to the internal
performance registers for setting and reading of operating
parameters and operates at 400kHz. The Operating
parameters that can be adjusted through the I2C interface.
Read N bytes from RT8881A
Slave Address
Register Address
S
0
A
R/W
MSB
Slave Address
A Sr
1
A
A
Assume Address = m
MSB
Data 2
LSB
Data 1
Data for Address = m
LSB
MSB
Data N
LSB
A
A
P
Data for Address = m+N-1
Data for Address = m+1
Write N bytes to RT8881A
Slave Address
Register Address
S
0
R/W
A
MSB
Data 1
A
Assume Address = m
LSB
MSB
Data 2
LSB
A
Data for Address = m
MSB
A
Data for Address = m+1
Data N
LSB
A P
Driven by Master,
Driven by Slave (RT8881A), P Stop,
S Start,
Data for Address = m+N-1
Sr Repeat Start
Figure 20. I2C format
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DS8881A-01 January 2014
RT8881A
SDA
tLOW
tF
tSU;DAT
tR
tF
tSP
tHD;STA
tR
tBUF
SCL
S
tHD;STA
tHD;DAT
tHIGH
tSU;STA
tSU;STO
Sr
P
S
Figure 21. I2C Waveform Information
Thermal Considerations
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-52L 6x6 package, the thermal resistance, θJA, is
26.5°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
4.0
Maximum Power Dissipation (W)
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
Four-Layer PCB
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 22. Derating Curve of Maximum Power
Dissipation
PD(MAX) = (125°C − 25°C) / (26.5°C/W) = 3.77W for
WQFN-52L 6x6 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 22 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
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37
RT8881A
Outline Dimension
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min.
Max.
Min.
Max.
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
5.950
6.050
0.234
0.238
D2
4.650
4.750
0.183
0.187
E
5.950
6.050
0.234
0.238
E2
4.650
4.750
0.183
0.187
e
0.400
0.016
L
0.350
0.450
0.014
0.018
L1
0.300
0.400
0.012
0.016
W-Type 52L QFN 6x6 Package
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RT8881A
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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