RT8880C

®
RT8880C
Dual-Output PWM Controller with 3 Integrated Drivers for
AMD SVI2 Mobile CPU Power Supply
General Description
Features
The RT8880C is a 3 + 2 phases PWM controller, and is
compliant with AMD SVI2 Voltage Regulator Specification
to support both CPU core (VDD) and Northbridge portion
of the CPU (VDDNB). The RT8880C features CCRCOT
(Constant Current Ripple Constant On-Time) with G-NAVP
(Green-Native AVP), which is Richtek's proprietary
topology. The G-NAVP makes it an easy setting controller
to meet all AMD AVP (Adaptive Voltage Positioning) VDD/
VDDNB requirements. The droop is easily programmed
by setting the DC gain of the error amplifier. With proper
compensation, the load transient response can achieve
optimized AVP performance. The controller also uses the
interface to issue VOTF Complete and to send digitally
encoded voltage and current values for the VDD and
VDDNB domains. It can operate in single phase and diode
emulation mode and reach up to 90% efficiency in different
modes according to different loading conditions. The
RT8880C provides special purpose offset capabilities by
pin setting. The RT8880C also provides power good
indication, over-current indication (OCP_L) and dual OCP
mechanism for AMD SVI2 CPU core and NB. It also
features complete fault protection functions including overvoltage, under-voltage and negative-voltage protections.

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











3/2/1-Phase (VDD) + 2/1/0-Phase (VDDNB) PWM
Controller
3 Embedded MOSFET Drivers
G-NAVPTM Topology
Support Dynamic Load-Line and Zero Load-Line
Diode Emulation Mode at Light Load Condition
SVI2 Interface to Comply with AMD Power
Management Protocol
Build-in ADC for VOUT and IOUT Reporting
Immediate OV, UV and NV Protections and UVLO
Programmable Dual OCP Mechanism
0.5% DAC Accuracy
Fast Transient Response
Power Good Indicator
Over-Current Indicator
RoHS Compliant and Halogen Free
Applications


AMD SVI2 Mobile CPU
Laptop Computer
Simplified Application Circuit
RT8880C
PHASE1
OCP_L
MOSFET
PHASE2
MOSFET
PWM3
RT9610
PHASEA1
MOSFET
PWMA2
RT9610
SVC
To CPU
SVD
SVT
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8880C-02
January 2015
VVDD
MOSFET
VVDDNB
MOSFET
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT8880C
Ordering Information
Pin Configurations
RT8880C
(TOP VIEW)
PHASE2
LGATE2
PVCC
LGATE1
PHASE1
UGATE1
BOOT1
LGATEA1
PHASEA1
UGATEA1
BOOTA1
PWMA2
TONSETA
Package Type
QW : WQFN-52L 6x6 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Richtek products are :

RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
RT8880CGQW : Product Number
RT8880C
GQW
YMDNN
YMDNN : Date Code
52 51 50 49 48 47 46 45 44 43 42 41 40
UGATE2
BOOT2
PWM3
TONSET
ISEN2P
ISEN2N
ISEN1N
ISEN1P
ISEN3P
ISEN3N
VSEN
FB
COMP
1
39
2
38
3
37
4
36
5
35
6
7
34
GND
33
8
32
9
10
31
30
53
11
29
12
28
13
27
PGOOD
PGOODA
EN
ISENA1P
ISENA1N
ISENA2N
ISENA2P
VSENA
FBA
COMPA
IBIAS
VCC
OCP_L
14 15 16 17 18 19 20 21 22 23 24 25 26
RGND
IMON
V064
IMONA
VDDIO
PWROK
SVC
SVD
SVT
OFS
OFSA
SET1
SET2
Note :
WQFN-52L 6x6
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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2
is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
RT8880C
Functional Pin Description
Pin No.
Pin Name
Pin Function
3
PWM3
PWM Outputs for Channel 3 VDD Controller.
4
TONSET
VDD Controller On-Time Setting. Connect this pin to the converter input
voltage, VIN, through a resistor, RTON, to set the on-time of UGATE and
also the output voltage ripple of VDD controller.
5, 8, 9
ISEN1P to ISEN3P
Positive Current Sense Input of Channel 1, 2 and 3 for VDD Controller.
6, 7, 10
ISEN1N to ISEN3N
Negative Current Sense Input of Channel 1, 2 and 3 for VDD Controller.
11
VSEN
VDD Controller Voltage Sense Input. This pin is connected to the terminal
of VDD controller output voltage.
12
FB
Output Voltage Feedback Input of VDD Controller. This pin is the negative
input of the error amplifier for the VDD controller.
13
COMP
14
RGND
15
IMON
16
V064
Fixed 0.64V Output Reference Voltage Output. This voltage is only used to
offset the output voltage of IMON pin and IMONA pin. Connect a 0.47F
capacitor from this pin to GND.
17
IMONA
Current Monitor Output for the VDDNB Controller. This pin outputs a
voltage proportional to the output current.
18
VDDIO
Processor Memory Interface Power Rail and Serves as the Reference for
PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the
SVI pins.
19
PWROK
System Power Good Input. If PWROK is low, the SVI interface is disabled
and VR returns to BOOT-VID state with initial load line slope and initial
offset. If PWROK is high, the SVI interface is running and the DAC
decodes the received serial VID codes to determine the output voltage.
20
SVC
Serial VID Clock Input from Processor.
21
SVD
Serial VID Data input from Processor. This pin is a serial data line.
22
SVT
Serial VID Telemetry Input from VR. This pin is a push-pull output.
23
OFS
Over Clocking Offset Setting for the VDD Controller.
24
OFSA
Over Clocking Offset Setting for the VDDNB Controller.
25
SET1
1st Platform Setting. Platform can use this pin to set OCP_TDC threshold,
DVID compensation bit1 and internal ramp slew rate.
26
SET2
2st Platform Setting. Platform can use this pin to set quick response
threshold, OCP_TDC trigger delay time, DVID compensation bit0, VDDNB
rail zero load-line enable setting and over clocking offset enable setting.
27
OCP_L
Over-Current Indicator for Dual OCP Mechanism. This pin is an open-drain
output.
28
VCC
Controller Power Supply Input. Connect this pin to 5V with an 1F or
greater ceramic capacitor for decoupling.
Compensation Node of the VDD Controller.
Return Ground of VDD and VDDNB Controller. This pin is the common
negative input of output voltage differential remote sense for VDD and
VDDNB controllers.
Current Monitor Output for the VDD Controller. This pin outputs a voltage
proportional to the output current.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8880C-02
January 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT8880C
Pin No.
Pin Name
Pin Function
29
IBIAS
Internal Bias Current Setting. Connect only a 100k resistor from this pin to
GND to generate bias current for internal circuit. Place this resistor as close to
the IBIAS pin as possible.
30
COMPA
Compensation Node of the VDDNB Controller.
31
FBA
Output Voltage Feedback Input of VDDNB Controller. This pin is the negative
input of the error amplifier for the VDDNB controller.
32
VSENA
VDDNB Controller Voltage Sense Input. This pin is connected to the terminal
of VDDNB controller output voltage.
33, 36
ISENA2P,
ISENA1P
Positive Current Sense Input of Channel 1 and 2 for VDDNB Controller.
34, 35
ISENA2N,
ISENA1N
Negative Current Sense Input of Channel 1 and 2 for VDDNB Controller.
37
EN
Controller Enable Control Input. A logic high signal enables the controller.
38
PGOODA
Power Good Indicator for the VDDNB Controller. This pin is an open-drain
output.
39
PGOOD
Power Good Indicator for the VDD Controller. This pin is an open-drain output.
40
TONSETA
VDDNB Controller On-Time Setting. Connect this pin to the converter input
voltage, VIN, through a resistor, RTONNB, to set the on-time of
UGATE_VDDNB and also the output voltage ripple of VDDNB controller.
41
PWMA2
PWM Output for Channel 2 of VDDNB Controller.
46, 2, 42
BOOT1,
BOOT2,
BOOTA1
Bootstrap Supply for High-Side MOSFET. This pin powers high-side MOSFET
driver.
47, 1, 43
UGATE1,
UGATE2,
UGATEA1
High-Side Gate Driver Outputs. Connect this pin to Gate of high-side
MOSFET.
48, 52, 44
PHASE1,
PHASE2,
PHASEA1
Switch Nodes of High-Side Driver. Connect this pin to high-side MOSFET
Source together with the low-side MOSFET Drain and the inductor.
49, 51, 45
LGATE1,
LGATE2,
LGATEA1
Low-Side Gate Driver Outputs. This pin drives the Gate of low-side MOSFET.
50
PVCC
Driver Power. Connect this pin to GND by ceramic capacitor larger than 1F.
53 (Exposed Pad)
GND
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
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is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
RT8880C
PGOODA
OCP_L
PGOOD
VCC
EN
PWROK
VDDIO
SVT
SVD
SVC
VSEN
VSENA
OFSA
IMONI
IMONAI
OFS
SET2
SET1
Function Block Diagram
UVLO
MUX
GND
ADC
SVI2 Interface
Configuration Registers
Control Logic
IBIAS
OFS/OFSA
Load Line
/Load Line A
From Control Logic
RGND
RSET/RSETA
PWMA2
ERROR
VSETA
AMP
+
+
Offset
Cancellation
-
FBA
COMPA
+
-
+
x2
-
ISENA1N
ISENA2P
V064
+
x2
-
ISENA2N
BOOTA1
1-PH
Driver
TONA
+
0.4
-
UGATEA1
PHASEA1
Current
Balance
RSETA
Average
IBA2
IMONA
IMONAI
+
OCP_TDCA,
OCP_SPIKEA
From Control Logic
IBA1
OCA
-
IBA2
Driver
POR
PVCC
To Protection Logic
TONSET
OV/UV/NV
VSENA
DAC
Soft-Start & Slew Rate
Control
VSET
FB
ERROR
AMP
+
+
-
+
Current mirror
ISEN1P
ISEN1N
+
x1
-
ISEN2P
+
x1
-
PWM
CMP
QR
TON
GEN
PWM2
2-PH
Driver
UGATEx
PHASEx
LGATEx
PWM3
TON
IB1
+
0.4
-
RSET
Current mirror
IB2
Current Balance
Average
IMONI
Current mirror
+
x1
-
BOOTx
PWM1
Offset
Cancellation
COMP
ISEN3N
TON
GENA PWMA1
LGATEA1
IBA1
Current mirror
ISEN3P
QRA
PWM
CMPA
Current mirror
ISENA1P
ISEN2N
TONSETA
OCP Threshold
DAC
Soft-Start & Slew
Rate Control
RGND
Loop Control
Protection Logic
IB1
IB2
IB3
IB3
OCP_TDC,
OCP_SPIKE
+
OC
-
VSEN
To Protection Logic
OV/UV/NV
IMON V064
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8880C-02
January 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT8880C
Operation
MUX and ADC
Error Amplifier
The MUX supports the inputs from SET1, SET2, OFS,
OFSA, IMON, IMONA, VSEN, or VSENA. The ADC
converts these analog signals to digital codes for reporting
or performance adjustment.
The Error amplifier generates COMP/COMPA signal by
the difference between VSET/VSETA and FB/FBA.
SVI2 Interface
The SVI2 interface uses the SVC, SVD, and SVT pins to
communicate with CPU. The RT8880C's performance and
behavior can be adjusted by commands sent by CPU or
platform.
Offset Cancellation
This block cancels the output offset voltage from voltage
ripple and current ripple to achieve accurate output voltage.
PWM CMPx
The PWM comparator compares COMP signal and current
feedback signal to generate a signal for TONGENx.
UVLO
TONGEN/TONGENA
The UVLO detects the VCC pin voltages for under voltage
lockout protection and power on reset operation.
This block generates an on-time pulse which high interval
is based on the on-time setting and current balance.
Loop Control Protection Logic
Current Balance
Loop control protection logic detects EN and UVLO signals
to initiate soft-start function and control PGOOD,
PGOODA and OCP_L signals after soft-start is finished.
When dual OCP event occurs, the OCP_L pin voltage will
be pulled low.
Per-phase current is sensed and adjusted by adjusting
on-time of each phase to achieve current balance for each
phase.
DAC
The DAC receives VID codes from the SVI2 control logic
to generate an internal reference voltage (VSET/VSETA)
for controller.
Soft-Start and Slew-Rate Control
OC/OV/UV/NV
VSEN/VSENA and output current are sensed for overcurrent, over-voltage, under-voltage, and negative-voltage
protections.
RSET/RSETA
The Ramp generator is designed to improve noise immunity
and reduce jitter.
This block controls the slew rate of the internal reference
voltage when output voltage changes.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
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is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
RT8880C
Table 1. Serial VID Codes
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
0000_0000
1.55000
0010_0111
1.30625
0100_1110
1.06250
0111_0101
0.81875
0000_0001
1.54375
0010_1000
1.30000
0100_1111
1.05625
0111_0110
0.81250
0000_0010
1.53750
0010_1001
1.29375
0101_0000
1.05000
0111_0111
0.80625
0000_0011
1.53125
0010_1010
1.28750
0101_0001
1.04375
0111_1000
0.80000
0000_0100
1.52500
0010_1011
1.28125
0101_0010
1.03750
0111_1001
0.79375
0000_0101
1.51875
0010_1100
1.27500
0101_0011
1.03125
0111_1010
0.78750
0000_0110
1.51250
0010_1101
1.26875
0101_0100
1.02500
0111_1011
0.78125
0000_0111
1.50625
0010_1110
1.26250
0101_0101
1.01875
0111_1100
0.77500
0000_1000
1.50000
0010_1111
1.25625
0101_0110
1.01250
0111_1101
0.76875
0000_1001
1.49375
0011_0000
1.25000
0101_0111
1.00625
0111_1110
0.76250
0000_1010
1.48750
0011_0001
1.24375
0101_1000
1.00000
0111_1111
0.75625
0000_1011
1.48125
0011_0010
1.23750
0101_1001
0.99375
1000_0000
0.75000
0000_1100
1.47500
0011_0011
1.23125
0101_1010
0.98750
1000_0001
0.74375
0000_1101
1.46875
0011_0100
1.22500
0101_1011
0.98125
1000_0010
0.73750
0000_1110
1.46250
0011_0101
1.21875
0101_1100
0.97500
1000_0011
0.73125
0000_1111
1.45625
0011_0110
1.21250
0101_1101
0.96875
1000_0100
0.72500
0001_0000
1.45000
0011_0111
1.20625
0101_1110
0.96250
1000_0101
0.71875
0001_0001
1.44375
0011_1000
1.20000
0101_1111
0.95625
1000_0110
0.71250
0001_0010
1.43750
0011_1001
1.19375
0110_0000
0.95000
1000_0111
0.70625
0001_0011
1.43125
0011_1010
1.18750
0110_0001
0.94375
1000_1000
0.70000
0001_0100
1.42500
0011_1011
1.18125
0110_0010
0.93750
1000_1001
0.69375
0001_0101
1.41875
0011_1100
1.17500
0110_0011
0.93125
1000_1010
0.68750
0001_0110
1.41250
0011_1101
1.16875
0110_0100
0.92500
1000_1011
0.68125
0001_0111
1.40625
0011_1110
1.16250
0110_0101
0.91875
1000_1100
0.67500
0001_1000
1.40000
0011_1111
1.15625
0110_0110
0.91250
1000_1101
0.66875
0001_1001
1.39375
0100_0000
1.15000
0110_0111
0.90625
1000_1110
0.66250
0001_1010
1.38750
0100_0001
1.14375
0110_1000
0.90000
1000_1111
0.65625
0001_1011
1.38125
0100_0010
1.13750
0110_1001
0.89375
1001_0000
0.65000
0001_1100
1.37500
0100_0011
1.13125
0110_1010
0.88750
1001_0001
0.64375
0001_1101
1.36875
0100_0100
1.12500
0110_1011
0.88125
1001_0010
0.63750
0001_1110
1.36250
0100_0101
1.11875
0110_1100
0.87500
1001_0011
0.63125
0001_1111
1.35625
0010_0110
1.11250
0110_1101
0.86875
1001_0100
0.62500
0010_0000
1.35000
0100_0111
1.10625
0110_1110
0.86250
1001_0101
0.61875
0010_0001
1.34375
0100_1000
1.10000
0110_1111
0.85625
1001_0110
0.61250
0010_0010
1.33750
0100_1001
1.09375
0111_0000
0.85000
1001_0111
0.60625
0010_0011
1.33125
0100_1010
1.08750
0111_0001
0.84375
1001_1000
0.60000
0010_0100
1.32500
0100_1011
1.08125
0111_0010
0.83750
1001_1001
0.59375
0010_0101
1.31875
0100_1100
1.07500
0111_0011
0.83125
1001_1010
0.58750
0010_0110
1.31250
0100_1101
1.06875
0111_0100
0.82500
1001_1011
0.58125
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8880C-02
January 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
7
RT8880C
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
1001_1100
0.57500
1011_0101 *
0.41875
1100_1110 *
0.26250
1110_0111*
0.10625
1001_1101
0.56875
1011_0110 *
0.41250
1100_1111 *
0.25625
1110_1000*
0.10000
1001_1110
0.56250
1011_0111 *
0.40625
1101_0000 *
0.25000
1110_1001*
0.09375
1001_1111
0.55625
1011_1000 *
0.40000
1101_0001 *
0.24375
1110_1010*
0.08750
1010_0000
0.55000
1011_1001 *
0.39375
1101_0010 *
0.23750
1110_1011*
0.08125
1010_0001
0.54375
1011_1010 *
0.38750
1101_0011 *
0.23125
1110_1100*
0.07500
1010_0010
0.53750
1011_1011 *
0.38125
1101_0100 *
0.22500
1110_1101*
0.06875
1010_0011
0.53125
1011_1100 *
0.37500
1101_0101 *
0.21875
1110_1110*
0.06250
1010_0100
0.52500
1011_1101 *
0.36875
1101_0110 *
0.21250
1110_1111*
0.05625
1010_0101
0.51875
1011_1110 *
0.36250
1101_0111 *
0.20625
1111_0000*
0.05000
1010_0110
0.51250
1011_1111 *
0.35625
1101_1000 *
0.20000
1111_0001*
0.04375
1010_0111
0.50625
1100_0000 *
0.35000
1101_1001 *
0.19375
1111_0010*
0.03750
1010_1000 *
0.50000
1100_0001 *
0.34375
1101_1010 *
0.18750
1111_0011*
0.03125
1010_1001 *
0.49375
1100_0010 *
0.33750
1101_1011 *
0.18125
1111_0100*
0.02500
1010_1010 *
0.48750
1100_0011 *
0.33125
1101_1100 *
0.17500
1111_0101*
0.01875
1010_1011 *
0.48125
1100_0100 *
0.32500
1101_1101 *
0.16875
1111_0110*
0.01250
1010_1100 *
0.47500
1100_0101 *
0.31875
1101_1110 *
0.16250
1111_0111*
0.00625
1010_1101 *
0.46875
1100_0110 *
0.31250
1101_1111 *
0.15625
1111_1000*
0.00000
1010_1110 *
0.46250
1100_0111 *
0.30625
1110_0000*
0.15000
1111_1001*
OFF
1010_1111 *
0.45625
1100_1000 *
0.30000
1110_0001*
0.14375
1111_1010*
OFF
1011_0000 *
0.45000
1100_1001 *
0.29375
1110_0010*
0.13750
1111_1011*
OFF
1011_0001 *
0.44375
1100_1010 *
0.28750
1110_0011*
0.13125
1111_1100*
OFF
1011_0010 *
0.43750
1100_1011 *
0.28125
1110_0100*
0.12500
1111_1101*
OFF
1011_0011 *
0.43125
1100_1100 *
0.27500
1110_0101*
0.11875
1111_1110*
OFF
1011_0100 *
0.42500
1100_1101 *
0.26875
1110_0110*
0.11250
1111_1111*
OFF
* Indicates TOB is 80mV for this VID code; unconditional VR controller stability required at all VID codes
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
RT8880C
Table 2. SET1 Pin Setting for VDD Controller OCP_TDC Threshold,
DVID Compensation and Ramp Ratio (RSET)
SET1 Pin
Voltage
Before
Current
Injection
VSET1 (mV)
RSET
SET1 Pin
Voltage
Before
Current
Injection
VSET1 (mV)
34
145%
836
145%
59
130%
861
130%
115%
886
100%
911
135
85%
936
85%
160
70%
961
70%
235
145%
1036
145%
260
130%
1061
130%
115%
1086
100%
1112
335
85%
1137
85%
360
70%
1162
70%
435
145%
1237
145%
460
130%
1262
130%
115%
1287
100%
1312
535
85%
1337
85%
560
70%
1362
70%
636
145%
1437
145%
661
130%
1462
130%
115%
1487
100%
1512
736
85%
1537
85%
761
70%
1562
70%
85
110
285
310
485
510
686
711
OCP_TDC
(Respect
to OCP_
SPIKE)
60%
70%
75%
Disable
DVID
Compensation
[1]
0
0
0
0
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8880C-02
January 2015
OCP_TDC
(Respect
to OCP_
SPIKE)
60%
70%
75%
Disable
DVID
Compensation
[1]
1
1
1
1
RSET
115%
100%
115%
100%
115%
100%
115%
100%
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9
RT8880C
Table 3. SET1 Pin Setting for VDDNB Controller OCP_TDCA Threshold,
DVIDA Compensation and Ramp Ratio (RSETA)
SET1 Pin
SET1 Pin
Voltage
Voltage
OCP_TDCA
OCP_TDCA
Difference
DVIDA
DVIDA
Difference
(Respect to
(Respect to
VSET1 (Before
Compensation RSETA VSET1 (Before
Compensation RSETA
OCP_
OCP_
and After
and After
[1]
[1]
SPIKEA)
SPIKEA)
Current
Current
Injection) (mV)
Injection) (mV)
34
145%
836
145%
59
130%
861
130%
115%
886
100%
911
135
85%
936
85%
160
70%
961
70%
235
145%
1036
145%
260
130%
1061
130%
115%
1086
100%
1112
335
85%
1137
85%
360
70%
1162
70%
435
145%
1237
145%
460
130%
1262
130%
115%
1287
100%
1312
535
85%
1337
85%
560
70%
1362
70%
636
145%
1437
145%
661
130%
1462
130%
115%
1487
100%
1512
736
85%
1537
85%
761
70%
1562
70%
85
110
285
310
485
510
686
711
60%
70%
75%
Disable
0
0
0
0
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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10
60%
70%
75%
Disable
1
1
1
1
115%
100%
115%
100%
115%
100%
115%
100%
is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
RT8880C
Table 4. SET2 Pin Setting for VDD Controller QR Threshold, DVID Compensation,
NB 0LL and OCP Trigger Delay
NB OLL
Setting
OCPTRGDELAY
(for VDD/VDDNB)
0
10ms
0
40ms
122
1
10ms
172
1
40ms
222
0
10ms
0
40ms
323
1
10ms
373
1
40ms
423
0
10ms
0
40ms
523
1
10ms
573
1
40ms
623
0
10ms
0
40ms
723
1
10ms
773
1
40ms
823
0
10ms
0
40ms
924
1
10ms
974
1
40ms
1024
0
10ms
0
40ms
1124
1
10ms
1174
1
40ms
1224
0
10ms
0
40ms
1324
1
10ms
1375
1
40ms
1425
0
10ms
0
40ms
1525
1
10ms
1575
1
40ms
SET2 Pin Voltage
Before Current Injection VSET2 (mV)
QRTH
(for VDD)
DVID
Compensation [0]
19
72
272
473
673
874
Disable
39mV
47mV
55mV
Disable
0
0
0
0
1
1074
39mV
1274
1475
47mV
55mV
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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January 2015
1
1
1
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11
RT8880C
Table 5. SET2 Pin Setting for VDDNB Controller QR Threshold,
DVIDA Compensation and External Offset Function
SET2 Pin Voltage Difference VSET2
OFSENABLE OFSAENABLE
(Before and After Current Injection) (mV)
DVIDA
Compensation [0]
19
Disable
72
0
122
55mV
0
222
Disable
272
1
323
39mV
47mV
55mV
0
423
Disable
473
0
523
39mV
47mV
573
55mV
1
623
Disable
673
1
39mV
723
47mV
773
55mV
823
Disable
874
0
924
55mV
0
1024
Disable
1074
1
1124
1174
55mV
1
Disable
1274
0
1324
39mV
47mV
55mV
1
1425
1475
39mV
47mV
1224
1375
39mV
47mV
974
Disable
1
39mV
1525
47mV
1575
55mV
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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12
39mV
47mV
172
373
QRTHA
(for VDDNB)
is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
RT8880C
Table 6. DVID Boost Compensation Setting
DVID Compensation [1]
DVID Compensation [0]
DVID Boost Compensation
0
0
22.5mV
0
1
18mV
1
0
13.5mV
1
1
9mV
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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January 2015
is a registered trademark of Richtek Technology Corporation.
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13
RT8880C
Absolute Maximum Ratings















(Note 1)
WQFN-52L 6x6 ----------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
WQFN-52L 6x6, θJA -----------------------------------------------------------------------------------------------WQFN-52L 6x6, θJC ----------------------------------------------------------------------------------------------Junction Temperature ---------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------------------Storage Temperature Range ------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------
Recommended Operating Conditions




−0.3V to 6V
−0.3V to 6V
−0.3V to 0.3V
−0.3V to 28V
−0.3V to 6V
VCC to GND --------------------------------------------------------------------------------------------------------PVCC to GND ------------------------------------------------------------------------------------------------------RGND to GND ------------------------------------------------------------------------------------------------------TONSET, TONSETA to GND ------------------------------------------------------------------------------------BOOTx to PHASEx -----------------------------------------------------------------------------------------------PHASEx to GND
DC ---------------------------------------------------------------------------------------------------------------------< 20ns ---------------------------------------------------------------------------------------------------------------LGATEx to GND
DC ---------------------------------------------------------------------------------------------------------------------< 20ns ---------------------------------------------------------------------------------------------------------------UGATEx to PHASEx
DC ---------------------------------------------------------------------------------------------------------------------< 20ns ---------------------------------------------------------------------------------------------------------------Other Pins -----------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
−0.3V to 32V
−8V to 38V
−0.3V to 6V
−2.5V to 7.5V
−0.3V to 6V
−2.5V to 7.5V
−0.3V to (VCC + 0.3V)
3.77W
26.5°C/W
6.5°C/W
150°C
260°C
−65°C to 150°C
2kV
(Note 4)
Supply Voltage, VCC ---------------------------------------------------------------------------------------------Input Voltage, VIN -------------------------------------------------------------------------------------------------Junction Temperature Range ------------------------------------------------------------------------------------Ambient Temperature Range -------------------------------------------------------------------------------------
4.5V to 5.5V
4.5V to 26V
−40°C to 125°C
−40°C to 85°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Power Supply
Supply Current
IVCC
EN = 3V, Not Switching
--
12
--
mA
Shutdown Current
ISHDN
EN = 0V
--
--
5
A
PVCC Supply Voltage
VPVCC
4.5
--
5.5
V
PVCC Supply Current
IPVCC
--
150
--
A
VBOOTx = 5V, Not Switching
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
RT8880C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Driver Power On Reset (Driver POR)
Driver POR Threshold
Driver POR Hysteresis
VPOR_r
PVCC Rising
--
3.85
4.1
VPOR_f
PVCC Falling
3.4
3.65
--
--
200
--
mV
VFB = 1.0000  1.5500
(No Load, CCM Mode )
0.5
0
0.5
%SVID
VFB = 0.8000  1.0000
5
0
5
VFB = 0.3000  0.8000
8
0
8
VFB = 0.2500  0.3000
80
0
80
IRGND
EN = 3V, Not Switching
--
200
--
A
SR
SetVID Fast
7.5
12
--
mV/s
--
--
2
mV
VPOR_Hys
V
Reference and DAC
DC Accuracy
VFB
mV
RGND Current
RGND Current
Slew Rate
Dynamic VID Slew Rate
Error Amplifier
Input Offset
VEAOFS
DC Gain
ADC
RL = 47k
70
80
--
dB
Gain-Bandwidth Product
GBW
CLOAD = 5pF
--
10
--
MHz
Output Voltage Range
VCOMP
0.3
--
3.6
V
Maximum Source Current IEA, SRC
1
--
--
mA
Maximum Sink Current
1
--
--
mA
0.2
--
0.2
mV
97
--
103
%
194
--
206
%
IEA, SNK
Current Sense Amplifier
Input Offset Voltage
VOSCS
Current Mirror Gain for
CORE
AMIRROR, VDD
Current Mirror Gain for NB AMIRROR, VDDNB
Internal Sum Current
Ai, VDD
Sense DC Gain for CORE
VDD Controller
--
0.4
--
V/V
Internal Sum Current
Sense DC Gain for NB
Ai, VDDNB
VDDNB Controller
--
0.8
--
V/V
Maximum Source Current
ICS, SRC
0 < VFB < 2.35
100
--
--
A
Maximum Sink Current
ICS, SNK
0 < VFB < 2.35
10
--
--
A
VZCD_TH
VZCD_TH = GND  VPHASEx
--
1
--
mV
--
0.5
--
V
Zero Current Detection
Zero Current Detection
Threshold
Ton Setting
TONSETx Pin Minimum
Voltage
VTON, MIN
TONSETx Ton
TON
IRTON = 80A, VFB = 1.1V
270
305
340
ns
TONSETx Input Current
Range
IRTON
VFB = 1.1V
25
--
280
A
Minimum TOFF
TOFF
--
250
--
ns
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8880C-02
January 2015
is a registered trademark of Richtek Technology Corporation.
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15
RT8880C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
1.97
2
2.03
V
0.61
0.64
0.67
V
800
--
--
A
IBIAS
IBIAS Pin Voltage
VIBIAS
RIBIAS = 100k
V064
Reference Voltage Output
V064
Sink Current Capability
IV064, SNK
Source Current Capability
IV064, SRC
--
--
100
A
VFB Limit
VFB, LIMIT
0
--
2.35
V
OFS Update Rate
FOFS
--
50
--
kHz
Board Offset Resolution
VOFS
--
6.25
--
mV
Logic-High
VIH_EN
2
--
--
Logic-Low
VIL_EN
--
--
0.8
Leakage Current of EN
ILEK_EN
1
--
1
Logic-High
SVC, SVD,
SVT, PWROK Logic-Low
VIH_SVI
Respect to VDDIO
70
--
100
VIL_SVI
Respect to VDDIO
0
--
35
Respect to VDDIO
10
--
--
%
VCC Falling edge
4
4.2
4.4
V
--
100
--
mV
--
3
--
s
VID Higher than 0.9V
VID
+ 275
VID
+ 325
VID
+ 375
mV
VID Lower than 0.9V
1175
1225
1275
--
1
--
s
575
500
425
mV
--
3
--
s
--
0
--
mV
--
10
--
A
--
1
--
s
68
75
83
A
6
--
12
s
V064 = 0.64V
Board OFSx
Logic Inputs
EN Input
Voltage
Hysteresis of SVC, SVD,
V
SVT, PWROK Input Voltage HYS_SVI
V
A
%
Protection
Under-Voltage Lockout
Threshold
VUVLO
Under-Voltage Lockout
Hysteresis
VUVLO
Under-Voltage Lockout
Delay
TUVLO
Over-Voltage Protection
Threshold
VOVP
Over-Voltage Protection
Delay
TOVP
VSEN Rising above Threshold
Under-Voltage Protection
Threshold
VUVP
Respect to VID Voltage
Under-Voltage Protection
Delay
TUVP
VSEN Falling below Threshold
Negative-Voltage
Protection Threshold
VNV
Per Phase OCP Threshold
IOCP_PERPHASE
Delay of Per Phase OCP
TPHOCP
OCP_SPIKE Threshold
IOCP_SPIKE
OCP_SPIKE Action Delay
TOCPSPIKE
_ACTION_DLY
VCC Rising above UVLO
Threshold
IISENxN Per-Phase OCP
Threshold.
DCR = 1.1m, RSENSE = 1.1k,
RIMON = 34.3k
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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January 2015
RT8880C
Parameter
Min
Typ
Max
Unit
12
--
24
s
0
--
0.2
V
2
--
--
s
I PGOOD = 4mA, I PGOODA = 4mA
0
--
0.2
V
Respect to VBOOT
--
300
--
mV
VSEN = VBOOT to
PGOOD/PGOODA High
70
100
130
s
Maximum Reported
Current (FFh = OCP)
--
100
--
%IDD_SP
IKE_OCP
Minimum Reported Current
(00h)
--
0
--
%IDD_SP
IKE_OCP
IDDSpike Current Accuracy
--
--
3
%
Maximum Reported
Voltage (0_00h)
--
3.15
--
V
Minimum Reported Voltage
(1_F8h)
--
0
--
V
Voltage Accuracy
2
--
2
LSB
OCP_TDC Action Delay
Symbol
Test Conditions
TOCPTDC
_ACTION_DLY
OCP_L, PGOOD and PGOODA
Output Low Voltage at
OCP_L
VOCP_L
OCP_L Assertion Time
TOCP_L
Output Low Voltage at
PGOOD, PGOODA
PGOOD and PGOODA
Threshold Voltage
VPGOOD,
VPGOODA,
VTH_PGOOD
VTH_PGOODA
PGOOD and PGOODA
Delay Time
TPGOOD
TPGOODA
I OCP_L = 4mA
Current Report
Voltage Report
PWM Driving Capability
PWMx Source Resistance
RPWM_SRC
--
20
--

PWMx Sink Resistance
RPWM_SNK
--
10
--

Switching Time
UGATEx Rise Time
tUGATEr
3nf Load
--
8
--
ns
UGATEx Fall Time
tUGATEf
3nf Load
--
8
--
ns
LGATEx Rise Time
tLGATEr
3nf Load
--
8
--
ns
LGATEx Fall Time
tLGATEf
3nf Load
--
4
--
ns
UGATEx Turn-On
Propagation Delay
tPDHU
Outputs Unloaded
--
20
--
ns
LGATEx Turn-On
Propagation Delay
tPDHL
Outputs Unloaded
--
20
--
ns
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8880C-02
January 2015
is a registered trademark of Richtek Technology Corporation.
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17
RT8880C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Output
UGATEx Driver Source
Resistance
RUGATEsr
100mA Source Current
--
1
--

UGATEx Driver Source
Current
IUGATEsr
VUGATE VPHASE = 2.5V
--
2
--
A
UGATEx Driver Sink
Resistance
RUGATEsk
100mA Sink Current
--
1
--

UGATEx Driver Sink
Current
IUGATEsk
VUGATE VPHASE = 2.5V
--
2
--
A
LGATEx Driver Source
Resistance
RLGATEsr
100mA Source Current
--
1
--

LGATEx Driver Source
Current
ILGATEsr
VLGATE = 2.5V
--
2
--
A
LGATEx Driver Sink
Resistance
RLGATEsk
100mA Sink Current
--
0.5
--

LGATEx Driver Sink
Current
ILGATEsk
VLGATE = 2.5V
--
4
--
A
f SVC
(Note 5)
0.1
--
20
MHz
SVI2 Bus
SVC Frequency
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Min. SVC frequency defined in electrical spec. is related with different application. As min. SVC < 1MHz, VR can't support
telemetry reporting function. As min. SVC < 400kHz, VR can't support telemetry reporting function and VOTF complete
function.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
DS8880C-02
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
January 2015
MLCC : 22µF x 10
POSCAP : 330µF x 2
LOAD
VVDDNB
10
VSS_SENSE
10
330
1µF
330
0.36µH/1.1m 
1µF
20k
3.3nF
1
270µF
3.3nF
1
VIN
VIN
0
470
270µF
1k
1k
20k
124k
124k
0.36µH/1.1m
VVDDNB_SENSE
VCC5
VCC5
VCC5
VCC5
2.2
4.7
10
VCC
0.1µF
0
0
RSENSEA2
1.1k
2.2
RSENSEA1
1.1k
EN
LGATE
RT9610
PWM
UGATE PGND
COMPA
31 FBA
14 RGND
30
ISENA1P
LGATEA1
PHASEA1
34 ISENA2N
33 ISENA2P
45
44
42 BOOTA1
43
UGATEA1
35 ISENA1N
36
41 PWMA2
1µF
5V
5V
51.28k
10k
32 VSENA
IMONA
IMON
37 EN
16
V064
RNTC RIMONA
100k 11.665k 17
PHASE
SET2
18
29
22
21
20
RIBIAS
100k
1µF
49
48
ISEN3N 10
ISEN3P 9
PWM3 3
ISEN2N 6
ISEN2P 5
PHASE2 52
LGATE2 51
BOOT2
UGATE2 1
2
ISEN1N 7
ISEN1P 8
LGATE1
PHASE1
UGATE1 47
BOOT1
46
FB 12
COMP
13
VSEN 11
10k
RSENSE1
1.1k
5V
5V
VIN
PHASE
LGATE
RT9610
RSENSE3
1.1k
EN
PWM
PGND UGATE
VCC
RSENSE2
1.1k
1µF
0
0
2.2 0.1µF
0
0
BOOT
270pF
2.2 0.1µF
65.48k
22pF
VIN
To CPU
4.7k 4.7k
VDDIO
2.2
GND 53 (Exposed Pad)
IBIAS
SVT
SVD
SVC
PGOOD 39
PGOODA 38
19
OCP_L 27
VDDIO
PWROK
RT8880C
4 TONSET
RTONNB
137k 40
TONSETA
0.1µF
22pF
BOOT
26
25 SET1
0.1µF
270pF
10.47k
VCC
PVCC
23 OFS
24 OFSA
RNTC RIMON
100k 18.432k 15
16k
7.999k
28
50
2.2µF
VCC5
Enable
4.7
18.7k
VIN
0.1µF
0.1µF
0.1µF
0
0
2.2
0
5V
2.2µF
0.1µF 6.32k
RTON
150k
6.32k
0.47µF
0.1µF
VIN
1.47k
43k
5V
270µF
10k
0.1µF
0
0
2.2 0.1µF
3.3nF
1
270µF
0.1µF
3.3nF
1
0.1µF
0
10k
3.3V
VIN
330
330
1µF
0.36µH/1.1m 
3.3nF
1
POSCAP : 330µF x 4
LOAD
VVDD
10
MLCC : 22µF x 15
270µF
1µF
0.36µH/1.1m 
330
1µF
0.36µH/1.1m 
10
VSS_SENSE
VVDD_SENSE
RT8880C
Typical Application Circuit
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19
RT8880C
Typical Operating Characteristics
CORE VR Power On from EN
CORE VR Power Off from EN
VVDD
(500mV/Div)
VVDD
(500mV/Div)
EN
(4V/Div)
EN
(4V/Div)
PGOOD
(2V/Div)
PGOOD
(2V/Div)
UGATE1
(30V/Div)
Boot VID = 0.8V
UGATE1
(30V/Div)
Time (200μs/Div)
Time (200μs/Div)
CORE VR OCP_TDC
CORE VR OCP_SPIKE
I LOAD
(40A/Div)
I LOAD
(40A/Div)
OCP_L
(2V/Div)
OCP_L
(2V/Div)
PGOOD
(2V/Div)
PGOOD
(2V/Div)
UGATE1
(30V/Div)
UGATE1
(30V/Div)
ILOAD = 20A to 60A
ILOAD = 25A to 80A
Time (5ms/Div)
Time (10μs/Div)
CORE VR OVP and NVP
CORE VR UVP
VVDD
(1V/Div)
VVDD
(1V/Div)
PGOOD
(2V/Div)
PGOOD
(2V/Div)
UGATE1
(50V/Div)
LGATE1
(10V/Div)
UGATE1
(50V/Div)
LGATE1
(10V/Div)
VID = 1.1V
Time (20μs/Div)
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20
Boot VID = 0.8V
VID = 1.1V
Time (10μs/Div)
is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
RT8880C
CORE VR Dynamic VID Up
CORE VR Dynamic VID Up
VVDD
(1V/Div)
VVDD
(1V/Div)
I LOAD
(5A/Div)
I LOAD
(18A/Div)
SVD
(2V/Div)
SVD
(2V/Div)
SVT
(2V/Div)
VID = 0.4V to 1V, ILOAD = 3.6A
SVT
(2V/Div)
VID = 1V to 1.06875V, ILOAD = 18A
Time (20μs/Div)
Time (20μs/Div)
CORE VR Dynamic VID Up
CORE VR Dynamic VID Up
VVDD
(1V/Div)
VVDD
(1V/Div)
I LOAD
(18A/Div)
I LOAD
(18A/Div)
SVD
(2V/Div)
SVD
(2V/Div)
SVT
(2V/Div)
VID = 1V to 1.1V, ILOAD = 18A
SVT
(2V/Div)
VID = 1V to 1.2V, ILOAD = 18A
Time (20μs/Div)
Time (20μs/Div)
CORE VR Dynamic VID Up
CORE VR Load Transient
VVDD
(1V/Div)
VVDD
(50mV/Div)
I LOAD
(18A/Div)
SVD
(2V/Div)
SVT
(2V/Div)
VID = 1V to 1.4V, ILOAD = 18A
Time (20μs/Div)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8880C-02
January 2015
I LOAD
(25A/Div)
fLOAD = 10kHz, ILOAD = 18A to 50A
Time (5μs/Div)
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21
RT8880C
NB VR Power On from EN
CORE VR Load Transient
V VDDNB
(500mV/Div)
VVDD
(50mV/Div)
EN
(4V/Div)
PGOODA
(2V/Div)
I LOAD
(25A/Div)
fLOAD = 10kHz, ILOAD = 50A to 18A
UGATEA1
(30V/Div)
Boot VID = 0.8V
Time (5μs/Div)
Time (200μs/Div)
NB VR Power Off from EN
NB VR OCP_TDC
V VDDNB
(500mV/Div)
I LOAD
(25A/Div)
EN
(4V/Div)
OCP_L
(2V/Div)
PGOODA
(2V/Div)
UGATEA1
(30V/Div)
Boot VID = 0.8V
PGOODA
(2V/Div)
UGATEA1
(50V/Div)
Time (200μs/Div)
Time (5ms/Div)
NB VR OCP_SPIKE
NB VR OVP and NVP
I LOAD
(40A/Div)
V VDDNB
(1V/Div)
OCP_L
(2V/Div)
PGOODA
(2V/Div)
PGOODA
(2V/Div)
UGATEA1
(50V/Div)
UGATEA1
(50V/Div)
LGATEA1
(10V/Div)
ILOAD = 20A to 60A
Time (10μs/Div)
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22
ILOAD = 10A to 45A
VID = 1.1V
Time (20μs/Div)
is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
RT8880C
NB VR UVP
NB VR Dynamic VID Up
V VDDNB
(1V/Div)
V VDDNB
(1V/Div)
I LOAD
(5A/Div)
PGOODA
(2V/Div)
SVD
(2V/Div)
UGATEA1
(50V/Div)
LGATEA1
(10V/Div)
VID = 1.1V
SVT
(2V/Div)
Time (10μs/Div)
Time (20μs/Div)
NB VR Dynamic VID Up
NB VR Dynamic VID Up
V VDDNB
(1V/Div)
V VDDNB
(1V/Div)
I LOAD
(8A/Div)
I LOAD
(8A/Div)
SVD
(2V/Div)
SVD
(2V/Div)
SVT
(2V/Div)
VID = 1V to 1.06875V, ILOAD = 12.5A
SVT
(2V/Div)
VID = 1V to 1.1V, ILOAD = 12.5A
Time (20μs/Div)
Time (20μs/Div)
NB VR Dynamic VID Up
NB VR Dynamic VID Up
V VDDNB
(1V/Div)
V VDDNB
(1V/Div)
I LOAD
(8A/Div)
I LOAD
(8A/Div)
SVD
(2V/Div)
SVD
(2V/Div)
SVT
(2V/Div)
VID = 1V to 1.2V, ILOAD = 12.5A
Time (20μs/Div)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8880C-02
VID = 0.4V to 1V, ILOAD = 2.5A
January 2015
SVT
(2V/Div)
VID = 1V to 1.4V, ILOAD = 12.5A
Time (20μs/Div)
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23
RT8880C
NB VR Load Transient
V VDDNB
(40mV/Div)
I LOAD
(20A/Div)
V VDDNB
(40mV/Div)
fLOAD = 10kHz, ILOAD = 13A to 33A
Time (5μs/Div)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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24
NB VR Load Transient
I LOAD
(20A/Div)
fLOAD = 10kHz, ILOAD = 33A to 13A
Time (5μs/Div)
is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
RT8880C
Application Information
Power Ready (POR) Detection
During start-up, the RT8880C will detect the voltage at
the voltage input pins : VCC, PVCC and EN. When VCC
> 4.2V and PVCC > 3.85V, the IC will recognize the power
state of system to be ready (POR = high) and wait for
enable command at the EN pin. After POR = high and VEN
+ CMP
VCC
4.2V
PVCC
+
3.85V
CMP
POR
+ CMP
EN
2V
Chip EN
-
2V
+
-
> 2V, the IC will enter start-up sequence for both VDD rail
and VDDNB rail. If the voltage at the pins of VCC and EN
drop below low threshold, the IC will enter power down
sequence and all the functions will be disabled. Normally,
connecting system power to the EN pin is recommended.
The SVID will be ready in 2ms (max) after the chip has
been enabled. All the protection latches (OVP, OCP, UVP)
will be cleared only after POR = low. The condition of VEN
= low will not clear these latches.
Current
Mirror
+
-
IBIAS
100k
Figure 2. IBIAS Setting
Boot VID
When EN goes high, both VDD and VDDNB output begin
to soft-start to the boot VID in CCM. Table 7 shows the
Boot VID setting. The Boot VID is determined by the SVC
and SVD input states at EN rising edge and it is stored in
the internal register. The digital soft-start circuit ramps up
the reference voltage at a controlled slew rate to reduce
inrush current during start-up. When all the output voltages
are above power good threshold (300mV below Boot VID)
at the end of soft-start, the controller asserts power good
after a time delay.
Figure 1. Power Ready (POR) Detection
Table 7. 2-Bit Boot VID Code
Precise Reference Current Generation
The RT8880C includes complicated analog circuits inside
the controller. The IC needs very precise reference voltage/
current to drive these analog circuits. The IC will auto
generate a 2V voltage source at the IBIAS pin, and a 100kΩ
resistor is required to be connected between IBIAS and
analog ground, as shown in Figure 2. Through this
connection, the IC will generate a 20μA current from the
IBIAS pin to analog ground, and this 20μA current will be
mirrored for internal use. Note that other type of connection
or other values of resistance applied at the IBIAS pin may
cause functional failure, such as slew rate control, OFS
accuracy, etc. In other words, the IBIAS pin can only be
connected with a 100kΩ resistor to GND. The resistance
accuracy of this resistor is recommended to be 1% or
higher.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8880C-02
January 2015
Initial Startup VID (Boot VID)
SVC
SVD
VDD/VDDNB Output Voltage (V)
0
0
1.1
0
1
1.0
1
0
0.9
1
1
0.8
Start-Up Sequence
After EN goes high, the RT8880C starts up and operates
according to the initial settings. Figure 3 shows the
simplified sequence timing diagram. The detailed operation
is described in the following.
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25
RT8880C
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
PVCC, VCC
SVID
Send
Byte
SVC
SVID
Send
Byte
SVD
VOTF
Complete
VOTF
Complete
SVT
EN
PWROK
CCM
Boot VID
CCM
VDD/
VDDNB
VID
CCM
Boot VID
CCM CCM
VID
CCM
CCM
PGOOD/
PGOODA
Figure 3. Simplified Sequence Timing Diagram
Description of Figure 3 :
T0 : The RT8880C waits for VCC and PVCC POR.
T1 : The SVC pin and SVD pin set the Boot VID. Boot VID
is latched at EN rising edge. SVT is driven high by the
RT8880C.
T2 : The enable signal goes high and all output voltages
ramp up to the Boot VID in CCM. The soft-start slew rate
is 3mV/μs.
T3 : All output voltages are within the regulation limits and
the PGOOD and PGOODA signal goes high.
T4 : The PWROK pin goes high and the SVI2 interface
starts running. The RT8880C waits for SVID command
from processor.
T5 : A valid SVID command transaction occurs between
the processor and the RT8880C.
T7 : The PWROK pin goes low and the SVI2 interface
stops running. All output voltages go back to the boot VID
in CCM.
T8 : The PWROK pin goes high again and the SVI2
interface starts running. The RT8880C waits for SVID
command from processor.
T9 : A valid SVID command transaction occurs between
the processor and the RT8880C.
T10 : The RT8880C starts VID on-the-Fly transition
according to the received SVID command and send a
VOTF Complete if the VID reaches target VID.
T11 : The enable signal goes low and all output voltages
enter soft-shutdown mode.
T6 : The RT8880C starts VOTF (VID on-the-Fly) transition
according to the received SVID command and send a
VOTF Complete if the VID reaches target VID.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
RT8880C
Power-Down Sequence
SVI2 Wire Protocol
If the voltage at the EN pin falls below the enable falling
threshold, the controller is disabled. The voltage at the
PGOOD and PGOODA pins will immediately go low at
the loss of enable signal at the EN pin and the controller
executes soft-shutdown operation. The internal digital
circuit ramps down the reference voltage at the same slew
rate as that of in soft-start, making VDD and VDDNB output
voltages gradually decrease in CCM. Each of the controller
channels stops switching when the voltage at the voltage
sense pin VSEN/VSENA, cross about 0.2V. The Boot VID
information stored in the internal register is cleared at IC
POR. This event forces the RT8880C to check the SVC
and SVD inputs for a new boot VID when the EN voltage
goes high again.
The RT8880C complies with AMD's Voltage Regulator
Specification, which defines the Serial VID Interface 2
(SVI2) protocol. With SVI2 protocol, the processor directly
controls the reference voltage level of each individual
controller channel and determines which controller
operates in power saving mode. The SVI2 interface is a
three-wire bus that connects a single master to one or
above slaves. The master initiates and terminates SVI2
transactions and drives the clock, SVC, and the data, SVD,
during a transaction. The slave drives the telemetry, SVT
during a transaction. The AMD processor is always the
master. The voltage regulator controller (RT8880C) is
always the slave. The RT8880C receives the SVID code
and acts accordingly. The SVI protocol supports 20MHz
high speed mode I2C, which is based on SVD data packet.
Table 8 shows the SVD data packet. A SVD packet
consists of a “Start” signal, three data bytes after each
byte, and a “Stop” signal. The 8-bit serial VID codes are
listed in Table1. After the RT8880C has received the stop
sequence, it decodes the received serial VID code and
executes the command. The controller has the ability to
sample and report voltage and current for the VDD and
VDDNB domains. The controller reports this telemetry
serially over the SVT wire which is clocked by the
processor driven SVC. A bit TFN at SVD packet along
with the VDD and VDDNB domain selector bits are used
by the processor to change the telemetry functionality.
The telemetry bit definition is listed in Figure 4. The detailed
SVI2 specification is outlined in the AMD Voltage Regulator
and Voltage Regulator Module (VRM) and Serial VID
Interface 2.0 (SVI2) Specification.
PGOOD and PGOODA
The PGOOD and PGOODA are open-drain logic outputs.
The two pins provide the power good signal when VDD
and VDDNB output voltage are within the regulation limits
and no protection is triggered. These pins are typically
tied to 3.3V or 5V power source through a pull-high
resistor. During shutdown state (EN = low) and the softstart period, the PGOOD and PGOODA voltages are pulled
low. After a successful soft-start and VDD and VDDNB
output voltages are within the regulation limits, the PGOOD
and PGOODA are released high individually.
The voltages at the PGOOD and PGOODA pins are pulled
low individually during normal operation when any of the
following events occurs : over-voltage protection, undervoltage protection, over-current protection, and logic low
EN voltage. If one rail triggers protection, another rail's
PGOOD will be pull low after 5μs delay.
Table 8. SVD Data Packet
Description
Bit Time
1:5
6
7
Always 11000b
VDD domain selector bit, if set then the following two data bytes contain the VID for VDD, the
PSI state for VDD, and the load-line slope trim and offset trim state for VDD.
VDDNB domain selector bit, if set then the following two data bytes contain the VID for VDDNB,
the PSI state for VDDNB, and the load-line slope trim and offset trim state for VDDNB.
8
Always 0b
10
PSI0_L
11 : 17
19
VID Code bits [7:1]
VID Code bit [0]
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January 2015
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RT8880C
Bit Time
Description
20
PSI1_L
21
TFN (Telemetry Functionality)
22 : 24
Load Line Slope Trim [2:0]
25 : 26
Offset Trim [1:0]
Voltage and Current
Mode Selection
Bit Time…… START
1
2
3
VDDNB Voltage Bit in Voltage Only Mode;
Current Bit in Voltage and Current Mode
VDD Voltage Bits
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
STOP
SVC
SVT
Figure 4. Telemetry Bit Definition
PWROK and SVI2 Operation
VID on-the-Fly Transition
The PWROK pin is an input pin, which is connected to
After the RT8880C has received a valid SVID code, it enters
CCM mode and executes the VID on-the-Fly transition by
stepping up/down the reference voltage of the required
controller channel(s) in a controlled slew rate, hence
allowing the output voltage(s) to ramp up/down to the target
VID. The output voltage slew rate during the VID on-theFly transition is faster than that in a soft-start/soft-shutdown
operation. If the new VID level is higher than the current
VID level, the controller begins stepping up the reference
voltage with a typical slew rate of 12.5mV/μs upward to
the target VID level. If the new level is lower than the current
VID level, the controller begins stepping down the reference
voltage with a typical slew rate of −12.5mV/μs downward
to the target VID level.
the global power good signal from the platform. Logic high
at this pin enables the SVI2 interface, allowing data
transaction between processor and the RT8880C. Once
the RT8880C receives a valid SVID code, it decodes the
information from processor to determine which output
plane is going to move to the target VID. The internal DAC
then steps the reference voltage in a controlled slew rate,
making the output voltage shift to the required new VID.
Depending on the SVID code, more than one controller
channel can be targeted simultaneously in the VID
transition. For example, VDD and VDDNB voltages can
ramp up/down at the same time.
If the PWROK input goes low during normal operation,
the SVI2 protocol stops running. The RT8880C
immediately drives SVT high and modifies all output
voltages back to the boot VID, which is stored in the internal
register right after the controller is enabled. The controller
does not read SVD and SVC inputs after the loss of
PWROK. If the PWROK input goes high again, the SVI2
protocol resumes running. The RT8880C then waits to
decode the SVID command from processor for a new VID
and acts as previously described. The SVI2 protocol is
only runs when the PWROK input goes high after the
voltage at the EN pin goes high; otherwise, the RT8880C
will not soft-start due to incorrect signal sequence.
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28
During the VID on-the-Fly transition, the RT8880C will force
the controller channel to operate in CCM mode. If the
controller channel operates in the power-saving mode prior
to the VID on-the-Fly transition, it will be in CCM mode
during the transition and then back to the power saving
mode at the end of the transition. The voltage at the
PGOOD and PGOODA pins will keep high during the VID
on-the-Fly transition. The RT8880C checks the output
voltage for voltage-related protections and send a VOTF
complete at the end of VID on-the-Fly transition. In the
event of receiving a VID off code, the RT8880C steps the
reference voltage of required controller channel down to
zero, hence making the required output voltage decrease
to zero. The voltage at the PGOOD pin and PGOODA pin
will remain high since the VID code is valid.
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DS8880C-02
January 2015
RT8880C
Power State Transition
Differential Remote Sense Setting
The RT8880C supports power state transition function in
VDD and VDDNB VR for the PSI[x]_L and command from
AMD processor. The PSI[x]_L bit in the SVI2 protocol
controls the operating mode of the RT8880C controller
channels. The default operation mode of VDD and VDDNB
VR is CCM.
The VDD and VDDNB controllers have differential, remotesense inputs to eliminate the effects of voltage drops along
the PC board traces, processor internal power routes and
socket contacts. The processor contains on-die sense
pins, VDD_SENSE, VDDNB_SENSE and VSS_SENSE.
Connect RGND to VSS_SENSE. For VDD controller,
connect FB to VDD_SENSE with a resistor to build the
negative input path of the error amplifier. Connect FBA to
VDDNB_SENSE with a resistor using the same way in
VDD controller. Connect VSS_SENSE to RGND using
separate trace as shown in Figure 5. The precision
reference voltages refer to RGND for accurate remote
sensing.
When the VDD VR is in N phase configuration and receives
PSI0_L = 0 and PSI1_L = 1, the VDD VR will entries
single-phase diode emulation mode. When the VDD VR
receives PSI0_L = 0 and PSI1_L = 0, the VDD VR remains
diode emulation mode. In reverse, the VDD VR goes back
to N phase operation in CCM upon receiving PSI0_L = 1
and PSI1_L = 0 or 1, see Table 9. When the VDDNB VR
receives PSI0_L = 0 and PSI1_L = 1, it enters singlephase diode emulation mode, when the VDDNB VR
receives PSI0_L = 0 and PSI1_L = 0, it remains singlephase diode emulation mode. When the VDDNB VR goes
back to full-phase CCM operation after receiving PSI0_L
= 1 and PSI1_L = 0 or 1, see Table 10.
3
2
1
PSI0_L : PSI1_L
Mode
11 or 10
3 phase CCM
01
1 phase DEM
00
1 phase DEM
11 or 10
2 phase CCM
01
1 phase DEM
00
1 phase DEM
11 or 10
1 phase CCM
01
1 phase DEM
00
1 phase DEM
Table 10. VDDNB VR Power State
Full Phase
PSI0_L : PSI1_L
Mode
Number
11 or 10
2 phase CCM
2
1
01
1 phase DEM
00
1 phase DEM
11 or 10
1 phase CCM
01
1 phase DEM
00
1 phase DEM
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8880C-02
January 2015
VDD
Controller
FB
FBA
RGND
VDD NB
Controller
RGND
VSS_SENSE
Figure 5. Differential Remote Voltage Sense Connection
Table 9. VDD VR Power State
Full Phase
Number
Processor
VDD_SENSE VDDNB_SENSE
SET1 and SET2 Pin Setting
The RT8880C provides the SET1 pin for platform users to
set the VDD and VDDNB controller OCP_TDC threshold,
DVIDx compensation bit1 and internal ramp amplitude
(RSET & RSETA), and the SET2 pin to set VDD and
VDDNB controller OCP trigger delay (OCPTRGDELAY),
DVIDx compensation bit0, external offset function, VDDNB
zero load-line and quick response threshold (QRTH &
QRTHA). To set these pin, platform designers should use
resistive voltage divider on these pins, refer to Figure 6
and Figure 7. The voltages at the SET1 and SET2 pins
are :
VSET1  VCC 
RSET1,D
RSET1,U  RSET1,D
(1)
VSET2  VCC 
RSET2,D
RSET2,U  RSET2,D
(2)
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RT8880C
The ADC monitors and decodes the voltage at this pin
only once after power up. After ADC decoding (only once),
a 40μA current (when VCC = 5V) will be generated at the
SET1 and SET2 pin for internal use. That is the voltage at
SET1 and SET2 pin is
VSET1  40A 
RSET1,U  RSET1,D
RSET1,U  RSET1,D
(3)
VSET2  40A 
RSET2,U  RSET2,D
RSET2,U  RSET2,D
(4)
From equation (1) to equation (4) and Table 2 to Table 5,
platform users can set the above described pin setting
functions.
DVIDx
Compensation
OCPTDCx
40µA
(VCC = 5V)
RSETx
2.24V
VSET1
RSET1,U
SET1
SET1
Register
 VSET1
RSET1,D
RT8880C
Figure 6. SET1 Pin Setting
DVIDx Compensation
and VDDNB zero LL
OCPTR
GDELAY
QRTHx OFSx
40µA
(VCC = 5V)
VCC
ADC
2.24V
VSET2
SET2
Register
RSET2,U
SET2
RSET2,D
VSET2
Active Phase Determination
The number of active phases is determined by the internal
circuitry that monitors the ISENxN voltages during startup. Normally, the VDD controller operates as a 3-phase
PWM controller. Pulling ISEN3N to VCC programs a 2phase operation, and pulling ISEN2N to VCC programs a
1-phase operation. At EN rising edge, VDD controller
detects whether the voltages of ISEN2N and ISEN3N are
higher than “VCC − 0.5V” respectively to decide how
many phases should be active. Phase selection is only
active during IC POR. When IC_POR = high, the number
of active phases is determined and latched. The unused
ISENxP pins are recommended to be connected to VCC
and unused PWM pins can be left floating.
Loop Control
VCC
ADC
VDD Controller
RT8880C
The VDD controller adopts Richtek's proprietary G-NAVPTM
topology. The G-NAVPTM is based on the finite gain peak
current mode with CCRCOT (Constant Current Ripple
Constant On-Time) topology. The output voltage, VVDD will
decrease with increasing output load current. The control
loop consists of PWM modulators with power stages,
current sense amplifiers and an error amplifier as shown
in Figure 8.
Similar to the peak current mode control with finite
compensator gain, the HS_FET on-time is determined by
CCRCOT on-time generator. When load current increases,
VCS increases, the steady state COMP voltage also
increases and induces VOUT,VDD to decrease, thus achieving
AVP. A near-DC offset canceling is added to the output of
EA to eliminate the inherent output offset of finite gain
peak current mode controller.
Figure 7. SET2 Pin Setting
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is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
RT8880C
VIN
COMP2
+
CMP
-
CCRCOT
PWM
Logic
PWM3
Loop Compensation
HS_FET
VVDD
L RSENSE
Driver
RX
CX
RC
LS_FET
0.4
x1
VCS
+
-
C
ISENxP
ISENxN
Offset
Canceling
IMON
RCSx
RIMON
VREF
+
EA
+
COMP
FB
RGND
C2
R2
C1
R1
VVDD_SENSE
VSS_SENSE
VDAC,VDD
Optimized compensation of the VDD controller allows for
best possible load step response of the regulator's output.
A type-I compensator with one pole and one zero is
adequate for proper compensation. Figure 10 shows the
compensation circuit. Previous design procedure shows
how to select the resistive feedback components for the
error amplifier gain. Next, C1 and C2 must be calculated
for compensation. The target is to achieve constant
resistive output impedance over the widest possible
frequency range.
The pole frequency of the compensator must be set to
compensate the output capacitor ESR zero :
Figure 8. VDD Controller : Simplified Schematic for
Droop and Remote Sense in CCM
1
2   C  RC
fP 
Droop Setting
It is very easy to achieve Active Voltage Positioning (AVP)
by properly setting the error amplifier gain due to the native
droop characteristics as shown in Figure 9. This target is
to have
VVDD = VDAC, VDD − ILOAD x RDROOP
(5)
Then solving the switching condition VCOMP2 = VCS in
Figure 8 yields the desired error amplifier gain as
GI
A V  R2 
R1 RDROOP
(6)
R
GI  SENSE  RIMON  4
RCSx
10
(7)
C  RC
(9)
R2
The zero of compensator has to be placed at half of the
switching frequency to filter the switching related noise.
Such that,
C2 
1
R1   fSW
(10)
COMP
EA
+
C2
C1
R2
R1
VVDD_SENSE
FB
+
VVDD
Where C is the capacitance of output capacitor, and RC is
the ESR of output capacitor. C2 can be calculated as
follows :
C1 
where GI is the internal current sense amplifier gain. RSENSE
is the current sense resistor. If no external sense resistor
present, it is the equivalent resistance of the inductor.
RDROOP is the equivalent load-line resistance as well as
the desired static output impedance.
(8)
RGND
VSS_SENSE
VDAC
Figure 10. VDD Controller : Compensation Circuit
AV2 > AV1
TON Setting
AV2
AV1
0
Load Current
Figure 9. VDD Controller : Error Amplifier gain (AV)
Influence on VVDD Accuracy
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8880C-02
January 2015
High frequency operation optimizes the application for the
smaller component size, trading off efficiency due to higher
switching losses. This may be acceptable in ultra portable
devices where the load currents are lower and the
controller is powered from a lower voltage supply.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
31
RT8880C
Low frequency operation offers the best overall efficiency
at the expense of component size and board space.
Figure 11 shows the On-Time setting circuit. Connect a
resistor (RTON) between VIN and TONSET to set the ontime of UGATE :
tON (0.5V  VDAC  1.8V) 
12
24.4  10
 RTON
VIN  VDAC
(11)
where tON is the UGATE turn-on period, VIN is Input voltage
of the VDD controller, and VDAC is the DAC voltage.
When VDAC is larger than 1.8V, the equivalent switching
frequency may be over 500kHz, and this too fast switching
frequency is unacceptable. Therefore, the VDD controller
implements a pseudo constant frequency technology to
avoid this disadvantage of CCRCOT topology. When VDAC
is larger than 1.8V, the on-time equation will be modified
to :
12
13.55  10
 RTON  VDAC (12)
tON (VDAC  1.8V) 
VIN  VDAC
Current Sense Setting
The current sense topology of the VDD controller is
continuous inductor current sensing. Therefore, the
controller has less noise sensitive. Low offset amplifiers
are used for current balance, loop control and over current
detection. The ISENxP and ISENxN pins denote the
positive and negative input of the current sense amplifier
of each phase.
Users can either use a current sense resistor or the
inductor's DCRL for current sensing. Using the inductor's
DCRL allows higher efficiency as shown in Figure 12.
VVDD
IL
L
DCRL
RX
ISENxN
+
-
CX
ISENxP
ISENxN
RCSx
Figure 12. VDD Controller : Lossless Inductor Sensing
On-time translates only roughly to switching frequencies.
For better efficiency of the given load range, the maximum
switching frequency is suggested to be :
fSW(MAX) 
VDAC(MAX)  ILOAD(MAX)  DCRL  RON_LS-FET  RDROOP 
 VIN(MAX)  ILOAD(MAX)  RON_LS-FET  RON_HS-FET     TON  TD  TON, VAR   ILOAD(MAX)  RON_LS-FET   TD


(13)
Where fS(MAX) is the maximum switching frequency, TD is
the driver dead time, TON,VAR is the TON variation value.
VDAC(MAX) is the Maximum VDAC of application, VIN(MAX) is
the Maximum application Input voltage, ILOAD(MAX) is the
maximum load of application, R ON_LS-FET is the onresistance of low side FET RDS(ON), RON_HS-FET is the of
resistance of high side FET RDS(ON) , DCRL is the equivalent
resistance of the inductor, and RDROOP is the load-line
setting.
CCRCOT
On-Time
Computer
TONSET
VDAC
RTON
R1
VIN
C1
In order to optimize transient performance, RX and CX must
be set according to the equation below :
L  R C
(14)
X
X
DCRL
Then the proportion between the phase current, IL, and
the sensed current, ISENxN, is driven by the value of the
effective sense resistance, RCSx, and the DCRL of the
inductor. The resistance value of RCSx is limited by the
internal circuitry. The recommended value is from 500Ω
to 1.2kΩ.
DCRL
ISENxN  IL 
RCSx
(15)
Considering the inductance tolerance, the resistor RX has
to be tuned on board by examining the transient voltage.
If the output voltage transient has an initial dip below the
minimum load-line requirement and the response time is
too fast causing a ring back, the value of resistance should
be increased. Vice versa, with a high resistance, the output
voltage transient has only a small initial dip with a slow
response time.
On-Time
Figure 11. VDD Controller : On-Time Setting with RC filter
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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32
is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
RT8880C
Using current sense resistor in series with the inductor
can have better accuracy, but the efficiency is a trade-off.
Considering the equivalent inductance (LESL) of the current
sense resistor, an RC filter is recommended. The RC filter
calculation method is similar to the above mentioned
inductor equivalent resistance sensing method.
Per-Phase Over Current Protection
The VDD controller provides over current protection in each
phase. For VDD controller in three-phase configuration,
either phase can trigger Per-Phase Over Current Protection
(PHOCP).
The VDD controller senses each phase inductor current
IL, and PHOCP comparator compares sensed current with
PHOCP threshold current, as shown in Figure 13.
1 I
8 SENAxN
PHOCP trigger
10µA
Current Mirror
ISENAxN
The resistor RCSx determines PHOCP threshold.
RCSx 
The VDD controller features over clocking offset function
which provides the possibility of wide range offset of output
voltage. The initial offset function can be implemented
through the SVI interface. When the OFS pin voltage
< 0.3V at EN rising edge, the initial offset is disabled. The
external offset function can be implemented by the SET2
pin setting. For example, referring to Table 11, when the
both rail external offset functions are enabled, the output
voltage is :
VVDD  VDAC  ILOAD x RDROOP + VExternal _ OFS
+ VInitial _ OFS
(18)
VInitial_OFS is the initial offset voltage set by SVI interface,
and the external offset voltage, VExternal_OFS is set by
supplying a voltage into the OFS pin.
It can be calculated as below :
VExternal _ OFS = VOFS  1.2V
Figure 13. VDD Controller : Per-Phase OCP Setting
IL,PERPHASE(MAX) 
Initial Offset and External Offset (Over Clocking
Offset Function)
DCRL 1
 = 10A
RCSx 8
IL,PERPHASE(MAX)  DCRL
8  10A
(16)
(17)
The controller will turn off all high-side/low-side MOSFETs
to protect CPU if the per-phase over current protection is
triggered.
(19)
If supplying 1.3V at OFS pin, it will achieve 100mV offset
at the output. Connecting a filter capacitor between the
OFS and GND pins is necessary. Designers can design
the offset slew rate by properly setting the filter bandwidth.
Table 11. External Offset Function Setting for VDD
and VDDNB Controller
Core_
NB_
OFFSET_ OFFSET_
EN
EN
0
1
Description
0
Disable external offset function.
1
Core rail external offset is set
by OFS pin voltage, and NB rail
external offset is set by OFSA
pin voltage.
Current Balance
The VDD controller implements internal current balance
mechanism in the current loop. The VDD controller senses
and compares per-phase current signal with average
current. If the sensed current of any particular phase is
larger than average current, the on-time of this phase will
be adjusted to be shorter.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8880C-02
January 2015
Dynamic VID Enhancement
During a dynamic VID event, the charging (dynamic VID
up) or discharging (dynamic VID down) current causes
unwanted load-line effect which degrades the settling time
performance. The RT8880C will hold the inductor current
to hold the load-line during a dynamic VID event. The VDD
controller will always enter three-phase configuration when
VDD controller receives dynamic VID up and VDD controller
will hold the operating state when VDD controller receives
dynamic VID down.
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33
RT8880C
The RT8880C also has DVID compensation which can boost
up the Dynamic VID slew rate and adjust the voltage onthe-fly complete timing. The DVID compensation parameter
can be selected by DVIDx compensation bits using the
SET1 and SET2 pins.
VVDD_SENSE voltage drops abruptly due to load apply
transient, the mirrored current flowing into quick response
circuit will also increase instantaneously.
The QR threshold setting for VDD controller refers to Table
4.
Ramp Amplitude Adjust
Current Monitoring and Current Reporting
The VDD controller provides current monitoring function
via inductor current sensing. In the G-NAVPTM technology,
the output voltage is dependent on output current, and
the current monitoring function is achieved by this
characteristic of output voltage. The equivalent output
current will be sensed from inductor current sensing and
mirrored to the IMON pin. The resistor connected to the
IMON pin determines voltage of the IMON output.
DCRL
(20)
VIMON = IL,SUM 
 RIMON  0.64
RCSx
Where IL is the phase current, RCSx is the effective sense
resistance, and RIMON is the current monitor current setting
resistor. Note that the IMON pin cannot be monitored.
The ADC circuit of the VDD controller monitors the voltage
variation at the IMON pin from 0V to 3.19375V, and this
voltage is decoded into digital format and stored into
Output_Current register. The ADC divides 3.19375V into
511 levels, so LSB = 3.19375V / 511 = 6.25mV.
Quick Response
The VDD controller utilizes a quick response feature to
support heavy load current demand during instantaneous
load transient. The VDD controller monitors the current of
the VVDD_SENSE, and this current is mirrored to internal
quick response circuit. At steady state, this mirrored
current will not trigger a quick response. When the
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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34
+
CMP
-
+
When the VDD controller takes phase shedding operation
and enters diode emulation mode, the internal ramp of
VDD controller will be modified for the reason of stability.
In case of smooth transition into DEM, the CCM ramp
amplitude should be designed properly. The RT8880C
provides the SET1 pin for platform users to set the ramp
amplitude of the VDD controller in CCM.
QRTH
QR Pulse
Generation
Circuit
VVDD_SENSE
Figure 14. VDD Controller : Quick Response Triggering
Circuit
When quick response is triggered, the quick response
circuit will generate a quick response pulse. The pulse
width of quick response is almost the same as tON.
After generating a quick response pulse, the pulse is then
applied to the on-time generating circuit, and all the active
phases' on-time will be overridden by the quick response
pulse.
Over-Current Protection
The RT8880C has dual OCP mechanism. The dual OCP
mechanism has two types of thresholds. The first type,
referred to as OCP-TDC, is a time and current based
threshold. OCP-TDC should trip when the average output
current exceeds TDC by some percentage and for a period
of time. This period of time is referred to as the trigger
delay. The second type, referred to as OCP-SPIKE, is a
current based threshold. OCP-SPIKE should trip when
the cycle-by-cycle output current exceeds IDDSPIKE by
some percentage. If either mechanism trips, then the VDD
controller asserts OCP_L and delays any further action.
This delay is called an action delay. Refer to action delay
time. After the action delay has expired and the VDD
controller has allowed its current sense filter to settle out
and the current has not decreased below the threshold,
then the VDD controller will turn off both high-side
MOSFETs and low-side MOSFETs of all channels.
is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
RT8880C
Users can set OCP-SPIKE threshold, IL,SUM(SPIKE), by the
current monitor resistor RIMON of the following equation :
R
IL,SUM (SPIKE) = 3.19375  0.64  CSx
DCRL
RIMON
(21)
And set the OCP-TDC threshold, IL(TDC), refer to some
percentage of OCP-SPIKE through Table 2.
Under-Voltage Lock Out (UVLO)
During normal operation, if the voltage at the VCC pin
drops below IC POR threshold, the VDD controller will
trigger UVLO. The UVLO protection forces all high-side
MOSFETs and low-side MOSFETs off by shutting down
internal PWM logic drivers. A 3μs delay is used in UVLO
detection circuit to prevent false trigger.
Over-Voltage Protection (OVP)
The over-voltage protection circuit of the VDD controller
monitors the output voltage via the VSEN pin after IC POR.
When VID is lower than 0.9V, once VSEN voltage exceeds
“0.9V + 325mV”, OVP is triggered and latched. When
VID is larger than 0.9V, once VSEN voltage exceeds the
internal reference by 325mV, OVP is triggered and latched.
The VDD controller will try to turn on low-side MOSFETs
and turn off high-side MOSFETs of all active phases of the
VDD controller to protect the CPU. When OVP is triggered
by one rail, the other rail will also enter soft shut down
sequence. A 1μs delay is used in OVP detection circuit
to prevent false trigger.
Negative-Voltage Protection (NVP)
During OVP latch state, the VDD controller also monitors
the VSEN pin for negative voltage protection. Since the
OVP latch continuously turns on all low-side MOSFETs
of the VDD controller, the VDD controller may suffer
negative output voltage. As a consequence, when the VSEN
voltage drops below 0V after triggering OVP, the VDD
controller will trigger NVP to turn off all low-side MOSFETs
of the VDD controller while the high-side MOSFETs
remains off. After triggering NVP, if the output voltage rises
above 0V, the OVP latch will restart to turn on all low-side
MOSFETs. The NVP function will be active only after OVP
is triggered.
VDDNB Controller
VDDNB Controller Disable
The VDDNB controller can be disabled by connecting
ISENA1N to a voltage higher than VCC. If not in use,
ISENAxP is recommended to be connected to VCC, while
PWMAx is left floating. When VDDNB controller is disabled,
all SVID commands related to VDDNB controller will be
rejected.
Loop Control
The VDDNB controller adopts Richtek's proprietary GNAVPTM topology. The G-NAVPTM is based on the finite
gain peak current mode with CCRCOT (Constant Current
Ripple Constant On-Time) topology. The output voltage,
VVDDNB will decrease with increasing output load current.
The control loop consists of PWM modulators with power
stages, current sense amplifiers and an error amplifier as
shown in Figure 15.
Similar to the peak current mode control with finite
compensator gain, the HS_FET on-time is determined by
CCRCOT on-time generator. When load current increases,
VCS increases, the steady state COMPA voltage also
increases and induces VVDDNB to decrease, thus achieving
AVP. A near-DC offset canceling is added to the output of
EA to eliminate the inherent output offset of finite gain
peak current mode controller.
Under-Voltage Protection (UVP)
The VDD controller implements under-voltage protection
of VOUT,VDD. If VSEN voltage is less than the internal
reference by 500mV, the VDD controller will trigger UVP
latch. The UVP latch will turn off both high-side and lowside MOSFETs. When UVP is triggered by one rail, the
other rail will also enter soft shutdown sequence. A 3μs
delay is used in UVP detection circuit to prevent false
trigger.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8880C-02
January 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
35
RT8880C
VIN
COMP2
+
CMP
-
CCRCOT
PWMA2
PWM
Logic
Loop Compensation
VVDDNB
HS_FET
L RSENSE
Driver
RX
CX
RC
LS_FET
0.4
x2
VCS
+
-
C
ISENAxP
ISENAxN
RCSx
IMONA RIMONA
Offset
Canceling
VREF
+
COMPA
FBA
EA
RGND
+
VDAC, VDDNB
C2
R2
C1
R1
VVDDNB_SENSE
VSS_SENSE
Figure 15. VDDNB Controller : Simplified Schematic for
Droop and Remote Sense in CCM
Droop Setting
It is very easy to achieve Active Voltage Positioning (AVP)
by properly setting the error amplifier gain due to the native
droop characteristics as shown in Figure 16. This target
is to have
VVDDNB = VDAC,VDDNB − ILOAD x RDROOP
(22)
Then solving the switching condition VCOMP2 = VCS in
Figure 15 yields the desired error amplifier gain as
GI
A V  R2 
R1 RDROOP
where GI 
(23)
RSENSE
 RIMON  8
RCSx
10
Where C is the capacitance of output capacitor, and RC is
the ESR of output capacitor. C2 can be calculated as
follows :
C x RC
(26)
C2 
R2
The zero of compensator has to be placed at half of the
switching frequency to filter the switching related noise.
Such that,
C1 
1
R1   fSW
(27)
COMPA
C2
C1
R2
R1
EA
+
VVDDNB_SENSE
FBA
+
VVDDNB
RGND
VSS_SENSE
VDAC,VDDNB
Figure 17. VDDNB Controller : Compensation Circuit
TON Setting
AV2 > AV1
AV2
AV1
Load Current
Figure 16. VDDNB Controller : Error Amplifier gain (AV)
Influence on VVDDNB Accuracy
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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36
The pole frequency of the compensator must be set to
compensate the output capacitor ESR zero :
1
fP 
(25)
2   C  RC
(24)
where GI is the internal current sense amplifier gain. RSENSE
is the current sense resistor. If no external sense resistor
present, it is the equivalent resistance of the inductor.
RDROOP is the equivalent load-line resistance as well as
the desired static output impedance.
0
Optimized compensation of the VDDNB controller allows
for best possible load step response of the regulator’s
output. A type-I compensator with one pole and one zero
is adequate for proper compensation. Figure 17 shows
the compensation circuit. Previous design procedure
shows how to select the resistive feedback components
for the error amplifier gain. Next, C1 and C2 must be
calculated for compensation. The target is to achieve
constant resistive output impedance over the widest
possible frequency range.
High frequency operation optimizes the application for the
smaller component size, trading off efficiency due to higher
switching losses. This may be acceptable in ultra portable
devices where the load currents are lower and the
controller is powered from a lower voltage supply. Low
frequency operation offers the best overall efficiency at
the expense of component size and board space. Figure
18 shows the On-Time setting circuit. Connect a resistor
(RTON) between VIN and TONSETA to set the on-time of
UGATE :
is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
RT8880C
tON (0.5V  VDAC  1.8V) 
24.4  1012  RTON
VIN  VDAC,VDDNB
(28)
where tON is the UGATE turn-on period, VIN is Input voltage
of the VDDNB controller, and VDAC,VDDNB is the DAC
voltage.
When VDAC,VDDNB is larger than 1.8V, the equivalent
switching frequency may be over 500kHz, and this too
fast switching frequency is unacceptable. Therefore, the
VDDNB controller implements a pseudo constant
frequency technology to avoid this disadvantage of
CCRCOT topology. When VDAC,VDDNB is larger than 1.8V,
the on-time equation will be modified to :
tON (VDAC  1.8V)
Current Sense Setting
The current sense topology of the VDDNB controller is
continuous inductor current sensing. Therefore, the
controller has less sensitive noise. Low offset amplifiers
are used for current balance, loop control and over current
detection. The ISENAxP and ISENAxN pins denote the
positive and negative input of the current sense amplifier
of each phase.
Users can either use a current sense resistor or the
inductor's DCRL for current sensing. Using the inductor's
DCRL allows higher efficiency as shown in Figure 19.
IL
L
VVDDNB
DCRL
12

13.55  10
 RTON  VDAC,VDDNB
VIN  VDAC,VDDNB
RX
(29)
ISENAxN
+
On-time translates only roughly to switching frequencies.
For better efficiency of the given load range, the maximum
switching frequency is suggested to be :
fSW(MAX) 
-
CX
ISENAxP
ISENAxN
RCSx
Figure 19. VDDNB Controller : Lossless Inductor
Sensing
VDAC(MAX)  ILOAD(MAX)  DCRL  RON_LS-FET  RDROOP 


 VIN(MAX)  ILOAD(MAX)  RON_LS-FET  RON_HS-FET     TON  TD  TON, VAR   ILOAD(MAX)  RON_LS-FET   TD
(30)
Where fS(MAX) is the maximum switching frequency,
TD is the driver dead time, TON,VAR is the TON variation
value. VDAC(MAX) is the Maximum VDAC,VDDNB of application,
V IN(MAX) is the Maximum application Input voltage,
ILOAD(MAX) is the maximum load of application, RON_LS-FET
is the on-resistance of low side FET RDS(ON) , RON_HS-FET
is the on-resistance of high side FET RDS(ON), DCRL is the
inductor equivalent resistance of the inductor, and RDROOP
is the load-line setting.
CCRCOT
On-Time
Computer
TONSETA
RTON
R1
VIN
C1
VDAC,VDDNB
On-Time
Figure 18. VDDNB Controller : On-Time Setting with RC
filter
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8880C-02
January 2015
In order to optimize transient performance, RX and CX must
be set according to the equation below :
L  R C
X
X
DCRL
(31)
Then the proportion between the phase current, IL, and
the sensed current, ISENAxN, is driven by the value of the
effective sense resistance, RCSx, and the DCRL of the
inductor. The resistance value of RCSx is limited by the
internal circuitry. The recommended value is from 500Ω
to 1.2kΩ.
DCRL
(32)
ISENAxN  IL 
RCSx
Considering the inductance tolerance, the resistor RX has
to be tuned on board by examining the transient voltage.
If the output voltage transient has an initial dip below the
minimum load-line requirement and the response time is
too fast causing a ring back, the value of resistance should
be increased. Vice versa, with a high resistance, the output
voltage transient has only a small initial dip with a slow
response time.
is a registered trademark of Richtek Technology Corporation.
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37
RT8880C
Using current sense resistor in series with the inductor
can have better accuracy, but the efficiency is a trade-off.
Considering the equivalent inductance (LESL) of the current
sense resistor, an RC filter is recommended. The RC filter
calculation method is similar to the above mentioned
inductor equivalent resistance sensing method.
The external offset function can be implemented by the
SET2 pin setting. For example, referring to Table 11, when
the both rail external offset functions are enabled, the
output voltage is :
Per-Phase Over Current Protection
VInitial_OFSA is the initial offset voltage set by SVI interface,
and the external offset voltage, VExternal_OFSA is set by
supplying a voltage into the OFSA pin.
The VDDNB controller provides over current protection in
each phase. For VDDNB controller in two-phase
configuration, either phase can trigger Per-Phase Over
Current Protection (PHOCP).
The VDDNB controller senses each phase inductor current
IL, and PHOCP comparator compares sensed current with
PHOCP threshold current, as shown in Figure 20.
1 I
8 SENAxN
PHOCP trigger
10µA
Current Mirror
The resistor RCSx determines PHOCP threshold.
RCSx 
DCRL 1
 = 10A
RCSx 8
IL,PERPHASE(MAX)  DCRL
8  10A
(33)
(34)
The controller will turn off all high-side/low-side MOSFETs
to protect CPU if the per-phase over current protection is
triggered.
Initial Offset and External Offset (Over Clocking
Offset Function)
The VDDNB controller features over clocking offset function
which provides the possibility of wide range offset of output
voltage. The initial offset function can be implemented
through the SVI interface. When the OFSA pin voltage
< 0.3V at EN rising edge, the initial offset is disabled.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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38
+ VExternal _ OFSA + VInitial _ OFSA
(35)
It can be calculated as below :
VExternal _ OFSA = VOFSA  1.2V
(36)
If supplying 1.3V at OFSA pin, it will achieve 100mV offset
at the output. Connecting a filter capacitor between the
OFSA and GND pins is necessary. Designers can design
the offset slew rate by properly setting the filter bandwidth.
Dynamic VID Enhancement
ISENAxN
Figure 20. VDDNB Controller : Per-Phase OCP Setting
IL,PERPHASE(MAX) 
VVDDNB  VDAC,VDDNB  ILOAD  RDROOP
During a dynamic VID event, the charging (dynamic VID
up) or discharging (dynamic VID down) current causes
unwanted load-line effect which degrades the settling time
performance. The RT8880C will hold the inductor current
to hold the load-line during a dynamic VID event. The
VDDNB controller will always enter two-phase configuration
when VDDNB controller receives dynamic VID up and
VDDNB controller will hold the operating state when
VDDNB controller receives dynamic VID down.
The RT8880C also has DVID compensation which can boost
up the Dynamic VID slew rate and adjust the voltage onthe-fly complete timing. The DVID compensation parameter
can be selected by DVIDx compensation bits using the
SET1 and SET2 pins.
Ramp Amplitude Adjust
When the VDDNB controller takes phase shedding
operation and enters diode emulation mode, the internal
ramp of VDDNB controller will be modified for the reason
of stability. In case of smooth transition into DEM, the
CCM ramp amplitude should be designed properly. The
RT8880C provides the SET1 pin for platform users to set
the ramp amplitude of the VDDNB controller in CCM.
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RT8880C
Current Monitoring and Current Reporting
The VDDNB controller provides current monitoring function
via inductor current sensing. In the G-NAVPTM technology,
the output voltage is dependent on output current, and
the current monitoring function is achieved by this
characteristic of output voltage. The equivalent output
current will be sensed from inductor current sensing and
mirrored to the IMONA pin. The resistor connected to the
IMONA pin determines voltage of the IMONA output.
VIMONA = IL,SUM  2 
DCRL
 RIMONA  0.64
RCSx
(37)
Where IL is the phase current, RCSx is the effective sense
resistance, and RIMONA is the current monitor current setting
resistor. Note that the IMONA pin cannot be monitored.
The ADC circuit of the VDDNB controller monitors the
voltage variation at the IMONA pin from 0V to 3.19375V,
and this voltage is decoded into digital format and stored
into Output_Current register. The ADC divides 3.19375V
into 511 levels, so LSB = 3.19375V / 511 = 6.25mV.
Quick Response
The VDDNB controller utilizes a quick response feature
to support heavy load current demand during instantaneous
load transient. The VDDNB controller monitors the current
of the VVDDNB_SENSE, and this current is mirrored to internal
quick response circuit. At steady state, this mirrored
current will not trigger a quick response. When the
VVDDNB_SENSE voltage drops abruptly due to load apply
transient, the mirrored current flowing into quick response
circuit will also increase instantaneously.
The QR threshold setting for VDDNB controller refers to
Table 5.
QRTHA
+
CMP
-
+
QR Pulse
Generation
Circuit
VVDDNB_SENSE
Figure 21. VDDNB Controller : Quick Response
Triggering Circuit
When quick response is triggered, the quick response
circuit will generate a quick response pulse. The pulse
width of quick response is almost the same as tON.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8880C-02
January 2015
After generating a quick response pulse, the pulse is then
applied to the on-time generation circuit, and all the active
phases' on-times will be overridden by the quick response
pulse.
Over-Current Protection
The RT8880C has dual OCP mechanism. The dual OCP
mechanism has two types of thresholds. The first type,
referred to as OCP-TDCA, is a time and current based
threshold. OCP-TDCA should trip when the average output
current exceeds TDCA by some percentage and for a
period of time. This period of time is referred to as the
trigger delay. The second type, referred to as OCPSPIKEA, is a current based threshold. OCP-SPIKEA
should trip when the cycle-by-cycle output current
exceeds IDDSPIKEA by some percentage. If either
mechanism trips, then the VDDNB controller asserts
OCP_L and delays any further action. This delay is called
an action delay. Refer to action delay time. After the action
delay has expired and the VDDNB controller has allowed
its current sense filter to settle out and the current has
not decreased below the threshold, then the VDDNB
controller will turn off both high-side MOSFETs and lowside MOSFETs of all channels.
Users can set OCP-SPIKEA threshold, IL,SUM(SPIKEA), by
the current monitor resistor RIMONA of the following equation :
R
IL,SUM (SPIKE) = 3.19375  0.64  CSx
(38)
2  DCR
RIMONA
And set the OCP-TDCA threshold, IL(TDCA), refer to some
percentage of OCP-SPIKEA through Table 3.
Over-Voltage Protection (OVP)
The over-voltage protection circuit of the VDDNB controller
monitors the output voltage via the VSENA pin after IC
POR. When VID is lower than 0.9V, once VSENA voltage
exceeds “0.9V + 325mV”, OVP is triggered and latched.
When VID is larger than 0.9V, once VSENA voltage
exceeds the internal reference by 325mV, OVP is triggered
and latched. The VDDNB controller will try to turn on lowside MOSFETs and turn off high-side MOSFETs of all active
phases of the VDDNB controller to protect the CPU. When
OVP is triggered by one rail, the other rail will also enter
soft shut down sequence. A 1μs delay is used in OVP
detection circuit to prevent false trigger.
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RT8880C
During OVP latch state, the VDDNB controller also
monitors the VSENA pin for negative voltage protection.
Since the OVP latch continuously turns on all low-side
MOSFETs of the VDDNB controller, the VDDNB controller
may suffer negative output voltage. As a consequence,
when the VSENA voltage drops below 0V after triggering
OVP, the VDDNB controller will trigger NVP to turn off all
low-side MOSFETs of the VDDNB controller while the highside MOSFETs remains off. After triggering NVP, if the
output voltage rises above 0V, the OVP latch will restart
to turn on all low-side MOSFETs. The NVP function will
be active only after OVP is triggered.
Under-Voltage Protection (UVP)
The VDDNB controller implements under-voltage protection
of VOUT,VDDNB. If VSENA voltage is less than the internal
reference by 500mV, the VDDNB controller will trigger UVP
latch. The UVP latch will turn off both high-side and lowside MOSFETs. When UVP is triggered by one rail, the
other rail will also enter soft shutdown sequence. A 3μs
delay is used in UVP detection circuit to prevent false
trigger.
Under-Voltage Lock Out (UVLO)
During normal operation, if the voltage at the VCC pin
drops below IC POR threshold, the VDDNB controller will
trigger UVLO. The UVLO protection forces all high-side
MOSFETs and low-side MOSFETs off by shutting down
internal PWM logic drivers. A 3μs delay is used in UVLO
detection circuit to prevent false trigger.
Thermal Considerations
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction
to ambient thermal resistance, θJA, is layout dependent.
For WQFN-52L 6x6 package, the thermal resistance, θJA,
is 26.5°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (26.5°C/W) = 3.77W for
WQFN-52L 6x6 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 22 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
4.0
Maximum Power Dissipation (W)1
Negative-Voltage Protection (NVP)
Four-Layer PCB
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 22. Derating Curve of Maximum Power
Dissipation
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
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is a registered trademark of Richtek Technology Corporation.
DS8880C-02
January 2015
RT8880C
Outline Dimension
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min.
Max.
Min.
Max.
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
5.950
6.050
0.234
0.238
D2
4.650
4.750
0.183
0.187
E
5.950
6.050
0.234
0.238
E2
4.650
4.750
0.183
0.187
e
0.400
0.016
L
0.350
0.450
0.014
0.018
L1
0.300
0.400
0.012
0.016
W-Type 52L QFN 6x6 Package
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January 2015
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RT8880C
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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DS8880C-02
January 2015