® RT3606BE Dual Channel PWM Controller for IMVP8 CPU Core Power Supply General Description Features The RT3606BE is an IMVP8 compliant CPU power controller which includes two voltage rails : a 3/2/1 phase synchronous Buck controller, the CORE VR and a 2/1 phase synchronous Buck controller, the AXG VR. The RT3606BE adopts G-NAVPTM (Green Native AVP) which is Richtek's proprietary topology derived from finite DC gain of EA amplifier with current mode control, making it easy to set the droop to meet all Intel CPU requirements of AVP (Adaptive Voltage Positioning). Based on the GNAVPTM topology, the RT3606BE also features a quick response mechanism for optimized AVP performance during load transient. The RT3606BE supports mode transition function with various operating states. A serial VID (SVID) interface is built in the RT3606BE to communicate with Intel IMVP8 compliant CPU. The RT3606BE supports VID on-the-fly function with three different slew rates : Fast, Slow and Decay. By utilizing the G-NAVPTM topology, the operating frequency of the RT3606BE varies with VID, load and input voltage to further enhance the efficiency even in CCM. Moreover, the GNAVPTM with CCRCOT (Constant Current Ripple COT) technology provides superior output voltage ripple over the entire input/output range. The built-in high accuracy DAC converts the SVID code ranging from 0.25V to 1.52V with 5mV per step. The RT3606BE integrates a high accuracy ADC for platform setting functions, such as quick response trigger level or over-current level. Besides, the setting function also supports this two rails address exchange. The RT3606BE provides VR ready output signals. It also features complete fault protection functions including over-voltage (OV), negative voltage (NV), overcurrent (OC) and under-voltage lockout (UVLO). The RT3606BE is available in the WQFN-48L 6x6 small foot print package. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 Intel IMVP8 Serial VID Interface Compatible Power Management States 3/2/1 Phase (CORE VR) + 2/1 Phase (AXG VR) PWM Controller G-NAVP TM (Green Native Adaptive Voltage Positioning) Topology 0.5% DAC Accuracy Differential Remote Voltage Sensing Built-in ADC for Platform Programming Accurate Current Balance System Thermal Compensated AVP Diode Emulation Mode at Light Load Condition for Single Phase Operation Fast Transient Response VR Ready Indicator Thermal Throttling Current Monitor Output OVP, OCP, NVP, UVLO Slew Rate Setting/Address Flip Function Rail Address Flexibility DVID Enhancement Applications IMVP8 Intel Core Supply Notebook/ Desktop Computer Multi-phase CPU Core Supply AVP Step-Down Converter Simplified Application Circuit To PCH RT3606BE PGOOD PWM1 Driver MOSFET PWM2 Driver MOSFET VCLK PWM3 Driver MOSFET VDIO PWMA2 Driver MOSFET ALERT PWMA1 Driver MOSFET VR_HOT To CPU VCORE VAXG is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT3606BE Ordering Information Pin Configurations (TOP VIEW) TONSET PGOOD PWM3 PWM1 PWM2 PS4 PWMA1 PWMA2 PS4_Dr DVD TONSETA TSENA RT3606BE Package Type QW : WQFN-48L 6x6 (W-Type) (Exposed Pad-Option 1) Lead Plating System G : Green (Halogen Free and Pb Free) Note : Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Marking Information 48 47 46 45 44 43 42 41 40 39 38 37 TSEN ISEN3P ISEN3N ISEN1N ISEN1P ISEN2P ISEN2N FB COMP VSEN RGND SET1 36 2 35 3 34 4 33 5 32 6 31 GND 7 30 29 8 28 9 49 10 27 26 11 25 12 RT3606BEGQW : Product Number RT3606BE GQW YMDNN 1 ISENA1N ISENA1P ISENA2P ISENA1N FBA COMPA VSENA RGNDA IBIAS VCC OFSA/PSYS OFSM 13 14 15 16 17 18 19 20 21 22 23 24 SET2 SET3 SETA1 SETA2 IMON VREF IMONA VR_HOT ALERT VDIO VCLK EN YMDNN : Date Code WQFN-48L 6x6 Functional Pin Description Pin No 1 Pin Name Pin Function TSEN Thermal Sense Input for CORE rail VR. 4, 7, 3 ISEN[1:3]N Negative Current Sense Inputs of Multi-Phase CORE rail VR Channel 1, 2 and 3. 5, 6, 2 ISEN[1:3]P Positive Current Sense Inputs of Multi-Phase CORE rail VR Channel 1, 2 and 3. Negative Input of the Error Amplifier. This pin is for CORE rail VR output voltage feedback to controller. CORE rail VR Compensation. This pin is the error amplifier output pin. CORE rail VR Voltage Sense Input. This pin is connected to the terminal of CORE rail VR output voltage. Return Ground for CORE rail VR. This pin is the negative node of the differential remote voltage sensing. 1st Platform Setting. Platform can use this pin to set OCS, DVID threshold and ICCMAX for CORE rail VR. 2nd Platform Setting. Platform can use this pin to set RSET, QRTH, QRWIDTH and DVID width for CORE rail VR. Moreover, SET2 pin features a special function for users to confirm the soldering condition of the controller under zero VBOOT condition. Connect the SET2 pin to 5V and turn on the EN pin, if the soldering is good, both rails will output 0.8V. 3rd Platform setting. Platform can use this pin to set VR address, Zero load-line, Anti-overshoot function and behavior, AI gain, Disable DVID compensation, Decrease GTU and SA ramp (only in maximum phase = 1-phase), high frequency ramp, DVID slew rate, and PSYS function for CORE VR and AXG VR. 1st Platform Setting. Platform can use this pin to set OCS, DVID threshold and ICCMAX for AXG rail VR. 2nd Platform Setting. Platform can use this pin to set RSET, QRTH, QRWIDTH and DVID width for AXG rail VR. 8 FB 9 COMP 10 VSEN 11 RGND 12 SET1 13 SET2 14 SET3 15 SETA1 16 SETA2 Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Pin No Pin Name Pin Function 17 IMON 18 VREF 19 IMONA 20 VR_HOT CORE rail VR Current Monitor Output. This pin outputs a voltage proportional to the loading current and a 1 resistor. Fixed 0.6V Output Reference Voltage. This voltage is only used to offset the output voltage of IMON pin. Between this pin and GND must be placed a exact 0.47F decoupling capacitor. AXG rail VR Current Monitor Output. This pin outputs a voltage proportional to the loading current. Thermal Monitor Output, this Pin is Active Low. 21 ALERT SVID Alert. (Active low) 22 VDIO VR and CPU Data Transmission Interface. 23 VCLK Synchronous Clock from the CPU. 24 EN VR Enable Control Input. 25 OFSM Output Voltage Offset Setting for CORE rail VR. 26 OFSA/PSYS Output Voltage Offset Setting for AXG rail VR / System Input Power Monitor. Controller Power Supply. Connect this pin to 5V and place a decoupling capacitor VCC 2.2F at least. The decoupling capacitor is placed as close VR controller as possible. Internal Bias Current Setting. Connect a 100k resistor from this pin tied to GND to IBIAS set the internal current. Don’t connect a bypass pass capacitor from this pin to GND. Return Ground for AXG rail VR. This pin is the negative node of the differential remote RGNDA voltage sensing. AXG rail VR Voltage Sense Input. This pin is connected to the terminal of AXG rail VSENA VR output voltage. 27 28 29 30 31 COMPA 32 FBA AXG rail VR Compensation. This pin is the error amplifier output pin. Negative Input of the Error Amplifier. This pin is for AXG rail VR output voltage feedback to controller. 35, 34 ISENA[1:2]P Positive Current Sense Inputs of Multi-Phase AXG rail VR Channel 1 and 2. 36, 33 ISENA[1:2]N Negative Current Sense Inputs of Multi-Phase AXG rail VR Channel 1 and 2. 37 TSENA 38 TONSETA 39 DVD 40 PS4_Dr 42, 41 Thermal Sense Input for AXG rail VR. AXG rail VR On-time Setting. An on-time setting resistor is connected from this pin to input voltage. Divided Input Voltage Detection of power stage. Connect this pin to a voltage divider from input voltage of power stage to detect input voltage. Dr.MOS Enable Control. Connecting to Dr.MOS PS4 function pin. As received PS4 command, this pin will be floating. If the Dr. MOS needs active low to enter PS4 or use discrete MOSFET, please reserve a 100k resistor to GND. PWMA[1:2] PWM Output for AXG rail VR. PS4 External Driver Enable Control. Connecting to driver enable pin. As received PS4 command, this pin will be low state. PWM[1:3] PWM Outputs for CORE rail VR of Channel 1, 2 and 3. 47 PGOOD VR Ready Indicator. 48 TONSET 43 45, 44, 46 49 GND (Exposed Pad) CORE rail VR On-time Setting. An on-time setting resistor is connected from this pin to input voltage. Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT3606BE PGOOD DVD VCC VSENA PS4_Dr EN VSENM PS4 VR_HOT ALERT VDIO VCLK OFSA/PSYS IMONI_A SETA1 SETA2 TSENA IMONI_M OFS_M SET1 SET2 SET3 TSEN Functional Block Diagram UVLO MUX MUX ADC ADC DAC Current Mirror 2V IBIAS + IBIASI From Control Logic DAC DVID SR DVIDTH_M DVIDWIDTH_M Soft-Start & Slew Rate Control ERROR VSET_M AMP + FB - COMP IC1_M IC2_M IC3_M IC4_M IC1_A IC2_A IC3_A OCS_M OCS_A VID_M VID_A VR address H/L fSW ramp DVID SR Disable DVID compensation Decrease GTV/SA ramp (only in 1-phase) Zero load-line Anti-OVS Anti-OVS behavior AI gain PSYS function PWM CMP Offset + Cancellation + DVIDTH_X DVIDWIDTH_X QR_X QRWIDTH_X OCS_TH_X RSET_X ICCMAX_X OCP_PER_X - RGND SVID Interface Configuration Registers Control Logic ISEN1P ISEN1N + IB1_M VREF + ISEN2N - + ISEN3N - IB2_M IMON Filter IMONI_M IMON DAC VSET_A FBA TONSETA ERROR AMP Offset Cancellation + + + - - IB1_A RSET_A IMON Filter IC2_A IMONI_A IMONA + OCS_TH_A + PWMA1 PWMA2 Current Balance IB1_A IB2_A VREFI PS_A TON GEN/ Driver Interface QRWIDTH_A 1/3 + GM - IC1_A Current Mirror + PWM CMP QRTH_A Current Mirror ISENA2P ISENA2N PWM3 OCS_M COMPA - PWM2 Anti-OVS behavior - + PWM1 Anti-OVS - DVID SR DVIDTH_A DVIDWIDTH_A Soft-Start & Slew Rate Control ISENA1P ISENA1N TON GEN/ Driver Interface IB1_M IB2_M IB3_M IB3_M + RGNDA PS_M IC3_M OCS_TH_M From Control Logic TONSET Current Balance IC2_M Current Mirror ISEN3P OV_X/UV_X/NV_X/ OC_PER_X/OC_SUM_X RSET_M Current Mirror ISEN2P PS_M PS_A QRWIDTH_M 1/3 + GM - IC1_M - Loop Control Protection Logic QRTH_M Current Mirror GND IB2_A OCS_A - - VREF Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Operation The RT3606BE adopts G-NAVPTM (Green Native AVP) which is Richtek's proprietary topology derived from finite DC gain of EA amplifier with current mode control, making it easy to set the droop to meet all Intel CPU requirements of AVP (Adaptive Voltage Positioning). Current Balance The G-NAVPTM controller is one type of current mode constant on-time control with DC offset cancellation. The approach can not only improve DC offset problem for increasing system accuracy but also provide fast transient response. When current feedback signal reaches COMP signal, the RT3606BE generates an on-time width to achieve PWM modulation. Offset Cancellation TON GEN/Driver Interface Generate the PWM1 to PWM3 sequentially according to the phase control signal from the Loop Control/Protection Logic. Pulse width is determined by current balance result and TONSET pin setting. Once quick response mechanism is triggered, VR will allow all PWM to turn on at the same time. PWM status is also controlled by Protection Logic. Different protections may cause different PWM status (Both High-Z or LG turn-on). SVID Interface/Configuration Registers/Control Logic The interface receives the SVID signal from CPU and sends the relative signals to Loop Control/Protection Logic for loop control to execute the action by CPU. The registers save the pin setting data from ADC output. The Control Logic controls the ADC timing and generates the digital code of the VID for VSEN voltage. Each phase current sense signal is sent to the current balance circuit which adjusts the on-time of each phase to optimize current sharing. Cancel the current/voltage ripple issue to get the accurate VSEN. UVLO Detect the DVD and VCC voltage and issue POR signal as they are high enough. DAC Generate an analog signal according to the digital code generated by Control Logic. Soft-Start & Slew Rate Control Control the Dynamic VID slew rate of DAC according to the SetVID fast or SetVID slow. Error Amp Error amplifier generates COMP/COMPA signal by the difference between VSEN/VSENA and FB/FBA. RSET/RSETA The Ramp generator is designed to improve noise immunity and reduce jitter. PWM CMP The PWM comparator compares COMP signal and current feedback signal to generate a signal for TON trigger. Loop Control/Protection Logic IMON Filter It controls the power on sequence, the protection behavior, and the operational phase number. IMON Filter is used to average sum current signal by analog RC filter. MUX and ADC The MUX supports the inputs from SET1, SET2, SET3, SETA1, SETA2, IMONI_M, IMONI_A, TSEN or TSENA. The ADC converts these analog signals to digital codes for reporting or performance adjustment. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT3606BE Table 1. IMVP8 VID Code Table VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 0 0 0 0 0 0 0 1 01 0.25 0 0 0 0 0 0 1 0 02 0.255 0 0 0 0 0 0 1 1 03 0.26 0 0 0 0 0 1 0 0 04 0.265 0 0 0 0 0 1 0 1 05 0.27 0 0 0 0 0 1 1 0 06 0.275 0 0 0 0 0 1 1 1 07 0.28 0 0 0 0 1 0 0 0 08 0.285 0 0 0 0 1 0 0 1 09 0.29 0 0 0 0 1 0 1 0 0A 0.295 0 0 0 0 1 0 1 1 0B 0.3 0 0 0 0 1 1 0 0 0C 0.305 0 0 0 0 1 1 0 1 0D 0.31 0 0 0 0 1 1 1 0 0E 0.315 0 0 0 0 1 1 1 1 0F 0.32 0 0 0 1 0 0 0 0 10 0.325 0 0 0 1 0 0 0 1 11 0.33 0 0 0 1 0 0 1 0 12 0.335 0 0 0 1 0 0 1 1 13 0.34 0 0 0 1 0 1 0 0 14 0.345 0 0 0 1 0 1 0 1 15 0.35 0 0 0 1 0 1 1 0 16 0.355 0 0 0 1 0 1 1 1 17 0.36 0 0 0 1 1 0 0 0 18 0.365 0 0 0 1 1 0 0 1 19 0.37 0 0 0 1 1 0 1 0 1A 0.375 0 0 0 1 1 0 1 1 1B 0.38 0 0 0 1 1 1 0 0 1C 0.385 0 0 0 1 1 1 0 1 1D 0.39 0 0 0 1 1 1 1 0 1E 0.395 0 0 0 1 1 1 1 1 1F 0.4 0 0 1 0 0 0 0 0 20 0.405 0 0 1 0 0 0 0 1 21 0.41 0 0 1 0 0 0 1 0 22 0.415 0 0 1 0 0 0 1 1 23 0.42 0 0 1 0 0 1 0 0 24 0.425 Copyright © 2016 Richtek Technology Corporation. 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DS3606BE-00 April 2016 RT3606BE VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 0 0 1 0 0 1 0 1 25 0.43 0 0 1 0 0 1 1 0 26 0.435 0 0 1 0 0 1 1 1 27 0.44 0 0 1 0 1 0 0 0 28 0.445 0 0 1 0 1 0 0 1 29 0.45 0 0 1 0 1 0 1 0 2A 0.455 0 0 1 0 1 0 1 1 2B 0.46 0 0 1 0 1 1 0 0 2C 0.465 0 0 1 0 1 1 0 1 2D 0.47 0 0 1 0 1 1 1 0 2E 0.475 0 0 1 0 1 1 1 1 2F 0.48 0 0 1 1 0 0 0 0 30 0.485 0 0 1 1 0 0 0 1 31 0.49 0 0 1 1 0 0 1 0 32 0.495 0 0 1 1 0 0 1 1 33 0.5 0 0 1 1 0 1 0 0 34 0.505 0 0 1 1 0 1 0 1 35 0.51 0 0 1 1 0 1 1 0 36 0.515 0 0 1 1 0 1 1 1 37 0.52 0 0 1 1 1 0 0 0 38 0.525 0 0 1 1 1 0 0 1 39 0.53 0 0 1 1 1 0 1 0 3A 0.535 0 0 1 1 1 0 1 1 3B 0.54 0 0 1 1 1 1 0 0 3C 0.545 0 0 1 1 1 1 0 1 3D 0.55 0 0 1 1 1 1 1 0 3E 0.555 0 0 1 1 1 1 1 1 3F 0.56 0 1 0 0 0 0 0 0 40 0.565 0 1 0 0 0 0 0 1 41 0.57 0 1 0 0 0 0 1 0 42 0.575 0 1 0 0 0 0 1 1 43 0.58 0 1 0 0 0 1 0 0 44 0.585 0 1 0 0 0 1 0 1 45 0.59 0 1 0 0 0 1 1 0 46 0.595 0 1 0 0 0 1 1 1 47 0.6 0 1 0 0 1 0 0 0 48 0.605 0 1 0 0 1 0 0 1 49 0.61 Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT3606BE VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 0 1 0 0 1 0 1 0 4A 0.615 0 1 0 0 1 0 1 1 4B 0.62 0 1 0 0 1 1 0 0 4C 0.625 0 1 0 0 1 1 0 1 4D 0.63 0 1 0 0 1 1 1 0 4E 0.635 0 1 0 0 1 1 1 1 4F 0.64 0 1 0 1 0 0 0 0 50 0.645 0 1 0 1 0 0 0 1 51 0.65 0 1 0 1 0 0 1 0 52 0.655 0 1 0 1 0 0 1 1 53 0.66 0 1 0 1 0 1 0 0 54 0.665 0 1 0 1 0 1 0 1 55 0.67 0 1 0 1 0 1 1 0 56 0.675 0 1 0 1 0 1 1 1 57 0.68 0 1 0 1 1 0 0 0 58 0.685 0 1 0 1 1 0 0 1 59 0.69 0 1 0 1 1 0 1 0 5A 0.695 0 1 0 1 1 0 1 1 5B 0.7 0 1 0 1 1 1 0 0 5C 0.705 0 1 0 1 1 1 0 1 5D 0.71 0 1 0 1 1 1 1 0 5E 0.715 0 1 0 1 1 1 1 1 5F 0.72 0 1 1 0 0 0 0 0 60 0.725 0 1 1 0 0 0 0 1 61 0.73 0 1 1 0 0 0 1 0 62 0.735 0 1 1 0 0 0 1 1 63 0.74 0 1 1 0 0 1 0 0 64 0.745 0 1 1 0 0 1 0 1 65 0.75 0 1 1 0 0 1 1 0 66 0.755 0 1 1 0 0 1 1 1 67 0.76 0 1 1 0 1 0 0 0 68 0.765 0 1 1 0 1 0 0 1 69 0.77 0 1 1 0 1 0 1 0 6A 0.775 0 1 1 0 1 0 1 1 6B 0.78 0 1 1 0 1 1 0 0 6C 0.785 0 1 1 0 1 1 0 1 6D 0.79 0 1 1 0 1 1 1 0 6E 0.795 Copyright © 2016 Richtek Technology Corporation. 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DS3606BE-00 April 2016 RT3606BE VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 0 1 1 0 1 1 1 1 6F 0.8 0 1 1 1 0 0 0 0 70 0.805 0 1 1 1 0 0 0 1 71 0.81 0 1 1 1 0 0 1 0 72 0.815 0 1 1 1 0 0 1 1 73 0.82 0 1 1 1 0 1 0 0 74 0.825 0 1 1 1 0 1 0 1 75 0.83 0 1 1 1 0 1 1 0 76 0.835 0 1 1 1 0 1 1 1 77 0.84 0 1 1 1 1 0 0 0 78 0.845 0 1 1 1 1 0 0 1 79 0.85 0 1 1 1 1 0 1 0 7A 0.855 0 1 1 1 1 0 1 1 7B 0.86 0 1 1 1 1 1 0 0 7C 0.865 0 1 1 1 1 1 0 1 7D 0.87 0 1 1 1 1 1 1 0 7E 0.875 0 1 1 1 1 1 1 1 7F 0.88 1 0 0 0 0 0 0 0 80 0.885 1 0 0 0 0 0 0 1 81 0.89 1 0 0 0 0 0 1 0 82 0.895 1 0 0 0 0 0 1 1 83 0.9 1 0 0 0 0 1 0 0 84 0.905 1 0 0 0 0 1 0 1 85 0.91 1 0 0 0 0 1 1 0 86 0.915 1 0 0 0 0 1 1 1 87 0.92 1 0 0 0 1 0 0 0 88 0.925 1 0 0 0 1 0 0 1 89 0.93 1 0 0 0 1 0 1 0 8A 0.935 1 0 0 0 1 0 1 1 8B 0.94 1 0 0 0 1 1 0 0 8C 0.945 1 0 0 0 1 1 0 1 8D 0.95 1 0 0 0 1 1 1 0 8E 0.955 1 0 0 0 1 1 1 1 8F 0.96 1 0 0 1 0 0 0 0 90 0.965 1 0 0 1 0 0 0 1 91 0.97 1 0 0 1 0 0 1 0 92 0.975 1 0 0 1 0 0 1 1 93 0.98 Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT3606BE VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 1 0 0 1 0 1 0 0 94 0.985 1 0 0 1 0 1 0 1 95 0.99 1 0 0 1 0 1 1 0 96 0.995 1 0 0 1 0 1 1 1 97 1 1 0 0 1 1 0 0 0 98 1.005 1 0 0 1 1 0 0 1 99 1.01 1 0 0 1 1 0 1 0 9A 1.015 1 0 0 1 1 0 1 1 9B 1.02 1 0 0 1 1 1 0 0 9C 1.025 1 0 0 1 1 1 0 1 9D 1.03 1 0 0 1 1 1 1 0 9E 1.035 1 0 0 1 1 1 1 1 9F 1.04 1 0 1 0 0 0 0 0 A0 1.045 1 0 1 0 0 0 0 1 A1 1.05 1 0 1 0 0 0 1 0 A2 1.055 1 0 1 0 0 0 1 1 A3 1.06 1 0 1 0 0 1 0 0 A4 1.065 1 0 1 0 0 1 0 1 A5 1.07 1 0 1 0 0 1 1 0 A6 1.075 1 0 1 0 0 1 1 1 A7 1.08 1 0 1 0 1 0 0 0 A8 1.085 1 0 1 0 1 0 0 1 A9 1.09 1 0 1 0 1 0 1 0 AA 1.095 1 0 1 0 1 0 1 1 AB 1.1 1 0 1 0 1 1 0 0 AC 1.105 1 0 1 0 1 1 0 1 AD 1.11 1 0 1 0 1 1 1 0 AE 1.115 1 0 1 0 1 1 1 1 AF 1.12 1 0 1 1 0 0 0 0 B0 1.125 1 0 1 1 0 0 0 1 B1 1.13 1 0 1 1 0 0 1 0 B2 1.135 1 0 1 1 0 0 1 1 B3 1.14 1 0 1 1 0 1 0 0 B4 1.145 1 0 1 1 0 1 0 1 B5 1.15 1 0 1 1 0 1 1 0 B6 1.155 1 0 1 1 0 1 1 1 B7 1.16 1 0 1 1 1 0 0 0 B8 1.165 Copyright © 2016 Richtek Technology Corporation. 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DS3606BE-00 April 2016 RT3606BE VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 1 0 1 1 1 0 0 1 B9 1.17 1 0 1 1 1 0 1 0 BA 1.175 1 0 1 1 1 0 1 1 BB 1.18 1 0 1 1 1 1 0 0 BC 1.185 1 0 1 1 1 1 0 1 BD 1.19 1 0 1 1 1 1 1 0 BE 1.195 1 0 1 1 1 1 1 1 BF 1.2 1 1 0 0 0 0 0 0 C0 1.205 1 1 0 0 0 0 0 1 C1 1.21 1 1 0 0 0 0 1 0 C2 1.215 1 1 0 0 0 0 1 1 C3 1.22 1 1 0 0 0 1 0 0 C4 1.225 1 1 0 0 0 1 0 1 C5 1.23 1 1 0 0 0 1 1 0 C6 1.235 1 1 0 0 0 1 1 1 C7 1.24 1 1 0 0 1 0 0 0 C8 1.245 1 1 0 0 1 0 0 1 C9 1.25 1 1 0 0 1 0 1 0 CA 1.255 1 1 0 0 1 0 1 1 CB 1.26 1 1 0 0 1 1 0 0 CC 1.265 1 1 0 0 1 1 0 1 CD 1.27 1 1 0 0 1 1 1 0 CE 1.275 1 1 0 0 1 1 1 1 CF 1.28 1 1 0 1 0 0 0 0 D0 1.285 1 1 0 1 0 0 0 1 D1 1.29 1 1 0 1 0 0 1 0 D2 1.295 1 1 0 1 0 0 1 1 D3 1.3 1 1 0 1 0 1 0 0 D4 1.305 1 1 0 1 0 1 0 1 D5 1.31 1 1 0 1 0 1 1 0 D6 1.315 1 1 0 1 0 1 1 1 D7 1.32 1 1 0 1 1 0 0 0 D8 1.325 1 1 0 1 1 0 0 1 D9 1.33 1 1 0 1 1 0 1 0 DA 1.335 1 1 0 1 1 0 1 1 DB 1.34 1 1 0 1 1 1 0 0 DC 1.345 1 1 0 1 1 1 0 1 DD 1.35 Copyright © 2016 Richtek Technology Corporation. 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DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT3606BE VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 1 1 0 1 1 1 1 0 DE 1.355 1 1 0 1 1 1 1 1 DF 1.36 1 1 1 0 0 0 0 0 E0 1.365 1 1 1 0 0 0 0 1 E1 1.37 1 1 1 0 0 0 1 0 E2 1.375 1 1 1 0 0 0 1 1 E3 1.38 1 1 1 0 0 1 0 0 E4 1.385 1 1 1 0 0 1 0 1 E5 1.39 1 1 1 0 0 1 1 0 E6 1.395 1 1 1 0 0 1 1 1 E7 1.4 1 1 1 0 1 0 0 0 E8 1.405 1 1 1 0 1 0 0 1 E9 1.41 1 1 1 0 1 0 1 0 EA 1.415 1 1 1 0 1 0 1 1 EB 1.42 1 1 1 0 1 1 0 0 EC 1.425 1 1 1 0 1 1 0 1 ED 1.43 1 1 1 0 1 1 1 0 EE 1.435 1 1 1 0 1 1 1 1 EF 1.44 1 1 1 1 0 0 0 0 F0 1.445 1 1 1 1 0 0 0 1 F1 1.45 1 1 1 1 0 0 1 0 F2 1.455 1 1 1 1 0 0 1 1 F3 1.46 1 1 1 1 0 1 0 0 F4 1.465 1 1 1 1 0 1 0 1 F5 1.47 1 1 1 1 0 1 1 0 F6 1.475 1 1 1 1 0 1 1 1 F7 1.48 1 1 1 1 1 0 0 0 F8 1.485 1 1 1 1 1 0 0 1 F9 1.49 1 1 1 1 1 0 1 0 FA 1.495 1 1 1 1 1 0 1 1 FB 1.5 1 1 1 1 1 1 0 0 FC 1.505 1 1 1 1 1 1 0 1 FD 1.51 1 1 1 1 1 1 1 0 FE 1.515 1 1 1 1 1 1 1 1 FF 1.52 Copyright © 2016 Richtek Technology Corporation. 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DS3606BE-00 April 2016 RT3606BE Absolute Maximum Ratings (Note 1) VCC to GND ------------------------------------------------------------------------------------------- −0.3V to 6.5V RGND to GND ----------------------------------------------------------------------------------------- −0.3V to 0.3V TONSET to GND -------------------------------------------------------------------------------------- −0.3V to 28 BOOTx to PHASEx ---------------------------------------------------------------------------------- −0.3V to 15V PHASEx to GND DC -------------------------------------------------------------------------------------------------------- −0.3V to 30V <20ns --------------------------------------------------------------------------------------------------- −10V to 35V LGATEx to GND DC -------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V) <20ns --------------------------------------------------------------------------------------------------- −2V to (VCC + 0.3V) UGATEx to GND DC -------------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V) <20ns --------------------------------------------------------------------------------------------------- (VPHASE − 2V) to (VBOOT + 0.3V) Other Pins ---------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V) Power Dissipation, PD @ TA = 25°C WQFN-48L 6x6 --------------------------------------------------------------------------------------- 3.73W Package Thermal Resistance (Note 2) WQFN-48L 6x6, θJA ---------------------------------------------------------------------------------- 26.8°C/W WQFN-48L 6x6, θJC --------------------------------------------------------------------------------- 1.3°C/W Junction Temperature -------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------- 260°C Storage Temperature Range ----------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Mode) ------------------------------------------------------------------------- 2kV MM (Machine Mode) --------------------------------------------------------------------------------- 200V Recommended Operating Conditions (Note 4) Supply Voltage, VCC -------------------------------------------------------------------------------- 4.5V to 5.5V Junction Temperature Range ----------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ----------------------------------------------------------------------- −40°C to 85°C Copyright © 2016 Richtek Technology Corporation. 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DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT3606BE Electrical Characteristics (VCC = 5V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 4.5 5 5.5 V Supply Input Supply Voltage VCC Supply Current IVCC VEN = H, No Switching -- 13 -- Supply Current at PS4 IVCC_PS4 VEN = H, No Switching -- 0.1 -- Shutdown Current ISHDN VEN = 0V -- -- 5 A VDAC = 0.75V 1.52V 0.5% 0 0.5% % of VID VDAC = 0.5V 0.745V 8 0 8 VDAC = 0.25V 0.495V 10 0 10 Set VID Fast -- 11.25 -- Set VID Slow -- 5.625 -- Set VID Fast -- 33.75 -- Set VID Slow -- 16.875 -- mA Reference and DAC DAC Accuracy VFB mV Slew Rate Dynamic VID Slew Rate SR (S Line) Dynamic VID Slew Rate SR (H, Y, U Line) mV/s mV/s EA DC Gain EAGAIN RL = 47k 70 -- -- dB Gain-Bandwidth Product GBW CLOAD = 5pF -- 5 -- MHz Output Voltage Range VCOMP RL = 47k 0.5 -- 3.6 V VCOMP = 2V -- 5 -- mA Max Source/Sink Current IOUTEA Load Line Current Gain Amplifier Input Offset Voltage VILOFS VIMON = 1V 5 -- 5 mV Current Gain AILGAIN VIMON VVREF = 1V VFB = VCOMP = 1V -- 1/3 -- A/A 0.5 -- 0.5 mV 1 -- -- M Current Sensing Amplifier Input Offset Voltage Impedance at Positive Input Current Mirror Gain VOSCS RISENxP AMIRROR IIMON/ISENxN 0.97 1 1.03 A/A TON Pin Voltage VTON IRTON = 26.8A, VDAC = 1V 0.9 1 1.1 V On-Time Setting TON IRTON = 26.8A, VDAC = 1V 189 210 231 ns Input Current Range IRTON VDAC = 1V 6 -- 70 A Minimum Off time TOFF VDAC = 1V -- 150 -- ns TON Setting Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Parameter Symbol Test Conditions Min Typ Max Unit IBIAS IBIAS Pin Voltage VIBIAS RIBIAS = 100k 1.9 2 2.1 V VUVLO Falling edge 3.95 4.05 4.15 V VUVLO Rising edge hysteresis -- 190 -- mV VID + 300 1300 VID + 350 1350 VID + 400 1400 mV 100 70 -- mV Protections Under-Voltage Lockout Threshold Over-Voltage Protection Threshold Negative Voltage Protection Threshold EN and VR_REDAY EN Input Voltage VOV Respect to VID voltage Lower limit to 1V VNV VIH Respect to 1V, 70% 0.7 -- -- V VIL Respect to 1V, 30% -- -- 0.3 V 1 -- 1 A -- -- 0.13 V 2 -- -- V -- -- 1.3 V 0.65 -- -- -- -- 0.45 1 -- 1 A -- -- 0.13 V 0.55 0.6 0.65 V VIMON VIMON_INI = 1.6V -- 255 -- Decimal VIMON VIMON_INI = 0.8V -- 128 -- Decimal VIMON VIMON_INI = 0V -- 0 -- Decimal Leakage Current of EN PGOOD Pull Low Voltage mV VPGOOD IVR_Ready = 10mA DVD (Note 5) DVD Input High Voltage VIH DVD Input low Voltage VIL VDVD = 2V or above, VR judge VIN high VDVD = 1.3V or below, VR judge VIN low Serial VID and VR_HOT VCLK, VDIO Leakage Current of VCLK, VDIO, ALERT and VR_HOT VIH VIL Respect to INTEL Spec. with 50mV hysteresis ILEAK_IN V IVDIO = 10mA VDIO, ALERT and VR_HOT Pull Low Voltage IALERT = 10mA IVR_HOT = 10mA VREF VREF Voltage VREF ADC Digital IMON Set VIMON Copyright © 2016 Richtek Technology Corporation. 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DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT3606BE Parameter Update Period Symbol Test Conditions TIMON Min Typ Max Unit -- 125 -- s TSEN Threshold for Tmp_Zone[7] Transition 100C -- 1.092 -- TSEN Threshold for Tmp_Zone[6] Transition 97C -- 1.132 -- TSEN Threshold for Tmp_Zone[5] Transition 94C -- 1.176 -- 91C -- 1.226 -- TSEN Threshold for Tmp_Zone[4] Transition TSEN Threshold for Tmp_Zone[3] Transition VTSEN V 88C -- 1.283 -- TSEN Threshold for Tmp_Zone[2] Transition 85C -- 1.346 -- TSEN Threshold for Tmp_Zone[1] Transition 82C -- 1.418 -- TSEN Threshold for Tmp_Zone[0] Transition 75C -- 1.624 -- -- 100 -- s 61 64 67 Decimal 125 128 131 Decimal 251 254 255 Decimal -- 30 -- Update Period Ttsen CICCMAX1 Digital Code of ICCMAX CICCMAX2 CICCMAX3 VREF = 3.2V, VSET1 = 0.404V, VSETA1 = 0.404V VREF = 3.2V, VSET1 = 0.804V, VSETA1 = 0.804V VREF = 3.2V, VSET1 = 1.592V, VSETA1 = 1.592V PWM Driving Capability PWM Source Resistance RPWM_SRC Note 1. Si Stresses thoseRlisted “Absolute Maximum Ratings” may cause permanent damage10 to the device. These PWM k R ibeyond t are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5.(1) DVD Input High Voltage: DVD pin is an input pin of VR. VR always identify high level while the voltage given at DVD pin >= 2V. The high-low transition is within 1.3V ~2V. (2) DVD Input low Voltage: DVD pin is an input pin of VR. VR always identify low level while the voltage given at DVD pin <= 1.3V. The high-low transition is within 1.3V ~2V. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Typical Application Circuit Discrete MOS 12V RT3606BE R1 510k VIN 39 R2 100k C17 1µF DVD C1 0.1µF PWM1 45 VREF R3 2.2 C2 2.2µF R4 59k VCC 12 SET1 13 SET2 R5 69.8k R6 174k R8 46.4k R10 7.5k R11 3.32k R12 18.2k R13 11k VIN R15 2.2 487k C3 0.22µF VCC C21 1µF PWM2 2.2 C4 0.22µF 38 R18 28 18 R19 13k R87 1 RNTC R20 C5 0.47µF R22 17 3.09k 100k/4485 ( ) 16.5k 44 TONSETA RNTCA 16k VCCIO R26 NC IBIAS R28 55 R25 19 R29 75 IMONA R30 10k 24 Enable C6 470pF VCC_SENSE C8 Optional VSS_SENSE R32 32.4k C9 Optional R34 R35 10k 34k Optional C16 COMP 8 FB 11 RGND 31 VCC C37 1µF BOOT PGND UGATE PHASE PWM LGATE EN RT9624A PWMA2 41 ISENA2N C23 3.3nF R50 0.47湩 / X7R/0603 1k C24 C26 0.1µF R52 2.2 R36 93.1k RNTC 1 8.77k 150k/4500 ( ) R38 93.1k C41 1µF PWMA1 42 COMPA TSEN PS4 35 ISENA1P 36 ISENA1N 25 OFSM 26 OFSA/PSYS PS4 RNTC 37 TSENA 8.77k 150k/4500 ( ) 49 (Exposed Pad) PS4_Dr VSS_SENSE R89 100 R88 100 C48 VCORE_OUT R53 L3 220nH/0.49m 0 R54 R55 1 0 R56 C27 1k 3.3nF C38 0.1µF R70 2.2 C44 470µF x4 0.47湩 / X7R/0603 C45 22µF x 19 LOAD C28 Optional VIN R71 L6 220nH/0.49m 0 R72 R73 1 0 R74 C39 820 3.3nF VCC 0.47湩 / X7R/0603 C40 R75 R33 680 33 VSEN VSENA Optional VIN 34 32 FBA 29 RGNDA 30 VCCAXG_SENSE BOOT PGND UGATE PWM PHASE EN LGATE RT9624A C42 0.1µF R76 2.2 VIN Optional VCCAXG_SENSE R90 100 R77 L7 220nH/0.49m 0 R78 0 R79 1 R80 1k C43 3.3nF R91 100 C49 VAXG_OUT C46 470µF x4 0.47湩 / X7R/0603 C10 VSSAXG_SENSE C47 22µF x 14 LOAD Optional Optional R21 680 43 PS4 40 PS4_Dr R81 GND Copyright © 2016 Richtek Technology Corporation. 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DS3606BE-00 April 2016 R49 1 0 R57 EN Optional R39 R48 R84 680 C12 330pF C13 33pF R37 L2 220nH/0.49m 0 PHASE PWM LGATE EN RT9624A 46 12V VCC_SENSE VSSAXG_SENSE PGND UGATE PS4 9 10 C15 R47 C7 56pF C11 C14 BOOT 12V Optional Optional VIN ISEN3P 2 ISENA2P R31 12k VCC C25 1µF ISEN3N 3 47 PGOOD 20 VR_HOT 23 VCLK 22 VDIO 21 ALERT To CPU C22 0.1µF R46 2.2 Optional VCC_SENSE 12V PWM3 C20 R51 VREF IMON 0.47湩 / X7R/0603 R83 680 PS4 100k/4485 ( ) 15.8k R27 110 R43 R44 1 C19 1k 3.3nF 0 PWM PHASE EN LGATE RT9624A ISEN2N 7 R23 24.3k R24 R42 ISEN2P 6 100k VREF BOOT PGND UGATE 48 TONSET R17 412k R16 VIN L1 220nH/0.49m 0 R45 12V PS4 R14 R41 R82 680 ISEN1N 4 16 SETA2 R9 12k VIN ISEN1P 5 14 SET3 15 SETA1 R7 64.9k BOOT PGND UGATE PWM PHASE EN LGATE RT9624A PS4 27 5V VCC C18 0.1µF R40 2.2 is a registered trademark of Richtek Technology Corporation. www.richtek.com 17 RT3606BE Typical Operating Characteristics CORE VR Power Off from EN CORE VR Power On from EN V CORE (300mV/Div) V CORE (300mV/Div) PGOOD (1V/Div) PGOOD (1V/Div) UGATE1 (10V/Div) UGATE1 (10V/Div) EN (1V/Div) EN (1V/Div) VIN = 12V, No Load, VID = 0.8V VIN = 12V, No Load, VID = 0.8V Time (500μs/Div) Time (50μs/Div) CORE VR OCP CORE VR OVP V CORE (200mV/Div) V CORE (500mV/Div) PGOOD (1V/Div) UGATE1 (20V/Div) LGATE1 (10V/Div) PGOOD (1V/Div) UGATE1 (20V/Div) I LOAD (60A/Div) VIN = 12V, VID = 0.9V Time (100μs/Div) Time (50μs/Div) CORE VR Dynamic VID Up CORE VR Dynamic VID Down V CORE V CORE VCLK VCLK (1V/Div) VCLK (1V/Div) VDIO V CORE (200mV/Div) VDIO (1V/Div) ALERT (1V/Div) VCLK ALERT VIN = 12V, VID = 0.6V to 0.9V, Slew Rate = Slow Time (10μs/Div) Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 18 V CORE (200mV/Div) VDIO (1V/Div) ALERT (1V/Div) VDIO VIN = 12V, VID = 0.9V to 0.6V, Slew Rate = Slow ALERT Time (10μs/Div) is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE CORE VR Dynamic VID Up CORE VR Mode Transient V CORE V CORE VCLK VCLK (1V/Div) V CORE (200mV/Div) VDIO (1V/Div) VDIO ALERT ALERT (1V/Div) VIN = 12V, VID = 0.6V to 0.9V, Slew Rate = Fast Time (10μs/Div) VCLK VLCK (1V/Div) UGATE1 UGATE1 (20V/Div) LGATE1 (5V/Div) V CORE (20mV/Div) LGATE1 VIN = 12V, VID = 0.9V, PS0 to PS2, ILOAD = 1A Time (50μs/Div) CORE VR Thermal Monitioring CORE VR Mode Transient V CORE VCLK VLCK (1V/Div) UGATE1 VTSEN (500mV/Div) UGATE1 (20V/Div) LGATE1 LGATE1 (5V/Div) V CORE (20mV/Div) VIN = 12V, VID = 0.9V, PS2 to PS0, ILOAD = 1A VR_HOT (1V/Div) VIN = 12V, VTSEN Sweep from 1V to 2V Time (50μs/Div) Time (5ms/Div) VIMON vs. Load Current AXG VR Power On from EN 2.5 VIMON (V) 2.0 VAXG (300mV/Div) 1.5 PGOOD (1V/Div) 1.0 UG_GT1 (10V/Div) 0.5 EN (1V/Div) 0.0 0 20 40 60 80 100 VIN = 12V, No Load, VID = 0.8V, SET2 pin tied to 5V Time (500μs/Div) Load Current (A) Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 19 RT3606BE AXG VR Power Off from EN AXG VR OCP VAXG VAXG (300mV/Div) PGOOD (1V/Div) VAXG (200mV/Div) PGOOD (1V/Div) UG_GT1 (20V/Div) UG_GT1 (10V/Div) EN (1V/Div) VIN = 12V, No Load, VID = 0.8V I LOAD (50A/Div) Time (50μs/Div) Time (100μs/Div) AXG VR OVP AXG VR Dynamic VID Up VAXG PGOOD PGOOD (1V/Div) VAXG (500mV/Div) UG_GT1 (20V/Div) PGOOD VCLK VAXG VCLK (1V/Div) VAXG (200mV/Div) VDIO (1V/Div) LG_GT1 (5V/Div) VIN = 12V, VID = 0.9V ALERT (1V/Div) VDIO ALERT VIN = 12V, VID = 0.6V to 0.9V, Slew Rate = Slow Time (50μs/Div) Time (10μs/Div) AXG VR Dynamic VID Down AXG VR Dynamic VID Up VAXG VAXG VCLK VCLK (1V/Div) VAXG (200mV/Div) VDIO (1V/Div) ALERT (1V/Div) VDIO ALERT VIN = 12V, VID = 0.9V to 0.6V, Slew Rate = Slow Time (10μs/Div) Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 20 VCLK VCLK (1V/Div) VAXG (200mV/Div) VDIO (1V/Div) ALERT (1V/Div) VDIO ALERT VIN = 12V, VID = 0.6V to 0.9V, Slew Rate = Fast Time (10μs/Div) is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE AXG VR Mode Transient AXG VR Mode Transient VAXG VAXG VCLK VCLK VLCK (1V/Div) UGATE1 UG_GT1 (20V/Div) LG_GT1 (5V/Div) VAXG (20mV/Div) LGATE1 VIN = 12V, VID = 0.9V, PS0 to PS2, ILOAD = 1A VLCK (1V/Div) UGATE1 UG_GT1 (20V/Div) LGATE1 LG_GT1 (5V/Div) VAXG (20mV/Div) VIN = 12V, VID = 0.9V, PS2 to PS0, ILOAD = 1A Time (50μs/Div) Time (50μs/Div) AXG VR Thermal Monitioring VIMONA vs. Load Current 2.5 VIMONA (V) 2.0 VTSENA (500mV/Div) VR_HOT (1V/Div) 1.5 1.0 0.5 VIN = 12V, VTSENA Sweep from 1V to 2V Time (5ms/Div) 0.0 0 20 40 60 80 100 Load Current (A) Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 21 RT3606BE Applications information The RT3606BE includes two voltage rails : a 3/2/1 multiphase synchronous buck controller, the CORE VR, and a 2/1 multiphase synchronous buck controller, the AXG VR, designed to meet Intel IMVP8 compatible CPUs specification with a serial SVID control interface. The controller uses an ADC to implement the all kinds of settings to save total pin number for easy use and increasing PCB space utilization. RT3606BE is used in notebook, desktop computers and servers. Current feedback signal Comp signal PWM1 PWM2 General loop Function PWM3 G-NAVP TM Control Mode The RT3606BE adopts the G-NAVPTM controller, which is a current mode constant on-time control with DC offset cancellation. The approach can not only improve DC offset problem for increasing system accuracy but also provide fast transient response. When current feedback signal reaches comp signal, the RT3606BE generates an ontime width to achieve PWM modulation. Figure 1 shows the basic G-NAVPTM behavior waveforms in continuous conduct mode (CCM). Current feedback signal Comp signal PWM1 PWM2 PWM3 PWM4 Figure 1 (a). G-NAVPTM CCM behavior waveforms in CCM in Steady State Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 22 PWM4 Figure 1 (b). G-NAVPTM CCM behavior waveforms in CCM in Load Transient. Diode Emulation Mode (DEM) As well-known, the dominate power loss is switching related loss during light load, hence VR needs to be operated in asynchronous mode (or called discontinuous conduct mode, DCM) to reduce switching related loss since switching frequency is dependent on loading in the asynchronous mode. The RT3606BE can operate in diode emulation mode (DEM) to improve light load efficiency. In DEM operation, the behavior of the low side MOSFET(s) needs to work like a diode, that is, the low side MOSFET(s) will be turned on when the phase voltage is a negative value, i.e. the inductor current follows from Source to Drain of low-side MOSFET(s). And the low-side MOSFET(s) will be turned off when phase voltage is a positive value, i.e. reversed current is not allowed. Figure 2 shows the control behavior in DEM. Figure 3 shows the G-NAVPTM operation in DEM to illustrate the control behaviors. When load decreases, the discharge time of output capacitors increases during UGATE and LGATE are turned off. Hence, the switching frequency and switching loss will be reduced to improve efficiency in light load condition. is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Inductor current Phase node UGATE LGATE Figure 2. Diode Emulation Mode (DEM) in Steady State Inductor current signal Output capacitor discharge slope COMP signal UGATE LGATE Figure 3. (a) Inductor current signal Output capacitor discharge slope COMP signal UGATE LGATE Figure 3. (b) Figure 3. G-NAVPTM operation in DEM. (a) : The load is lighter, output capacitor discharge slope is smaller and the switching frequency is lower. (b) : The load is increasing, output capacitor discharge slope is increased and switching frequency is increased, too. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 23 RT3606BE Phase Interleaving Function RT3606BE is a multiphase controller, which has a phase interleaving function, 120 degree phase shift for 3-phase operation and 180 degree phase shift for 2-phase operation which can help reduce output voltage ripple and EMI problem. Function 2 <5:0> Function 1 <5:0> 80µA ADC VREF Function 1 Register R1 SETX Multi-Function Pin Setting Mechanism For reducing total pin number of package, SET [1:3] and SETA[1:2] pins adopt the multi-function pin setting mechanism in the RT3606BE. SET [1:3] and SETA[1:2] are used to set CORE VR and AXG VR, respectively. Figure 4 illustrates this operating mechanism. The voltage at VREF pin will be pulled up to 3.2V after power ready (POR). First, external voltage divider is used to set the Function1 and then internal current source 80μA is used to set the Function2. The setting voltage of Function1 and Function2 can be represented as (SETAX) Function 2 Register Function 2 <5:0> VREF Function 1 Register R1 3.2V VFunction2 80 VFunction1 R2 R1 VFunction1 3.2V VFunction1 In addition, Richtek provides a Microsoft Excel-based spreadsheet to help design the SETx and SETAx resistor network for RT3606BE. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 24 R1 SETX (SETAX) R2 3.2V R1 R2 VFunction2 80μΑ R1 R2 R1 R2 If VFunction1 and VFunction2 are determined, R1 and R2 can be calculated as follows : 80µA ADC VFunction1 All function setting will be done within 500μs after power ready (POR), and the voltage at VREF pin will fix to 0.6V after all function setting over. Function 1 <5:0> R2 Function 2 Register R2 Figure 4. Multi-Function Pin Setting Mechanism Connects a R3 resistor from SETx pin or SETAx pin to the middle node of voltage divider can help to fine tune the set voltage of Function2, which does not affect the set voltage of Function1. The Figure 5 shows the setting method and the set voltage of Function 1 and Function2 can be represented as : R2 3.2V R1 R2 80μΑ R3 R1 R2 R1 R2 VFunction1 VFunction2 By the way, SET1 and SET2 are used to set CORE rail setting and SETA1 and SETA2 are used to set AXG rail setting. The setting of SET3 is suitable for both CORE rail and AXG rail. Table 2 summarizes the overall pin setting function. Table 3 and Table 4 show the SET3 pin setting function table. is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Table 2. Pin Setting Function Table Function1 Function2 Set1 (CORE Rail) ICCMAX DVID threshold Over Current Protection (OCP) threshold Set2 (CORE Rail) DVID width Ramp Amplitude Quick Response (QR) threshold Quick Response (QR) width Set3 (CORE / AXG Rail) VR Address Enable Zero Load-line Enable Anti-overshoot Function Anti-overshoot Behavior Current Gain AI Enable PSYS Function Enable High Switching Frequency Ramp DVID Slew Rate Disable DVID compensation Decrease GTU/SA Ramp Amplitude (Only Active in max phase = 1 Application) SetA1 (AXG Rail) ICCMAXA DVID threshold Over Current Protection (OCP) threshold SetA2 (AXG Rail) DVID width Ramp Amplitude Quick Response (QR) threshold Quick Response (QR) width Table 3. SET3 Pin Setting for VR Address, Enable Zero Load-line, Enable Anti-overshoot Function, Anti-overshoot Behavior, and Current Gain AI R2 x V REF R1+R2 (VREF is 3.2V during Pin Setting) Min Typical Max Unit VSET3 = 0.000 10.948 21.896 mV 25.024 35.973 46.921 mV 50.049 60.997 71.945 mV 75.073 86.022 96.970 mV 100.098 111.046 121.994 mV 125.122 136.070 147.019 mV 150.147 161.095 172.043 mV 175.171 186.119 197.067 mV 200.196 211.144 222.092 mV 225.220 236.168 247.116 mV 250.244 261.193 272.141 mV 275.269 286.217 297.165 mV 300.293 311.241 322.190 mV 325.318 336.266 347.214 mV 350.342 361.290 372.239 mV 375.367 386.315 397.263 mV VR Address Zero Load Line ANTI_OVS AHTI_OVS Behavior AI GAIN High-Low-Floating Disable High-Floating CORE : With LL AXG : With LL High-Low-Floating Enable High-Floating CORE : 00 AXG : 01 High-Low-Floating Disable High-Floating CORE : With LL AXG : W/O LL High-Low-Floating Enable High-Floating 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 25 RT3606BE R2 x V REF R1+R2 is 3.2V during Pin Setting) Typical Max Unit VSET3 = (VREF Min 400.391 411.339 422.287 mV 425.415 436.364 447.312 mV 450.440 461.388 472.336 mV 475.464 486.413 497.361 mV 500.489 511.437 522.385 mV 525.513 536.461 547.410 mV 550.538 561.486 572.434 mV 575.562 586.510 597.458 mV 600.587 611.535 622.483 mV 625.611 636.559 647.507 mV 650.635 661.584 672.532 mV 675.660 686.608 697.556 mV 700.684 711.632 722.581 mV 725.709 736.657 747.605 mV 750.733 761.681 772.630 mV 775.758 786.706 797.654 mV 800.782 811.730 822.678 mV 825.806 836.755 847.703 mV 850.831 861.779 872.727 mV 875.855 886.804 897.752 mV 900.880 911.828 922.776 mV 925.904 936.852 947.801 mV 950.929 961.877 972.825 mV 975.953 986.901 997.849 mV 1000.978 1011.926 1022.874 mV 1026.002 1036.950 1047.898 mV 1051.026 1061.975 1072.923 mV 1076.051 1086.999 1097.947 mV 1101.075 1112.023 1122.972 mV 1126.100 1137.048 1147.996 mV 1151.124 1162.072 1173.021 mV 1176.149 1187.097 1198.045 mV VR Address Zero Load Line ANTI_OVS AHTI_OVS Behavior AI GAIN High-Low-Floating Disable High-Floating CORE : With LL AXG : With LL High-Low-Floating Enable High-Floating CORE : 00 AXG : 02 High-Low-Floating Disable High-Floating CORE : With LL AXG : W/O LL High-Low-Floating Enable High-Floating High-Low-Floating Disable High-Floating CORE : With LL AXG : With LL High-Low-Floating Enable High-Floating CORE : 01 AXG : 00 High-Low-Floating Disable High-Floating CORE : W/O LL AXG : With LL High-Low-Floating Enable High-Floating 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 26 is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE R2 x V REF R1+R2 (VREF is 3.2V during Pin Setting) Min Typical Max Unit VSET3 = 1201.173 1212.121 1223.069 mV 1226.197 1237.146 1248.094 mV 1251.222 1262.170 1273.118 mV 1276.246 1287.195 1298.143 mV 1301.271 1312.219 1323.167 mV 1326.295 1337.243 1348.192 mV 1351.320 1362.268 1373.216 mV 1376.344 1387.292 1398.240 mV 1401.369 1412.317 1423.265 mV 1426.393 1437.341 1448.289 mV 1451.417 1462.366 1473.314 mV 1476.442 1487.390 1498.338 mV 1501.466 1512.414 1523.363 mV 1526.491 1537.439 1548.387 mV 1551.515 1562.463 1573.412 mV 1576.540 1587.488 1598.436 mV VR Address Zero Load Line ANTI_OVS AHTI_OVS Behavior AI GAIN High-Low-Floating Disable High-Floating CORE : With LL AXG : With LL High-Low-Floating Enable High-Floating CORE : 01 AXG : 03 High-Low-Floating Disable High-Floating CORE : With LL AXG : W/O LL High-Low-Floating Enable High-Floating 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X 1X 2X Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 27 RT3606BE Table 4. SET3 Pin Setting for Enable PSYS Function, Enable High Switching Frequency Ramp, DVID Slew Rate, Disable DVID compensation, Decrease GTU/SA Ramp Amplitude (Only Active in max phase =1 Application) VSET3 80μA R1 R2 R1 R2 EN HIGH EN PSYS FREQ RAMP Min Typical Max Unit 0.000 10.948 21.896 mV 25.024 35.973 46.921 mV 50.049 60.997 71.945 mV 75.073 86.022 96.970 mV 100.098 111.046 121.994 mV 125.122 136.070 147.019 mV 150.147 161.095 172.043 mV 175.171 186.119 197.067 mV 200.196 211.144 222.092 mV 225.220 236.168 247.116 mV 250.244 261.193 272.141 mV 275.269 286.217 297.165 mV 300.293 311.241 322.190 mV 325.318 336.266 347.214 mV 350.342 361.290 372.239 mV 375.367 386.315 397.263 mV 400.391 411.339 422.287 mV 425.415 436.364 447.312 mV 450.440 461.388 472.336 mV 475.464 486.413 497.361 mV 500.489 511.437 522.385 mV 525.513 536.461 547.410 mV 550.538 561.486 572.434 mV 575.562 586.510 597.458 mV 600.587 611.535 622.483 mV 625.611 636.559 647.507 mV 650.635 661.584 672.532 mV 675.660 686.608 697.556 mV 700.684 711.632 722.581 mV 725.709 736.657 747.605 mV 750.733 761.681 772.630 mV 775.758 786.706 797.654 mV Disable Disable Enable 33.75mV/s Disable Enable Enable Disable Disable Disable Enable 11.25mV/s Disable Enable Enable Disable Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 28 Decrease GTU/SA Disable DIVD Ramp DVID SR Compensation (Only active as max phase number =1) Disable Disable Enable 33.75mV/s Disable Enable Enable Enable Disable Disable Enable 11.25mV/s Disable Enable Enable is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE VSET3 80μA R1 R2 R1 R2 Min Typical Max EN HIGH EN PSYS FREQ RAMP Unit 800.782 811.730 822.678 mV 825.806 836.755 847.703 mV 850.831 861.779 872.727 mV 875.855 886.804 897.752 mV 900.880 911.828 922.776 mV 925.904 936.852 947.801 mV 950.929 961.877 972.825 mV 975.953 986.901 997.849 mV 1000.978 1011.926 1022.874 mV 1026.002 1036.950 1047.898 mV 1051.026 1061.975 1072.923 mV 1076.051 1086.999 1097.947 mV 1101.075 1112.023 1122.972 mV 1126.100 1137.048 1147.996 mV 1151.124 1162.072 1173.021 mV 1176.149 1187.097 1198.045 mV 1201.173 1212.121 1223.069 mV 1226.197 1237.146 1248.094 mV 1251.222 1262.170 1273.118 mV 1276.246 1287.195 1298.143 mV 1301.271 1312.219 1323.167 mV 1326.295 1337.243 1348.192 mV 1351.320 1362.268 1373.216 mV 1376.344 1387.292 1398.240 mV 1401.369 1412.317 1423.265 mV 1426.393 1437.341 1448.289 mV 1451.417 1462.366 1473.314 mV 1476.442 1487.390 1498.338 mV 1501.466 1512.414 1523.363 mV 1526.491 1537.439 1548.387 mV 1551.515 1562.463 1573.412 mV 1576.540 1587.488 1598.436 mV Decrease GTU/SA Ramp Disable DIVD DVID SR Compensation (Only active as max phase number = 1) Disable Disable Enable 33.75mV/s Disable Enable Enable Disable Disable Disable Enable 11.25mV/s Disable Enable Enable Enable Disable Disable Enable 33.75mV/s Disable Enable Enable Enable Disable Disable Enable 11.25mV/s Disable Enable Enable Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 29 RT3606BE Function 2 <5:0> Function 1 <5:0> Anti-Overshoot and Anti-Overshoot Behavior 80µA ADC VREF Function 1 Register R1 SETX R3 (SETAX) R2 Function 2 Register Function 2 <5:0> Function 1 <5:0> 80µA ADC VREF Function 1 Register R1 SETX R3 (SETAX) R2 Function 2 Register Figure 5. Multi-Function Pin Setting Mechanism with a R3 Resistor to Fine Tune the Set Voltage of Function2 VR Rail Addressing Setting The VR address of RT3606BE can be flipped by setting the voltage on SET3 with an external voltage divider as shown in Figure 6. The voltage at VREF pin will be pulled up to 3.2V after power ready (POR) and the voltage at VREF pin will fix to 0.6V within 500μs after power ready (POR). Besides, when AXG rail address is set to 2, the boot voltage of AXG rail is 1.05V. Function 1 <5:0> VREF ADC The anti-overshoot function can be enabled or disabled by setting the voltage on SET3 with an external voltage divider. During the anti-overshoot function is triggered, the high side and low side MOS will both turn off. Therefore, the output voltage adds the forward voltage of the MOS parasitic body diode will crosses on the inductor to speed up the discharge speed and eases the overshoot magnitude. However, if the MOS driver has tri-state delay time, the performance of the anti-overshoot function will be degenerated. To prevent this phenomenon, RT3606BE provides two kinds of anti-overshoot low side MOS behavior. With the driver has tri-state delay time, the behavior of anti-overshoot can choose as high-low-floating, and with the driver without tri-state delay time, the behavior of antiovershoot can choose as high-floating. High Switching Frequency Ramp The switching frequency of RT3606BE can support from 300kHz to 1.1MHz, however, with higher switching frequency, the ramp is needed to increase simultaneously to improve the system stability and smooth the mode transient performance. As switching is higher than 550kHz, the high switching frequency ramp is suggested to be enabled. The high switching frequency ramp can be enabled or disabled by the internal current source 80μA and the parallel of the high low side resistor on SET3 pin. Decrease GTU/SA Ramp Amplitude (Only Active in max phase = 1 Application) If RT3606BE apply in GTU or SA application and the maximum phase number is 1. The ramp amplitude will automatically increase to improve the stability. This function can be disabled to improve the transient performance by the internal current source 80μA and the parallel of the high low side resistor on SET3 pin. R1 Function 1 Register SET3 R2 Figure 6. VR Rail Addressing and Zero Load-Line Setting for SET3 Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 30 is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE VDDIO Precise Reference Current Generation, IBIAS Analog circuits need very precise reference voltage/current to drive/set these analog devices. The RT3606BE provides a 2V voltage source at the IBIAS pin, and a 100kΩ resistor is required to be connected between the IBIAS pin and analog ground to generate a very precise reference current. Through this connection, the RT3606BE will generate a 20μA current from the IBIAS pin to analog ground, and this 20μA current will be mirrored inside the RT3606BE for internal use. The IBIAS pin can only be connected with a 100kΩ resistor to GND for internal analog circuit use. The resistance accuracy of this resistor is recommended to be 1% or smaller. Figure 7 shows the IBIAS setting circuit. VR_HOT 80µA - TSEN(A) + 1.092V RNTC R1 R2 Figure 8. VR_HOT Circuit Power Ready (POR) Detection Current Mirror 20µA 2V + IBIAS 100k Figure 7. IBIAS Setting Circuit TSEN, TSENA and VR_HOT The VR_HOT signal is an open-drain signal which is used for VR thermal protection. When the sensed voltage in TSEN(A) pin is less than 1.092, the VR_HOT signal will be pulled-low to notify CPU that the thermal protection needs to work. According to Intel VR definition, VR_HOT signal needs acting if VR power chain temperature exceeds 100°C. Placing an NTC thermistor at the hottest area in the VR power chain and its connection is shown in Figure 8, to design the voltage divider elements (R1, R2 and NTC) so that VTSEN(A) = 1.092V at 100°C. The resistance error of TSEN network is recommended to be 1% or smaller. VTSEN(Α) 80μΑ (R1//(R2 RNTC (100C )) Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 During start-up, the RT3606BE detects the voltage at the voltage input pins: VCC, EN and DVD. When VCC > 4.34V and VDVD > 2V, the RT3606BE recognizes the power state of system to be ready (POR = high) and waits for enable command at the EN pin. After POR = high and VEN > 0.7V, the RT3606BE will enter start-up sequence. If the voltage at any voltage pin drops below low threshold (POR = low), the RT3606BE will enter power down sequence and all the functions will be disabled. Normally, connecting system voltage VTT (1.05V) to the EN pin and power stage VIN (12V, through a voltage divider) to the DVD pin is recommended. 2ms (max) after the chip has been enabled, the SVID circuitry will be ready. All the protection latches (OVP, OCP, UVP) will be cleared only by VCC. The condition of VEN = low will not clear these latches. Figure 9 and Figure 10 show the POR detection and the timing chart for POR process, respectively. Under Voltage Lockout (UVLO) During normal operation, if the voltage at the VCC drops below POR threshold 3.95V (min) or DVD voltage drops below POR threshold 1.3V, the VR triggers UVLO. The UVLO protection forces all high-side MOSFETs and lowside MOSFETs off by shutting down internal PWM logic drivers. is a registered trademark of Richtek Technology Corporation. www.richtek.com 31 RT3606BE output voltage. Users can disable offset function by simply connecting OFSM pin to GND. Figure 11 shows a voltage divider used to set no load offset voltage. No load offset voltage setting is : VIN 5V VCC + 4.34V R1 DVD VTT 1.05V + 2V R2 EN CP POR VOFS_CORE 0.4 ( VOFSM 1.7) Chip Enable The range of VOFS_CORE is between −500mV and 590mV and the resolution is 10mV. - + 0.7V CP CP For example, a 100mV no load offset requirement, VOFSM needs to be set as 1.95V. - Figure 9. POR Detection SVID Offset Register VCC VCC DVD R1 POR SVID VID Register OFSM ADC + ++ DAC VID_REF PIN Offset Register R2 EN 2ms SVID Invalid Valid Invalid Figure 10. Timing Chart for POR Process CORE VR Phase Disable (Before POR) The number of active phases is determined by the internal circuitry that monitors the ISENxN voltages during startup. Normally, the VR operates as a 3-phase PWM controller. Pulling ISEN3N to VCC programs a 2-phase operation, and pulling ISEN2N and ISEN3N to VCC programs a 1phase operation. Before POR, VR detects whether the voltages of ISEN2N and ISEN3N are higher than “VCC− 1V” respectively to decide how many phases should be active. Phase selection is only active during POR. When POR = high, the number of active phases is determined and latched. The unused ISENxP pins are recommended to be connected to VCC and unused PWM pins can be left floating. NO Load Offset (Platform) The CORE VR features no load offset function which provides the possibility of wide range positive offset of Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 32 Figure 11. No Load Offset Circuit Switching Frequency Setting RT3606BE is one kind of constant on-time control. The patented CCRCOT (Constant Current Ripple COT) technology can generate an adaptive on-time, the on-time will vary with the input voltage and VID code to obtain a constant current ripple, so that the output voltage ripple can be controlled nearly like a constant as different input and output voltages change. For CORE VR, connect a resistor RTON between input terminal and TONSET pin to set the on-time width. RTON 4.73p 1.2 (VDAC 1.2) VIN VDAC R 4.73p VDAC TON TON (VDAC 1.2) VIN VDAC TON For better efficiency of the given load range, the maximum switching frequency is suggested to be : FSW(MAX) VID1 RON_LS,max IccTDC DCR N RLL N nLS IccTDC RON_LS,max RON_HS,max VIN(MAX) N nLS nHS IccTDC RON_LS,max TON TD TON,VAR TD N nLS Where Fsw(MAX) is the maximum switching frequency, VID1 is the typical VID of application, VIN(MAX) is the maximum application input voltage, IccTDC is the thermal design current of application, N is the phase number. The RON_HS,max is the maximum equivalent high-side RDS(ON), is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE and nHS is the number of high-side MOSFETs; RON_LS,max is the maximum equivalent low-side RDS(ON), and nLS is the number of low-side MOSFETs. TD is the summation of the high-side MOSFET delay time and the rising time, TON,VAR is the TON variation value. DCR is the inductor DCR, and RLL is the loadline setting. In addition, Richtek provides a Microsoft Excel-based spreadsheet to help design the RTON for RT3606BE. When load increases, on-time keeps constant. The offtime width will be reduced so that loading can load more power from input terminal to regulate output voltage. Hence the loading current usually increases in case the switching frequency also increases. Higher switching frequency operation can reduce power components' size and PCB space, trading off the whole efficiency since switching related switching related loss increases, vice versa. Total Current Sense Total current sense method is a patented topology, unlike conventional current sense method need a NTC resistor in per phase current loop for thermal compensation. RT3606BE adopts the total current sense method requiring only one NTC resistor for thermal compensation, and NTC resistor cost can be saved by using this method. Figure 13 shows the total current sense method which connects the resistor network between IMON pin and VREF pin to set a part of current loop gain for load line (droop) setting and set accurate over current protection. VIMON VREF = DCR REQ (IL1 +IL2 +IL3 ) RCS REQ includes a NTC resistor to compensate DCR thermal drifting for high accuracy load-line (droop). Per Phase Current Sense In the RT3606BE, the current signal is used for load-line setting and over-current protection (OCP). The inductor current sense method adopts the lossless current sensing for allowing high efficiency as illustrated in Figure 12. When inductance and DCR time constant is equal to RXCX filter network time constant, a voltage ILx x DCR will drop on Cx to generate inductor current signal. According to the Figure 12, the ISENxN is as follows : I DCR ISENxN LX RCSx Where Lx/DCR = RXCX is held. The method can get high efficiency performance, but DCR value will be drifted by temperature, a NTC resistor should add in the resistor network in the IMON pin to achieve DCR thermal compensation. In RT3606BE design, the resistance of RCSx is restricted to 680Ω; moreover, the error of RCSx is recommended to be 1% or smaller. VCORE ILx ISENxN + - LX DCR RX CX ISENxP ISENxN RCSx Figure 12. Lossless Current Sense Method Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 VCORE IL1 IMON ISEN1N + - L DCR R C ISEN1P RCS ISEN1N IL2 RNTC REQ ISEN2N + - L DCR R C ISEN2P RCS ISEN2N IL3 L DCR R C VREF ISEN3N + - ISEN3P ISEN3N RCS Figure 13. Total Current Sense Method Load-Line Setting (Droop) The G-NAVPTM topology can set load-line (droop) via the current loop and the voltage loop, the load-line is a slope between load current ICC and output voltage VCORE as shown Figure 14. Figure 15 shows the voltage control and current loop. By using the both loops, the load-line (droop) can be set easily. The load-line set equation is : 1 DCR R EQ 3 RCS AI RLL m AV R2 R1 is a registered trademark of Richtek Technology Corporation. www.richtek.com 33 RT3606BE C2 VCOEE C1 Load line slope = -RLL R2 + R1 RLL x ICC VID Figure 16. Type I Compensator ICC Differential Remote Sense Setting Figure 14. Load-Line (Droop) VCORE R2 Voltage Loop TON Generator - R1 + - + IL1.2.3 VID L 1/3 - + DCR R C ISEN[1:3]P RCS ISEN[1:3]N ISEN1N + ISEN2N + ISEN3N + RNTC IMON - The VR provides differential remote-sense inputs to eliminate the effects of voltage drops along the PC board traces, CPU internal power routes and socket contacts. The CPU contains on-die sense pins, VCC_SENSE and VSS_SENSE. Connect RGND to VSS_SENSE and connect FB to VCC_SENSE with a resistor to build the negative input path of the error amplifier as shown in Figure 17. The VDAC and the precision voltage reference are referred to RGND for accurate remote sensing. CPU VCC_SENSE VREF VOUT REQ VID RGND Compensator Design The compensator of RT3606BE doesn’t need a complex type II or type III compensator to optimize control loop performance. It can adopt a simple type I compensator (one pole, one zero) in G-NAVPTM topology to achieve constant output impedance design for Intel IMVP8 ACLL specification. The one pole one zero compensator is shown as Figure 16, the transfer function of compensator should be design as following transfer function to achieve constant output impedance, i.e. Zo(s) = load-line slope in the entire frequency range s 1 AI fsw GCON (S) RLL 1 s ESR Where AI is current loop gain, RLL is load line, fSW is switching frequency and ωESR is a pole that should be located at 1 / (COUT x ESR). Then the C1 and C2 should be designed as C1 1 R1 π fSW C2 COUT R2 CPU VSS_SENSE Figure 17. Remote Sensing Circuit Maximum Processor Current Setting, ICCMAX The maximum processor current ICCMAX can be set by the SET1 pin. ICCMAX register is set by an external voltage divider with the multi-function mechanism. The table 5 shows the ICCMAX setting on the SET1 pin. For example, ICCMAX = 80A, the VICCMAX needs to set as 0.503 typical. Additionally, VIMON − VREF needs to be set as 1.6V at ICCMAX when the maximum phase > 1. As in 1-phase application, the VIMON − VREF needs to be set as 0.4V at ICCMAX. The ICCMAX alert signal will be pulled to low level if VIMON − VREF = 1.6V (for maximum phase > 1) or VIMON − VREF = 0.4 (for 1-phase application). COUT ESR R2 Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 34 + Figure 15. Voltage Loop and Current Loop FB EA + R1 is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Table 5. SET1 Pin Setting in ICCMAX VSET1 R2 3.2V R1 R2 VSET1 ICCMAX Unit R2 3.2V R1 R2 ICCMAX Unit Min Typical Max Unit A 475.464 478.592 481.720 mV 76 A 2 A 487.977 491.105 494.233 mV 78 A mV 4 A 500.489 503.617 506.745 mV 80 A mV 6 A 513.001 516.129 519.257 mV 82 A 528.641 531.769 mV 84 A Min Typical Max Unit 0.000 3.128 6.256 mV 0 12.512 15.640 18.768 mV 25.024 28.152 31.281 37.537 40.665 43.793 50.049 53.177 56.305 mV 8 A 525.513 62.561 65.689 68.817 mV 10 A 538.025 541.153 544.282 mV 86 A 75.073 78.201 81.329 mV 12 A 550.538 553.666 556.794 mV 88 A 87.586 90.714 93.842 mV 14 A 563.050 566.178 569.306 mV 90 A 100.098 103.226 106.354 mV 16 A 575.562 578.690 581.818 mV 92 A 112.610 115.738 118.866 mV 18 A 588.074 591.202 594.330 mV 94 A 125.122 128.250 131.378 mV 20 A 600.587 603.715 606.843 mV 96 A 137.634 140.762 143.891 mV 22 A 613.099 616.227 619.355 mV 98 A 150.147 153.275 156.403 mV 24 A 625.611 628.739 631.867 mV 100 A 162.659 165.787 168.915 mV 26 A 638.123 641.251 644.379 mV 102 A 653.763 656.891 mV 104 A 175.171 178.299 181.427 mV 28 A 650.635 187.683 190.811 193.939 mV 30 A 663.148 666.276 669.404 mV 106 A 200.196 203.324 206.452 mV 32 A 675.660 678.788 681.916 mV 108 A 212.708 215.836 218.964 mV 34 A 688.172 691.300 694.428 mV 110 A 225.220 228.348 231.476 mV 36 A 700.684 703.812 706.940 mV 112 A 237.732 240.860 243.988 mV 38 A 713.196 716.325 719.453 mV 114 A 250.244 253.372 256.500 mV 40 A 725.709 728.837 731.965 mV 116 A 262.757 265.885 269.013 mV 42 A 738.221 741.349 744.477 mV 118 A 275.269 278.397 281.525 mV 44 A 750.733 753.861 756.989 mV 120 A 766.373 769.501 mV 122 A 287.781 290.909 294.037 mV 46 A 763.245 300.293 303.421 306.549 mV 48 A 775.758 778.886 782.014 mV 124 A 312.805 315.934 319.062 mV 50 A 788.270 791.398 794.526 mV 126 A 325.318 328.446 331.574 mV 52 A 800.782 803.910 807.038 mV 128 A 337.830 340.958 344.086 mV 54 A 813.294 816.422 819.550 mV 130 A 350.342 353.470 356.598 mV 56 A 825.806 828.935 832.063 mV 132 A 362.854 365.982 369.110 mV 58 A 838.319 841.447 844.575 mV 134 A 375.367 378.495 381.623 mV 60 A 850.831 853.959 857.087 mV 136 A 387.879 391.007 394.135 mV 62 A 863.343 866.471 869.599 mV 138 A 878.983 882.111 mV 140 A 400.391 403.519 406.647 mV 64 A 875.855 412.903 416.031 419.159 mV 66 A 888.368 891.496 894.624 mV 142 A 425.415 428.543 431.672 mV 68 A 900.880 904.008 907.136 mV 144 A 437.928 441.056 444.184 mV 70 A 913.392 916.520 919.648 mV 146 A 450.440 453.568 456.696 mV 72 A 925.904 929.032 932.160 mV 148 A 462.952 466.080 469.208 mV 74 A 938.416 941.544 944.673 mV 150 A Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 35 RT3606BE VSET1 R2 3.2V R1 R2 VSET1 ICCMAX Unit Min R2 3.2V R1 R2 Typical Max ICCMAX Unit Unit Min Typical Max Unit 950.929 954.057 957.185 mV 152 A 1426.393 1429.521 1432.649 mV 228 A 963.441 966.569 969.697 mV 154 A 1438.905 1442.033 1445.161 mV 230 A 975.953 979.081 982.209 mV 156 A 1451.417 1454.545 1457.674 mV 232 A 988.465 991.593 994.721 mV 158 A 1463.930 1467.058 1470.186 mV 234 A 1000.978 1004.106 1007.234 mV 160 A 1476.442 1479.570 1482.698 mV 236 A 1013.490 1016.618 1019.746 mV 162 A 1488.954 1492.082 1495.210 mV 238 A 1026.002 1029.130 1032.258 mV 164 A 1501.466 1504.594 1507.722 mV 240 A 1038.514 1041.642 1044.770 mV 166 A 1513.978 1517.107 1520.235 mV 242 A 1051.026 1054.154 1057.283 mV 168 A 1526.491 1529.619 1532.747 mV 244 A 246 A 1063.539 1066.667 1069.795 mV 170 A 1539.003 1542.131 1545.259 mV 1076.051 1079.179 1082.307 mV 172 A 1551.515 1554.643 1557.771 mV 248 A 1088.563 1091.691 1094.819 mV 174 A 1564.027 1567.155 1570.283 mV 250 A 1101.075 1104.203 1107.331 mV 176 A 1576.540 1579.668 1582.796 mV 252 A 1113.587 1119.844 mV 178 A 1589.052 1592.180 1595.308 mV 254 A 1126.100 1129.228 1132.356 mV 180 A 1138.612 1141.740 1144.868 mV 182 A 1151.124 1154.252 1157.380 mV 184 A 1163.636 1166.764 1169.892 mV 186 A 1176.149 1179.277 1182.405 mV 188 A 1188.661 1191.789 1194.917 mV 190 A 1201.173 1204.301 1207.429 mV 192 A 1213.685 1216.813 1219.941 mV 194 A 1226.197 1229.326 1232.454 mV 196 A 1238.710 1241.838 1244.966 mV 198 A 1251.222 1254.350 1257.478 mV 200 A 1263.734 1266.862 1269.990 mV 202 A 1276.246 1279.374 1282.502 mV 204 A 1288.759 1291.887 1295.015 mV 206 A 1116.716 1301.271 1304.399 1307.527 mV 208 A 1313.783 1316.911 1320.039 mV 210 A 1326.295 1329.423 1332.551 mV 212 A 1338.807 1341.935 1345.064 mV 214 A 1351.320 1354.448 1357.576 mV 216 A 1363.832 1366.960 1370.088 mV 218 A 1376.344 1379.472 1382.600 mV 220 A 1388.856 1391.984 1395.112 mV 222 A 1401.369 1404.497 1407.625 mV 224 A 1413.881 1417.009 1420.137 mV 226 A Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 36 is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Dynamic VID (DVID) Compensation When VID transition event occurs, a charger current will be generated in the loop to cause DVID performance. However, the DVID performance will be deteriorated by this induced charger current, this phenomenon is called droop effect. The droop effect is shown in Figure 18, when VID up transition occurs, the output capacitor will be charged by inductor current. Since current signal is sensed in inductor, an induced charge current will appear in control loop. The induced charge current will produce a voltage drop in R1 to cause output voltage to have a droop effect. Due to this, VID transition performance will be deteriorated. Charge current VIN L Q1 Gate Driver CO1 Q2 CO2 RESR CPU Ai Induced charge current signal VID tON Output voltage C1 R2 CCRCOT VIN C2 COMP + EA + R1 IDROOP VID VID Transition Figure 18. Droop Effect in VID transition DVID_Width (SET2) DVID_Threshold (SET1) Figure 19. Definition of Virtual Charge Current Signal RT3606BE provide a DVID compensation function. A virtual charge current signal can be established by the SET1/SET2 pins to cancel the real induced charge current signal and the virtual charge current signal is defined in Figure 19. Figure 20 shows the operation of canceling droop effect. A virtual charge current signal is established first and then VID signal plus virtual charge current signal to be generated on the FB pin. Hence, an induced charge current signal flows to R1 and is cancelled to reduce droop effect. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 37 RT3606BE Charge current VIN L Q1 Gate Driver CO1 Q2 CO2 RESR Ai Induced charge current signal Output voltage CPU C2 R2 C1 CCRCOT VIN COMP - VID + tON IDROOP EA + IDROOP has a great cancellation by adding a suitable virtual charge current R1 Virtual Charge Current + DVID Event Slew Rate Control Virtual Charge Current Generator VID VID Transition SET1 Figure 20. DVID Compensation Table 6 show the DVID_Threshold on the SET1 pin with internal 80μA current source and Table 7 describes DVID_Width settings in SET2 pin with external voltage divider. For example, 39.67mV DVID_Threshold (SR = 11.25mV/μs) / 119mV DVID_threshold (SR = 33.75mV/μs) and 36μs DVID_Width are designed (OCP sets as 110% ICCMAX, RSET sets as 133% low frequency ramp / 200% high frequency ramp). According to the Table 6 and Table 7, the DVID_Threshold set voltage should be between 0.4254V to 0.4473V and the DVID_Width set voltage should be between 1.051V to 1.073V. Please note that a high accuracy resistor is needed for this setting, < 1% error tolerance is recommended. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 38 is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Table 6. SET1 Pin Setting for DVID_Threshold VSET1 = 80Α R1 R2 R1+R2 DVID_Threshold OCP = %ICCMAX DVID SR = 11.25mV/s DVID SR = 33.75mV/s Min Typical Max Unit 0.000 10.948 21.896 mV NA 25.024 35.973 46.921 mV 110% 50.049 60.997 71.945 mV 120% 75.073 86.022 96.970 mV 100.098 111.046 121.994 mV 125.122 136.070 147.019 mV 150% 150.147 161.095 172.043 mV 160% 175.171 186.119 197.067 mV NA 200.196 211.144 222.092 mV NA 225.220 236.168 247.116 mV 110% 250.244 261.193 272.141 mV 120% 275.269 286.217 297.165 mV 300.293 311.241 322.190 mV 325.318 336.266 347.214 mV 150% 350.342 361.290 372.239 mV 160% 375.367 386.315 397.263 mV NA 400.391 411.339 422.287 mV NA 425.415 436.364 447.312 mV 110% 450.440 461.388 472.336 mV 120% 475.464 486.413 497.361 mV 500.489 511.437 522.385 mV 525.513 536.461 547.410 mV 150% 550.538 561.486 572.434 mV 160% 575.562 586.510 597.458 mV NA 600.587 611.535 622.483 mV NA 625.611 636.559 647.507 mV 110% 650.635 661.584 672.532 mV 120% 675.660 686.608 697.556 mV 700.684 711.632 722.581 mV 725.709 736.657 747.605 mV 150% 750.733 761.681 772.630 mV 160% 775.758 786.706 797.654 mV NA Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 18.33mV 29mV 39.67mV 50.33mV 55mV 87mV 119mV 151mV 130% 140% 130% 140% 130% 140% 130% 140% is a registered trademark of Richtek Technology Corporation. www.richtek.com 39 RT3606BE VSET1 = 80Α R1 R2 R1+R2 DVID_Threshold OCP = %ICCMAX Min Typical Max Unit 800.782 825.806 850.831 875.855 900.880 925.904 950.929 975.953 1000.978 1026.002 1051.026 1076.051 1101.075 1126.100 1151.124 1176.149 1201.173 1226.197 1251.222 1276.246 1301.271 1326.295 1351.320 1376.344 1401.369 1426.393 1451.417 1476.442 1501.466 1526.491 1551.515 1576.540 811.730 836.755 861.779 886.804 911.828 936.852 961.877 986.901 1011.926 1036.950 1061.975 1086.999 1112.023 1137.048 1162.072 1187.097 1212.121 1237.146 1262.170 1287.195 1312.219 1337.243 1362.268 1387.292 1412.317 1437.341 1462.366 1487.390 1512.414 1537.439 1562.463 1587.488 822.678 847.703 872.727 897.752 922.776 947.801 972.825 997.849 1022.874 1047.898 1072.923 1097.947 1122.972 1147.996 1173.021 1198.045 1223.069 1248.094 1273.118 1298.143 1323.167 1348.192 1373.216 1398.240 1423.265 1448.289 1473.314 1498.338 1523.363 1548.387 1573.412 1598.436 mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 40 DVID SR = 11.25mV/s DVID SR = 33.75mV/s 61mV 183mV 71.67mV 215mV 82.33mV 247mV 93mV 279mV NA 110% 120% 130% 140% 150% 160% NA NA 110% 120% 130% 140% 150% 160% NA NA 110% 120% 130% 140% 150% 160% NA NA 110% 120% 130% 140% 150% 160% NA is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Table 7. SET2 Pin Setting for DVID_Width R2 x VREF R1+R2 (VREF is 3.2V during Pin Setting) VSET2 = DVID_Width RSET %410k RTON Min Typical Max Unit Low FSW Ramp High FSW Ramp 0.000 25.024 50.049 75.073 100.098 125.122 150.147 175.171 200.196 225.220 250.244 275.269 300.293 325.318 350.342 375.367 400.391 425.415 450.440 475.464 500.489 525.513 550.538 575.562 600.587 625.611 650.635 675.660 700.684 725.709 750.733 775.758 800.782 825.806 850.831 875.855 900.880 925.904 950.929 975.953 10.948 35.973 60.997 86.022 111.046 136.070 161.095 186.119 211.144 236.168 261.193 286.217 311.241 336.266 361.290 386.315 411.339 436.364 461.388 486.413 511.437 536.461 561.486 586.510 611.535 636.559 661.584 686.608 711.632 736.657 761.681 786.706 811.730 836.755 861.779 886.804 911.828 936.852 961.877 986.901 21.896 46.921 71.945 96.970 121.994 147.019 172.043 197.067 222.092 247.116 272.141 297.165 322.190 347.214 372.239 397.263 422.287 447.312 472.336 497.361 522.385 547.410 572.434 597.458 622.483 647.507 672.532 697.556 722.581 747.605 772.630 797.654 822.678 847.703 872.727 897.752 922.776 947.801 972.825 997.849 mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV 100% 117% 133% 150% 167% 183% 200% 217% 100% 117% 133% 150% 167% 183% 200% 217% 100% 117% 133% 150% 167% 183% 200% 217% 100% 117% 133% 150% 167% 183% 200% 217% 100% 117% 133% 150% 167% 183% 200% 217% 133% 167% 200% 233% 267% 300% 333% 367% 133% 167% 200% 233% 267% 300% 333% 367% 133% 167% 200% 233% 267% 300% 333% 367% 133% 167% 200% 233% 267% 300% 333% 367% 133% 167% 200% 233% 267% 300% 333% 367% Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 6s 12s 18s 24s 30s is a registered trademark of Richtek Technology Corporation. www.richtek.com 41 RT3606BE R2 x VREF R1+R2 (VREF is 3.2V during Pin Setting) VSET2 = DVID_Width RSET %130k RTON Min Typical Max Unit Low FSW Ramp High FSW Ramp 1000.978 1026.002 1051.026 1076.051 1101.075 1126.100 1151.124 1176.149 1201.173 1226.197 1251.222 1276.246 1301.271 1326.295 1351.320 1376.344 1401.369 1426.393 1451.417 1476.442 1501.466 1526.491 1551.515 1576.540 1011.926 1036.950 1061.975 1086.999 1112.023 1137.048 1162.072 1187.097 1212.121 1237.146 1262.170 1287.195 1312.219 1337.243 1362.268 1387.292 1412.317 1437.341 1462.366 1487.390 1512.414 1537.439 1562.463 1587.488 1022.874 1047.898 1072.923 1097.947 1122.972 1147.996 1173.021 1198.045 1223.069 1248.094 1273.118 1298.143 1323.167 1348.192 1373.216 1398.240 1423.265 1448.289 1473.314 1498.338 1523.363 1548.387 1573.412 1598.436 mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV 100% 117% 133% 150% 167% 183% 200% 217% 100% 117% 133% 150% 167% 183% 200% 217% 100% 117% 133% 150% 167% 183% 200% 217% 133% 167% 200% 233% 267% 300% 333% 367% 133% 167% 200% 233% 267% 300% 333% 367% 133% 167% 200% 233% 267% 300% 333% 367% Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 42 36s 42s 48s is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Ramp Compensation QR Width TM The G-NAVP topology is one type of ripple based control that has fast transient response and can lower BOM cost. However, ripple based control usually has poor noise immunity. RT3606BE provides the ramp compensation to increase noise immunity and reduce jitter at the switching node. Figure 21 shows the ramp compensation. VCORE QR Threshold PWM1 Noise Margin w/o ramp compensation IMON-VREF PWM2 PWM3 VCOMP Load Figure 22. Quick Response Mechanism w/ ramp compensation IMON-VREF VCOMP Figure 21. Ramp Compensation For the RT3606BE, the ramp compensation also needs to be considered during mode transition from PS0/1 to PS2. For achieving smooth mode transition into PS2, a proper ramp compensation design is necessary. Since the ramp compensation needs to be proportional to the on-time, then RAMP is set as 133% FS 400k The output voltage signal behavior needs to be detected so that QR mechanism can be trigged. The output voltage signal is via a remote sense line to connect at VSEN pin that is shown in Figure 23. The QR mechanism needs to set QR width and QR threshold. Both definitions are shown in Figure 22. A proper QR mechanism set can meet different applications. SET2 can set QR threshold and QR width by internal current source 80μA with multi-function pin setting mechanism. QR_TH QR Pulse Generation Circuit CMP + + - Noise Margin VSEN QR_width Figure 23. Simplified QR Trigger Schematic Quick Response (QR) Mechanism When the transient load step-up becomes quite large, it is difficult for loop response to meet the energy transfer. Hence, that output voltage generate undershoot to fail specification. The RT3606BE has Quick Response (QR) mechanism being able to improve this issue. It adopts a nonlinear control mechanism which can disable interleaving function and simultaneously turn on all UGATE one pulse at instantaneous step-up transient load to restrain the output voltage drooping, Figure 22 shows the QR behavior. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 For example, QR threshold 20mV/10mV at PS0/PS1 and 2.22 x TON QR width are set. According to the Table 8, the set voltage should be between 0.4505V and 0.4723V. Please note that a high accuracy resistor is needed for this setting accuracy, < 1% error tolerance is recommended. In the Table 8, there are some “NA” marks in QRWIDTH section. It means that users should not use it to avoid the possibility of shift digital code due to tolerance concern. is a registered trademark of Richtek Technology Corporation. www.richtek.com 43 RT3606BE Table 8. SET2 Pin Setting for QR Threshold and QR Width Min Typical R1 R2 R1+R2 Max 0.000 10.948 21.896 VSET2 = 80Α QR Threshold PS0 QR Width (%TON) Unit PS1 mV NA 25.024 35.973 46.921 mV Disable 50.049 60.997 71.945 mV 222% 75.073 86.022 96.970 mV 100.098 111.046 121.994 mV 125.122 136.070 147.019 mV 88% 150.147 161.095 172.043 mV 44% 175.171 186.119 197.067 mV NA 200.196 211.144 222.092 mV NA 225.220 236.168 247.116 mV Disable 250.244 261.193 272.141 mV 222% 275.269 286.217 297.165 mV 300.293 311.241 322.190 mV 325.318 336.266 347.214 mV 88% 350.342 361.290 372.239 mV 44% 375.367 386.315 397.263 mV NA 400.391 411.339 422.287 mV NA 425.415 436.364 447.312 mV Disable 450.440 461.388 472.336 mV 222% 475.464 486.413 497.361 mV 500.489 511.437 522.385 mV 525.513 536.461 547.410 mV 88% 550.538 561.486 572.434 mV 44% 575.562 586.510 597.458 mV NA 600.587 611.535 622.483 mV NA 15mV 15mV 20mV 10mV 15mV 10mV 177.6% 133.2% 177.6% 133.2% 177.6% 133.2% 625.611 636.559 647.507 mV Disable 650.635 661.584 672.532 mV 222% 675.660 686.608 697.556 mV 700.684 711.632 722.581 mV 725.709 736.657 747.605 mV 88% 750.733 761.681 772.630 mV 44% 775.758 786.706 797.654 mV NA Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 44 20mV 15mV 177.6% 133.2% is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Min Typical R1 R2 R1+R2 Max 800.782 811.730 822.678 mV NA 825.806 836.755 847.703 mV Disable 850.831 861.779 872.727 mV 222% 875.855 886.804 897.752 mV 900.880 911.828 922.776 mV 925.904 936.852 947.801 mV 88% 950.929 961.877 972.825 mV 44% VSET2 = 80Α QR Threshold Unit PS0 25mV QR Width (%TON) PS1 10mV 177.6% 133.2% 975.953 986.901 997.849 mV NA 1000.978 1011.926 1022.874 mV NA 1026.002 1036.950 1047.898 mV Disable 1051.026 1061.975 1072.923 mV 222% 1076.051 1086.999 1097.947 mV 1101.075 1112.023 1122.972 mV 1126.100 1137.048 1147.996 mV 88% 1151.124 1162.072 1173.021 mV 44% 1176.149 1187.097 1198.045 mV NA 1201.173 1212.121 1223.069 mV NA 1226.197 1237.146 1248.094 mV Disable 1251.222 1262.170 1273.118 mV 222% 1276.246 1287.195 1298.143 mV 1301.271 1312.219 1323.167 mV 1326.295 1337.243 1348.192 mV 88% 1351.320 1362.268 1373.216 mV 44% 1376.344 1387.292 1398.240 mV NA 1401.369 1412.317 1423.265 mV NA 1426.393 1437.341 1448.289 mV Disable 1451.417 1462.366 1473.314 mV 222% 1476.442 1487.390 1498.338 mV 1501.466 1512.414 1523.363 mV 1526.491 1537.439 1548.387 mV 88% 1551.515 1562.463 1573.412 mV 44% 1576.540 1587.488 1598.436 mV NA Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 25mV 30mV 30mV 15mV 10mV 15mV 177.6% 133.2% 177.6% 133.2% 177.6% 133.2% is a registered trademark of Richtek Technology Corporation. www.richtek.com 45 RT3606BE Current Monitor, IMON Output Over-Voltage Protection RT3606BE includes a current monitor (IMON) function which can be used to detect over-current protection and the maximum processor current ICCMAX, and also sets a part of current gain in the load-line setting. It produces an analog voltage proportional to output current between the IMON and VREF pins. An OVP condition is detected when the VSEN pin is 350mV more than VID as VID > 1V. If VID < 1V, the OVP is detected when the VSEN pin is 350mV more than 1V. When OVP is detected, the high-side gate voltage UGATEx is pulled low and the low-side gate voltage LGATEx is pulled high. OVP is latched with a 0.5μs delay to prevent false trigger. Besides, the OVP function will be masked during DVID and soft-start period. After 46μs of DVID or soft-start alert is asserted, the OVP function will re-active. The calculation for IMON-VREF voltage is shown as below : VIMON VREF = DCR REQ (IL1 +IL2 +IL3 ) RCS Where IL1 + IL2 + IL3 are output current and the definitions of DCR, RCS and REQ can refer to Figure 13. Over-Current Protection The RT3606BE provides Over-Current Protection (OCP) which is set by the SET1 pin. The OCP threshold setting can refer to ICCMAX current in Table 5. For example, if ICCMAX is set as 120A, users can set voltage by using the external voltage divider on the SET1 pin as 0.754V typically. If 156A OCP (130% x ICCMAX) threshold and DVID_TH (SR = 11.25mV/μs) = 39.67mV / DVID_TH (SR = 33.75mV/μs) = 119mV will be set. According to Table 6, the set voltage should be between 0.4755V and 0.4974V. When output current is higher than the OCP threshold, OCP is latched with a 40μs delay to prevent false trigger. Besides, the OCP function is masked when dynamic VID transient occurs, and soft-start period. And the OCP function will re-active after 46μs of DVID or soft-start alert is asserted. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 46 Negative Voltage Protection Since the OVP latch continuously turns on all low side MOSFETs of the VR, the VR will suffer negative output voltage. When the VSEN detects a voltage below −0.07V after triggering OVP, the VR triggers NVP to turn off all low-side MOSFETs of the VR while the high-side MOSFETs remains off. After triggering NVP, if the output voltage rises above 0V, the OVP latch restarts to turn on all low-side MOSFETs. Therefore, the output voltage may bounce between 0V and −0.07V due to OVP latch and NVP triggering. The NVP function will be active only after OVP is triggered. is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Current Loop Design in Details IL1 VREF REQ RNTC IMON ISEN1N + - VCORE L1 DCR1 R1 C1 ISEN1P ISEN1N 680 IL2 COMP 1/3 L2 DCR2 - R2 C2 + 0.6V + ISEN2N + + - ISEN2P ISEN2N 680 IL3 L3 DCR3 R3 ISEN3N + - C3 ISEN3P ISEN3N 680 Figure 24. Current Loop Structure Figure 24 shows the whole current loop structure. The current loop plays an important role in RT3606BE that can decide ACLL performance, DCLL accuracy and ICCMAX accuracy. For ACLL performance, the correct compensator design is assumed, if RC network time constant matches inductor time constant LX / DCRX, an expected load transient waveform can be designed. If RXCX network time constant is larger than inductor time constant LX / DCRX, VCORE waveform has a sluggish droop during load transient. If RXCX network is smaller than inductor time constant LX / DCRX, a worst VCORE waveform will sag to create an undershooting to fail the specification. Figure 25 shows the variety RXCX constant corresponding to the output waveforms. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 47 RT3606BE R x Cx = VCORE Lx DCR x Where : IOUT x RLL (1) The relationship between DCR and temperature is as follows : DCR (T) = DCR (25C) 1+ 0.00393 (T - 25) IOUT VIMON REQ (T) = RIMON1 + RIMON2 / / RIMON3 + RNTC (T) Expected load transient waveform R x Cx < VCORE Lx DCR x (2) REQ (T) is the equivalent resistor of the resistor network with a NTC thermistor And the relationship between NTC and temperature is as follows : IOUT x RLL RNTC (T) = RNTC (25C) e β( 1 - 1 ) T+273 298 β is in the NTC thermistor datasheet. IOUT VIMON Undershoot created in VCORE R x Cx > VCORE Lx DCR x Step3 : Three equations and three unknowns, RIMON1, RIMON2 and RIMON3 can be found out unique solution. R (RNTCTR +RIMON3 ) RIMON1 = K TR IMON2 RIMON2 +RNTCTR +RIMON3 IOUT x RLL IOUT VIMON RIMON2 = 2 [KR3 +KR3 (RNTCTL +RNTCTR ) +RNTCTLRNTCTR ]α TL RIMON3 = RIMON2 +KR3 Where : Sluggish droop Figure 25. All Kinds of RxCx Constants α TH = K TH K TR RNTCTH RNTCTR α TL = K TL K TR RNTCTL RNTCTR KR3 = (α TH / α TL )RNTCTH RNTCTL 1 (α TH / α TL ) For DCLL performance and ICCMAX accuracy, since the copper wire of inductor has a positive temperature coefficient, when temperature goes high in the heavy load condition, DCR value goes large simultaneously. A resistor network with NTC thermistor compensation connecting between IMON and REF pins is necessary, to compensate the positive temperature coefficient of inductor DCR. The design flow is as follows : K TL = 1.6 GCS (TL) ICC-MAX K TR = Step1 : Given the three system temperature TL, TR and TH, at which are compensated. 1.6 GCS (TR) ICC-MAX K TH = 1.6 GCS (TH) ICC-MAX Step2 : Three equations can be listed as 4 DCR (TL ) iLi REQ (TL ) = 1.6 680 i=1 4 DCR (TR ) 680 iLi REQ (TR ) = 1.6 DCR (TH ) 680 iLi REQ (TH ) = 1.6 i=1 4 i=1 Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 48 is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Design Step : Current sensor adopts lossless RC filter to sense current signal in DCR. For getting an expect load transient waveform, RxCx time constant needs to match Lx / DCRx per phase. Cx = 1μF is set, then RT3606BE excel based design tool is available. Users can contact your Richtek representative to get the spreadsheet. Three main design procedures for RT3606BE design, first step is initial settings, second step is loop design and the last step is protection settings. The following design example is to explain the RT3606BE design procedure : RX IMON resistor network design : TL = 25°C, TR = 50°C and T H = 100°C are decided, NTC thermistor = 100kΩ@25°C, β = 4485 and ICCMAX = 90A. According to the sub-section “Current Loop Design in Details”, RIMON1 = 10.66kΩ, RIMON2 = 16.16kΩ and RIMON3 = 1 2.63kΩ can be decided. The REQ (25°C) = 24.91kΩ. VCORE Specification Input Voltage 12V No. of Phases 3 ICCMAX 90A ICC-DY 69A ICC-TDC 68A Load Line 2.1m Fast Slew Rate 10mV/s Max Switching Frequency 400kHz Load-line design : 2.1mΩ droop is requirement, because REQ (25°C) has decided, the voltage loop Av gain is also can be decided by following equation 1 DCR R EQ 3 RCS AI RLL m AV R2 R1 Where DCR (25°C) = 0.49mΩ, R CS = 680Ω and REQ (25°C) = 24.91kΩ. Hence the AV = R2 / R1 = 2.85 can be obtained. R1 = 10kΩ usually decided, so R2 = 28.5kΩ. In IMVP8 VRTB Guideline, the output filter requirements of VRTB specification for desktop platform are : Output Inductor : 220nH/0.49mΩ Output Bulk Capacitor : 560μF/2.5V/5mΩ (max) 4 to 5pcs Output Ceramic Capacitor : 22μF/0805 (19pcs max in cavity) Typical compensator design can use the following equations to design the C1 and C2 values C1 1 470pF R1 fSW C2 COUT ESR 98pF R2 Initial Settings : IBIAS needs to connect a 100kW resistor to ground. A voltage divider for setting DVD can choose RDVD_U = 510kW and RDVD_L = 125kW to set VDVD > 2V, RT3606BE enabled. For Intel platform, in order to induce the band width to enhance transient performance to meet Intel’ s criterion, the compensator of zero can be designed close to 1/10 of switching frequency. (1) Loop Design : On time setting : Using the specification, TON is TON RTON 4.73p 1.2 ( VDAC 1.2) 246n VIN VDAC The on time setting resistor RTON = 483kΩ Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 LX 960 0.47μF DCR X SET1 resistor network design : First the ICCMAX is design as 90A. Next, OCP threshold is designed as 1.5 x ICCMAX. Last, DVID compensation parameters need to be decided. The DVID_TH can be calculated as following equation VDVID_TH = LL COUT dVID dt is a registered trademark of Richtek Technology Corporation. www.richtek.com 49 RT3606BE Where LL is load-line, COUT is total output capacitance and dVID/dt is DVID fast slew rate. Thus VDVID_TH = 50.33mV is needed in this case. By using above information, the two equations can be listed by using multi-function pin setting mechanism R2 3.2 R1 R2 0.736 80μΑ R1 R2 R1 R2 0.566 R1 = 52kΩ, R2 = 11.2kΩ. SET2 resistor network design : 400k RAMP = 133% x = 133%, 133% is set. And 400k DVID_Width is chosen as 24μsec typical. Last, the QR mechanism parameters need to be designed first. Initial QR_TH is designed as 25mV and QR_Width is designed as 0.44 x TON. By using the information, the two equations can be listed by using multi-function pin setting mechanism R2 3.2 R1 R2 1.162 80μΑ R1 R2 R1 R2 0.661 R 1= 70.3kΩ, R2 = 18.2kΩ. (2) Protection Settings : OVP protections : When VSEN pin voltage is 350mV more than VID, the OVP will be latched. TSEN and VR_HOT design : Using the following equation to calculate related resistances for VR_HOT setting. AXG VR Phase Disable (Before POR) The number of active phases is determined by the internal circuitry that monitors the ISENAxN voltages during startup. Normally, the VR operates as a 2-phase PWM controller. Pulling ISENA2N to VCC programs a 1-phase operation. Before POR, VR detects whether the voltages of ISENA2N is higher than “VCC-1V” respectively to decide how many phases should be active. Phase selection is only active during POR. When POR = high, the number of active phases is determined and latched. The unused ISENAxP pins are recommended to be connected to VCC and unused PWM pins can be left floating. No Load Offset (Platform) The AXG VR features no load offset function which provides the possibility of wide range positive offset of output voltage. Users can disable offset function by simply connecting OFSA/PSYS pin to GND. Figure 26 shows a voltage divider used to set no load offset voltage. No load offset voltage setting is : VOFS_AXG 0.4 ( VOFSA 1.7) The range of VOFS_AXG is between −500mV and 590mV and the resolution is 10mV. For example, a 100mV no load offset requirement, VOFSA needs to be set as 1.95V. VTSEN 80μA R1// R2 RNTC (100C) Choosing R1 is open and an NTC thermistor RNTC (25°C) = 100kΩ which β = 4485. When temperature is 100°C, the RNTC (100!) = 4.85kΩ. Then R2 = 8.8kΩ can be calculated. SVID Offset Register VCC R1 SVID VID Register OFSA/PSYS ADC + ++ DAC VID_REF PIN Offset Register R2 Figure 26. No Load Offset Circuit Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 50 is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE RAXCAX filter network time constant, a voltage ILAx x DCR will drop on CAX to generate inductor current signal. According to the Figure 27, the ISENAxN is as follows : Switching Frequency Setting As mention in switching frequency setting section of CORE VR, connect a resistor RTONA between input terminal and TONSETA pin to set the on-time width. ILAX DCR RCSAx Where LAX / DCR = RAXCAX is held. The method can get ISENAxN RTONA 4.793p 1.2 (VDAC 1.2) VIN VDAC R 4.793p VDAC TONA TONA (VDAC 1.2) VIN VDAC TONA high efficiency performance, but DCR value will be drifted by temperature, a NTC resistor should add in the resistor network in the IMONA pin to achieve DCR thermal compensation. For better efficiency of the given load range, the maximum switching frequency is suggested to be : FSWA(MAX) RON_LS,max IccTDC VID1 DCR N RLL N nLS IccTDC RON_LS,max RON_HS,max IccTDC RON_LS,max VIN(MAX) TONA TD TONA,VAR N nLS nHS N nLS where FSW(MAX) is the maximum switching frequency, VID1 is the typical VID of application, VIN (MAX) is the maximum application input voltage, IccTDC is the thermal design current of application, N is the phase number. The RON_HS,max is the maximum equivalent high-side RDS(ON), and nHS is the number of high-side MOSFETs; RON_LS,max is the maximum equivalent low-side RDS(ON), and nLS is the number of low-side MOSFETs. TD is the summation of the high-side MOSFET delay time and the rising time, TON,VAR is the TON variation value. DCR is the inductor DCR, and RLL is the loadline setting. In addition, Richtek provides a Microsoft Excel-based spreadsheet to help design the RTON for RT3606BE. When load increases, on-time keeps constant. The offtime width will be reduced so that loading can load more power from input terminal to regulate output voltage. Hence the loading current usually increases in case the switching frequency also increases. Higher switching frequency operation can reduce power components' size and PCB space, trading off the whole efficiency since switching related switching related loss increases, vice versa. TD In RT3606BE design, the resistance of RCSAx is restricted to 680Ω; moreover, the error of RCSAx is recommended to be 1% or smaller. VAXG ILAx LAX DCR CAX RAX ISENAxN + - ISENAxP ISENAxN RCSAx Figure 27. Lossless Current Sense Method Total Current Sense As presented in total current sense section of AXG VR, Figure 28 shows the total current sense method which connects the resistor network between IMONA and VREF pins to set a part of current loop gain for load-line (droop) setting and set accurate over current protection. VIMONA VREF DCR REQA (ILA1 ILA2 ) RCS REQA includes a NTC resistor to compensate DCR thermal drifting for high accuracy load-line (droop). Per Phase Current Sense In the RT3606BE, the current signal is used for load-line setting and Over-Current Protection (OCP). The inductor current sense method adopts the lossless current sensing for allowing high efficiency as illustrated in the Figure 27. When inductance and DCR time constant is equal to Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 51 RT3606BE VAXG ILA1 R IMONA ISENA1N + - VAXG DCR RA2 Voltage Loop C ISENA1P ISENA1N DCR REQA R ISENA2N + - DCR C VID LA ISENA[1:2]P C RCS ISENA[1:2]N ISENA2P ISENA2N + 1/3 - R ILA2 L + - IL1.2 RCSA RNTC TON Generator - RA1 + L ISENA1N + ISENA2N RNTC + IMONA - VREF REQA RCSA Figure 30. Voltage Loop and Current Loop Compensator Design VREF Figure 28. Total Current Sense Method Load-Line (Droop) Setting The G-NAVPTM topology can set load-line (droop) via the current loop and the voltage loop, the load-line is a slope between load current ICCA and output voltage VAXG as shown Figure 29. Figure 30 shows the voltage control and current loop. By using the both loops, the load-line (droop) can be set easily. The load-line set equation is : RLLA 1 DCR R EQA 3 RCS AI m AV RA2 RA1 The compensator of RT3606BE doesn't need a complex type II or type III compensator to optimize control loop performance. It can adopt a simple type I compensator (one pole, one zero) in G-NAVPTM topology to achieve constant output impedance design for Intel IMVP8 ACLL specification. The one pole one zero compensator is shown as Figure 31, the transfer function of compensator should be design as following transfer function to achieve constant output impedance, i.e. Zo(s) = load-line slope in the entire frequency range s 1 fSWA AI GCON (S) RLLA 1 s ESRA Where AI is current loop gain, RLLA is load line for AXG VR, fSWA is switching frequency for AXG VR and ωESRA is a pole that should be located at 1 / (COUTA x ESR). Then the CA1 and CA2 should be designed as follows : 1 CA1 RA1 fSWA VAXG Load line slope = -RLLA RLLA x ICCA CA2 COUTA ESR RA2 CA2 ICCA CA1 RA2 Figure 29. Load-Line (Droop) RA1 + VID Figure 31. Type I Compensator Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 52 is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Differential Remote Sense Setting Maximum Processor Current Setting, ICCMAXA The VR provides differential remote-sense inputs to eliminate the effects of voltage drops along the PC board traces, CPU internal power routes and socket contacts. The CPU contains on-die sense pins, VCCAXG_SENSE and VSSAXG_SENSE. Connect RGNDA to VSSAXG_SENSE and connect FBA to VCCAXG_SENSE with a resistor to build the negative input path of the error amplifier as shown in Figure 32. The VDAC and the precision voltage reference are referred to RGNDA for accurate remote sensing. The maximum processor current ICCMAXA can be set by the SETA1 pin. ICCMAXA register is set by an external voltage divider with the multi-function mechanism. Table 9 shows the ICCMAXA setting on the SETA1 pin. For example, ICCMAXA = 40A, the VICCMAXA needs to set as 0.253 typical. Additionally, VIMONA − VREF needs to be set as 1.6V at ICCMAXA when the maximum phase >1. As in 1-phase application, the VIMONA − VREF needs to be set as 0.4V at ICCMAXA. The ICCMAXA alert signal will be pulled to low level. if VIMONA − VREF = 1.6V (for maximum phase >1) or VIMONA − VREF = 0.4V (for 1-phase application) CPU VCCAXG_SENSE VOUTA FBA EA + COUTA + VID R1 RGNDA R2 CPU VSSAXG_SENSE Figure 32. Remote Sensing Circuit Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 53 RT3606BE Table 9. SETA1 Pin Setting for ICCMAXA VSETA1 R2 3.2V R1 R2 ICCMAXA Unit Min Typical Max Unit 0.000 3.128 6.256 mV 0 A 12.512 15.640 18.768 mV 2 A 25.024 28.152 31.281 mV 4 A 37.537 40.665 43.793 mV 6 A 50.049 53.177 56.305 mV 8 A 62.561 65.689 68.817 mV 10 A 75.073 78.201 81.329 mV 12 A 87.586 90.714 93.842 mV 14 A 100.098 103.226 106.354 mV 16 A 112.610 115.738 118.866 mV 18 A 125.122 128.250 131.378 mV 20 A 137.634 140.762 143.891 mV 22 A 150.147 153.275 156.403 mV 24 A 162.659 165.787 168.915 mV 26 A 175.171 178.299 181.427 mV 28 A 187.683 190.811 193.939 mV 30 A 200.196 203.324 206.452 mV 32 A 212.708 215.836 218.964 mV 34 A 225.220 228.348 231.476 mV 36 A 237.732 240.860 243.988 mV 38 A 250.244 253.372 256.500 mV 40 A 262.757 265.885 269.013 mV 42 A 275.269 278.397 281.525 mV 44 A 287.781 290.909 294.037 mV 46 A 300.293 303.421 306.549 mV 48 A 312.805 315.934 319.062 mV 50 A 325.318 328.446 331.574 mV 52 A 337.830 340.958 344.086 mV 54 A 350.342 353.470 356.598 mV 56 A 362.854 365.982 369.110 mV 58 A 375.367 378.495 381.623 mV 60 A 387.879 391.007 394.135 mV 62 A 400.391 403.519 406.647 mV 64 A 412.903 416.031 419.159 mV 66 A Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 54 is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE VSETA1 R2 3.2V R1 R2 ICCMAXA Unit Min Typical Max Unit 425.415 428.543 431.672 mV 68 A 437.928 441.056 444.184 mV 70 A 450.440 453.568 456.696 mV 72 A 462.952 466.080 469.208 mV 74 A 475.464 478.592 481.720 mV 76 A 487.977 491.105 494.233 mV 78 A 500.489 503.617 506.745 mV 80 A 513.001 516.129 519.257 mV 82 A 525.513 528.641 531.769 mV 84 A 538.025 541.153 544.282 mV 86 A 550.538 553.666 556.794 mV 88 A 563.050 566.178 569.306 mV 90 A 575.562 578.690 581.818 mV 92 A 588.074 591.202 594.330 mV 94 A 600.587 603.715 606.843 mV 96 A 613.099 616.227 619.355 mV 98 A 625.611 628.739 631.867 mV 100 A 638.123 641.251 644.379 mV 102 A 650.635 653.763 656.891 mV 104 A 663.148 666.276 669.404 mV 106 A 675.660 678.788 681.916 mV 108 A 688.172 691.300 694.428 mV 110 A 700.684 703.812 706.940 mV 112 A 713.196 716.325 719.453 mV 114 A 725.709 728.837 731.965 mV 116 A 738.221 741.349 744.477 mV 118 A 750.733 753.861 756.989 mV 120 A 763.245 766.373 769.501 mV 122 A 775.758 778.886 782.014 mV 124 A 788.270 791.398 794.526 mV 126 A 800.782 803.910 807.038 mV 128 A 813.294 816.422 819.550 mV 130 A 825.806 828.935 832.063 mV 132 A 838.319 841.447 844.575 mV 134 A 850.831 853.959 857.087 mV 136 A Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 55 RT3606BE VSETA1 R2 3.2V R1 R2 ICCMAXA Unit Min Typical Max Unit 863.343 866.471 869.599 mV 138 A 875.855 878.983 882.111 mV 140 A 888.368 891.496 894.624 mV 142 A 900.880 904.008 907.136 mV 144 A 913.392 916.520 919.648 mV 146 A 925.904 929.032 932.160 mV 148 A 938.416 941.544 944.673 mV 150 A 950.929 954.057 957.185 mV 152 A 963.441 966.569 969.697 mV 154 A 975.953 979.081 982.209 mV 156 A 988.465 991.593 994.721 mV 158 A 1000.978 1004.106 1007.234 mV 160 A 1013.490 1016.618 1019.746 mV 162 A 1026.002 1029.130 1032.258 mV 164 A 1038.514 1041.642 1044.770 mV 166 A 1051.026 1054.154 1057.283 mV 168 A 1063.539 1066.667 1069.795 mV 170 A 1076.051 1079.179 1082.307 mV 172 A 1088.563 1091.691 1094.819 mV 174 A 1101.075 1104.203 1107.331 mV 176 A 1113.587 1116.716 1119.844 mV 178 A 1126.100 1129.228 1132.356 mV 180 A 1138.612 1141.740 1144.868 mV 182 A 1151.124 1154.252 1157.380 mV 184 A 1163.636 1166.764 1169.892 mV 186 A 1176.149 1179.277 1182.405 mV 188 A 1188.661 1191.789 1194.917 mV 190 A 1201.173 1204.301 1207.429 mV 192 A 1213.685 1216.813 1219.941 mV 194 A 1226.197 1229.326 1232.454 mV 196 A 1238.710 1241.838 1244.966 mV 198 A 1251.222 1254.350 1257.478 mV 200 A 1263.734 1266.862 1269.990 mV 202 A 1276.246 1279.374 1282.502 mV 204 A 1288.759 1291.887 1295.015 mV 206 A Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 56 is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE VSETA1 R2 3.2V R1 R2 ICCMAXA Unit Min Typical Max Unit 1301.271 1304.399 1307.527 mV 208 A 1313.783 1316.911 1320.039 mV 210 A 1326.295 1329.423 1332.551 mV 212 A 1338.807 1341.935 1345.064 mV 214 A 1351.320 1354.448 1357.576 mV 216 A 1363.832 1366.960 1370.088 mV 218 A 1376.344 1379.472 1382.600 mV 220 A 1388.856 1391.984 1395.112 mV 222 A 1401.369 1404.497 1407.625 mV 224 A 1413.881 1417.009 1420.137 mV 226 A 1426.393 1429.521 1432.649 mV 228 A 1438.905 1442.033 1445.161 mV 230 A 1451.417 1454.545 1457.674 mV 232 A 1463.930 1467.058 1470.186 mV 234 A 1476.442 1479.570 1482.698 mV 236 A 1488.954 1492.082 1495.210 mV 238 A 1501.466 1504.594 1507.722 mV 240 A 1513.978 1517.107 1520.235 mV 242 A 1526.491 1529.619 1532.747 mV 244 A 1539.003 1542.131 1545.259 mV 246 A 1551.515 1554.643 1557.771 mV 248 A 1564.027 1567.155 1570.283 mV 250 A 1576.540 1579.668 1582.796 mV 252 A 1589.052 1592.180 1595.308 mV 254 A Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 57 RT3606BE Dynamic VID (DVID) Compensation for AXG VR As mention in DVID compensation section of CORE VR, the RT3606BE also provide a DVID compensation function for AXG VR. A virtual charge current signal can be established by SETA1 and SETA2 pins to cancel the real induced charge current signal. Table 10 show the DVID_Threshold in SETA1 pin with internal 80μA current source and Table 11 describes DVID_Width settings on SETA2 pin with external voltage divider. For example, 39.67mV DVID_Threshold (SR = 11.25mV/μs) / 119mV DVID_Threshold (SR = 33.75mV/μs) and 36μs DVID_Width are designed (OCPA sets as 110% ICCMAXA, RSETA sets as 133% low frequency ramp / 200% high frequency ramp). According to the Table 10 and Table 11, the DVID_Threshold set voltage should be between 0.4254V to 0.4473V and the DVID_Width set voltage should be between 1.051V to 1.073V. Please note that a high accuracy resistor is needed for this setting, < 1% error tolerance is recommended. Table 10. SETA1 Pin Setting for DVID_Threshold VSETA1 = 80Α R1 R2 R1+R2 DVID_Threshold OCP = %ICCMAX Min Typical Max Unit 0.000 25.024 50.049 75.073 10.948 35.973 60.997 86.022 21.896 46.921 71.945 96.970 mV mV mV mV 100.098 125.122 150.147 175.171 200.196 225.220 111.046 136.070 161.095 186.119 211.144 236.168 121.994 147.019 172.043 197.067 222.092 247.116 mV mV mV mV mV mV 250.244 275.269 261.193 286.217 272.141 297.165 mV mV 300.293 325.318 350.342 375.367 400.391 425.415 450.440 475.464 311.241 336.266 361.290 386.315 411.339 436.364 461.388 486.413 322.190 347.214 372.239 397.263 422.287 447.312 472.336 497.361 mV mV mV mV mV mV mV mV 500.489 511.437 522.385 mV 525.513 550.538 575.562 536.461 561.486 586.510 547.410 572.434 597.458 mV mV mV Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 58 DVID SR DVID SR = 11.25mV/s = 33.75mV/s 18.33mV 55mV 29mV 87mV 39.67mV 119mV NA 110% 120% 130% 140% 150% 160% NA NA 110% 120% 130% 140% 150% 160% NA NA 110% 120% 130% 140% 150% 160% NA is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE VSETA1 = 80Α R1 R2 R1+R2 DVID_Threshold DVID SR DVID SR = 11.25mV/s = 33.75mV/s OCP = %ICCMAX Min Typical Max Unit 600.587 611.535 622.483 mV NA 625.611 636.559 647.507 mV 110% 650.635 661.584 672.532 mV 120% 675.660 686.608 697.556 mV 700.684 711.632 722.581 mV 725.709 736.657 747.605 mV 150% 750.733 761.681 772.630 mV 160% 775.758 800.782 825.806 850.831 875.855 900.880 925.904 950.929 975.953 1000.978 1026.002 1051.026 1076.051 1101.075 1126.100 1151.124 1176.149 1201.173 1226.197 1251.222 1276.246 1301.271 1326.295 1351.320 1376.344 1401.369 1426.393 1451.417 1476.442 1501.466 1526.491 1551.515 1576.540 786.706 811.730 836.755 861.779 886.804 911.828 936.852 961.877 986.901 1011.926 1036.950 1061.975 1086.999 1112.023 1137.048 1162.072 1187.097 1212.121 1237.146 1262.170 1287.195 1312.219 1337.243 1362.268 1387.292 1412.317 1437.341 1462.366 1487.390 1512.414 1537.439 1562.463 1587.488 797.654 822.678 847.703 872.727 897.752 922.776 947.801 972.825 997.849 1022.874 1047.898 1072.923 1097.947 1122.972 1147.996 1173.021 1198.045 1223.069 1248.094 1273.118 1298.143 1323.167 1348.192 1373.216 1398.240 1423.265 1448.289 1473.314 1498.338 1523.363 1548.387 1573.412 1598.436 mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV NA NA 110% 120% 130% 140% 150% 160% NA NA 110% 120% 130% 140% 150% 160% NA NA 110% 120% 130% 140% 150% 160% NA NA 110% 120% 130% 140% 150% 160% NA Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 50.33mV 151mV 61mV 183mV 71.67mV 215mV 82.33mV 247mV 93mV 279mV 130% 140% is a registered trademark of Richtek Technology Corporation. www.richtek.com 59 RT3606BE Table 11. SETA2 Pin Setting for DVID_Width R2 x VREF R1+R2 (VREF is 3.2V during Pin Setting) VSETA2 = DVID_Width RSET %410k RTON Low FSW Ramp High FSW Ramp mV 100% 117% 133% 167% 71.945 mV 133% 200% 86.022 96.970 mV 150% 233% 100.098 111.046 121.994 mV 167% 267% 125.122 136.070 147.019 mV 183% 300% 333% Min Typical Max Unit 0.000 10.948 21.896 mV 25.024 35.973 46.921 50.049 60.997 75.073 6s 150.147 161.095 172.043 mV 200% 175.171 186.119 197.067 mV 217% 367% 200.196 211.144 222.092 mV 225.220 236.168 247.116 mV 100% 117% 133% 167% 250.244 261.193 272.141 mV 133% 200% 275.269 286.217 297.165 mV 150% 233% 300.293 311.241 322.190 mV 167% 267% 325.318 336.266 347.214 mV 183% 300% 350.342 361.290 372.239 mV 200% 333% 375.367 386.315 397.263 mV 217% 367% 400.391 411.339 422.287 mV 425.415 436.364 447.312 mV 100% 117% 133% 167% 450.440 461.388 472.336 mV 133% 200% 475.464 486.413 497.361 mV 150% 233% 500.489 511.437 522.385 mV 167% 267% 525.513 536.461 547.410 mV 183% 300% 550.538 561.486 572.434 mV 200% 333% 575.562 586.510 597.458 mV 217% 367% 600.587 611.535 622.483 mV 625.611 636.559 647.507 mV 100% 117% 133% 167% 650.635 661.584 672.532 mV 133% 200% 675.660 686.608 697.556 mV 150% 233% 700.684 711.632 722.581 mV 167% 267% 300% 12s 18s 24s 725.709 736.657 747.605 mV 183% 750.733 761.681 772.630 mV 200% 333% 775.758 786.706 797.654 mV 217% 367% Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 60 is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE R2 x VREF R1+R2 is 3.2V during Pin Setting) VSETA2 = (VREF DVID_Width RSET %410k RTON Low FSW Ramp High FSW Ramp mV 100% 117% 133% 167% mV 133% 200% 150% 233% 167% 267% Min Typical Max Unit 800.782 811.730 822.678 mV 825.806 836.755 847.703 850.831 861.779 872.727 875.855 886.804 897.752 mV 900.880 911.828 922.776 mV 925.904 936.852 947.801 mV 183% 300% 950.929 961.877 972.825 mV 200% 333% 975.953 986.901 997.849 mV 217% 367% 1000.978 1011.926 1022.874 mV 1026.002 1036.950 1047.898 mV 100% 117% 133% 167% 1051.026 1061.975 1072.923 mV 133% 200% 1076.051 1086.999 1097.947 mV 150% 233% 1101.075 1112.023 1122.972 mV 167% 267% 1126.100 1137.048 1147.996 mV 183% 300% 333% 30s 36s 1151.124 1162.072 1173.021 mV 200% 1176.149 1187.097 1198.045 mV 217% 367% 1201.173 1212.121 1223.069 mV 1226.197 1237.146 1248.094 mV 100% 117% 133% 167% 1251.222 1262.170 1273.118 mV 133% 200% 1276.246 1287.195 1298.143 mV 150% 233% 1301.271 1312.219 1323.167 mV 167% 267% 1326.295 1337.243 1348.192 mV 183% 300% 1351.320 1362.268 1373.216 mV 200% 333% 1376.344 1387.292 1398.240 mV 217% 367% 1401.369 1412.317 1423.265 mV 1426.393 1437.341 1448.289 mV 100% 117% 133% 167% 1451.417 1462.366 1473.314 mV 133% 200% 1476.442 1487.390 1498.338 mV 150% 233% 1501.466 1512.414 1523.363 mV 167% 267% 1526.491 1537.439 1548.387 mV 183% 300% 1551.515 1562.463 1573.412 mV 200% 333% 1576.540 1587.488 1598.436 mV 217% 367% Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 42s 48s is a registered trademark of Richtek Technology Corporation. www.richtek.com 61 RT3606BE Ramp Compensation Quick Response (QR) Mechanism G-NAVPTM topology is one type of ripple based control that has fast transient response and can lower BOM cost. However, ripple based control usually has poor noise immunity. The RT3606BE provides the ramp compensation in AXG VR to increase noise immunity and reduce jitter at the switching node. Figure 33 shows the ramp compensation. As presented in QR mechanism section of CORE VR, RT3606BE also supports QR function in AXG VR. The output voltage signal behavior needs to be detected so that QR mechanism can be trigged. The output voltage signal is via a remote sense line to connect at VSENA pin that is shown in Figure 34. The QR mechanism needs to set QR width and QR threshold. Both definitions are shown in Figure 22. A proper QR mechanism set can meet different applications. SETA2 can set QR threshold and QR width by internal current source 80μA with multifunction pin setting mechanism. Noise Margin w/o ramp compensation IMONA-VREF VCOMPA Noise Margin w/ ramp compensation IMONA-VREF CMP + + - QR_TH QR Pulse Generation Circuit VSENA QR_width Figure 34. Simplified QR Trigger Schematic VCOMPA Figure 33. Ramp Compensation For the RT3606BE, the ramp compensation also needs to be considered during mode transition from PS0/1 to PS2. For achieving smooth mode transition into PS2, a proper ramp compensation design is necessary. Since the ramp compensation needs to be proportional to the on-time, then RAMP is set as F 133% S 400k Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 62 For example, QR threshold 20mV/10mV at PS0/PS1 and 2.22 x TON QR width are set. According to the Table 12, the set voltage should be between 0.4504V and 0.4723V. Please note that a high accuracy resistor is needed for this setting accuracy, < 1% error tolerance is recommended. In the Table 12, there are some “NA”marks in QRWIDTH section. It means that user should not use it to avoid the possibility of shift digital code due to tolerance concern. is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Table 12. SETA2 Pin Setting for QR Threshold and QR Width Min 0.000 Typical 10.948 R1 R2 R1+R2 Max 21.896 25.024 50.049 35.973 60.997 46.921 71.945 mV mV 75.073 100.098 125.122 150.147 175.171 200.196 225.220 250.244 86.022 111.046 136.070 161.095 186.119 211.144 236.168 261.193 96.970 121.994 147.019 172.043 197.067 222.092 247.116 272.141 mV mV mV mV mV mV mV mV 275.269 300.293 325.318 350.342 375.367 400.391 425.415 450.440 286.217 311.241 336.266 361.290 386.315 411.339 436.364 461.388 297.165 322.190 347.214 372.239 397.263 422.287 447.312 472.336 mV mV mV mV mV mV mV mV 475.464 500.489 486.413 511.437 497.361 522.385 mV mV 525.513 550.538 575.562 600.587 625.611 650.635 536.461 561.486 586.510 611.535 636.559 661.584 547.410 572.434 597.458 622.483 647.507 672.532 mV mV mV mV mV mV 675.660 700.684 725.709 686.608 711.632 736.657 697.556 722.581 747.605 mV mV mV 750.733 775.758 761.681 786.706 772.630 797.654 mV mV VSETA2 = 80Α Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 QR Threshold Unit mV PS0 QR Width (%TON) PS1 NA Disable 222% 15mV 10mV 15mV 15mV 20mV 10mV 177.6% 133.2% 88% 44% NA NA Disable 222% 177.6% 133.2% 88% 44% NA NA Disable 222% 177.6% 133.2% 88% 44% NA NA Disable 222% 20mV 15mV 177.6% 133.2% 88% 44% NA is a registered trademark of Richtek Technology Corporation. www.richtek.com 63 RT3606BE VSETA2 = 80Α R1 R2 R1+R2 QR Threshold PS0 QR Width (%TON) Min Typical Max Unit 800.782 825.806 811.730 836.755 822.678 847.703 mV mV NA Disable 850.831 861.779 872.727 mV 222% 875.855 886.804 897.752 mV 900.880 911.828 922.776 mV 925.904 950.929 936.852 961.877 947.801 972.825 mV mV 88% 44% 25mV PS1 10mV 177.6% 133.2% 975.953 986.901 997.849 mV NA 1000.978 1026.002 1011.926 1036.950 1022.874 1047.898 mV mV NA Disable 1051.026 1061.975 1072.923 mV 222% 1076.051 1101.075 1086.999 1112.023 1097.947 1122.972 mV mV 1126.100 1137.048 1147.996 mV 88% 1151.124 1176.149 1162.072 1187.097 1173.021 1198.045 mV mV 44% NA 1201.173 1212.121 1223.069 mV NA 1226.197 1251.222 1237.146 1262.170 1248.094 1273.118 mV mV Disable 222% 1276.246 1287.195 1298.143 mV 1301.271 1326.295 1312.219 1337.243 1323.167 1348.192 mV mV 1351.320 1362.268 1373.216 mV 44% 1376.344 1401.369 1387.292 1412.317 1398.240 1423.265 mV mV NA NA 1426.393 1437.341 1448.289 mV Disable 1451.417 1462.366 1473.314 mV 222% 1476.442 1487.390 1498.338 mV 1501.466 1512.414 1523.363 mV 1526.491 1551.515 1537.439 1562.463 1548.387 1573.412 mV mV 88% 44% 1576.540 1587.488 1598.436 mV NA Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 64 25mV 30mV 30mV 15mV 10mV 15mV 177.6% 133.2% 177.6% 133.2% 88% 177.6% 133.2% is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Current Monitor, IMONA Output Over-Voltage Protection RT3606BE includes a current monitor (IMONA) function which can be used to detect over current protection and the maximum processor current ICCMAXA, and also sets a part of current gain in the load-line setting. It produces an analog voltage proportional to output current between the IMONA and VREF pins. An OVP condition is detected when the VSENA pin is 150mV more than VID. as VID > 1V. If VID < 1V, the OVP is detected when the VSEN pin is 350mV more than 1V. When OVP is detected, the high-side gate voltage UGATEAx is pulled low and the low-side gate voltage LGATEAx is pulled high, OVP is latched with a 0.5μs delay to prevent false trigger. Besides, the OVP function will be masked during DVID and soft-start period. After 46μs of DVID or soft-start alert is asserted, the OVP function will re-active. The calculation for IMONA-VREF voltage is shown as below : VIMONA VREF DCR REQA (ILA1 ILA2 ) RCSA Where ILA1 + ILA2 are output current and the definitions of DCR, RCSA and REQA can refer to Figure 28. Over Current Protection RT3606BE provides the Over Current Protection (OCP) which is set by the SETA1 pin in AXG VR. The OCP threshold setting can refer to ICCMAXA current in the Table 9. For example, if ICCMAXA is set as 120A, user can set voltage by using the external voltage divider on SETA1 pin as 0.759V typically. If 156A OCP (130% x ICCMAX) threshold and DVID_TH (SR = 11.25mV/μs) = 39.67mV / DVID_TH (SR = 33.75mV/μs) = 119mV will be set. According to Table 10, the set voltage should be between 0.4755V and 0.4974V. When output current is higher than the OCP threshold, OCP is latched with a 40μs delay to prevent false trigger. Besides, the OCP function is masked when dynamic VID transient occurs, and soft-start period. And the OCP function will re-active after 46μs of DVID or soft-start alert is asserted. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 Negative Voltage Protection Since the OVP latch continuously turns on all low-side MOSFETs of the VR, the VR will suffer negative output voltage. When the VSENA detects a voltage below −0.07V after triggering OVP, the VR triggers NVP to turn off all low-side MOSFETs of the VR while the high-side MOSFETs remain off. After triggering NVP, if the output voltage rises above 0V, the OVP latch restarts to turn on all low-side MOSFETs. Therefore, the output voltage may bounce between 0V and −0.07V due to OVP latch and NVP triggering. The NVP function will be active only after OVP is triggered. is a registered trademark of Richtek Technology Corporation. www.richtek.com 65 RT3606BE Current Loop Design in Details VAXG ILA1 LA1 VREF REQA RNTC R1 IMONA ISENA1N + - DCR1 C1 ISENA1P 680 ISENA1N ILA2 COMPA 1/3 LA2 - R2 + 0.6V + ISENA2N + + - DCR2 C2 ISENA2P ISENA2N 680 Figure 35. Current Loop Structure Figure 35 shows the whole current loop structure. The current loop plays an important role in the RT3606BE that can decide ACLL performance, DCLL accuracy and ICCMAXA accuracy. For ACLL performance, the correct compensator design is assumed, if RC network time constant matches inductor time constant LAX / DCRX, an expected load transient waveform can be designed. If RXCX network time constant is larger than inductor time constant LAX / DCRX, VAXG waveform has a sluggish droop during load transient. If RXCX network is smaller than inductor time constant LAX /DCRX, a worst VAXG waveform will sag to create an undershooting to fail the specification. For DCLL performance and ICCMAXA accuracy, since the copper wire of inductor has a positive temperature coefficient, when temperature goes high in the heavy load condition, DCR value goes large simultaneously. A resistor network with NTC thermistor compensation connecting between the IMONA to REF pins is necessary, to compensate the positive temperature coefficient of inductor DCR. The design flow is as presented in current loop design in details of CORE VR. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 66 Design Step The RT3606BE excel based design tool is available. Users can contact your Richtek representative to get the spreadsheet. Three main design procedures for RT3606BE design, first step is initial settings, second step is loop design and the last step is protection settings. The following design example is to explain RT3606BE design procedure : VAXG Specification Input Voltage 12V No. of Phases 2 Vboot 0.9V ICCMAX 76A ICC-DY 42A ICC-TDC 45A Load Line 3.1m Fast Slew Rate 10mV/s Max Switching Frequency 400kHz is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE In IMVP8 VRTB Guideline, the output filter requirements of VRTB specification for desktop platform are : 1 87pF R1 fSWA C ESR C2 OUT 115pF R2 Output Inductor : 220nH/0.49mΩ C2 Output Bulk Capacitor : 470μF/2.5V/7mΩ (max) 4 to 5pcs Output Ceramic Capacitor : 22μF/0805 (14pcs max in cavity) For Intel platform, in order to induce the band width to enhance transient performance to meet Intel’s criterion, the compensator of zero can be designed close to 1/10 of switching frequency. (1) Initial Settings : RT3606BE initial voltage is 0.9V (2) Loop Design : On time setting : Using the specification, TONA is TONA = TONA 4.73p 1.2 ( VDAC < 1.2) = 204n VIN -VDAC The on time setting resistor RTONA = 400kΩ Where LL is load line, COUT is total output capacitance and dVID/dt is DVID fast slew rate. Thus VDVID_TH = 39.67mV is needed in this case. By using above information, the two equations can be listed by using multi-function pin setting mechanism LX 780 0.47 F DCR X IMONA resistor network design : TL = 25°C, TR = 50°C and T H = 100°C are decided, NTC thermistor = 100kΩ@25°C, β = 4485 and ICCMAXA = 76A. According to the sub-section “Current Loop Design in Details”, RIMONA1 = 10.6kΩ, RIMONA2 = 15.05kΩ and RIMONA3 = 11.46kΩ can be decided. The REQA (25°C) = 23.86kΩ. Load-line design : 2.1mΩ droop is requirement, because REQA(25°C) has decided, the voltage loop Av gain is also can be decided by following equation 1 DCR R EQA 3 RCSA AI RLLA m AV R2 R1 Where DCR (25°C) = 0.6mΩ, R CS = 680Ω and REQA (25°C) = 23.86kΩ. Hence the AV = R2 / R1 = 2.26 can be obtained. R = 10kΩ usually is decided, so R2 = 22.6kΩ. SETA1 resistor network design : First the ICCMAX is design as 76A. Next, OCP threshold is designed as 1.5 x ICCMAX. Last, DVID compensation parameters need to be decided. The DVID_TH can be calculated as following equation VDVID_TH = LL COUT dVID dt Current sensor adopts lossless RC filter to sense current signal in DCR. For getting an expect load transient waveform, RxCx time constant needs to match Lx / DCRx per phase. Cx = 0.47μF is set, then RX Typical compensator design can use the following equations to design the C1 and C2 values R2 3.2 R1 R2 0.536 80 Α R1 R2 R1 R2 0.479 R1 = 44.84kΩ, R2 = 7.89kΩ. SETA2 resistor network design : 400k RAMP = 133% x = 133%, 133% is set. And 400k DVID_Width is chosen as 24μsec typical. Last, the QR mechanism parameters need to be designed first. Initial QR_TH is designed as 20mV and QR_Width is designed as 0.44 x TON. By using the information, the two equations can be listed by using multi-function pin setting mechanism R2 3.2 R1 R2 0.761 80 Α R1 R2 R1 R2 0.661 R1 = 46.05kΩ, R2 = 12kΩ. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 67 RT3606BE (4) Addressing Settings : (3) Protection Settings : OVP protections : When the VSENA pin voltage is 350mV more than VID, the OVP will be latched. When VSENA pin voltage is 350mV less than VID, the UVP will be latched. TSEN and VR_HOT design : Using the following equation to calculate related resistances for VR_HOT setting. VTSENA 80 A RA1// RA2 R ANTC (100C) SET3 resistor network design : Based on table13 information, the two equations can be listed as following R2 3.2V R1 R2 R1 R2 0.261 80Α R1 R2 R1 = 171.3kΩ, R2 = 3.32kΩ. 0.060 Table 13. SET3 design information Function1 Main address:00 Auxiliary address:01 Main and auxiliary rail disable zero load Anti-oversh oot function disable Anti-overshoot PWM behavior is high to tri stage. AI gain is 1. Function2 PSYS function disable Select low frequency ramp table DVID slew rate is 11.25mV/s Enable DVID compensation function When 1 phase application, ramp increase. Thermal Considerations PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN-60L 7x7 package, the thermal resistance, θJA, is 25.5°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : resistance, θJA. The derating curve in Figure 36 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. 4.5 Maximum Power Dissipation (W)1 For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : Four-Layer PCB 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 36. Derating Curve of Maximum Power Dissipation PD(MAX) = (125°C − 25°C) / (25.5°C/W) = 3.92W for WQFN-60L 7x7 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 68 is a registered trademark of Richtek Technology Corporation. DS3606BE-00 April 2016 RT3606BE Outline Dimension 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min. Max. Min. Max. A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 5.950 6.050 0.234 0.238 Option 1 4.250 4.350 0.167 0.171 Option 2 4.350 4.450 0.171 0.175 5.950 6.050 0.234 0.238 Option 1 4.250 4.350 0.167 0.171 Option 2 4.350 4.450 0.171 0.175 D2 E E2 e L 0.400 0.350 0.016 0.450 0.014 0.018 W-Type 48L QFN 6x6 Package Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3606BE-00 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 69 RT3606BE Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 70 DS3606BE-00 April 2016