DS2776 01

®
RT2776
Dual Channel PWM Controller with 3/2/1 Phase for CORE VR
and Single Phase for AXG VR
General Description
Features
The RT2776 is a VR12/IMVP7 compliant CPU power
controller which includes two channels : a 3/2/1 phase
with 3 integrated drivers synchronous Buck controller for
the CORE VR, and a single phase Buck controller for the
AXG VR. The RT2776 adopts G-NAVPTM (Green Native
Adaptive Voltage Positioning), which is Richtek's
proprietary topology derived from a finite DC gain
compensator with current mode control, making it an easy
setting PWM controller, meeting all Intel CPU
requirements of AVP. Based on the G-NAVPTM topology,
the RT2776 also features a quick response mechanism
for optimizing AVP performance during load transient. The
RT2776 supports mode transition function with various
operating states. A serial VID (SVID) interface is built in
the RT2776 to communicate with Intel VR12/IMVP7
compliant CPU. The RT2776 supports VID on-the-fly
function with three different slew rates : Fast, Slow and
Decay. By utilizing the G-NAVPTM topology, the operating
z
frequency of the RT2776 varies with VID, load and input
voltage to further enhance the efficiency even in CCM.
The built-in high accuracy DAC converts the SVID code
ranging from 0.25V to 1.52V with 5mV per step. The
RT2776 integrates a high accuracy ADC for platform setting
functions, such as no-load offset or over current level.
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
VR12/IMVP7 Compatible Power Management
3/2/1 Phase for CORE VR and Single Phase for AXG
VR
3 Embedded MOSFET Drivers at the CORE VR
G-NAVPTM Topology
Serial VID Interface
0.5% DAC Accuracy
Differential Remote Voltage Sensing
Built-in ADC for Platform Programming
Accurate Current Balance
System Thermal Compensated AVP
Diode Emulation Mode at Light Load Condition for
Single Phase
Fast Transient Response
1.1VINITIAL / 0.0VINITIAL for both Rails at Startup
Power Ready Indicator
Thermal Throttling
Current Monitor Output
OVP, UVP, OCP, OTP, UVLO
External No-load Offset Setting for both Rails
DVID Enhancement
56-Lead WQFN Package
RoHS Compliant and Halogen Free
Applications
z
VR12/IMVP7 Intel Core Supply
Notebook/ Desktop Computer/ Servers Multi-phase CPU
Core Supply
z
AVP Step-Down Converter
z
Simplified Application Circuit
To CPU
RT2776
VR_RDY PHASE1
MOSFET
VRHOT
PHASE2
MOSFET
VCLK
PHASE3
MOSFET
PWMA
RT9612
VDIO
ALERT
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS2776-01 January 2014
VCORE
MOSFET
VAXG
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT2776
Pin Configurations
Ordering Information
(TOP VIEW)
BOOT2
UGATE2
PHASE2
LGATE2
BOOT1
UGATE1
PHASE1
LGATE1
VCC12
LGATE3
PHASE3
UGATE3
BOOT3
TONSET
RT2776
Package Type
QW : WQFN-56L 7x7 (W-Type)
Note :
Richtek products are :
`
RoHS compliant and compatible with the current
requirements of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.
56 55 54 53 52 51 50 49 48 47 46 45 44 43
QRSET
DVIDA
ISEN2P
ISEN2N
ISEN1N
ISEN1P
ISEN3P
ISEN3N
RSET
COMP
FB
RGND
DVID
OFS
1
42
2
41
3
40
4
39
5
38
6
37
7
36
GND
8
35
34
9
33
10
57
11
12
32
31
13
30
14
29
TONSETA
VRHOT
TSEN
TSENA
OCSET
OCSETA
VCC5
VR_RDY
EN
PWMA
QRSETA
ISENAP
ISENAN
COMPA
15 16 17 18 19 20 21 22 23 24 25 26 27 28
IMON
IMONFB
VCLK
VDIO
ALERT
IBIAS
TEMPMAX
ICCMAX
ICCMAXA
IMONFBA
IMONA
OFSA
RGNDA
FBA
Lead Plating System
G : Green (Halogen Free and Pb Free)
WQFN-56L 7x7
Functional Pin Description
Pin No.
Pin Name
1
QRSET
2
DVIDA
Pin Function
Multi-phase CORE VR channel quick response time setting and initial voltage
(VINITIAL) setting.
Place a resistor and a capacitor from this pin to GND to enhance DVID
performance. Short this pin to GND if not use.
5, 4, 8
ISEN [1:3] N
Negative Current Sense Pin of Phase 1, 2, 3 for CORE VR.
6, 3, 7
ISEN [1:3] P
Positive Current Sense Pin of Phase 1, 2, 3 for CORE VR.
9
RSET
10
COMP
11
FB
12
RGND
13
DVID
14
OFS
15
IMON
16
IMONFB
Multi-Phase CORE VR Ramp Setting. This is used to set the multi-phase
CORE VR loop external ramp slope.
Multi-Phase CORE VR Compensation Node. This pin is the output node of the
error amplifier.
Multi-Phase CORE VR Feedback Input. This is the negative input node of the
error amplifier.
Return Ground for Multi-Phase CORE VR. This pin is the negative node of the
differential remote voltage sensing.
Place a Resistor and a Capacitor from this Pin to GND to enhance DVID
Performance. Short this pin to GND if not use.
Output Voltage Offset Setting.
Current Monitor Output. This pin outputs a voltage proportional to the output
current.
Current Monitor Output Gain External Setting. Connect this pin with one
resistor to CPU VCC_SENSE while IMON pin is connected to ground with one
another resistor. The current monitor output gain can be set by the ratio of
these two resistors.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
2
is a registered trademark of Richtek Technology Corporation.
DS2776-01 January 2014
RT2776
Pin No.
Pin Name
Pin Function
17
VCLK
Synchronous Clock from the CPU.
18
VDIO
Controller and CPU Data Transmission Interface.
19
ALERT
SVID Alert Pin. (Active Low)
20
IBIAS
Internal Bias Current Setting. Connecting this pin to GND by a resistor can set
the internal current.
21
TEMPMAX
ADC Input for Multi-Phase CORE VR Maximum Temperature Setting.
22
ICCMAX
ADC Input for Multi-Phase CORE VR Maximum Current Setting.
23
ICCMAXA
ADC Input for Single Phase AXG VR Maximum Current Setting.
Single Phase AXG VR Current Monitor Output Gain External Setting. Connect
this pin with one resistor to AXG rail VCCAXG_SENSE while IMONA pin is
connected to ground with another resistor. The current monitor output gain can
be set by the ratio of these two resistors.
Single Phase AXG VR Current Monitor Output. This pin outputs a voltage
proportional to the output current.
24
IMONFBA
25
IMONA
26
OFSA
27
RGNDA
28
FBA
29
COMPA
30
ISENAN
Negative Current Sense Pin for Single Phase AXG VR.
31
ISENAP
32
QRSETA
33
PWMA
Positive Current Sense Pin for Single Phase AXG VR.
Single Phase AXG VR Quick Response Time Setting and Address Flipping
Setting.
PWM Output for Single Phase AXG VR.
34
EN
Voltage Regulator Enabler.
35
VR_RDY
Power Ready Indicator of Multi-Phase CORE VR.
36
VCC5
37
OCSETA
38
OCSET
Chip Power. Connect this pin to GND by a ceramic cap larger than 1μF.
Single Phase AXG VR Over Current Protection Setting. Connect a resistor
voltage divider from VCC to ground, the joint of the resistor divider is connected
to OCSETA pin, with a voltage VOCSETA , to set the over current threshold
ILIMIT_AXG.
Multi-Phase CORE VR Over Current Protection Setting. Connect a resistor
voltage divider from VCC to ground, the joint of the resistor divider is connected
to OCSET pin, with a voltage VOCSET, to set the over current threshold
ILIMIT_CORE .
39
TSENA
Thermal Monitor Sense Point of AXG VR.
40
TSEN
Thermal Monitor Sense Point of CORE VR.
41
VRHOT
42
TONSETA
43
TONSET
48
VCC12
Thermal Monitor Output (Active Low).
Single Phase AXG VR On-time Setting. Connect this pin to VIN with one
resistor to set ripple size in PWM-mode.
Multi-Phase CORE VR On-time Setting. Connect this pin to VIN with one
resistor to set ripple size in PWM-mode.
Driver Power. Connect this pin to GND by a ceramic cap larger than 1μF.
Set the AXG No-Load Offset.
Return Ground for Single Phase AXG VR. This pin is the negative node of the
differential remote voltage sensing.
Single Phase AXG VR Feedback Input. This is the negative input node of the
error amplifier.
Single Phase AXG VR Compensation Node. This pin is the output node of the
error amplifier.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS2776-01 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT2776
Pin No.
Pin Name
Pin Function
49, 53, 47
LGATE [1:3]
Low Side Drive Output. This pin drives the gate of low side MOSFET.
50, 54, 46
PHASE [1:3]
Switch node of High Side Driver. Connect the pin to high side MOSFET source
together with the low side MOSFET drain and the inductor.
51, 55, 45
UGATE [1:3]
High Side Drive Output. Connect the pin to the gate of high side MOSFET.
52, 56, 44
BOOT [1:3]
Bootstrap Power Pin. This pin powers high side MOSFET driver.
GND
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
57
(Exposed Pad)
VSET
VSETA
VR_RDY
EN
ALERT
VDIO
VCLK
VRHOT
UVLO
GND
Control &
Protection Logic
+
SVID XCVR
QRSET
QRSETA
VSETA
+/-
+
FBA
ERROR
AMP
COMPA
PWM
CMP
+
Offset
Cancellation
-
DVIDA
POR
ADC
DAC
Soft-Start & Slew
Rate Control
TON
Gen
-
PWMA
TONSETA
1/20
DVID
To Protection Logic
1/20
From Control Logic
OFS
ICCMAXA
TSENA
TSEN
MUX
From Control Logic
RGNDA
ICCMAX
TEMPMAX
Offset
Generator
VCC5
Current
Monitor
OFSA
IMONFBA
Current
Monitor
VCC12
IMON
IMONA
IMONFB
Function Block Diagram
Offset
Generator
OVP/UVP/NVP
ISENAP
ISENAN
+
20
-
OCP
OCSETA
TONSET
DAC
Soft-Start & Slew
Rate Control
FB
+
RGND
VSET
+
+
Offset
Cancellation
-
COMP
PWM
CMP
BOOTx
-
+
+
QR
CMP
-
PHASE
Selector
TON
Gen PWM
[1:3]
3-PH
Driver
UGATEx
PHASEx
LGATEx
VQR_TRIP
IBIAS
RSET
ISEN3P
ISEN3N
+
ISEN2P
ISEN2N
+
ISEN1P
+
ISEN1N
-
-
-
10
SUM
10
To Protection Logic
OVP/UVP/NVP
Current Balance
OCP
10
OCSET
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
4
is a registered trademark of Richtek Technology Corporation.
DS2776-01 January 2014
RT2776
Operation
PWM CMP
Offset Cancellation
Generate a signal to trigger Ton pulse.
Cancel the current/voltage ripple issue to get the accurate
VSEN.
TON GEN
Generate the PWM1 to PWM4 sequentially according
to the phase control signal from the Loop control
protection logic.
UVLO
Control and Protection Logic
DAC
Execute the command from CPU.
Generate a analog signal according to the digital code
generated by Control Logic.
The control logic also generates the digital code of the
VID.
Detect the DVD and VCC voltage and issue POR signal as
they are large enough.
Soft-Start and Slew Rate Control
Control the protection behavior.
Control the Dynamic VID slew rate of VSET according to
the SetVID fast or SetVID slow.
Control the operational phase number.
3-PHASE Driver
Current Balance
Generate UGATE [1:3] and LGATE [1:3] signal by PWM
[1:3] signal.
Control the Power On Sequence
Generate the signal to control Ton to achieve current
balance.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS2776-01 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT2776
Table 1. VR12 VID Code Table
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
0
0
0
0
0
0
0
0
0
0
0.000
0
0
0
0
0
0
0
1
0
1
0.250
0
0
0
0
0
0
1
0
0
2
0.255
0
0
0
0
0
0
1
1
0
3
0.260
0
0
0
0
0
1
0
0
0
4
0.265
0
0
0
0
0
1
0
1
0
5
0.270
0
0
0
0
0
1
1
0
0
6
0.275
0
0
0
0
0
1
1
1
0
7
0.280
0
0
0
0
1
0
0
0
0
8
0.285
0
0
0
0
1
0
0
1
0
9
0.290
0
0
0
0
1
0
1
0
0
A
0.295
0
0
0
0
1
0
1
1
0
B
0.300
0
0
0
0
1
1
0
0
0
C
0.305
0
0
0
0
1
1
0
1
0
D
0.310
0
0
0
0
1
1
1
0
0
E
0.315
0
0
0
0
1
1
1
1
0
F
0.320
0
0
0
1
0
0
0
0
1
0
0.325
0
0
0
1
0
0
0
1
1
1
0.330
0
0
0
1
0
0
1
0
1
2
0.335
0
0
0
1
0
0
1
1
1
3
0.340
0
0
0
1
0
1
0
0
1
4
0.345
0
0
0
1
0
1
0
1
1
5
0.350
0
0
0
1
0
1
1
0
1
6
0.355
0
0
0
1
0
1
1
1
1
7
0.360
0
0
0
1
1
0
0
0
1
8
0.365
0
0
0
1
1
0
0
1
1
9
0.370
0
0
0
1
1
0
1
0
1
A
0.375
0
0
0
1
1
0
1
1
1
B
0.380
0
0
0
1
1
1
0
0
1
C
0.385
0
0
0
1
1
1
0
1
1
D
0.390
0
0
0
1
1
1
1
0
1
E
0.395
0
0
0
1
1
1
1
1
1
F
0.400
0
0
1
0
0
0
0
0
2
0
0.405
0
0
1
0
0
0
0
1
2
1
0.410
0
0
1
0
0
0
1
0
2
2
0.415
0
0
1
0
0
0
1
1
2
3
0.420
0
0
1
0
0
1
0
0
2
4
0.425
0
0
1
0
0
1
0
1
2
5
0.430
0
0
1
0
0
1
1
0
2
6
0.435
0
0
1
0
0
1
1
1
2
7
0.440
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
6
Hex
Voltage (V)
is a registered trademark of Richtek Technology Corporation.
DS2776-01 January 2014
RT2776
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
0
0
1
0
1
0
0
0
2
8
0.445
0
0
1
0
1
0
0
1
2
9
0.450
0
0
1
0
1
0
1
0
2
A
0.455
0
0
1
0
1
0
1
1
2
B
0.460
0
0
1
0
1
1
0
0
2
C
0.465
0
0
1
0
1
1
0
1
2
D
0.470
0
0
1
0
1
1
1
0
2
E
0.475
0
0
1
0
1
1
1
1
2
F
0.480
0
0
1
1
0
0
0
0
3
0
0.485
0
0
1
1
0
0
0
1
3
1
0.490
0
0
1
1
0
0
1
0
3
2
0.495
0
0
1
1
0
0
1
1
3
3
0.500
0
0
1
1
0
1
0
0
3
4
0.505
0
0
1
1
0
1
0
1
3
5
0.510
0
0
1
1
0
1
1
0
3
6
0.515
0
0
1
1
0
1
1
1
3
7
0.520
0
0
1
1
1
0
0
0
3
8
0.525
0
0
1
1
1
0
0
1
3
9
0.530
0
0
1
1
1
0
1
0
3
A
0.535
0
0
1
1
1
0
1
1
3
B
0.540
0
0
1
1
1
1
0
0
3
C
0.545
0
0
1
1
1
1
0
1
3
D
0.550
0
0
1
1
1
1
1
0
3
E
0.555
0
0
1
1
1
1
1
1
3
F
0.560
0
1
0
0
0
0
0
0
4
0
0.565
0
1
0
0
0
0
0
1
4
1
0.570
0
1
0
0
0
0
1
0
4
2
0.575
0
1
0
0
0
0
1
1
4
3
0.580
0
1
0
0
0
1
0
0
4
4
0.585
0
1
0
0
0
1
0
1
4
5
0.590
0
1
0
0
0
1
1
0
4
6
0.595
0
1
0
0
0
1
1
1
4
7
0.600
0
1
0
0
1
0
0
0
4
8
0.605
0
1
0
0
1
0
0
1
4
9
0.610
0
1
0
0
1
0
1
0
4
A
0.615
0
1
0
0
1
0
1
1
4
B
0.620
0
1
0
0
1
1
0
0
4
C
0.625
0
1
0
0
1
1
0
1
4
D
0.630
0
1
0
0
1
1
1
0
4
E
0.635
0
1
0
0
1
1
1
1
4
F
0.640
0
1
0
1
0
0
0
0
5
0
0.645
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS2776-01 January 2014
Hex
Voltage (V)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
7
RT2776
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Hex
Voltage (V)
0
1
0
1
0
0
0
1
5
1
0.650
0
1
0
1
0
0
1
0
5
2
0.655
0
1
0
1
0
0
1
1
5
3
0.660
0
1
0
1
0
1
0
0
5
4
0.665
0
1
0
1
0
1
0
1
5
5
0.670
0
1
0
1
0
1
1
0
5
6
0.675
0
1
0
1
0
1
1
1
5
7
0.680
0
1
0
1
1
0
0
0
5
8
0.685
0
1
0
1
1
0
0
1
5
9
0.690
0
1
0
1
1
0
1
0
5
A
0.695
0
1
0
1
1
0
1
1
5
B
0.700
0
1
0
1
1
1
0
0
5
C
0.705
0
1
0
1
1
1
0
1
5
D
0.710
0
1
0
1
1
1
1
0
5
E
0.715
0
1
0
1
1
1
1
1
5
F
0.720
0
1
1
0
0
0
0
0
6
0
0.725
0
1
1
0
0
0
0
1
6
1
0.730
0
1
1
0
0
0
1
0
6
2
0.735
0
1
1
0
0
0
1
1
6
3
0.740
0
1
1
0
0
1
0
0
6
4
0.745
0
1
1
0
0
1
0
1
6
5
0.750
0
1
1
0
0
1
1
0
6
6
0.755
0
1
1
0
0
1
1
1
6
7
0.760
0
1
1
0
1
0
0
0
6
8
0.765
0
1
1
0
1
0
0
1
6
9
0.770
0
1
1
0
1
0
1
0
6
A
0.775
0
1
1
0
1
0
1
1
6
B
0.780
0
1
1
0
1
1
0
0
6
C
0.785
0
1
1
0
1
1
0
1
6
D
0.790
0
1
1
0
1
1
1
0
6
E
0.795
0
1
1
0
1
1
1
1
6
F
0.800
0
1
1
1
0
0
0
0
7
0
0.805
0
1
1
1
0
0
0
1
7
1
0.810
0
1
1
1
0
0
1
0
7
2
0.815
0
1
1
1
0
0
1
1
7
3
0.820
0
1
1
1
0
1
0
0
7
4
0.825
0
1
1
1
0
1
0
1
7
5
0.830
0
1
1
1
0
1
1
0
7
6
0.835
0
1
1
1
0
1
1
1
7
7
0.840
0
1
1
1
1
0
0
0
7
8
0.845
0
1
1
1
1
0
0
1
7
9
0.850
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
8
is a registered trademark of Richtek Technology Corporation.
DS2776-01 January 2014
RT2776
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
0
1
1
1
1
0
1
0
7
A
0.855
0
1
1
1
1
0
1
1
7
B
0.860
0
1
1
1
1
1
0
0
7
C
0.865
0
1
1
1
1
1
0
1
7
D
0.870
0
1
1
1
1
1
1
0
7
E
0.875
0
1
1
1
1
1
1
1
7
F
0.880
1
0
0
0
0
0
0
0
8
0
0.885
1
0
0
0
0
0
0
1
8
1
0.890
1
0
0
0
0
0
1
0
8
2
0.895
1
0
0
0
0
0
1
1
8
3
0.900
1
0
0
0
0
1
0
0
8
4
0.905
1
0
0
0
0
1
0
1
8
5
0.910
1
0
0
0
0
1
1
0
8
6
0.915
1
0
0
0
0
1
1
1
8
7
0.920
1
0
0
0
1
0
0
0
8
8
0.925
1
0
0
0
1
0
0
1
8
9
0.930
1
0
0
0
1
0
1
0
8
A
0.935
1
0
0
0
1
0
1
1
8
B
0.940
1
0
0
0
1
1
0
0
8
C
0.945
1
0
0
0
1
1
0
1
8
D
0.950
1
0
0
0
1
1
1
0
8
E
0.955
1
0
0
0
1
1
1
1
8
F
0.960
1
0
0
1
0
0
0
0
9
0
0.965
1
0
0
1
0
0
0
1
9
1
0.970
1
0
0
1
0
0
1
0
9
2
0.975
1
0
0
1
0
0
1
1
9
3
0.980
1
0
0
1
0
1
0
0
9
4
0.985
1
0
0
1
0
1
0
1
9
5
0.990
1
0
0
1
0
1
1
0
9
6
0.995
1
0
0
1
0
1
1
1
9
7
1.000
1
0
0
1
1
0
0
0
9
8
1.005
1
0
0
1
1
0
0
1
9
9
1.010
1
0
0
1
1
0
1
0
9
A
1.015
1
0
0
1
1
0
1
1
9
B
1.020
1
0
0
1
1
1
0
0
9
C
1.025
1
0
0
1
1
1
0
1
9
D
1.030
1
0
0
1
1
1
1
0
9
E
1.035
1
0
0
1
1
1
1
1
9
F
1.040
1
0
1
0
0
0
0
0
A
0
1.045
1
0
1
0
0
0
0
1
A
1
1.050
1
0
1
0
0
0
1
0
A
2
1.055
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS2776-01 January 2014
Hex
Voltage (V)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
9
RT2776
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1
0
1
0
0
0
1
1
A
3
1.060
1
0
1
0
0
1
0
0
A
4
1.065
1
0
1
0
0
1
0
1
A
5
1.070
1
0
1
0
0
1
1
0
A
6
1.075
1
0
1
0
0
1
1
1
A
7
1.080
1
0
1
0
1
0
0
0
A
8
1.085
1
0
1
0
1
0
0
1
A
9
1.090
1
0
1
0
1
0
1
0
A
A
1.095
1
0
1
0
1
0
1
1
A
B
1.100
1
0
1
0
1
1
0
0
A
C
1.105
1
0
1
0
1
1
0
1
A
D
1.110
1
0
1
0
1
1
1
0
A
E
1.115
1
0
1
0
1
1
1
1
A
F
1.120
1
0
1
1
0
0
0
0
B
0
1.125
1
0
1
1
0
0
0
1
B
1
1.130
1
0
1
1
0
0
1
0
B
2
1.135
1
0
1
1
0
0
1
1
B
3
1.140
1
0
1
1
0
1
0
0
B
4
1.145
1
0
1
1
0
1
0
1
B
5
1.150
1
0
1
1
0
1
1
0
B
6
1.155
1
0
1
1
0
1
1
1
B
7
1.160
1
0
1
1
1
0
0
0
B
8
1.165
1
0
1
1
1
0
0
1
B
9
1.170
1
0
1
1
1
0
1
0
B
A
1.175
1
0
1
1
1
0
1
1
B
B
1.180
1
0
1
1
1
1
0
0
B
C
1.185
1
0
1
1
1
1
0
1
B
D
1.190
1
0
1
1
1
1
1
0
B
E
1.195
1
0
1
1
1
1
1
1
B
F
1.200
1
1
0
0
0
0
0
0
C
0
1.205
1
1
0
0
0
0
0
1
C
1
1.210
1
1
0
0
0
0
1
0
C
2
1.215
1
1
0
0
0
0
1
1
C
3
1.220
1
1
0
0
0
1
0
0
C
4
1.225
1
1
0
0
0
1
0
1
C
5
1.230
1
1
0
0
0
1
1
0
C
6
1.235
1
1
0
0
0
1
1
1
C
7
1.240
1
1
0
0
1
0
0
0
C
8
1.245
1
1
0
0
1
0
0
1
C
9
1.250
1
1
0
0
1
0
1
0
C
A
1.255
1
1
0
0
1
0
1
1
C
B
1.260
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
10
Hex
Voltage (V)
is a registered trademark of Richtek Technology Corporation.
DS2776-01 January 2014
RT2776
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1
1
0
0
1
1
0
0
C
C
1.265
1
1
0
0
1
1
0
1
C
D
1.270
1
1
0
0
1
1
1
0
C
E
1.275
1
1
0
0
1
1
1
1
C
F
1.280
1
1
0
1
0
0
0
0
D
0
1.285
1
1
0
1
0
0
0
1
D
1
1.290
1
1
0
1
0
0
1
0
D
2
1.295
1
1
0
1
0
0
1
1
D
3
1.300
1
1
0
1
0
1
0
0
D
4
1.305
1
1
0
1
0
1
0
1
D
5
1.310
1
1
0
1
0
1
1
0
D
6
1.315
1
1
0
1
0
1
1
1
D
7
1.320
1
1
0
1
1
0
0
0
D
8
1.325
1
1
0
1
1
0
0
1
D
9
1.330
1
1
0
1
1
0
1
0
D
A
1.335
1
1
0
1
1
0
1
1
D
B
1.340
1
1
0
1
1
1
0
0
D
C
1.345
1
1
0
1
1
1
0
1
D
D
1.350
1
1
0
1
1
1
1
0
D
E
1.355
1
1
0
1
1
1
1
1
D
F
1.360
1
1
1
0
0
0
0
0
E
0
1.365
1
1
1
0
0
0
0
1
E
1
1.370
1
1
1
0
0
0
1
0
E
2
1.375
1
1
1
0
0
0
1
1
E
3
1.380
1
1
1
0
0
1
0
0
E
4
1.385
1
1
1
0
0
1
0
1
E
5
1.390
1
1
1
0
0
1
1
0
E
6
1.395
1
1
1
0
0
1
1
1
E
7
1.400
1
1
1
0
1
0
0
0
E
8
1.405
1
1
1
0
1
0
0
1
E
9
1.410
1
1
1
0
1
0
1
0
E
A
1.415
1
1
1
0
1
0
1
1
E
B
1.420
1
1
1
0
1
1
0
0
E
C
1.425
1
1
1
0
1
1
0
1
E
D
1.430
1
1
1
0
1
1
1
0
E
E
1.435
1
1
1
0
1
1
1
1
E
F
1.440
1
1
1
1
0
0
0
0
F
0
1.445
1
1
1
1
0
0
0
1
F
1
1.450
1
1
1
1
0
0
1
0
F
2
1.455
1
1
1
1
0
0
1
1
F
3
1.460
1
1
1
1
0
1
0
0
F
4
1.465
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS2776-01 January 2014
Hex
Voltage (V)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11
RT2776
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1
1
1
1
0
1
0
1
F
5
1.470
1
1
1
1
0
1
1
0
F
6
1.475
1
1
1
1
0
1
1
1
F
7
1.480
1
1
1
1
1
0
0
0
F
8
1.485
1
1
1
1
1
0
0
1
F
9
1.490
1
1
1
1
1
0
1
0
F
A
1.495
1
1
1
1
1
0
1
1
F
B
1.500
1
1
1
1
1
1
0
0
F
C
1.505
1
1
1
1
1
1
0
1
F
D
1.510
1
1
1
1
1
1
1
0
F
E
1.515
1
1
1
1
1
1
1
1
F
F
1.520
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
12
Hex
Voltage (V)
is a registered trademark of Richtek Technology Corporation.
DS2776-01 January 2014
RT2776
Table 2. Serial VID Command
Master Payload
Slave Payload
Contents
Contents
N/A
N/A
Code
Commands
00h
Not Supported
01h
SetVID_Fast
VID code
N/A
Set new target VID code, VR jumps to
new VID target with controlled default
“fast” slew rate 12.5mV/μs.
02h
SetVID_Slow
VID code
N/A
Set new target VID code, VR jumps to
new VID target with controlled default
“slow” slew rate 3.125mV/μs.
N/A
Set new target VID code, VR jumps to
new VID target, but does not control
the slew rate. The output voltage
decays at a rate proportional to the
load current
03h
SetVID_Decay
04h
SetPS
05h
SetRegADR
06h
SetRegDAT
07h
08h
1Fh
VID code
Description
N/A
Byte indicating power
states
Pointer of registers in
data table
New data register
content
N/A
Set power state
N/A
Set the pointer of the data register
N/A
Write the contents to the data register
GetReg
Pointer of registers in
data table
Specified
register
contents
Not Supported
N/A
N/A
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS2776-01 January 2014
Slave returns the contents of the
specified register as the payload.
N/A
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT2776
Table 3. SVID Data and Configuration Register
Index
Register Name
Description
Access
Default
00h
Vendor_ID
Vendor ID
RO
1Eh
01h
02h
05h
Product_ID
Product_Revision
Protocol_Version
RO
RO
RO
5Bh
01h
01h
06h
VR_Capability
Product ID
Product Revision
SVID Protocol version
Bit mapped register, identifies the SVID VR
Capabilities and which of the optional telemetry
registers is supported.
RO
81h
10h
Status_1
Data register containing the status of VR
R-M, W-PWM
00h
11h
Status_2
R-M, W-PWM
00h
12h
Temperature_Zone
R-M, W-PWM
00h
15h
Output_Current
R-M, W-PWM
00h
1Ch
Status_2_Lastread
Data register containing the status of transmission.
Data register showing temperature Zone that has
been entered.
Data register showing direct ADC conversion of
output current, scaled to ICC_MAX = ADC full range.
Binary format (IE : 64h = 100/255 ICC_MAX)
The register contains a copy of the Status_2
R-M, W-PWM
00h
21h
ICC_Max
RO, Platform
N/A
RO, Platform
N/A
RO
0Ah
RO
02h
RW, Master
FBh
RW, Master
00h
RW, Master
00h
RW, Master
00h
RW, Master
00h
RW, Master
30h
22h
Temp_Max
24h
SR_fast
25h
SR_slow
30h
VOUT_Max
31h
VID_Setting
32h
Power_State
33h
Offset
34h
Multi_VR_Config
35h
Pointer
Data register containing the maximum ICC the
platform supports.
Binary format in A. (IE : 64h = 100A)
Data register containing the maximum temperature
the platform supports.
Binary format in °C. (IE : 64h = 100°C)
Not supported by AXG VR.
Data register containing the capability of fast slew
rate the platform can sustain. Binary format in
mV/μs. (IE : 0Ah = 10mV/μs)
Data register containing the capability of slow slew
rate.
Binary format in mV/μs. (IE : 02h = 2mV/μs)
The register is programmed by the master and sets
the maximum VID.
Data register containing currently programmed VID
Register containing the current programmed power
state
Set offset in VID steps
Bit mapped data register which configures multiple
VRs’ behavior on the same bus
Scratch pad register for temporary storage of the
SetRegADR pointer register
Notes :
RO = Read Only
RW = Read/Write
R-M = Read by Master
W-PWM = Write by PWM only
Platform = programmed by platform
Master = programmed by the master
PWM = programmed by the VR control IC
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
14
is a registered trademark of Richtek Technology Corporation.
DS2776-01 January 2014
RT2776
Absolute Maximum Ratings
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
(Note 1)
VCC12 to GND --------------------------------------------------------------------------------------- −0.3V to 15V
VCC5 to GND ---------------------------------------------------------------------------------------- −0.3V to 6.5V
RGND, RGNDA to GND ---------------------------------------------------------------------------- −0.3V to 0.3V
TONSET, TONSETA to GND ---------------------------------------------------------------------- −0.3V to 28V
BOOTx to PHASEx --------------------------------------------------------------------------------- −0.3V to 15V
PHASEx to GND
DC ------------------------------------------------------------------------------------------------------- −0.3V to 30V
<20ns -------------------------------------------------------------------------------------------------- −10V to 35V
LGATEx to GND
DC ------------------------------------------------------------------------------------------------------- (GND − 0.3V) to (VCC12 + 0.3V)
<20ns -------------------------------------------------------------------------------------------------- (GND − 2V) to (VCC12 + 0.3V)
UGATEx to GND
DC ------------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V)
<20ns -------------------------------------------------------------------------------------------------- (VPHASE − 2V) to (VBOOT + 0.3V)
PWMA to GND --------------------------------------------------------------------------------------- −0.3V to 7V
Other Pins --------------------------------------------------------------------------------------------- −0.3V to (VCC5 + 0.3V)
Power Dissipation, PD @ TA = 25°C
WQFN−56L 7x7 -------------------------------------------------------------------------------------- 3.226W
Package Thermal Resistance (Note 2)
WQFN−56L 7x7, θJA -------------------------------------------------------------------------------- 31°C/W
WQFN−56L 7x7, θJC ------------------------------------------------------------------------------- 6°C/W
Junction Temperature ------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------- 260°C
Storage Temperature Range ---------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) ------------------------------------------------------------------------ 2kV
Recommended Operating Conditions
z
z
z
z
z
(Note 4)
Supply Voltage, VCC12 ---------------------------------------------------------------------------- 4.5V to 13.2V
Supply Voltage, VCC5 ----------------------------------------------------------------------------- 4.5V to 5.5V
Input Voltage, (VIN + VCC12) --------------------------------------------------------------------- <35V
Junction Temperature Range ---------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ---------------------------------------------------------------------- −40°C to 85°C
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS2776-01 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
15
RT2776
Electrical Characteristics
(VCC5 = 5V, VCC12 = 12V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Supply Input
VCC12 Supply Voltage
VCC12
4.5
--
13.2
V
VCC5 Supply Voltage
VCC5
4.5
5
5.5
V
VCC12 Supply Current
IVCC12
VCC12 = 12V, VBOOTx = 12V
--
1.2
--
mA
VCC5 Supply Current
IVCC5
EN = 1.05V, Not Switching
--
12
20
mA
Shutdown Current
ISHDN
EN = 0V
--
--
5
μA
POR Threshold
VPOR_r
VCC12 Rising
3
--
4.4
V
POR Hysteresis
VPOR_HYS
--
0.5
--
V
VDAC = 1.000 to 1.520
(No Load, Active Mode)
VDAC = 0.800 to 1.000
−0.5
0
0.5
%VID
−5
0
5
VDAC = 0.500 to 0.800
−8
0
8
VDAC = 0.250 to 0.500
−8
0
8
EN = 1.05V, Not Switching
--
--
500
μA
SetVID Slow
2.5
3.125
3.75
mV/μs
SetVID Fast
10
12.5
15
mV/μs
RL = 47kΩ
70
80
--
dB
Power On Reset (POR)
Reference and DAC
DC Accuracy
mV
RGND Current
RGND Current
IRGND
Slew Rate
Dynamic VID Slew Rate
Error Amplifier
DC Gain
Gain-Bandwidth Product
GBW
CLOAD = 5pF
--
10
--
MHz
Slew Rate
SR
CLOAD = 10pF (gain = −4,
RF = 47k, VOUT = 0.5V − 3V)
--
5
--
V/μs
Output Voltage Range
VCOMP
RL = 47kΩ
0.3
--
3.6
V
MAX Source/Sink Current
IOUTEA
VCOMP = 2V
--
250
--
μA
−0.75
--
0.75
mV
Current Sense Amplifier
Input Offset Voltage
VOSCS
Impedance at Neg. Input
RISENxN
1
--
--
mΩ
Impedance at Pos. Input
RISENxP
1
--
--
mΩ
CORE VR
--
10
--
V/V
AXG VR
--
20
--
V/V
−50
--
100
mV
DC Gain
Input Range
VISEN_in
VISEN Linearity
VISEN _ACC
−30mV < VISEN_in < 50mV
−1
--
1
%
TONSET/TONSETA pin
Voltage
VTon
IRTON = 80μA, VDAC = 0.75V
--
0.75
--
V
CCM On-time Setting
TON
IRTON = 80μA, PS0, PS1
275
305
335
ns
Ton Setting
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DS2776-01 January 2014
RT2776
Parameter
TONSET/TONSETA Input
Current Range
Symbol
IRTON
Ton in PS2 (CORE Only)
TON ps2
Minimum Off-Time
TOFF_MIN
Test Conditions
Min
Typ
Max
Unit
25
--
280
μA
--
85
--
%
--
250
--
ns
2.09
2.14
2.19
V
--
305
--
ns
-VCC5
− 0.5
80
--
μA
--
--
V
VIL
--
--
VCC5
− 1.8
V
VIH
VCC5
− 0.5
--
--
V
VIL
--
--
VCC5
− 1.8
V
VOFS > VEN_OFS before EN
rising
0.52
1.2
--
V
VID = 1V, offset +400mV
1.58
1.6
1.62
VID = 1V, offset −200mV
0.98
1
1.02
VID = 1V. No Offset Voltage
1.19
1.2
1.21
1
--
--
MΩ
With Respect to PS0 Ton
IBIAS
IBIAS Pin Voltage
VIBIAS
RIBIAS = 53.6k
Quick Response Tonx
TONx _QR
VDAC = 0.75V, Q RSET = 1.2V,
IRTON = 80μA
QRSET Source Current
IQRSET
Before POR
QRSET/QRSETA
VIH
VINITIAL Threshold
Non-flipping ADDR Threshold
OFS/OFSA Function
OFS Enable/Disable Threshold
Voltage
VEN_OFS
Set OFS/OFSA Voltage
Impedance
ROFS
V
RSET Setting
RSET Voltage
VRSET
VDAC = 1V
--
1.000
--
V
VZCD
ISEN1P − ISEN1N,
ISENAP − ISENAN
--
1
--
mV
VUVLO
Falling edge, 100mV Hysteresis
4.04
4.24
4.44
V
VOVABS
With Respect to VOUT(MAX), pin
offset is disabled
100
150
200
mV
Delay of UVLO
tUVLO
Rising above Threshold
--
3
--
μs
Delay of OVP
tOV
--
1
--
μs
−350
−300
−250
mV
--
3
--
μs
−100
−50
--
mV
Zero Current Detection
Zero Current Detection
Threshold
Protection
Under Voltage Lockout (UVLO)
Threshold
Absolute Over Voltage
Protection Threshold
Under Voltage Protection (UVP)
VUV
Threshold
Delay of UVP
tUV
Negative Voltage Protection
Threshold
VNV
ISEN1N/ISENAN Rising above
Threshold
Measured at ISEN1N/ISENAN
with respect to unloaded output
voltage (UOV)
(for 0.8V < UOV < 1.52V)
ISEN1N/ISENAN Falling below
Threshold
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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17
RT2776
Parameter
Min
Typ
Max
Unit
--
1
--
μs
GILIMT = V OCSET / (VISENxP
− VISENxN) VOCSET = 2.4V,
(V ISENxP − V ISENxN) = 50mV
43.2
48
52.8
GILIMT = V OCSETA / (VISENAP
−V ISENAN) V OCSETA = 2.4V,
(V ISENAP − VISENAN) = 25mV
86.4
96
105.6
--
15
--
VIH_EN
0.7
--
--
VIL_EN
--
--
0.3
EN Hysteresis
VENHYS
--
30
--
mV
Leakage Current of EN
IEN
−1
--
1
μA
VCLK, VDIO Threshold
Voltage
VIH
0.665
--
--
VIL
--
--
0.367
VCLK, VDIO Hysteresis
Leakage Current of VCLK,
VDIO
VHYS
--
70
--
mV
ILEAK_IN
−1
--
1
μA
Delay of NVP
Symbol
tNV
Current Limit Threshold
Voltage (Per Phase)
Current limit latch Counter
(per phase)
Logic Inputs
EN Threshold Voltage
NILIMIT
Test Conditions
ISEN1N/ISENAN Falling below
Threshold
Continuous Current Limit Cycle
V/V
times
V
V
ALERT
V ALERT
IALERT = 4mA
--
--
0.4
V
SVID Ready Delay Time
tA
From EN to VR Controller is
ready to accept SVID command
--
--
2
ms
VR Ready Trip Threshold
VTH_VR_RDY ISEN1N − 1 VDAC
--
−100
--
mV
VR_RDY Low Voltage
VVR_RDY
IVR_RDY = 4mA
--
--
0.4
V
VR_RDY Delay
tVR_RDY
ISEN1N = VINITIAL to VR_RDY
high
--
100
--
μs
VVRHOT
IVRHOT = 40mA
--
--
0.4
V
3.2
3.3
3.4
V
Leakage Current of ALERT,
ILEAK_OUT
VR_RDY and VRHOT Pins
SVID
−1
--
1
μA
SVID Frequency
fSVIDfreq
5
25
26.25
MHz
SVID Clock To Data Delay
tCO
4
--
8.3
ns
Setup Time Of VDIO
tSU
7
--
--
ns
Hold Time Of VDIO
tHLD
14
--
--
ns
ALERT Low Voltage
Power On Sequence
st
Thermal Throttling
VRHOT Output Voltage
Current Monitor
Current Monitor Maximum
Output Voltage in Operating VIMON
Range
High Impedance Output
VDAC = 1V, VRIMONFB = 100mV,
RIMONFB = 10kΩ, RIMON = 330kΩ
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RT2776
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
ADC
Digital Code of ICCMAX
Digital Code of ICCMAXA
Digital Code of TEMPMAX
Digital Code of Output
Current Report
Updating Period of Output
Current Report
Tolerance Band of Temp.
Zone Trip Points b7, b6, b5
Updating Period of
Temperature Zone
Timing
CICCMAX1
VICCMAX = 12.74% x VCC5
29
32
35
CICCMAX2
VICCMAX = 25.284% x VCC5
61
64
67
CICCMAX3
VICCMAX = 50.372% x VCC5
125
128
131
CICCMAXA1
VICCMAXA = 3.332% x VCC5
5
8
11
CICCMAXA2
VICCMAXA = 6.468% x VCC5
13
16
19
CICCMAXA3
VICCMAXA = 12.74% x VCC5
29
32
35
CTEMPMAX1
VTEMPMAX = 33.516% x VCC5
82
85
88
CTEMPMAX2
VTEMPMAX = 39.396% x VCC5
97
100
103
CTEMPMAX3
VTEMPMAX = 49.196% x VCC5
122
125
128
COCR1
VIMONA = VIMONA = 3.3V
252
255
255
COCR2
VIMONA = VIMONA = 2.208V
167
170
173
COCR3
VIMONA = VIMONA = 1.107V
82
85
88
t OCR
--
--
500
μs
t TSEN_TOL
20
--
20
mV
t TZ
--
--
500
μs
decimal
decimal
decimal
decimal
UGATE Rise Time
t UGATEr
3nF load
--
25
--
ns
UGATE Fall Time
t UGATEf
3nF load
--
12
--
ns
LGATE Rise Time
t LGATEr
3nF load
--
24
--
ns
LGATE Fall Time
t LGATEf
3nF load
--
10
--
ns
t UGATEpgh
--
60
--
t UGATEpdl
--
22
--
t LGATEpdh
--
20
--
t LGATEpdl
--
8
--
Propagation Delay
ns
Output
UGATE Drive Source
Current
UGATE Drive Sink
Resistance
LGATE Drive Source
Current
LGATE Drive Sink
Resistance
UGATE Drive Source
I UGATEsr
VBOOTx − VPHASEx = 12V,
VUGATEx − VPHASEx = 2V
--
2
--
A
RUGATEsk
VBOOTx − VPHASEx = 12V
--
1.4
--
Ω
I LGATEsr
VLGATEx = 2V
--
2.2
--
A
--
1.1
--
Ω
--
2
--
A
6
8
10
μA
RLGATEsk
I UGATEsr
VBOOTx − VPHASEx = 12V,
VUGATEx − VPHASEx = 2V
DVID, DVIDA, ICCMAX, ICCMAXA and TEMPMAX
Current Sourcing Out from
DVIDx Pin to GND
I DVIDx
During dynamic VID fast event
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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RT2776
Parameter
Current Sinking in from 5V
to ICCMAX Pin
Current Sinking in from 5V
to ICCMAXA Pin
Current Sinking in from 5V
to TEMPMAX Pin
Symbol
Test Conditions
Min
Typ
Max
Unit
ICCMAX
After EN
--
16
--
μA
ICCMAXA
After EN
--
128
--
μA
ITEMPMAX
After EN
--
16
--
μA
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS2776-01 January 2014
RT2776
Typical Application Circuit
VCCIO
RT2776
48
12V
36
5V
43
VIN
42
VIN
VCC12
VCC5
VRHOT 41
VR_RDY 35
VCLK 17
TONSETA
13 DVID
2 DVIDA
OFS
TEMPMAX
ICCMAX
ICCMAXA
QRSETA
QRSET
OFSA
IBIAS
16 IMONFB
VCC_SENSE
VIN
52 BOOT1
51 UGATE1
VCLK
ALERT
14
21
22
23
32
1
26
20
IMONA 25
OCSETA 37
VCC5
OCSET 38
VCC5
50 PHASE1
49 LGATE1
6 ISEN1P
5 ISEN1N
VIN
54 PHASE2
53 LGATE2
Load
3 ISEN2P
4 ISEN2N
100
VIN
RNTC
TSEN 40
56 BOOT2
55 UGATE2
VOUT_CORE
VCC5
VDIO
IMON 15
10 COMP
11 FB
RNTC
VR_RDY
VDIO 18
19
ALERT
TONSET
9 RSET
VRHOT
VCC5
RNTC
TSENA 39
VCC5
IMONFBA 24
44 BOOT3
45 UGATE3
COMPA
46 PHASE3
47 LGATE3
VCCAXG_SENSE
29
FBA 28
12V
12V
7 ISEN3P
8 ISEN3N
VCC
RNTC
BOOT
PGND UGATE
12 RGND
PHASE
VSS_SENSE
Chip Enable
PWMA 33
34 EN
PWM
LGATE
RT9612
VOUT_AXG
100
Load
ISENAP 31
30
ISENAN
27
RGNDA
GND
57 (Exposed Pad)
VSSAXG_SENSE
Figure 1. Thernal Compersation at Voltage Loop for AXG VR
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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RT2776
VCCIO
RT2776
48
12V
36
5V
43
VIN
42
VIN
VCC12
VCC5
TONSET
TONSETA
9 RSET
13 DVID
2 DVIDA
VRHOT 41
VR_RDY 35
VCLK 17
10 COMP
11 FB
RNTC
VIN
52 BOOT1
51 UGATE1
50 PHASE1
49 LGATE1
VR_RDY
VCLK
VDIO 18
19
ALERT
OFS
TEMPMAX
ICCMAX
ICCMAXA
QRSETA
QRSET
OFSA
IBIAS
16 IMONFB
VCC_SENSE
VRHOT
ALERT
14
21
22
23
32
1
26
20
IMON 15
IMONA 25
OCSETA 37
VCC5
OCSET 38
VCC5
6 ISEN1P
5 ISEN1N
VIN
56 BOOT2
55 UGATE2
54 PHASE2
53 LGATE2
VCC5
VDIO
RNTC
TSEN 40
VCC5
RNTC
TSENA 39
VCC5
VOUT_CORE
3 ISEN2P
4 ISEN2N
Load
100
VIN
44 BOOT3
45 UGATE3
46 PHASE3
47 LGATE3
IMONFBA 24
COMPA
29
FBA 28
VCC
BOOT
PGND UGATE
12 RGND
Chip Enable
12V
12V
7 ISEN3P
8 ISEN3N
VSS_SENSE
VCCAXG_SENSE
PHASE
34 EN
PWMA 33
PWM
VOUT_AXG
LGATE
100
Load
RT9612
ISENAP 31
30
ISENAN
27
RGNDA
57 (Exposed Pad)
GND
RNTC
VSSAXG_SENSE
Figure 2. Thernal Compersation at Current Loop for AXG VR
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is a registered trademark of Richtek Technology Corporation.
DS2776-01 January 2014
RT2776
VCCIO
RT2776
48
12V
36
5V
43
VIN
9
13
VCC12
VCC5
TONSET
RSET
DVID
16 IMONFB
VCC_SENSE
10 COMP
11 FB
RNTC
VIN
6 ISEN1P
5 ISEN1N
VIN
56 BOOT2
55 UGATE2
54 PHASE2
53 LGATE2
VOUT_CORE
3 ISEN2P
4 ISEN2N
100
VRHOT
VR_RDY
VCLK 17
VDIO 18
19
ALERT
VCLK
VIN
44 BOOT3
45 UGATE3
46 PHASE3
47 LGATE3
ALERT
OFS 14
TEMPMAX 21
ICCMAX 22
1
QRSET
IBIAS
20
IMON 15
OCSET 38
VCC5
RNTC
TSEN 40
VCC5
DVIDA 2
ICCMAXA 23
IMONFBA
24
IMONA 25
26
OFSA
27
RGNDA
28
FBA
29
COMPA
32
QRSETA
33
PWMA
37
OCSETA
42
TONSETA
ISENAN
7 ISEN3P
8 ISEN3N
VCC5
VDIO
52 BOOT1
51 UGATE1
50 PHASE1
49 LGATE1
Load
VRHOT 41
VR_RDY 35
Floating
30
5V
ISENAP 31
39
TSENA
12 RGND
VSS_SENSE
Chip Enable
34 EN
GND
57 (Exposed Pad)
Figure 3. Application Circuit for AXG VR Being Disabled
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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23
RT2776
Typical Operating Characteristics
CORE VR Power On
CORE VR Power Off from EN
V CORE
(1V/Div)
V CORE
(1V/Div)
VR_RDY
(2V/Div)
ALERT
(2V/Div)
VR_RDY
(2V/Div)
EN
(2V/Div)
VDIO
(1V/Div)
PWM1
(5V/Div)
VCORE = 1.1V, ILOAD = 5A
VCORE = 1.1V, ILOAD = 5A
Time (100μs/Div)
Time (1ms/Div)
CORE VR Dynamic VID Up
CORE VR Dynamic VID Up
Fast Slew Rate
Slow Slew Rate
V CORE
(500mV/Div)
V CORE
(500mV/Div)
VCLK
(1V/Div)
ALERT
(2V/Div)
VDIO
(2V/Div)
VCLK
(1V/Div)
VCORE = 0.7V up to 1.2V, ILOAD = 20A
ALERT
(2V/Div)
VDIO
(2V/Div)
Time (40μs/Div)
Time (100μs/Div)
CORE VR Dynamic VID Down
CORE VR Dynamic VID Down
Fast Slew Rate
Slow Slew Rate
V CORE
(500mV/Div)
V CORE
(500mV/Div)
VCLK
(1V/Div)
ALERT
(2V/Div)
VDIO
(2V/Div)
VCLK
(1V/Div)
ALERT
(2V/Div)
VDIO
(2V/Div)
VCORE = 1.2V down to 0.7V, ILOAD = 20A
Time (40μs/Div)
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VCORE = 0.7V up to 1.2V, ILOAD = 20A
VCORE = 1.2V down to 0.7V, ILOAD = 20A
Time (100μs/Div)
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DS2776-01 January 2014
RT2776
CORE VR Load Transient Response
V CORE
(50mV/Div)
CORE VR Load Transient Response
V CORE
(50mV/Div)
70A
I LOAD
5A
70A
I LOAD
5A
VCORE = 1.1V, fLOAD = 300Hz, ILOAD = 5A to 70A
VCORE = 1.1V, fLOAD = 300Hz, ILOAD = 70A to 5A
Time (100μs/Div)
Time (100μs/Div)
CORE VR OCP
CORE VR OVP & NVP
V CORE
(2V/Div)
VR_RDY
(2V/Div)
V CORE
(1V/Div)
PWM1
(5V/Div)
VR_RDY
(1V/Div)
I LOAD
(100A/Div)
PWM1
(5V/Div)
VCORE = 1.1V
VCORE = 1.1V
Time (100μs/Div)
Time (40μs/Div)
CORE VR UVP
VIMON vs. Load Current
3.3
3.0
2.7
2.4
VIMON (V)
V CORE
(1V/Div)
VR_RDY
(1V/Div)
2.1
1.8
1.5
1.2
0.9
PWM1
(5V/Div)
0.6
VCORE = 1.1V, ILOAD = 1A
0.3
0.0
Time (1ms/Div)
0
10
20
30
40
50
60
70
80
90
100
Load Current (A)
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RT2776
AXG VR Power On
AXG VR Power Off from EN
VAXG
(1V/Div)
VAXG
(1V/Div)
VDIO
(1V/Div)
EN
(1V/Div)
ALERT
(1V/Div)
PWMA
(10V/Div)
VAXG = 1.1V, ILOAD = 5A
VAXG = 1.1V, ILOAD = 5A
Time (100μs/Div)
Time (1ms/Div)
AXG VR Dynamic VID Up
AXG VR Dynamic VID Up
Fast Slew Rate
Slow Slew Rate
VAXG
(500mV/Div)
VAXG
(500mV/Div)
VCLK
(2V/Div)
VDIO
(2V/Div)
VCLK
(2V/Div)
VDIO
(2V/Div)
ALERT
(2V/Div)
VAXG = 0.7V up to 1.2V, ILOAD = 20A
ALERT
(2V/Div)
Time (40μs/Div)
Time (100μs/Div)
AXG VR Dynamic VID Down
AXG VR Dynamic VID Down
Fast Slew Rate
Slow Slew Rate
VAXG
(500mV/Div)
VAXG
(500mV/Div)
VCLK
(2V/Div)
VDIO
(2V/Div)
VCLK
(2V/Div)
VDIO
(2V/Div)
ALERT
(2V/Div)
VAXG = 1.2V down to 0.7V, ILOAD = 20A
Time (40μs/Div)
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VAXG = 0.7V up to 1.2V, ILOAD = 20A
ALERT
(2V/Div)
VAXG = 1.2V down to 0.7V, ILOAD = 20A
Time (100μs/Div)
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RT2776
AXG VR Load Transient Response
VAXG
(50mV/Div)
AXG VR Load Transient Response
VAXG
(50mV/Div)
22A
I LOAD
2A
22A
I LOAD
2A
VAXG = 1.1V, fLOAD = 300Hz, ILOAD = 2A to 22A
VAXG = 1.1V, fLOAD = 300Hz, ILOAD = 22A to 2A
Time (100μs/Div)
Time (100μs/Div)
AXG VR OCP
AXG VR OVP & NVP
VAXG
(2V/Div)
VAXG
(1V/Div)
PWMA
(10V/Div)
I LOAD
(50A/Div)
PWMA
(5V/Div)
VAXG = 1.1V
VAXG = 1.1V
Time (100μs/Div)
Time (100μs/Div)
AXG VR UVP
VIMONA vs. Load Current
3.3
3.0
VAXG
(1V/Div)
2.7
2.4
VIMONA (V)
2.1
PWMA
(5V/Div)
1.8
1.5
1.2
0.9
0.6
VAXG = 1.1V, ILOAD = 1A
0.3
0.0
Time (1ms/Div)
0
3
6
9
12
15
18
21
24
27
30
Load Current (A)
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RT2776
Thermal Monitoring
TSEN
(100mV/Div)
VRHOT
(1V/Div)
TSEN from 1.7V Sweep to 1.9V, ILOAD = 0A
Time (400μs/Div)
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is a registered trademark of Richtek Technology Corporation.
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RT2776
Application Information
The RT2776 is a CPU power controller which includes
two channels : a 3/2/1 phase synchronous Buck controller
with three integrated drivers for CORE VR, and a single
phase Buck controller for AXG VR. The RT2776 is
compliant with Intel VR12/IMVP7 voltage regulator
specification to fulfill Intel's CPU power supply
requirements of both CORE and AXG voltage regulators.
A Serial VID (SVID) interface is built-in in the RT2776 to
communicate with Intel VR12/IMVP7 compliant CPU. The
RT2776 adopts G-NAVPTM (Green Native Adaptive Voltage
Positioning), which is Richtek's proprietary topology
derived from finite DC gain EA amplifier with current mode
control, making it an easy setting PWM controller, meeting
all Intel CPU requirements of AVP. The load line can be
easily programmed by setting the DC gain of the error
amplifier. The RT2776 has fast transient response because
of the G-NAVP TM commanding variable switching
frequency. Based on the G-NAVPTM topology, the RT2776
also features a quick response mechanism so that fully
phases can respond for optimized AVP performance during
load transient. The G-NAVPTM topology also represents a
high efficiency system with green power concept. With
the G-NAVPTM topology, the RT2776 is also a green power
controller with high efficiency under heavy load, light load,
and very light load conditions. The RT2776 supports mode
transition function with various operating states, including
multi-phase, single phase and DEM (Diode Emulation
Modes). These different operating states allow the overall
power control system to have the lowest power loss. By
utilizing the G-NAVPTM topology, the operating frequency
of the RT2776 varies with VID, load, and input voltage to
further enhance the efficiency even in CCM. The built-in
high accuracy DAC converts the SVID code ranging from
0.25V to 1.52V with 5mV per step. The RT2776 supports
VID on-the-fly function with three different slew rates :
Fast, Slow and Decay. The RT2776 also builds in a high
accuracy ADC for some platform setting functions, such
as no-load offset or over current level. The controller
supports both DCR and sense resistor current sensing.
The RT2776 provides power VR ready signals for both
CORE VR and AXG VR. It also features complete fault
protection functions including over voltage, under voltage,
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS2776-01 January 2014
negative voltage, over current and under voltage lockout.
The RT2776 is available in a WQFN-56L 7x7 small footprint
package.
General Loop Functions :
Power Ready (POR) Detection
During start-up, the RT2776 will detect the voltage at the
voltage input pins : VCC5, VCC12 and EN. When VCC5
> 4.24V and VCC12 > 4V, the RT2776 will recognize the
power state of system to be ready (POR = high) and wait
for enable command at the EN pin. After POR = high and
VEN > 0.7V, the RT2776 will enter start-up sequence for
both CORE rail and AXG rail. If the voltage at any voltage
pin drops below low threshold (POR = low), the RT2776
will enter power down sequence and all the functions will
be disabled. Normally, connecting system VTT (1.05V) to
the EN pin and power stage VIN (12V) to the VCC12 pin is
recommended. 2ms (max) after the chip has been
enabled, the SVID circuitry will be ready. All the protection
latches (OVP, OCP, UVP) will be cleared only after POR
= low. The condition of VEN = low will not clear these
latches.
VCC5
+
4.24V
VCC12
+
4V
-
+
1.06V
EN
POR
-
Chip EN
+
0.7V
+
1.06V
-
Figure 4. Power Ready (POR) Detection
Precise Reference Current Generation
The RT2776 includes complicated analog circuits inside
the controller. These analog circuits need very precise
reference voltage/current to drive these analog devices.
The RT2776 will auto generate a 2.14V voltage source at
the IBIAS pin, and a 53.6kΩ resistor is required to be
connected between IBIAS and analog ground. Through
this connection, the RT2776 will generate a 40μA current
from the IBIAS pin to analog ground, and this 40μA current
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29
RT2776
will be mirrored inside the RT2776 for internal use. Note
that other types of connection or other values of resistance
applied at the IBIAS pin may cause failure of the RT2776's
functions, such as slew rate control, OFS accuracy, etc.
In other words, the IBIAS pin can only be connected with
a 53.6kΩ resistor to GND. The resistance accuracy of
this resistor is recommended to be 1% or higher.
setting at these ADC pins. The maximum level settings
at these ADC pins are different from over current protection
or over temperature protection. In other words, these
maximum level setting pins are only for platform users to
define their system operating conditions and these
messages will only be utilized by the CPU.
VCC5
Current
Mirror
ICCMAX
2.14V
+
-
A/D
Converter
+
-
ICCMAXA
TEMPMAX
IBIAS
53.6k
I
Figure 6. ADC Pins Setting
Figure 5. IBIAS Setting
VINITIAL Setting
ICCMAX, ICCMAXA and TEMPMAX
The RT2776 provides ICCMAX, ICCMAXA and TEMPMAX
pins for platform users to set the maximum level of output
current or VR temperature : ICCMAX for CORE VR max
current, ICCMAXA for AXG VR max current, and TEMPMAX
for CORE VR max temperature. To set ICCMAX, ICCMAXA
and TEMPMAX platform designers should use resistive
voltage divider on these three pins. The current of the
divider should be several milliamps to avoid noise effect.
The 3 items share the same algorithms : the ADC divides
5V into 255 levels. Therefore, the LSB = 5 / 255 = 19.6mV,
which means 19.6mV applied to ICCMAX pin equals to
1A setting. For example, if the maximum level of
temperature is desired to be 120°C, the voltage applied to
TEMPMAX should be 120 x 19.6mV = 2.352V. The ADC
circuit inside these three pins will decode the voltage
applied and store the maximum current/temperature
setting into ICC_Max and Temp_Max registers. The ADC
monitors and decodes the voltage at these three pins only
ONCE after power up. After ADC decoding (only once), a
128μA current will be generated at the ICCMAXA pin for
internal use. Make sure the voltage at the ICCMAXA pin
is greater than 1.55V to guarantee proper functionality
The RT2776 will NOT take any action even when the VR
output current or temperature exceeds its maximum
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30
The VR's VINITIAL can be selected as 0V or 1.1V by QRSET
pin. The connection of the QRSET pin is usually a voltage
divider circuit which is described later in the Quick
Response section in CORE rail part. Before POR, the
RT2776 will source an 80μA current from the QRSET pin
to the external voltage divider to determine the voltage
level while the RT2776 is still not powered on. Before POR,
if the voltage at the QRSET pin is higher than
VCC5 − 0.5V, the VINITIAL will be 1.1V. If the voltage is
lower than VCC5 − 1.8V, the VINITIAL will be 0V. For
example, a 5V voltage divided by two 1kΩ resistors
connected to the QRSET pin generates 2.54V (5V / 2 +
80μA x 1kΩ / 2) before POR and 2.5V (5V/2) after POR.
So the VINITIAL will be 0V under this condition. Please
note that the both Core rail and AXG rail are simultaneously
set as VINITIAL = 1.1V or 0V.
VR Rail Addressing
The VR's address can be flipped by setting QRSETA pin.
The connection of the QRSETA pin is usually a voltage
divider circuit which is described later in the Quick
Response section in AXG rail part. Before POR, the RT2776
will source an 80μA current from the QRSETA pin to the
external voltage divider to determine the voltage level while
the RT2776 is still not powered on. Before POR, if the
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DS2776-01 January 2014
RT2776
voltage at the QRSETA pin is lower than
VCC5 − 1.8V, the address will be flipped, that is, VR0
(CORE) address is flipped from 0000 to 0001 and VR1
(AXG) address is flipped from 0001 to 0000. For example,
a 5V voltage divided by two 1kΩ resistors connected to
the QRSETA pin generates 2.54V (5V / 2 + 80μA x 1kΩ /
2) before POR and 2.5V (5V/2) after POR. So the address
will be flipped under this condition.
receives valid VID code (typically SetVID_Slow command),
VOUT will ramp up to the target voltage with specified slew
rate (see section “Data and Configuration Register”). After
VOUT reaches target voltage (VID voltage for VINITIAL = 0V
or VINITIAL for VINITIAL = 1.1V), the RT2776 will send out
VR_RDY signal to indicate that the power state of the
RT2776 is ready. The VR ready circuit is an open-drain
structure, so a pull-up resistor connected to a voltage
source is recommended.
Start-Up Sequence
The RT2776 utilizes an internal soft-start sequence which
strictly follows Intel VR12/IMVP7 start-up sequence
specifications. After POR = high and EN = high, the
controller considers all the power inputs ready and enters
start-up sequence. If VINITIAL = 0V, VOUT is programmed
to stay at 0V for 2ms waiting for SVID command. If V
INITIAL = 1.1V, VOUT will ramp up to VINITIAL voltage (which
is not zero) immediately after both POR = high and EN =
high. After VOUT reaches target VINITIAL, VOUT will stay at
VINITIAL waiting for SVID command. After the RT2776
VCC12
VCC5
Power Down Sequence
Similar to the start-up sequence, the RT2776 also utilizes
a soft shutdown mechanism during turn-off. After EN =
low, the internal reference voltage (positive terminal of
compensation EA) starts ramping down with 3.125mV/μs
slew rate, and VOUT will follow the reference voltage to 0V.
After VOUT drops below 0.2V, the RT2776 shuts down and
all functions (drivers) are disabled. The VR_RDY will be
pulled down immediately after POR = low or EN = low.
4V
3.5V
4.2V
3.7V
POR
EN
SVID
Valid
XX
xx
2ms
0.2V
VOUT,CORE
UGATE
Hi-Z
SVID defined
Hi-Z
MAX Phases
MAX Phases
100µs
VR_RDY
0.2V
VOUT,AXG
PWMA
Hi-Z
SVID defined
Hi-Z
1 Phase CCM
1 Phase CCM
Figure 7 (a). Power Sequence for VINITIAL = 0V
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DS2776-01 January 2014
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31
RT2776
VCC12
VCC5
4V
3.5V
4.2V
3.7V
POR
EN
SVID
Valid
XX
xx
2ms
VINITIAL = 1.1V
0.2V
VOUT,CORE
UGATE
Hi-Z
SVID defined
Hi-Z
MAX Phases
MAX Phases
100µs
VR_RDY
VINITIAL = 1.1V
0.2V
VOUT,AXG
PWMA
Hi-Z
SVID defined
Hi-Z
1 Phase CCM
1 Phase CCM
Figure 7 (b). Power Sequence for VINITIAL = 1.1V
CORE VR
Active Phase Determination : Before POR
The number of active phases is determined by the internal
circuitry that monitors the ISENxN voltages during startup. Normally, the CORE VR operates as a 3-phase PWM
controller. Pulling ISEN3N to VCC5 programs a 2-phase
operation, pulling ISEN3N and ISEN2N to VCC5 programs
a 1-phase operation. Before POR, CORE VR detects
whether the voltages of ISEN2N and ISEN3N are higher
than “VCC5 − 1V” respectively to decide how many
phases should be active. Phase selection is only active
during POR. When POR = high, the number of active
phases is determined and latched. The unused ISENxP
pins are recommended to be connected to VCC5.
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32
Loop Control Introduction
The CORE VR adopts Richtek's proprietary G-NAVPTM
topology. G-NAVPTM is based on the finite gain peak current
mode with CCRCOT (Constant Current Ripple Constant
On-Time) topology. The control loop consists of PWM
modulators with power stages, current sense amplifiers
and an error amplifier as shown in Figure 8. Similar to the
peak current mode control with finite compensator gain,
the HS_FET on-time is determined by CCRCOT on-time
generator. When load current increases, VCS increases,
the steady state COMP voltage also increases and induces
VOUT,CORE to decrease, thus achieving AVP to meet Intel's
load line specification. A near-DC offset canceling is added
to the output of EA to eliminate the inherent output offset
of finite gain peak current mode controller.
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DS2776-01 January 2014
RT2776
Since the DCR of the inductor is temperature dependent,
it affects the output accuracy at hot conditions.
Temperature compensation is recommended for the
lossless inductor DCR current sense method. Figure 10
shows a simple but effective way of compensating the
temperature variations of the sense resistor using an NTC
thermistor placed in the feedback path.
VIN, CORE
HS_FET
RX
COMP2
VOUT, CORE
L
CX
RC
LS_FET
+
-
CMP
UGATEx
CCRCOT
Driver
PWM
LGATEx
Logic
AI
VCS
+
-
C
ISENxP
ISENxN
C2
C2
Offset
Canceling
R2
COMP
FB
RGND
R1
EA
+
VSS_SENSE
VDAC, CORE
Droop Setting (with Temperature Compensation)
It's very easy to achieve Active Voltage Positioning (AVP)
by properly setting the error amplifier gain due to the native
droop characteristics. The target is to have
VOUT = VDAC − ILOAD x RDROOP
(1)
Then solving the switching condition VCOMP2 = VCS in
Figure 8 yields the desired error amplifier gain AV as
AI × RSENSE
RDROOP
(2)
where AI is the internal current sense amplifier gain 10V/
V. RSENSE is the current sense resistor. Figure 9 shows
the error amplifier gain (AV) influence on VOUT accuracy
according to equation (2). In general, the DCR of the
inductor is adopted as RSENSE to achieve lossless current
sensing method. RDROOP is the equivalent load line
resistance as well as the desired static output impedance.
VOUT
FB
RGND
R1a
R1b
VCC_SENSE
RNTC
VSS_SENSE
Figure 10. Loop Setting with Temperature
Compensation
Usually, R1a is set to equal RNTC (25°C). R1b is selected
to linearize the NTC's temperature characteristic. For a
given NTC, design is to get R1b and R2 and then C1 and
C2. According to equation (2), to compensate the
temperature variations of the sense resistor, the error
amplifier gain (AV) should have the same temperature
coefficient with RSENSE. Hence
A V, HOT
RSENSE, HOT
(3)
=
A V, COLD RSENSE, COLD
From equation (2), AV can be obtained at any temperature
(T°C) as shown below :
A V, T °C =
R2
R1a // RNTC, T °C + R1b
(4)
The standard formula for the resistance of NTC thermistor
as a function of temperature is given by :
RNTC, T°C = R25°C
{(
e
) ( )}
1
β⎡
− 1 ⎤
⎢⎣ T+273
298 ⎥⎦
(5)
where R25°C is the thermistor's nominal resistance at room
temperature, β is the thermistor's material constant in
Kelvins, and T is the thermistor's actual temperature in
Celsius.
AV2 > AV1
AV2
AV1
0
R2
VDAC
Figure 8. CORE VR : Simplified Schematic for Droop
and Remote Sense in CCM
A V = R2 =
R1
COMP
VCC_SENSE
+
+
EA
+
C1
C1
The DCR value at different temperature can be calculated
by the following equation :
DCRT°C = DCR25°C x [1 + 0.00393 x (T − 25)]
Load Current
Figure 9. Error Amplifier gain (AV) Influence on Load Line
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS2776-01 January 2014
(6)
where 0.00393 is the temperature coefficient of copper.
For a given NTC thermistor, solving equation (4) at room
temperature (25°C) yields :
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33
RT2776
R2 = AV,
25°C
x (R1b + R1a // RNTC, 25°C)
(7)
where AV, 25°C is the error amplifier gain at room temperature
and can be obtained from equation (2). R1b can be obtained
by substituting (7) for (3),
R1b =
RSENSE, HOT
× (R1a / /RNTC, HOT ) − (R1a // RNTC, COLD )
RSENSE, COLD
RSENSE, HOT ⎞
⎛
⎜1 − R
⎟
SENSE, COLD ⎠
⎝
(8)
Loop Compensation
Optimized compensation of the CORE VR allows for best
possible load step response of the regulator's output. A
type-I compensator with one pole and one zero is adequate
for proper compensation. Figure 10 shows the
compensation circuit. Previous design procedure shows
how to select resistive feedback components for the error
amplifier gain. Next, C1 and C2 must be calculated for
compensation. The target is to achieve constant resistive
output impedance over the widest possible frequency
range. The pole frequency of the compensator must be
set to compensate the output capacitor ESR zero :
fP =
1
2 × π × C × RC
(9)
where C is the capacitance of output capacitor, and RC is
the ESR of output capacitor. C2 can be calculated as
follows :
C × RC
(10)
C2 =
R2
The zero of compensator has to be placed at half of the
switching frequency to filter the switching related noise.
Such that,
1
C1 =
(11)
(R1b + R1a // RNTC, 25°C ) × π × fSW
TON Setting
High frequency operation optimizes the application for the
smaller component size, trading off efficiency due to higher
switching related losses. This may be acceptable in ultra
portable devices where the load currents are lower and
the controller is powered from a lower voltage supply. Low
frequency operation offers the best overall efficiency at
the expense of component size and board space. Constant
on time control is adopted in RT2776, a constant on time
can be set by connecting a resistor from VIN to TONSET
pin first, and then the switching frequency of the regulator
can be decided to apply in different applications. Figure
11 shows the On-Time setting Circuit. Connect a resistor
(RTON) between VIN,CORE and TONSET to set the on-time
of UGATE :
−12
24.4 × 10
× RTON
(12)
tON (VDAC < 1.2V) =
VIN − VDAC
where tON is the UGATE turn on period, VIN is Input voltage
of the CORE VR, and VDAC is the DAC voltage. When
VDAC is larger than 1.2V, the equivalent switching
frequency may be over 500kHz, and this too fast switching
frequency is unacceptable. Therefore, the CORE VR
implements a pseudo constant frequency technology to
avoid this disadvantage of CCRCOT topology. When VDAC
is larger than 1.2V, the on-time equation will be modified
to :
tON (VDAC ≥ 1.2V) =
−12
20.33 × 10
× RTON × VDAC
VIN − VDAC
(13)
During PS2/PS3 operation, the CORE VR shrinks its ontime for the purpose of reducing output voltage ripple
caused by DCM operation. The shrink percentage is 15%
compared with original on-time setting by equation (12)
or (13). That is, after setting the PS0 operation on-time,
the PS2/PS3 operation on-time is 0.85 times the original
on-time. On-time translates only roughly to switching
frequencies. The on-times guaranteed in the Electrical
Characteristics are influenced by switching delays in
external HS-FET. Also, the dead-time effect increases the
effective on-time, which in turn reduces the switching
frequency. It occurs only in CCM and during dynamic output
voltage transitions, when the inductor current reverses at
light or negative load currents. With reversed inductor
current, the phase goes high earlier than normal, extending
the on-time by a period equal to the HS-FET rising dead
time. For better efficiency of the given load range, the
maximum switching frequency is suggested to be :
fS(MAX) (kHz) =
1
×
TON − THS−Delay
VDAC(MAX) + ILOAD(MAX) × ⎡⎣RON _ LS−FET + DCR − RDROOP ⎤⎦
VIN(MAX) + ILOAD(MAX) × ⎡⎣RON _ LS−FET − RON _ HS−FET ⎤⎦
(14)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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34
is a registered trademark of Richtek Technology Corporation.
DS2776-01 January 2014
RT2776
Where fS(MAX) is the maximum switching frequency, tHSDELAY is the turn-on delay of HS-FET, VDAC(MAX) is the
Maximum VDAC of application, VIN(MAX) is the Maximum
application Input voltage, ILOAD(MAX) is the maximum load
of application, RON_LS-FET is the Low side FET RDS(ON),
RON_HS-FET is the High side FET RDS(ON) ,DCR is the
inductor DCR, and RDROOP is the load line setting.
CCRCOT
On-Time
Computer
TONSET
RTON
VDAC
R1
C1
Figure 11. CORE VR : On-Time Setting with RC Filter
Differential Remote Sense Setting
The CORE VR includes differential, remote-sense inputs
to eliminate the effects of voltage drops along the PC
board traces, CPU internal power routes and socket
contacts. The CPU contains on-die sense pins, VCC_SENSE
and VSS_SENSE. Connect RGND to VSS_SENSE. Connect FB
to VCC_SENSE with a resistor to build the negative input
path of the error amplifier. The VDAC and the precision
voltage reference are referred to RGND for accurate remote
sensing.
Current Sense Setting
The current sense topology of the CORE VR is continuous
inductor current sensing. Therefore, the controller can be
less noise sensitive. Low offset amplifiers are used for
loop control and over current detection. The internal current
sense amplifier gain (Ai) is fixed to be 10. The ISENxP
and ISENxN denote the positive and negative input of the
current sense amplifier of any phase. Users can either
use a current sense resistor or the inductor's DCR for
current sensing. Using the inductor's DCR allows higher
efficiency because of lossless characteristic as shown in
Figure 12. Refer to below equation for optimum transient
performance :
0.36μH
= 3.6kΩ
1mΩ × 100nF
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS2776-01 January 2014
RX
ISENxP
DCR
CX
+ VX -
ISENxN
Considering the inductance tolerance, the resistor RX has
to be tuned on board by examining the transient voltage.
On-Time
RX =
L
Figure 12. CORE VR : Lossless Inductor Sensing
VIN, CORE
L = R ×C
X
X
DCR
VOUT, CORE
(15)
If the output voltage transient has an initial dip below the
minimum load line requirement with a slow recovery, RX
is chosen too small. Vice versa, with a resistance too
large the output voltage transient has only a small initial
dip and the recovery is too fast causing a ring back. Using
current sense resistor in series with the inductor can have
better accuracy, but the efficiency is a trade-off.
Considering the equivalent inductance (LESL) of the current
sense resistor, an RC filter is recommended. The RC filter
calculation method is similar to the above mentioned
inductor DCR sensing method.
Current Balance
The CORE VR implements internal current balance
mechanism in the current loop. The CORE VR senses
and compares per-phase current signal with average
current. If the sensed current of any particular phase is
larger than average current, the on-time of this phase will
be adjusted to be shorter, vice versa.
No Load Offset (SVID & Platform)
The CORE VR features no load offset function which
provides the possibility of wide range positive offset of
output voltage. The no-load offset function can be
implemented through the SVID interface or OFS pin. Users
can disable pin offset function by simply connecting OFS
pin to GND. The RT2776 will latch the OFS status after
POR.
If pin offset function is enabled, that the OFS pin voltage
is more than 0.6V before POR.
(16)
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35
RT2776
+ VSVID−OFS
Dynamic VID Enhancement
(17)
The pin offset voltage is set by supplying a voltage into
OFS pin. The linear range of offset pin voltage is from
0.9V to 1.83V. The pin offset voltage can be calculated as
below :
VPIN−OFS = VOFS − 1.2V
(18)
For example, supplying 1.3V at OFS pin will achieve
100mV offset at the output. Connecting a filter capacitor
between the OFS pin and GND is necessary.
Operation Mode Transition
RT2776 supports operation mode transition function at
the CORE VR for the SetPS command of Intel's VR12/
IMVP7 CPU. The default operation mode of the CORE
VR is PS0, which is full phase CCM operation. Other
operation modes include PS1 (single phase CCM
operation) and PS2 (single phase DEM operation). After
receiving SetPS command, the CORE VR will immediately
change to the new operation state. When the CORE VR
receives SetPS command of PS1 operation mode, the
CORE VR operates as a single phase CCM controller,
and only channel 1 is active. The CORE VR will disable
phase 2 and phase 3 by disabling Internal PWM logic
drivers (PWM = high impedance state). Therefore, 2
internal drivers which support tri-state shutdown are also
required for compatibility with PS1 operation mode.
Similarly, when the CORE VR receives SetPS command
of PS2 operation mode, the CORE VR operates as a single
phase DCM controller, and only channel 1 is active with
diode emulation operation. The CORE VR will disable
phase 2 and phase 3 by disabling internal PWM logic
drivers (PWM = high impedance state). Therefore, all
internal drivers which support tri-state shutdown are
required for compatibility with PS2 operation state. If the
CORE VR receives dynamic VID change command
(SetVID), the CORE VR will automatically enter PS0
operation mode and all phases will be activated. After
VOUT,CORE reaches target voltage, the CORE VR will stay
at PS0 state and ignore former SetPS command. Only
re-sending SetPS command after SetVID command will
the CORE VR be forced into PS1 or PS2 operation states
again.
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36
During a dynamic VID event, the charging (dynamic VID
up) or discharging (dynamic VID down) current causes
unwanted load-line effect which degrades the settling time
performance. The DVID pin can be used to compensate
the load-line effect, so that the output voltage can be settled
to the target value more quickly. During a dynamic VID up
event occurred, the RT2776 sources out a current (IDVID)
to DVID pin. The voltage on DVID pin is added to DAC
during DVID rising to enhance the dynamic VID
performance. Connecting a capacitor in parallel with a
resistor to DVID pin is recommended. IDVID is 8μA during a
SetVID_Fast event. If it is a SetVID_Slow event, IDVID
automatically shrinks to 2μA (if slow slew rate is 0.25 x
fast slew rate). This function is null during a dynamic VID
down event.
DAC
IDVID
Slew Rate
Control
DVID
Event
1/20
+
If then the output voltage is :
VOUT = VDAC − ILOAD × RDROOP + VPIN−OFS
+
EA
-
DVID
FB
Figure 13. DVID Compensation Circuit
Ramp Amplitude Adjust
When the CORE VR enters PS2 operation mode, the
internal ramp of CORE VR will be modified for the reason
of stability. In case of smooth transition into PS2, the
CCM ramp amplitude should be designed properly. The
RT2776 provides RSET pin for platform users to set the
ramp amplitude of the CORE VR in CCM. The criteria is
to set the ramp amplitude proportional to the on-time (when
VDAC <1.2V). The equation will be :
57.6 x 10−12 = tON x (VIN − VDAC) x 1 / RSET
where 57.6 x 10
circuit.
−12
(19)
is an internal coefficient of analog
According to equation (12), the RSET equation can be
simplified to :
RRSET = 0.4236 x RTON
(20)
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DS2776-01 January 2014
RT2776
Thermal Monitoring and Temperature Reporting
The CORE VR provides thermal monitoring function via
sensing TSEN pin voltage. Through the voltage divider
resistors, R1 and RNTC, the voltage of TSEN will be
proportional to VR temperature. When VR temperature
rises, TSEN voltage also rises. The ADC circuit of the
CORE VR monitors the voltage variation at the TSEN pin
from 1.46V to 1.845V with 55mV resolution. This voltage
is then decoded into digital format and stored into
Temperature_Zone register.
To meet Intel's VR12/IMVP7 specification, platform users
have to set the TSEN voltage to meet the temperature
variation of VR from 75% to 100% VR max temperature.
For example, if the VR max temperature is 100°C, platform
users have to set the TSEN voltage to be 1.515V when
VR temperature reaches 82°C and 1.845V when VR
temperature reaches 100°C. Detailed voltage setting
versus temperature variation is shown in Table 4. The
thermometer code is implemented in Temperature_Zone
register.
VCC5
R1
RNTC
R2
TSEN
R3
Figure 14. CORE VR : Thermal Monitoring Circuit
Table 4. Temperature_Zone Register
VRHOT
b7
100%
1.845V
SVID Thermal
Alert
b6
97%
1.79V
Comparator Trip Points Temperatures Scaled to maximum = 100%
Voltage Represents Assert bit Minimum Level
b5
b4
b3
b2
b1
b0
94%
91%
88%
85%
82%
75%
1.735V
1.68V
1.625V
1.57V
1.515V
1.46V
The VRHOT pin is an open-drain structure that sends out
active low VRHOT signal. When b6 of Temperature_Zone
register asserts to 1 (when TSEN voltage rises above
1.79V), the ALERT signal will be asserted to low, which is
so-called SVID thermal alert. In the mean time, the CORE
VR will assert bit 1 data to 1 in Status_1 register. The
ALERT assertion will be de-asserted when b5 of
Temperature_Zone register is de-asserted from 1 to 0
(which means TSEN voltage falls under 1.735V), and bit 1
of Status_1 register will also be cleared to 0. The bit 1
assertion of Status_1 is not latched and cannot be cleared
by GetReg command. When b7 of Temperature_Zone
register asserts to 1 (when TSEN voltage rises above
1.845V), the VRHOT signal will be asserted to low. The
VRHOT assertion will be de-asserted when b6 of
Temperature_Zone register is de-asserted from 1 to 0
(which means TSEN voltage falls under 1.79V). It is
typically recommended to connect a pull-up resistor from
the VRHOT pin to a voltage source.
voltage. In G-NAVPTM technology, the output voltage is
dependent on output current, and the current monitoring
function is achieved by this characteristic of output voltage.
Figure 15 shows the current monitoring setting principle.
The equivalent output current will be sensed from IMONFB
pin and mirrored to IMON pin. The resistor connected to
IMON pin determines voltage gain of the IMON output.
The current monitor indicator equation is shown as :
I
x RDROOP x RIMON
VIMON = LOAD
RIMONFB
(21)
where ILOAD is the output load current, RDROOP is the
equivalent load line resistance, and RIMON and RIMONFB are
the current monitor current setting resistors. In VR12/
IMVP7 specification, the voltage signal of current
monitoring will be restricted by a maximum value. Platform
designers have to select RIMON to meet the maximum
Current Monitoring and Current Reporting
voltage of IMON at full load. To find RIMON and RIMONFB
based on :
VIMON(MAX)
RIMON
(22)
=
RIMONFB IMAX x RDROOP
The CORE VR provides current monitoring function via
sensing the voltage difference of IMONFB pin and output
where the VIMON(MAX) is the maximum voltage at full load,
and IMAX is the full load current of VR.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS2776-01 January 2014
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37
RT2776
Current Mirror
FB
+
VCC_SENSE
-
IMirror
IMONFB RIMONFB
IMON
RIMON
Figure 15. CORE VR : Current Monitoring Circuit
The ADC circuit of the CORE VR monitors the voltage
variation at the IMON pin from 0V to 3.3V, and this voltage
is decoded into digital format and stored into
Output_Current register. The ADC divides 3.3V into 255
levels, so LSB = 3.3V/255 = 12.941mV. Platform designers
should design VIMON to be 3.3V at ICCMAX. For example,
when load current = 50% x ICCMAX, VIMON = 1.65V and
Output_Current register = 7Fh. The IMON pin is an output
of the internal operational amplifier and sends out IMON
signal. When the data of Output_Current register reaches
255d (when IMON voltage rises above 3.3V), the ALERT
signal will be asserted to low, which is so-called SVID
ICCMAX alert. In the mean time, the CORE VR will assert
the bit 2 data to 1 in Status_1 register. The ALERT
assertion will be de-asserted when the data of
Output_Current register decreases to 242d (when IMON
voltage falls under 3.144V). The bit 2 assertion of Status_1
register is latched and can only be cleared when two criteria
are met : the data of Output_Current register decreases
to 242d (when IMON voltage falls under 3.144V) and the
GetReg command is sent to the Status_1 register of the
CORE VR.
Quick Response
The CORE VR utilizes a quick response feature to support
heavy load current demand during instantaneous load
transient. The CORE VR monitors the current of the
IMONFB pin, and this current is mirrored to internal quick
response circuit. At steady state, this mirrored current
will not trigger a quick response. When the VOUT, CORE
voltage drops abruptly due to load apply transient, the
mirrored current flowing into quick response circuit will
also increase instantaneously. When the mirrored current
instantaneously rises above 5μA, quick response will be
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38
triggered. When quick response is triggered, the quick
response circuit will generate a quick response pulse.
The internal quick response pulse generation circuit is
similar to the on-time generation circuit. The only
difference is the QRSET pin. The voltage at the QRSET
pin also influences the pulse width of quick response. A
voltage divider circuit is recommended to be applied to
the QRSET pin. Therefore, with a little modification of
equation (12), the pulse width of quick response pulse
can be calculated as :
tON, QR =
VQRSET
× tON
1.2
=
20.33 × 10
−12
× RTON × VQRSET
VIN − VDAC
(23)
After generating a quick response pulse, the pulse is then
applied to the on-time generation circuit, and all the active
phases on-times will be overridden by the quick response
pulse.
Current Mirror
QR trigger
VDAC
+
-
IMirror
IMONFB RIMONFB
VCC_SENSE
Figure 16. CORE VR : Quick Response Triggering
Circuit
Over Current Protection
The CORE VR compares a programmable current limit
set point to the voltage from the current sense amplifier
output of each phase for Over Current Protection (OCP).
Therefore, the OCP mechanism of the RT2776 implements
per-phase current protections. The voltage applied to the
OCSET pin defines the desired current limit threshold,
ILIMIT_CORE :
VOCSET = 48 x ILIMIT_CORE x RSENSE
(24)
Connect a resistive voltage divider from VCC5 to GND,
and the joint of the resistive voltage divider is connected
to the OCSET pin as shown in Figure 17. For a given
ROC2,
⎛ V
⎞
(25)
ROC1 = ROC2 × ⎜ CC5 − 1⎟
⎝ VOCSET
⎠
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DS2776-01 January 2014
RT2776
The current limit is triggered when per-phase inductor
current exceeds the current limit threshold, ILIMIT_CORE,
as defined by VOCSET. The driver will then be forced to turn
off UGATE until the condition is cleared. If the over current
condition of any phase remains valid for 15 cycles, the
CORE VR will trigger OCP latch. Latched OCP forces
PWM into high impedance, which disables internal PWM
logic drivers. If the over current condition is not valid for 15
continuous cycles, the OCP latch counter will be reset.
When OCP is triggered by the CORE VR, the AXG VR
will also enter soft shut down sequence.
ROC1
ROC2
(27)
ROC1a // RNTC, T°C + ROC1b + ROC2
Re-write (27) from (26) to get VOCSET at room temperature
ROC1a // RNTC, COLD + ROC1b + ROC2
RSENSE, HOT
=
ROC1a // RNTC, HOT + ROC1b + ROC2
RSENSE, COLD
(28)
VOCSET, 25°C =
ROC2
ROC1a // RNTC, 25°C + ROC1b + ROC2
(29)
Solving (28) and (29) yields ROC1b and ROC2
OCSET
ROC2 =
α × REQU, HOT − REQU, COLD + (1 − α ) × REQU, 25°C
VCC5
× (1 − α )
(30)
VOCSET, 25°C
ROC1b =
ROC2
Figure 17. OCP Setting without Temperature
Compensation
If inductor DCR is used as the current sense component,
temperature compensation is recommended for proper
protection under all conditions. Figure 18 shows a typical
OCP setting with temperature compensation. Usually,
ROC1a is selected to be equal to the thermistor's nominal
resistance at room temperature. Ideally, assume VOCSET
has the same temperature coefficient as RSENSE (Inductor
DCR) :
(α − 1) × ROC2 + α × REQU, HOT − REQU, COLD
(1 − α )
(31)
where
α=
RSENSE, HOT
DCR25°C × [1 + 0.00393 x (THOT − 25)]
=
RSENSE, COLD DCR25°C × [1 + 0.00393 x (TCOLD − 25)]
(32)
REQU, T°C = ROC1a // RNTC, T°C
(33)
Over Voltage Protection (OVP)
VCC5
The over voltage protection circuit of the CORE VR
monitors the output voltage via the ISEN1N pin after POR.
NTC
ROC1b
OCSET
ROC2
Figure 18. OCP Setting without Temperature
Compensation
VOCSET, HOT
RSENSE, HOT
=
VOCSET, COLD RSENSE, COLD
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS2776-01 January 2014
= VCC5 ×
VCC5 ×
VCC5
ROC1a
According to the basic circuit calculation, we can get
VOCSET at any temperature :
VOCSET, T°C
(26)
The supported maximum operating VID of the VR (V(MAX))
is stored in the VOUT_Max register. Once VISEN1N
exceeds “V(MAX) + 150mV”, OVP is triggered and latched.
The CORE VR will try to turn on low side MOSFETs and
turn off high side MOSFETs of all active phases of the
CORE VR to protect the CPU. When OVP is triggered by
the CORE VR, the AXG VR will also enter soft shut down
sequence. A 1μs delay is used in OVP detection circuit
to prevent false trigger. Note that if OFS pin is higher than
0.9V before power up, OVP will trigger at “V(MAX) +
850mV”.
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39
RT2776
Negative Voltage Protection (NVP)
Loop Control
During OVP latch state, the CORE VR also monitors the
ISEN1N pin for negative voltage protection. Since the OVP
latch will continuously turn on all low side MOSFETs of
the CORE VR, the CORE VR may suffer negative output
voltage. As a consequence, when the ISEN1N voltage
drops below −0.05V after triggering OVP, the CORE VR
will trigger NVP to turn off all low side MOSFETs of the
CORE VR while the high side MOSFETs remains off. After
triggering NVP, if the output voltage rises above 0V, the
OVP latch will restart to turn on all low side MOSFETs.
Therefore, the output voltage may travel between 0V and
−0.05V due to OVP latch and NVP triggering. The NVP
function will be active only after OVP is triggered. A 1μs
delay is used in NVP detection circuit to prevent false
trigger.
The AXG VR adopts Richtek's proprietary G-NAVPTM
topology. G-NAVPTM is based on the finite gain peak current
mode with CCRCOT (Constant Current Ripple Constant
On-Time) topology. The output voltage, VOUT, AXG, will
decrease with increasing output load current. The control
loop consists of a PWM modulator with power stage, a
current sense amplifier and an error amplifier as shown in
Figure 19. Similar to the peak current mode control with
finite compensator gain, the HS_FET on-time is determined
by CCRCOT on-time generator. When load current
increases, VCS increases, steady state COMPA voltage
also increases and induces VOUT, AXG to decrease, thus
achieving AVP. A near-DC offset canceling is added to the
output of EA to cancel the inherent output offset of finitegain peak current mode controller.
VIN, AXG
Under Voltage Protection (UVP)
Under Voltage Lock Out (UVLO)
HS_FET
Driver
VOUT, AXG
L
RX
CMP
CX
RC
+
-
LS_FET
AI
VCS
+
-
C
ISENAP
ISENAN
C1
C2
Offset
Canceling
COMPA
EA
+
+
When UVP is triggered by the CORE VR, the AXG VR
will also enter soft shut down sequence. A 3μs delay is
used in UVP detection circuit to prevent false trigger. If
platform OFS function is enabled (OFS pin not connected
to GND), the UVP function will be disabled.
CCRCOT
PWMA
PWM
Logic
COMPA2
The CORE VR implements under voltage protection of
VOUT,CORE. If ISEN1N is less than the internal reference
by 300mV, the CORE VR will trigger UVP latch. The UVP
latch will turn off both high side and low side MOSFETs.
FBA
RGNDA
R2
R1
VCCAXG_SENSE
VSSAXG_SENSE
VDAC, CORE
Figure 19. AXG VR : Simplified Schematic for Droop and
Remote Sense in CCM
During normal operation, if the voltage at the VCC5 or
VCC12 pin drops below POR threshold, the CORE VR
will trigger UVLO. The UVLO protection forces all high
side MOSFETs and low side MOSFETs off by shutting
down internal PWM logic drivers. A 3μs delay is used in
UVLO detection circuit to prevent false trigger.
Droop Setting (with Temperature Compensation)
AXG VR
VOUT,AXG = VDAC,AXG − ILOAD x RDROOP
AXG VR Disable
, then solving the switching condition VCOMP2 = VCS in
Figure 19 yields the desired error amplifier gain as
The AXG VR can be disabled by connecting ISENAN to a
voltage higher than “VCC5 − 1V”. If not in use, ISENAP
and TSENA are recommended to be connected to VCC5,
while PWMA is left floating. When AXG VR is disabled,
all SVID commands related to AXG VR will be rejected.
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40
It's very easy to achieve Active Voltage Positioning (AVP)
by properly setting the error amplifier gain due to the native
droop characteristics. The target is to have
A V = R2 =
R1
AI x RSENSE
RDROOP
(34)
(35)
where AI is the internal current sense amplifier gain, RSENSE
is the current sense resistance (an external sense resistor
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DS2776-01 January 2014
RT2776
or the DCR of the inductor), and RDROOP is the equivalent
load line resistance as well as the desired static output
impedance. Since the DCR of the inductor is temperature
dependent, the output accuracy may be affected at high
temperature conditions. Temperature compensation is
recommended for the lossless inductor DCR current sense
method. Figure 20 shows a simple but effective way of
compensating the temperature variations of the sense
resistor by using an NTC thermistor placed in the feedback
path.
C2
R2
COMPA
R1b
R1a
VCCAXG_SENSE
RNTC
+
RGNDA
VSSAXG_SENSE
VDAC,AXG
Figure 20. AXG VR : Loop Setting with Temperature
Compensation
Usually, R1a is set to equal RNTC (25°C) and R1b is selected
to linearize the NTC's temperature characteristic. For a
given NTC, the design procedure is to get R1b and R2
first, and then C1 and C2 next. According to equation (35),
to compensate the temperature variations of the sense
resistor, the error amplifier gain (AV) should have the same
temperature coefficient as RSENSE. Hence :
A V, HOT
RSENSE, HOT
=
A V, COLD RSENSE, COLD
(36)
as :
R2
R1a // RNTC, T °C + R1b
(37)
The standard formula for the resistance of NTC thermistor
as a function of temperature is given by :
{(
RNTC, T°C = R25°C e
25°C
) ( )}
1
β⎡
− 1 ⎤
298 ⎦⎥
⎣⎢ T+273
(38)
Optimized compensation of the AXG VR allows for best
possible load step response of the regulator's output. A
type-I compensator with one pole and one zero is adequate
for a proper compensation. Figure 20 shows the
compensation circuit. Previous design procedure shows
how to select the resistive feedback components for the
error amplifier gain. Next, C1 and C2 must be calculated
for compensation. The target is to achieve constant
resistive output impedance over the widest possible
frequency range.
The pole frequency of the compensator must be set to
compensate the output capacitor ESR zero :
1
2 × π × C × RC
C × RC
(43)
R2
The zero of compensator has to be placed at half of the
switching frequency to filter the switching related noise.
Such that,
C2 =
1
TON Setting
where 0.00393 is the temperature coefficient of copper.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
(42)
where C is the capacitance of output capacitor, and RC is
the ESR of output capacitor. C2 can be calculated as
below :
temperature, β is the thermistor's material constant in
Kelvins, and T is the thermistor actual temperature in
Celsius. To calculate DCR value at different temperatures,
use the equation below :
(39)
(41)
Loop Compensation
C1 =
DCRT°C = DCR25°C x [1+ 0.00393 x (T − 25)]
(40)
RSENSE, HOT ⎞
⎛
⎜1 − R
⎟
SENSE, COLD ⎠
⎝
where R25°C is the thermistor's nominal resistance at room
DS2776-01 January 2014
x (R1b + R1a // RNTC, 25°C)
where AV, 25°C is the error amplifier gain at room temperature
and can be obtained from equation (35). R1b can be
obtained by substituting (40) to (36),
R1b =
RSENSE, HOT
× (R1a // RNTC, HOT ) − (R1a // RNTC, COLD )
RSENSE, COLD
fP =
From (33), Av can be obtained at any temperature (T°C)
A V, T °C =
R2 = AV,
C1
FBA
EA
+
For a given NTC thermistor, solving equation (37) at room
temperature (25°C) yields
(R1b + R1a // RNTC, 25°C ) × π × fSW
(44)
High frequency operation optimizes the application by
allowing smaller component size, but with the trade-off of
efficiency due to higher switching losses. This may be
acceptable in ultra portable devices where the load currents
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41
RT2776
are lower and the controller is powered from a lower voltage
supply. Low frequency operation offers the best overall
efficiency at the expense of component size and board
space. Figure 21 shows the on-time setting circuit.
Connect a resistor (RTON) between VIN,AXG and TONSETA
pin to set the on-time of UGATE :
tON (VDAC
24.4 × 10−12 × RTON
< 1.2V) =
VIN − VDAC,AXG
TONSETA
RTON
R1
VIN, AXG
C1
VDAC, AXG
On-Time
Figure 21. AXG VR : On-Time setting with RC Filter
(45)
where tON is the UGATE turn-on period, VIN is the input
voltage of the AXG VR, and VDAC, AXG is the DAC voltage.
When VDAC, AXG is larger than 1.2V, the equivalent switching
frequency may be too fast at over 500kHz, which is
unacceptable. Therefore, the AXG VR implements a pseudo
constant frequency technology to avoid this disadvantage
of CCRCOT topology. When VDAC, AXG is larger than 1.2V,
the on-time equation will be modified to :
−12
t ON (VDAC ≥ 1.2V) =
CCRCOT
On-Time
Computer
20.33 × 10
× RTON × VDAC, AXG
VIN − VDAC, AXG
(46)
Differential Remote Sense Setting
The AXG VR includes differential, remote sense inputs to
eliminate the effects of voltage drops along the PC board
traces, CPU internal power routes and socket contacts.
The CPU contains on-die sense pins VCCAXG_SENSE and
VSSAXG_SENSE. Connect the RGNDA to VSSAXG_SENSE.
Connect the FBA to VCCAXG_SENSE with a resistor to build
the negative input path of the error amplifier. The VDAC,AXG
and the precision voltage reference are referred to RGNDA
for accurate remote sensing.
Current Sense Setting
On-time translates only roughly to switching frequencies.
The on-times guaranteed in the Electrical Characteristics
are influenced by switching delays in the external HSFET. Also, the dead-time effect increases the effective
on-time, which in turn reduces the switching frequency. It
occurs only in CCM, and during dynamic output voltage
transitions when the inductor current reverses at light or
negative load currents. With reversed inductor current,
the phase goes high earlier than normal, extending the
on-time by a period equal to the HS-FET rising dead time.
The current sense topology of the AXG VR is continuous
inductor current sensing. Therefore, the controller can be
less noise sensitive. Low offset amplifiers are used for
loop control and over current detection. The internal current
sense amplifier gain (AI) is fixed to be 20. The ISENAP
and ISENAN denote the positive and negative input of the
current sense amplifier. Users can either use a current
sense resistor or the inductor's DCR for current sensing.
Using inductor's DCR allows higher efficiency as shown
in Figure 22. Refer to below equation for optimum transient
performance :
For better efficiency of the given load range, the maximum
L = R ×C
(48)
switching frequency is suggested to be :
X
X
DCR
1
For example, choosing L = 0.36μH with 1mΩ DCR and CX
fS(MAX) (kHz) =
×
tON − THS−Delay
= 100nF yields :
VDAC(MAX) + ILOAD(MAX) × ⎡⎣RON _ LS−FET + DCR − RDROOP ⎤⎦
0.36μH
RX =
= 3.6kΩ
(49)
1m
Ω × 100nF
VIN(MAX) + ILOAD(MAX) × ⎡⎣RON _ LS−FET − RON _ HS−FET ⎤⎦
VOUT, AXG
(47)
where fS(MAX) is the maximum switching frequency, tHSL
DCR
is
the
turn-on
delay
of
HS-FET,
V
is
the
DAC(MAX)
DELAY
CX
RX
maximum VDAC, AXG of application, VIN(MAX) is the maximum
application input voltage, ILOAD(MAX) is the maximum load
+ VX ISENAP
of application, RON_LS-FET is the Low side FET RDS(ON),
ISENAN
RON_HS-FET is the High side FET RDS(ON), DCR is the
inductor DCR, and RDROOP is the load line setting.
Figure 22. AXG VR : Lossless Inductor Sensing
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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42
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DS2776-01 January 2014
RT2776
Considering the inductance tolerance, the resistor RX has
to be tuned on board by examining the transient voltage.
If the output voltage transient has an initial dip below the
minimum load line requirement with a slow recovery, RX
is chosen too small. Vice versa, if the resistance is too
large the output voltage transient has only a small initial
dip and the recovery becomes too fast, causing a ring
back to occur. Using current sense resistor in series with
the inductor can have better accuracy, but at the expense
of efficiency. Considering the equivalent inductance (LESL)
of the current sense resistor, an RC filter is recommended.
The RC filter calculation method is similar to the above
mentioned inductor DCR sensing method.
new operation state. When the AXG VR receives SetPS
command of PS2 operation mode, the AXG VR operates
as a single phase DCM controller and diode emulation
operation is activated. Therefore, an external driver which
supports tri-state shutdown is required for compatibility
with PS2 operation state.
No Load Offset (SVID & Platform)
Dynamic VID Enhancement
The AXG VR features no load offset function which provides
the possibility of wide range positive offset of output voltage.
The no load offset function can be implemented through
the SVID interface or OFSA pin. Users can disable pin
offset function by simply connecting OFSA pin to GND.
The RT2776 will latch the OFSA status after POR. If pin
offset function is enabled, the OFSA pin voltage is more
than 0.6V before POR.
During a dynamic VID event, the charging (dynamic VID
up) or discharging (dynamic VID down) current causes
unwanted load-line effect which degrades the settling time
performance. The DVIDA pin can be used to compensate
the load-line effect, so that the output voltage can be settled
to the target value more quickly.
If then the output voltage is
VOUT = VDAC − ILOAD × RDROOP + VPIN−OFS
+ VSVID−OFS
(50)
The pin offset voltage is set by supplying a voltage into
OFSA pin. The linear range of offset pin voltage is from
0.9V to 1.83V. The pin offset voltage can be calculated as
below :
VPIN−OFSA = VOFSA − 1.2V
If the AXG VR receives dynamic VID change command
(SetVID), the AXG VR will automatically enter PS0
operation mode. After VOUT, AXG reach target voltage, AXG
VR will stay at PS0 state and ignore former SetPS
command. Only by resending SetPS command after
SetVID command will the AXG VR be forced into PS2
operation state again.
During a dynamic VID up event occurred, the RT2776
sources out a current (IDVIDA) to DVIDA pin. The voltage
on DVIDA pin is added to DAC during DVID rising to
enhance the dynamic VID performance. Connecting a
capacitor in parallel with a resistor to DVIDA pin is
recommended. IDVIDA is 8μA during a SetVID_Fast event.
If it is a SetVID_Slow event, IDVIDA automatically shrinks
to 2μA (if slow slew rate is 0.25x fast slew rate). This
function is null during a dynamic VID down event.
(51)
For example, supplying 1.3V at OFSA pin will achieve
100mV offset at the output. Connecting a filter capacitor
between the OFSA pin and GND is necessary.
DAC
Slew Rate
Control
IDVIDA
DVID
Event DVIDA
The RT2776 supports operation mode transition function
at AXG VR for the SetPS command of Intel VR12/IMVP7
CPU. The default operation mode of the AXG VR is PS0,
which is CCM operation. Other operation mode includes
PS2 (single phase DEM operation). After receiving SetPS
command, the AXG VR will immediately change to the
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS2776-01 January 2014
+
Operation Mode Transition
+
EA
-
1/20
FBA
Figure 23. DVID Compensation Circuit
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43
RT2776
Thermal Monitoring and Temperature Reporting
The AXG VR provides thermal monitoring function via
sensing TSENA pin voltage. Through the voltage divider
resistors, R1 and RNTC, the voltage of TSENA will be
proportional to VR temperature. When VR temperature
rises, the TSENA voltage also rises. The ADC circuit of
the AXG VR monitors the voltage variation at the TSENA
pin from 1.46V to 1.845V with 55mV resolution. This
voltage is then decoded into digital format and stored into
Temperature_Zone register. To meet Intel's VR12/IMVP7
specification, platform users have to set the TSENA voltage
to meet the temperature variation of VR from 75% to 100%
VR max temperature.
For example, if the VR max temperature is 100°C, platform
users have to set the TSENA voltage to be 1.46V when
VR temperature reaches 75°C and 1.845V when VR
temperature reaches 100°C. Detailed voltage setting versus
temperature variation is shown in Table 5. The thermometer
code is implemented in Temperature_Zone register.
VCC5
R1
RNTC
TSENA
R3
Figure 24. AXG VR : Thermal Monitoring Circuit
Table 5. Temperature_Zone register
SVID Thermal Alert
b7
100%
1.845V
b6
97%
1.79V
Comparator Trip Points
Temperatures Scaled to maximum = 100%
Voltage Represents Assert bit Minimum Level
b5
94%
1.735V
b4
91%
1.68V
b3
88%
1.625V
b2
85%
1.57V
b1
b0
82%
75%
1.515V 1.46V
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44
When b7 of Temperature_Zone register asserts to 1 (when
TSENA voltage rises above 1.845V), the VRHOT signal
will be asserted to low. The VRHOT assertion will be deasserted when b6 of Temperature_Zone register is deasserted from 1 to 0 (which means TSENA voltage falls
under 1.79V). The thermal monitoring function of the AXG
VR can be disabled by connecting TSENA to VCC5. If
TSENA is disabled, all the SVID commands related to
Tmperature_Zone register of the AXG VR will be rejected.
Current Monitoring and Current Reporting
The AXG VR provides current monitoring function via
sensing the IMONFBA pin. In G-NAVPTM technology, the
R2
VRHOT
The VRHOT pin is an open-drain structure that sends out
active-low VRHOT signal. When b6 of Temperature_Zone
register asserts to 1 (when TSENA voltage rises above
1.79V), the ALERT signal will be asserted to low, which is
so-called SVID thermal alert. In the mean time, the AXG
VR will assert the bit 1 data to 1 in Status_1 register. The
ALERT assertion will be de-asserted when b5 of
Temperature_Zone register is de-asserted from 1 to 0
(which means TSENA voltage falls under 1.735V), and
the bit 1 of Status_1 register will also be cleared to 0. The
bit 1 assertion of Status_1 is not latched and cannot be
cleared by GetReg command.
output voltage is dependent on the output current, and
the current monitoring function is achieved by this output
voltage characteristic. Figure 25 shows the current
monitoring setting principle. The equivalent output current
will be sensed from the IMONFBA pin and mirrored to the
IMONA pin. The resistor connected to the IMONA pin
determines the voltage gain of the IMONA output. The
current monitor indicator equation is shown as :
I
× RDROOP × RIMONA
(52)
VIMONA = LOAD
RIMONFBA
Where ILOAD is the output load current, RDROOP is the
equivalent load line resistance, and RIMONA and RIMONFBA
are the current monitor current setting resistors. In VR12/
IMVP7 specification, the voltage signal of current
monitoring will be restricted by a maximum value. Platform
designers have to select R IMONA to meet the maximum
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RT2776
voltage of IMONA at full load. Find RIMONA and RIMONFBA
based on :
VIMONA(MAX)
RIMONA
=
(53)
RIMONFBA IMAX × RDROOP
where VIMONA(MAX) is the maximum voltage at full load,
and IMAX is the full load current of VR.
Current Mirror
FBA
+
VCCAXG_SENSE
-
IMONFBA RIMONFBA
IMirror
IMONA
RIMONA
Figure 25. AXG VR : Current Monitoring Circuit
The ADC circuit of the AXG VR monitors the voltage
variation at the IMONA pin from 0V to 3.3V, and this
voltage is decoded into digital format and stored into the
Output_Current register. The ADC divides 3.3V into 255
levels, so LSB = 3.3V/255 = 12.941mV. Platform
designers should design VIMONA to be 3.3V at ICCMAXA.
For example, when load current = 50% x ICCMAXA,
VIMONA = 1.65V and Output_Current register = 7Fh. The
IMONA pin is an output of the internal operational amplifier
and sends out IMONA signal. When the data of
Output_Current register reaches 255d (when IMONA
voltage rises above 3.3V), the ALERT signal will be
asserted to low, which is so-called SVID ICCMAXA alert.
In the mean time, the AXG VR will assert the bit 2 data to
1 in Status_1 register. The ALERT assertion will be deasserted when the data of Output_Current register
decreases to 242d (when IMONA voltage falls under
3.144V). The bit 2 assertion of Status_1 register is latched
and can only be cleared when two criteria are met : the
data of Output_Current register decreases to 242d (when
IMONA voltage falls under 3.144V) and the GetReg
command is sent to the Status_1 register of the AXG VR.
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Quick Response
The AXG VR utilizes a quick response feature to support
heavy load current demand during instantaneous load
transient. The AXG VR monitors the current of the
IMONFBA pin, and this current is mirrored to internal quick
response circuit. At steady state, this mirrored current
will not trigger a quick response. When the VOUT, AXG voltage
drops abruptly due to load apply transient, the mirrored
current into quick response circuit will also increase
instantaneously. When the mirrored current
instantaneously rises above 5μA, quick response will be
triggered.
When quick response is triggered, the quick response
circuit will generate a quick response pulse. The internal
quick response pulse generation circuit is similar to the
on-time generation circuit. The only difference is the
QRSETA pin. The voltage at the QRSETA pin also
influences the pulse width of quick response. A voltage
divider circuit is recommended to be applied to the
QRSETA pin. Therefore, with a little modification of
equation (45), the pulse width of quick response pulse
can be calculated as :
tON, QR =
=
VQRSETA
× tON
1.2
−12
20.33 × 10
× RTON × VQRSETA
VIN − VDAC, AXG
(54)
After generating a quick response pulse, the pulse is then
applied to the on-time generation circuit and the AXG VR's
on-time will be overridden by the quick response pulse.
Over Current Protection
The AXG VR compares a programmable current limit set
point to the voltage from the current sense amplifier output
for Over Current Protection (OCP). Therefore, the OCP
mechanism of the RT2776 implements per-phase current
protection. The voltage applied to the OCSETA pin defines
the desired current limit threshold ILIMIT_AXG :
VOCSETA = 48 x ILIMIT_AXG x RSENSE
(55)
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RT2776
Connect a resistive voltage divider from VCC5 to GND,
and the joint of the resistive voltage divider is connected
to the OCSETA pin as shown in Figure 26. For a given
ROC2,
⎛ V
⎞
ROC1 = ROC2 × ⎜ CC5 − 1⎟
V
⎝ OCSET
⎠
VCC5
Usually, ROC1a is selected to be equal to the thermistor's
nominal resistance at room temperature. Ideally, assume
VOCSET has the same temperature coefficient as RSENSE
(Inductor DCR) :
VOCSETA, HOT
RSENSE, HOT
=
VOCSETA, COLD RSENSE, COLD
(56)
According to the basic circuit calculation, we can get
VOCSETA at any temperature :
ROC1
VOCSETA, T°C =
OCSETA
ROC2
VCC5 ×
ROC2
ROC1a // RNTC, 25°C + ROC1b + ROC2
(57)
Re-write (56) from (57) to get VOCSETA at room temperature:
Figure 26. AXG VR : OCP Setting without Temperature
Compensation
The current limit is triggered when inductor current
exceeds the current limit threshold, ILIMIT_AXG, as defined
by VOCSETA. The driver will then be forced to turn off UGATE
until the condition is cleared. If the over current condition
of any phase remains valid for 15 cycles, the AXG VR will
trigger OCP latch. Latched OCP forces PWM into high
impedance, which disables internal PWM logic drivers. If
the over current condition is not valid for 15 continuous
cycles, the OCP latch counter will be reset. When OCP
is triggered by the AXG VR, the CORE VR will also enter
soft shut down sequence. If inductor DCR is used as the
current sense component, temperature compensation is
recommended for proper protection under all conditions.
Figure 26 shows a typical OCP setting with temperature
compensation.
VCC5
ROC1a
(58)
VOCSETA, 25°C =
VCC5 ×
ROC2
ROC1a // RNTC, 25°C + ROC1b + ROC2
(59)
Solving (62) and (63) yields ROC1b and ROC2
ROC2 =
α × REQU, HOT − REQU, COLD + (1 − α ) × REQU, 25°C
VCC5
(60)
× (1 − α )
VOCSETA, 25°C
ROC1b =
(α − 1) × ROC2 + α × REQU, HOT − REQU, COLD
(1 − α )
(61)
where
α=
RSENSE, HOT
DCR25°C × [1 + 0.00393 × (THOT − 25)]
=
RSENSE, COLD DCR25°C × [1 + 0.00393 × (TCOLD − 25)]
(62)
REQU, T°C = ROC1a // RNTC, T°C
(63)
NTC
ROC1b
OCSETA
ROC2
Figure 27. AXG VR : OCP Setting with Temperature
Compensation
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46
ROC1a // RNTC, COLD + ROC1b + ROC2
RSENSE, HOT
=
ROC1a // RNTC, HOT + ROC1b + ROC2
RSENSE, COLD
Over Voltage Protection (OVP)
The over voltage protection circuit of the AXG VR monitors
the output voltage via the ISENAN pin after POR. The
supported maximum operating VID of the VR (V(MAX)) is
stored in the VOUT_Max register. Once VISENAN exceeds
“V(MAX) + 150mV”, OVP is triggered and latched. The
AXG VR will try to turn on low side MOSFETs and turn off
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RT2776
high side MOSFETs of the AXG VR to protect the CPU.
When OVP is triggered by the AXG VR, the CORE VR
will also enter shut down sequence. A 1μs delay is used
in OVP detection circuit to prevent false trigger. Note that
if OFSA pin is higher than 0.9V before power up, OVP
would trigger when “V(MAX) + 850mV”.
Output LC Filter
Inductor Selection
The switching frequency and ripple current determine the
inductor value as follows :
LMIN =
VIN − VOUT
× TON
IRipple(MAX)
(64)
Negative Voltage Protection (NVP)
During OVP latch state, the AXG VR also monitors the
ISENAN pin for negative voltage protection. Since the OVP
latch continuously turns on all low side MOSFETs of the
AXG VR, the AXG VR may suffer negative output voltage.
As a consequence, when the ISENAN voltage drops below
−0.05V after triggering OVP, the AXG VR will trigger NVP
to turn off all low side MOSFETs of the AXG VR while the
high side MOSFETs remains off. After triggering NVP, if
the output voltage rises above 0V, the OVP latch will restart
to turn on all low side MOSFETs.
Therefore, the output voltage may bounce between 0V
and −0.05V due to OVP latch and NVP triggering. The
NVP function will be active only after OVP is triggered. A
1μs delay is used in NVP detection circuit to prevent false
trigger.
Under Voltage Protection (UVP)
The AXG VR implements under voltage protection of VOUT,
AXG, if VFBA is less than the internal reference by 300mV,
the AXG VR will trigger UVP latch. The UVP latch will
turn off both high side and low side MOSFETs. When
UVP is triggered by the AXG VR, the CORE VR will also
enter soft shut down sequence. A 3μs delay is used in
UVP detection circuit to prevent false trigger. If platform
OFSA function is enabled (OFSA pin not connected to
GND), the UVP function will be disabled.
Under Voltage Lock Out (UVLO)
During normal operation, if the voltage at the VCC5 or
VCC12 pin drops below POR threshold, the AXG VR will
trigger UVLO. The UVLO protection forces all high side
MOSFETs and low side MOSFETs off by shutting down
internal PWM logic driver. A 3μs delay is used in UVLO
detection circuit to prevent false trigger.
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DS2776-01 January 2014
where TON is the UGATE turn-on period. Higher inductance
yields in less ripple current and hence higher efficiency.
The downside is a slower transient response of the power
stage to load transients. This might increase the need for
more output capacitors, thus driving up the cost. Select a
low loss inductor having the lowest possible DC resistance
that fits in the allotted dimensions. The core must be large
enough not to be saturated at the peak inductor current.
Output Capacitor Selection
Output capacitors are used to obtain high bandwidth for
the output voltage beyond the bandwidth of the converter
itself. Usually, the CPU manufacturer recommends a
capacitor configuration. Two different kinds of output
capacitors are typically used : bulk capacitors closely
located next to the inductors, and ceramic output
capacitors in close proximity to the load. Latter ones are
for mid-frequency decoupling with especially small ESR
and ESL values, while the bulk capacitors have to provide
enough stored energy to overcome the low frequency
bandwidth gap between the regulator and the CPU.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
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RT2776
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-56L 7x7 package, the thermal resistance, θJA, is
31°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :
Layout Considerations
Careful PC board layout is critical to achieve low switching
losses and clean, stable operation. The switching power
stage requires particular attention. If possible, mount all
of the power components on the top side of the board
with their ground terminals flushed against one another.
Follow these guidelines for PC board layout
considerations :
`
Input ceramic capacitors must be placed to the drain of
high side FET and source of low side FET as close as
possible. The loop (The drain of high side FET to phase
node to the source of low side FET) is very critical due
to it is the main EMI source in Buck converter, so the
loop has to be minimized.
`
Keep the high current paths short, especially at the
ground terminals.
`
Keep the power traces and load connections short. This
is essential for high efficiency.
`
When trade-offs in trace lengths must be made, it's
preferable to let the inductor charging path be longer
than the discharging path.
`
Place the current sense component close to the
controller. ISENxP and ISENxN connections for current
limit and voltage positioning must be made using Kelvin
sense connections to guarantee current sense accuracy.
`
The PCB trace from the sense nodes should be
paralleled back to the controller.
`
Route high speed switching nodes away from sensitive
analog areas (COMP, FB, ISENxP, ISENxN, etc...)
PD(MAX) = (125°C − 25°C) / (31°C/W) = 3.226W for
WQFN-56L 7x7 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 26 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Maximum Power Dissipation (W)1
3.5
Four-Layers PCB
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
Ambient Temperature (°C)
125
Figure 26. Derating Curve of Maximum Power
Dissipation
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DS2776-01 January 2014
RT2776
Outline Dimension
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
6.900
7.100
0.272
0.280
D2
5.150
5.250
0.203
0.207
E
6.900
7.100
0.272
0.280
E2
5.150
5.250
0.203
0.207
e
L
0.400
0.350
0.016
0.450
0.014
0.018
W-Type 56L QFN 7x7 Package
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DS2776-01 January 2014
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RT2776
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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