Freescale Semiconductor Application Note Document Number: AN5113 Rev. 1.0, 4/2015 Powering an i.MX 6SL Based System Using the PF3000 PMIC 1 Introduction The PF3000 is a SMARTMOS highly integrated Power Management IC, ideally suited to power Freescale's i.MX 6SL, i.MX 6S, i.MX 6DL, and the i.MX 7 series of application processors. This application note discusses the power tree configuration for powering an i.MX6SL based system using the PF3000. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 PF3000 Voltage Regulators . . . . . . . . . . . . . . . . . . . . . 2 3 i.MX 6SL Power Management Using the PF3000 . . . . . 3 4 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 © Freescale Semiconductor, Inc., 2015. All rights reserved. PF3000 Voltage Regulators 2 PF3000 Voltage Regulators Table 1. shows a summary of the voltage regulators in the PF3000. Output voltage and startup sequence of the regulators is programmed into the PMIC through One Time Programmable (OTP) memory. For more details refer to the product datasheet. Table 1. PF3000 Voltage Regulators Regulator Output Voltage Range Load Current Rating SW1A 0.7 V to 1.425 V; 1.8 V; 3.3 V 1000 mA SW1B 0.7 V to 1.475 V 1750 mA SW2 1.5 V to 1.85 V; 2.5 V to 3.3 V 1250 mA SW3 0.9 V to 1.65 V 1500 mA SWBST 5.0 V to 5.15 V 600 mA VSNVS 3.0 V 1.0 mA VLDO1 1.8 V to 3.3 V 100 mA VLDO2 0.8 V to 1.55 V 250 mA VLDO3 1.8 V to 3.3 V 100 mA VLDO4 1.8 V to 3.3 V 350 mA VCC_SD 1.8 V to 1.85 V; 2.85 V to 3.3 V 100 mA V33 2.85 V to 3.3 V 350 mA VREFDDR VINREFDDR/2 10 mA AN5113 Application Note Rev. 1.0 4/2015 2 Freescale Semiconductor i.MX 6SL Power Management Using the PF3000 3 i.MX 6SL Power Management Using the PF3000 The i.MX 6SL processor features Freescale's advanced implementation of the a single ARM® Cortex®-A9 MPCore™ multicore processor, which operates at speeds up to 1.0 GHz. Table 2. shows how PF3000 can be used to power an i.MX 6SL based system. This include the voltage rails required by the processor as well as memory and common peripherals. Being a programming PMIC, the PF3000 can be used in a number of ways to power the i.MX 6SL. Table 2. lists one of the many possibilities. Based on end application requirements, the power tree can be optimized. Contact your Freescale representative for a BSP patch for the PF3000 with i.MX 6SL. Table 2. PF3000 + i.MX 6SL Power Tree Regulator Voltage Sequence Load Domain SW1A 1.375 1 VDDCORE SW1B 1.375 1 VDDSOC SW2 3.15 2 VDDHIGH, VCC-eMCC, VCCQ-eMMC, MIC_VDD, EPDC Expansion Port, LCD Expansion Port, Mini-PCIe HMC, Debug UART to USB, Ethernet Transceiver, VCC_SPI_NOR_Flash SW3 1.2 4 DRAM_PWR, VDD2_LPDDR2, NVCC_1.2V SWBST 5.0 6 SYS_5V (OTG/Host, EPDC Expansion, LCD Expansion) VSNVS 3.0 Always On VLDO1 1.8 3 VLDO2 1.5 Off CMOS Camera, EPDC Expansion port, VLDO3 3.0V Off N/A VLDO4 1.8 3 NVCC_1.8V, EPDC Expansion Port, LCD Expansion Port, WEIM Expansion VCC_SD 3.15 2 VCC_SD1, VDD-SD2, VDD-SD3 V33 2.85 Off VREFDDR 0.6 4 VDD_SNVS_IN VDD1_LPDDR2, Audio Codec CMOS Camera DRAM_VREF AN5113 Application Note Rev. 1.0 4/2015 Freescale Semiconductor 3 Schematic 4 Schematic Figure 1. MCIMX6SLEVK-P3 Board Diagram AN5113 Application Note Rev. 1.0 4/2015 4 Freescale Semiconductor A B C 1 2 3 3 2 1 GND SHUTDOWN_B GND R4 10K wall_ov_base 2 0402_CC D2 MMSZ5231BT1G wall_ov_ctl SPDT_PWR_SWITCH A B SW14 DNP C4 1.0UF 10V R1 0.1 DNP 0603_CC R2 2.7K 0805_CC (6,11) (6,11) I2C1_SCL I2C1_SDA 5 R790 0 0402_CC R791 0 0402_CC VDDIO P3V15_VDDHIGH_SW2 R787 1.5K R788 1.5K R786 10k R789 10k C D3 RB521CS-30 A 0 0 C416 1.0UF PGND C417 2.2UF PSU_V1_5.0V WALL_OV_LED led1_3 GND Q3 NTS4001NT1G led1_2 R23 100K 0402_CC 1 D6 LED Red led1_1 R12 2.2K 0402_CC 5 R9 470K 0603_CC 2 D1 ESD9L5.0ST5G C1 0.1UF 0402_CC 16V 10V C2 1.0UF 0 D3 D2 A4 A5 B5 B4 C3 A3 A1 A2 PMID NOBAT BATSNSN BAT_REG CHGOUT_C5 CHGOUT_D5 CHGOUT_E5 VSYS_D4 VSYS_E3 VSYS_E4 LX_C1 LX_D1 BOOT PGND_E1 PGND_E2 4 PGND I2C ADDR: 0x92 MC32BC3770CS SHDN CHGEN SCL SDA INT VIO GND VL VBUS_A1 VBUS_A2 U36 C2 B3 C4 C5 D5 E5 D4 E3 E4 C1 D1 B2 E1 E2 B1 C419 2.2UF 1 2 GND C6 0.1UF DNP PGND PGND C8 10UF BATREG BAT_SNS NOBAT PGND C7 0.1UF SYS_4V325 C3 100UF CC1210 10V VBAT 3 PGND C25 1.0UF SH14 SH0805_40 SOLDER SHORT Lithium single cell battery connectors PGND C5 4.7uF 1UH ind_vls252010 L2 CHG_OUT_SM5418 C13 0.1UF 0402_CC 16V PGND 3 PSU_V1_5.0V Lithium Charger R22 100K 0402_CC wall_ctl_base2 Q2B MBT3906DW1T1 WALL_5V_DC_JACK GND 5 R5 10K wall_ctl_base1 0402_CC R3 10K 0402_CC 1 2 3 DNP JP1 Q1 FDMS6681Z 1 Over Voltage Protection Over-Voltage LED SHUTDOWN_B Q2A MBT3906DW1T1 WALL_5V_DC_JACK PWR Cut Switch For SW Development CON_1_PWR J6 TP73 GND TP74 4 3 DC JACK 5V 4 D C A 1 6 4 A 3 C C A Freescale Semiconductor 2 wall_filter 1803439 J140 PGND 1 2 3 PF0100_VIN GND BATT 2 B2B-PH-K-S 2 1 J1 2 A D11 LED Green R34 2.2K 0402_CC Main PWR LED GND C 5 FIUO: X 1 Sheet 3 of PUBI: ___ SCH-28549 PDF: SPF-28549 Monday, March 30, 2015 Date: SYS Power Document Number Size C Page Title: FCP: ___ MCIMX6SLEVK-P3 board ICAP Classification: Drawing Title: 1 16 Rev A A B C D Schematic AN5113 Application Note Rev. 1.0 4/2015 5 A B C D GND 5 R51 GND 0 0 C46 10V 1 0 0 R54 SH1 SH0805_40 SOLDER SHORT C27 0.22uF GND 12 11 10 9 8 7 6 5 4 3 2 1 GND C31 4.7uF 4 L7 2 1 1UH ind_vls3012_sm GND C30 4.7uF 0402_CC 6.3V 10V C21 1.0UF PF0100_VIN GND VCOREDIG 1.0UF 46 P1V8_SW4 P1V8_VGEN3 P1V8_VLDO1 GNDREF1 SW1BFB SW1BIN SW1BLX SW1ALX SW1AIN SW1AFB ICTEST STANDBY RESETBMCU SD_VSEL INT C22 10V P1V5_VGEN2 P1V5_VLDO2 GND C28 0.22uF pf0100_sw2_out C64 C65 22UF 22UF 0603_CC 0603_CC 6.3V 6.3V GND 0603_CC 0 P3V15_VDDHIGH_SW2 GND PF0100_VIN 4.7uF 0603_CC 4.7uF 0603_CC PF0100_VIN GND GPIO GND R40 0.22UF 0201_CC U35 0 0402_CC R48 0402_CC 47K DNP 0 0402_CC C23 6.3V R49 0402_CC R43 0 R745 REF_CLK_24M (6) P3V15_VDDHIGH_SW2 0603_CC DNP 0603_CC R53 P3V15_VDDHIGH_SW2 R52 PF0100_VIN 0603_CC DNP GND L3 0402_CC PMIC_ON_REQ (6) P3V0_STBY I2C1_SCL (6,11) P1V375_VDDARM_SW1AB 2 1UH C42 C43 22UF 22UF ind_vls3012_sm 0603_CC 0603_CC 6.3V 6.3V C47 GND 10V L5 P1V375_VDDSOC_SW1C 2 1 1UH C53 C54 22UF 22UF ind_vls252010 0603_CC 0603_CC 6.3V 6.3V PF0100_VIN SH3 SH0805_40 SOLDER SHORT VDD_SOC_IN SH2 SH0805_40 SOLDER SHORT VDD_ARM_IN PMIC_STBY_REQ (6) POR_B (6,8,11,13) GND C413 0.1UF 0402_CC 16V P3V15_VDDHIGH_SW2 I2C1_SDA GND (6,11) GND 4 VLDO1IN 13 47 VDDIO 48 PWRON VLDO1 14 VLDO2 15 SCL 45 SDA SW2LX 44 MC32PF300XEP VCOREREF SW2IN GND C66 4.7uF 0603_CC 10V 17 PF0100_VIN 18 SW2FB 19 VLDO2IN 16 43 VCOREDIG 42 VIN VLDO3 20 40 GNDREF VSNVS 39 PF0100_VIN GND R56 C39 0.1UF 0402_CC 16V 36 25 26 27 28 29 30 31 32 33 34 35 GND R55 3 C38 0.1UF GND C34 4.7uF 0402_CC 6.3V SW1A C55 0.1UF 0402_CC 16V GND C33 4.7uF P1V8_VGEN4 P3V15_VDDHIGH_SW2 P1V8_VLDO4 0 GND 10V C36 1.0UF DRAM_VREF GND V33 C50 22UF 0603_CC 6.3V GND SW1B C56 0.1UF 0402_CC 16V V33 SH5 SH0805_40 PF0100_5V 2 SW3A - DNP C61 0.1UF 0402_CC 16V pmic_pwr_on_led C PSU_V1_5.0V SYS_5V J17 HDR_1X3 GND GND SW4 C62 0.1UF 0402_CC 16V PF0100_VIN LED Green D15 SW2 C57 0.1UF 0402_CC 16V A PMIC-ON LED P1V2_DDR_SW3 R57 330 0402_CC SW1A C60 0.1UF 0402_CC 16V SOLDER SHORT SW1B C59 0.1UF 0402_CC 16V 2 FCP: ___ Date: 1 FIUO: X PMIC 1 Sheet 4 SCH-28549 PDF: SPF-28549 Monday, March 30, 2015 of PUBI: ___ MCIMX6SLEVK-P3 board Size Document Number Custom Page Title: ICAP Classification: Drawing Title: Note: J17 Shunt 1-2 for SYS_5V from PMIC: 600mA limited Shunt 2-3 for SYS_5V from wall adapter C35 GND 4.7uF PF0100_5V C70 47uF LDO decouples are 4.7 uF for BOM consolidation. C32 0.22uF 0402_CC GND 16V DNP GND P2V8_VGEN6 GND p1V2_sw3_out 1 2 1UH C49 22UF ind_vls252010 4.7uF 0603_CC 0603_CC 6.3V GND L4 GND HDR 1X2 P3V15_LICELL J14 1 2 D12 MBR140SFT C 0.22UF C412 GND C414 4.7uF A L8 C40 2.2uH P3V15_LICELL PF0100_VIN C41 10V R784 0 P3V0_VLDO3 0 C415 4.7uF 0603_CC 10V GND P3V0_VSNVS 0.22UF 10V C69 10uF 1.0UF 10V C24 VCC_SDX 3 P1V2_DDR_SW3 VREFDDR GNDREF2 SW3FB SW3IN SW3LX LDOG VPWR V33 VCC_SD C37 0.1UF 0402_CC 16V pf0100_vhlf GND LICELL GND PF0100_5V C68 0.1UF 0402_CC 16V GND SWBSTLX PF0100_VIN R783 0 0402_CC 38 VIN2 37 SWBSTFB 41 VCORE VLDO34IN 21 VLDO4 22 VDDOTP VHALF 23 VINREFDDR 24 EPAD 49 2 1 6 1 2 3 5 16 Rev A A B C D Schematic AN5113 Application Note Rev. 1.0 4/2015 Freescale Semiconductor A B C 5 P3V0_VLDO3 R58 0 0603_CC R785 0 0603_CC DNP SH4 SH0805_40 P1V8_VGEN4 SOLDER SHORT P3V15_VDDHIGH_SW2 P3V0_VSNVS C93 0.22UF 0201_CC 6.3V C81 22UF 0603_CC 6.3V GND GND GND GND 3 C99 0.22UF 0201_CC 6.3V C98 0.22UF 0201_CC 6.3V C97 0.22UF 0201_CC 6.3V 4 GND VDD_3V15_IN C96 0.22UF 0201_CC 6.3V P3V0_STBY GND C398 4.7uF 0402_CC 6.3V C396 4.7uF 0402_CC 6.3V C95 0.22UF 0201_CC 6.3V VDD_HIGH_CAP C401 4.7uF 0402_CC 6.3V C400 4.7uF 0402_CC 6.3V C399 4.7uF 0402_CC 6.3V D24 BAT54C-7-F GND C397 4.7uF 0402_CC 6.3V C76 22UF 0603_CC 6.3V 4 D24 ensures VDD_SNVS_IN is always powered whenever VDDHIGH_IN is powered to meet data sheet spec even if P3V0_STBY faults to 0 V. C92 0.22UF 0201_CC 6.3V VDD_SOC_IN VDD_ARM_IN 1 Freescale Semiconductor 2 D 5 M6 E14 E15 M20 Y11 H10 H11 H14 H15 L18 M18 T19 U10 U11 R12 R13 T12 T13 AC20 R10 R11 T10 T11 J10 J11 K10 K11 R16 R17 T16 T17 T18 J12 J13 J14 K12 K13 K14 MCIMX6L8DVN10AA DRAM_PWR_2P5 NVCC_1V8_1 NVCC_1V8_2 NVCC_1V8_3 NVCC_1V8_4 NVCC_3V3_1 NVCC_3V3_2 NVCC_3V3_3 NVCC_3V3_4 NVCC_3V3_5 NVCC_3V3_6 NVCC_3V3_7 NVCC_3V3_8 NVCC_3V3_9 VDD_HIGH_IN1 VDD_HIGH_IN2 VDD_HIGH_IN3 VDD_HIGH_IN4 VDD_SNVS_IN VDD_PU_IN1 VDD_PU_IN2 VDD_PU_IN3 VDD_PU_IN4 VDD_SOC_IN1 VDD_SOC_IN2 VDD_SOC_IN3 VDD_SOC_IN4 VDD_SOC_IN5 VDD_SOC_IN6 VDD_SOC_IN7 VDD_SOC_IN8 VDD_SOC_IN9 VDD_ARM_IN1 VDD_ARM_IN2 VDD_ARM_IN3 VDD_ARM_IN4 VDD_ARM_IN5 VDD_ARM_IN6 U1H 3 DRAM_PWR1 DRAM_PWR2 DRAM_PWR3 DRAM_PWR4 DRAM_PWR5 DRAM_PWR6 DRAM_PWR7 DRAM_PWR8 DRAM_PWR9 DRAM_PWR10 VDD_PLL_CAP NVCC_1.2V VDD_HIGH_CAP1 VDD_HIGH_CAP2 VDD_HIGH_CAP3 VDD_HIGH_CAP4 VDD_SNVS_CAP VDD_PU_CAP1 VDD_PU_CAP2 VDD_PU_CAP3 VDD_PU_CAP4 VDD_PU_CAP5 VDD_PU_CAP6 VDD_SOC_CAP1 VDD_SOC_CAP2 VDD_SOC_CAP3 VDD_SOC_CAP4 VDD_SOC_CAP5 VDD_SOC_CAP6 VDD_SOC_CAP7 VDD_SOC_CAP8 VDD_SOC_CAP9 VDD_ARM_CAP1 VDD_ARM_CAP2 VDD_ARM_CAP3 VDD_ARM_CAP4 VDD_ARM_CAP5 VDD_ARM_CAP6 VDD_ARM_CAP7 VDD_ARM_CAP8 3 E6 G7 H6 J6 N6 P7 T6 U6 V7 Y6 Y19 W7 R14 R15 T14 T15 GND C101 0.22UF 0201_CC 6.3V VDD_PLL_CAP GND C72 0.22UF 0201_CC 6.3V GND C82 0.22UF 0201_CC 6.3V C88 0.22UF 0201_CC 6.3V C77 0.22UF 0201_CC 6.3V C404 4.7uF 0402_CC 6.3V C405 4.7uF 0402_CC 6.3V 0603_CC 6.3V C102 GND 0.22UF 0201_CC 6.3V GND C403 4.7uF 0402_CC 6.3V C79 22UF 0603_CC 6.3V VDD_SOC_CAP C75 22UF 0603_CC 6.3V C80 GND 22UF C94 0.22UF 0201_CC 6.3V GND P1V2_DDR_SW3 VDD_HIGH_CAP GND VDD_SNVS_CAP C389 4.7uF 0402_CC 6.3V C390 4.7uF 0402_CC 6.3V GND C90 0.22UF 0201_CC 6.3V C91 0.22UF 0201_CC 6.3V VDD_SOC_CAP1 VDD_PU_CAP AD20 R7 R8 R9 T7 T8 T9 J7 J8 J9 K7 K8 K9 N18 P18 R18 J15 J16 J17 J18 K15 K16 K17 K18 VDD_ARM_CAP 2 C394 4.7uF 0402_CC 6.3V P1V2_DDR_SW3 FCP: ___ FIUO: X MCIMX6L8DVN10AA GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 U1I 1 1 Sheet 5 SCH-28549 PDF: SPF-28549 Monday, March 30, 2015 Date: IMX6SL_Power Document Number AD7 AD4 AD1 AD24 AC18 AB18 AB14 AB10 U22 AA2 AA1 Y5 V18 V17 V16 V15 V14 V13 V12 V11 V10 V9 V8 V1 U18 U7 U3 T5 N22 R1 P16 P15 P14 P13 P12 P11 P10 P9 N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N17 of PUBI: ___ GND98 GND97 GND96 GND95 GND94 GND93 GND92 GND91 GND90 GND89 GND88 GND87 GND86 GND85 GND84 GND83 GND82 GND81 GND80 GND79 GND78 GND77 GND76 GND75 GND74 GND73 GND72 GND71 GND70 GND69 GND68 GND67 GND66 GND65 GND64 GND63 GND62 GND61 GND60 GND59 GND58 GND57 GND56 GND55 GND54 GND53 GND52 GND51 GND50 MCIMX6SLEVK-P3 board GND A1 A4 A7 A24 C6 C10 C14 C19 D1 D2 E5 G1 G8 G9 G10 G11 G13 G14 G15 G17 G18 H3 H7 H18 H22 J5 K1 N3 L7 L9 L10 L11 L12 L13 L14 L15 L16 M17 M5 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 Size B Page Title: ICAP Classification: Drawing Title: Note: VDD_SOC_CAP1 to 6 and VDD_SOC_CAP7 to 9 can be connected together. If split, proper corresponding decoupling capacitance needs to be placed for each group of pins. 2 16 GND Rev A A B C D Schematic AN5113 Application Note Rev. 1.0 4/2015 7 A B C D LCD_CLK LCD_ENABLE LCD_HSYNC LCD_VSYNC LCD_RESET LCD_DAT0 LCD_DAT1 LCD_DAT2 LCD_DAT3 LCD_DAT4 LCD_DAT5 LCD_DAT6 LCD_DAT7 LCD_DAT8 LCD_DAT9 LCD_DAT10 LCD_DAT11 LCD_DAT12 LCD_DAT13 LCD_DAT14 LCD_DAT15 LCD_DAT16 LCD_DAT17 LCD_DAT18 LCD_DAT19 LCD_DAT20 LCD_DAT21 LCD_DAT22 LCD_DAT23 T22 J24 H23 J23 H24 Y24 W23 W24 V23 V24 U21 U23 U24 T23 T24 R23 R24 P23 P24 N21 N23 N24 M22 M23 M24 L23 L24 K23 K24 ENET SPI GND C402 4.7uF 0402_CC 6.3V VDD_USB_CAP U14 C100 0.22UF 0201_CC 6.3V AB7 AC8 AD9 AC9 AC10 Y10 AA7 AA10 AD10 W11 W10 N19 N20 M19 M21 U19 U20 T20 T21 AC13 AD13 E18 D18 B19 D19 J19 J21 J20 H20 H21 J22 H19 5 MCIMX6L8DVN10AA 3G Card Enable 3G Card Reset Primary Use USB_OTG2_VBUS USB_OTG2_DP USB_OTG2_DN AD18 AC17 AD17 AA18 AC19 AD19 AC22 Flag (9) (9) (9) A18 A17 B17 A16 B16 A15 B15 C15 D15 F15 G16 F14 D14 B14 A14 A13 B10 B8 E7 F7 C11 A10 B9 A9 A12 B13 B12 A11 C7 D7 C18 B18 D11 E11 F11 G12 B11 F10 E10 D10 REF_CLK_24M REF_CLK_32K 0 4 3GCARD_USB_D_P 3GCARD_USB_D_N Primary Use 0 PWM1 KEY_ROW0 KEY_ROW1 KEY_ROW2 KEY_ROW3 KEY_ROW4 KEY_ROW5 KEY_ROW6 KEY_ROW7 KEY_COL0 KEY_COL1 KEY_COL2 KEY_COL3 KEY_COL4 KEY_COL5 KEY_COL6 KEY_COL7 HSIC_DAT HSIC_STROBE MCIMX6L8DVN10AA CLKOUT USB_HSIC PWM KEY U1G (11) (9) 1 USB_Host_D_N (9) PCIE_USB_Host_D_N USB_Host_D_P PCIE_USB_Host_D_P P3V15_VDDHIGH_SW2 3 Primary Use (4) (8) (12) (12) GND Q31 2N7002 R410 10K 0402_CC 2 PMIC INT SD3 Card Detect Debug LED LCD_Brightness 3 USB_OTG1_VBUS Flag (9) SD3_CLK SD3_CMD SD3_DAT0 SD3_DAT1 SD3_DAT2 SD3_DAT3 SD2_RST SD2_CLK SD2_CMD SD2_DAT0 SD2_DAT1 SD2_DAT2 SD2_DAT3 SD2_DAT4 SD2_DAT5 SD2_DAT6 SD2_DAT7 SD1_CLK SD1_CMD SD1_DAT0 SD1_DAT1 SD1_DAT2 SD1_DAT3 SD1_DAT4 SD1_DAT5 SD1_DAT6 SD1_DAT7 1HSIC_STROBE AB11 AA11 AC11 AD11 AC12 AD12 Y23 AC24 AB24 AB22 AB23 AA22 AA23 AA24 Y20 Y21 Y22 B20 B21 B23 A23 C22 B22 A22 A21 A20 A19 GND DNP 128-0711-20 J20 SD3_CLK SD3_CMD SD3_DAT0 SD3_DAT1 SD3_DAT2 SD3_DAT3 SD2_RST SD2_CLK SD2_CMD SD2_DAT0 SD2_DAT1 SD2_DAT2 SD2_DAT3 SD2_DAT4 SD2_DAT5 SD2_DAT6 SD2_DAT7 SD1_CLK SD1_CMD SD1_DAT0 SD1_DAT1 SD1_DAT2 SD1_DAT3 SD1_DAT4 SD1_DAT5 SD1_DAT6 SD1_DAT7 MCIMX6L8DVN10AA SD3 SD2 SD1 SD U1E 1% 1% 1% 1% (6,10,11) (6,10,11) I2C2_SDA (4,6,11) I2C1_SDA I2C2_SCL (4,6,11) I2C1_SCL Due to board loadings this resistor was reduced. Validate your design, with the largest allowable resistor to reduce current usage. Note: Pull-up resistor must be sized to meet the signal rise times and also the Vil spec of all the bus components. R87 1.0K R86 1.0K P3V15_VDDHIGH_SW2 R85 1.0K R84 1.0K P3V15_VDDHIGH_SW2 I2C pullups Capacitive Touch Interrupt USB_OTG1_ID (11,12) (11,12) (11,12) (11) (9,11) USB_5V_OTG Over-current (11) LCD_Power_EN (11) Accelerometer Interrupt (8,11) SD1 Card Detect (11,12) (11,12) (11,12) (8,11) (9,11) USB_5V_OTG Enable (9,11) USB_5V_HOST Enable Capacitive Touch Reset (11) (8,11) SD1 Write Protect Q30 IRLML6401 REF_CLK_24M REF_CLK_32K HSIC_DAT HSIC_STROBE PWM1 KEY_ROW0 KEY_ROW1 KEY_ROW2 KEY_ROW3 KEY_ROW4 KEY_ROW5 KEY_ROW6 KEY_ROW7 KEY_COL0 KEY_COL1 KEY_COL2 KEY_COL3 KEY_COL4 KEY_COL5 KEY_COL6 KEY_COL7 3 Primary Use EPDC_D0 (11) EPDC_D1 (11) EPDC_D2 (11) EPDC_D3 (11) EPDC_D4 (11) EPDC_D5 (11) EPDC_D6 (11) EPDC_D7 (11) EPDC_D8 (11) EPDC_D9 (11) EPDC_D10 (11) EPDC_D11 (11) EPDC_D12 (11) EPDC_D13 (11) EPDC_D14 (11) EPDC_D15 (11) EPDC_SDCLK (11) EPDC_SDLE (11) EPDC_SDOE (11) EPDC_SDSHR (11) EPDC_SDCE0 (11) EPDC_SDCE1 (11) EPDC_SDCE2 (11) EPDC_SDCE3 (11) EPDC_GDCLK (11) EPDC_GDOE (11) EPDC_GDRL (11) EPDC_GDSP (11) EPDC_VCOM0 (11) EPDC_VCOM1 (11) EPDC_BDR0 (11) EPDC_BDR1 (11) EPDC_PWRCTRL0 (11) EPDC_PWRCTRL1 (11) EPDC_PWRCTRL2 (11) EPDC_PWRCTRL3 (11) EPDC_PWRCOM (9,11) EPDC_PWRINT (11) EPDC_PWRSTAT (11) EPDC_PWRWAKEUP (11) IMX_OTG_VBUS AC14 AD14 AA6 AB6 Y7 G24 F24 E24 E21 E19 D23 C24 B24 G23 F23 E23 E22 E20 D24 D22 C23 Keypad,HSIC,PWM Pin 1 Default SH13 MX_USB_HOST_D_N EPDC EPDC_D0 EPDC_D1 EPDC_D2 EPDC_D3 EPDC_D4 EPDC_D5 EPDC_D6 EPDC_D7 EPDC_D8 EPDC_D9 EPDC_D10 EPDC_D11 EPDC_D12 EPDC_D13 EPDC_D14 EPDC_D15 EPDC_SDCLK EPDC_SDLE EPDC_SDOE EPDC_SDSHR EPDC_SDCE0 EPDC_SDCE1 EPDC_SDCE2 EPDC_SDCE3 EPDC_GDCLK EPDC_GDOE EPDC_GDRL EPDC_GDSP EPDC_VCOM0 EPDC_VCOM1 EPDC_BDR0 EPDC_BDR1 EPDC_PWRCTRL0 EPDC_PWRCTRL1 EPDC_PWRCTRL2 EPDC_PWRCTRL3 EPDC_PWRCOM EPDC_PWRINT EPDC_PWRSTAT EPDC_PWRWAKEUP MCIMX6L8DVN10AA U1B Pin 1 Default SH12 MX_USB_HOST_D_P USB_Host_VBUS USB_OTG1_D_P USB_OTG1_D_N IMX_OTG_VBUS Ethernet power enable Headphone detect USB_OTG1_VBUS USB_OTG1_DP USB_OTG1_DN USB_OTG1_CHD (15) (15) (10) (15) (15) (15) (15) (15) (15) (15) (15) (8) (8) (8) (8) (8,9,11)USB_5V_HOST Over-current (3,11) Charger-Ok Status (3,11) Charger-fault status (3,11) Charging status (4,6,11) (4,6,11) (6,10,11) (6,10,11) (14) (14) (12) (12) (10) (10) (10) (10) (10) ANATOP FEC_MDIO FEC_TX_CLK FEC_RX_ER FEC_CRS_DV FEC_RXD1 FEC_TXD0 FEC_MDC FEC_RXD0 FEC_TX_EN FEC_TXD1 FEC_REF_CLK ECSPI1_SCLK ECSPI1_MOSI ECSPI1_MISO ECSPI1_SS0 ECSPI2_SCLK ECSPI2_MOSI ECSPI2_MISO ECSPI2_SS0 I2C1_SCL I2C1_SDA I2C2_SCL I2C2_SDA UART1_RXD UART1_TXD VDD_USB_CAP U1J USB FEC_MDIO FEC_TX_CLK FEC_RX_ER FEC_CRS_DV FEC_RXD1 FEC_TXD0 FEC_MDC FEC_RXD0 FEC_TX_EN FEC_TXD1 FEC_REF_CLK ECSPI1_SCLK ECSPI1_MOSI ECSPI1_MISO ECSPI1_SS0 ECSPI2_SCLK ECSPI2_MOSI ECSPI2_MISO ECSPI2_SS0 I2C UART1_RXD UART1_TXD AUD_RXFS AUD_RXC AUD_RXD AUD_TXC AUD_TXFS AUD_TXD AUD_MCLK I2C1_SCL I2C1_SDA I2C2_SCL I2C2_SDA UART AUDIO MCIMX6L8DVN10AA U1D AUD_RXFS AUD_RXC AUD_RXD AUD_TXC AUD_TXFS AUD_TXD AUD_MCLK LCD_CLK (11) LCD_ENABLE (11) LCD_HSYNC (11) LCD_VSYNC (11) LCD_RESET (11) LCD_DAT0 (11,13) LCD_DAT1 (11,13) LCD_DAT2 (11,13) LCD_DAT3 (11,13) LCD_DAT4 (11,13) LCD_DAT5 (11,13) LCD_DAT6 (11,13) LCD_DAT7 (11,13) LCD_DAT8 (11,13) LCD_DAT9 (11,13) LCD_DAT10 (11,13) LCD_DAT11 (11,13) LCD_DAT12 (11,13) LCD_DAT13 (11,13) LCD_DAT14 (11,13) LCD_DAT15 (11,13) LCD_DAT16 (11,13) LCD_DAT17 (11,13) LCD_DAT18 (11,13) LCD_DAT19 (11,13) LCD_DAT20 (11,13) LCD_DAT21 (11,13) LCD_DAT22 (11,13) LCD_DAT23 (11,13) Audio,UART,FEC MCIMX6L8DVN10AA LCD U1C 4 EPDC 2 3 LCD 5 1 3 2 1 GND C194 18pF 0402_CC 25V GND 2 GND GND HSIC_DAT 1 2 ON/OFF SPST PB SW1 4 3 2 RESET 1 SPST PB 4 SW2 JTAG_nSRST WDOG_B 1 JTAG_TRST JTAG_TDI JTAG_TMS JTAG_TCK JTAG_TDO JTAG_MOD DNP 2 1 2 GND WDOG_B ONOFF POR_B Monday, March 30, 2015 Date: GND R778 2.21M 0603_CC FIUO: X 1 Sheet 6 of PUBI: ___ (6) (6) (4,6,8,11,13) SCH-28549 PDF: SPF-28549 IMX6SL_SoC Document Number Size C Page Title: FCP: ___ R46 0 0603_CC DNP GND CLK1P CLK1N C196 16PF 0603_CC 50V 4 1 HSIC_DAT_GPIO ONOFF R50 0 0603_CC 3 24MHZ GND1 Y3 GND2 GND 16 Rev A P3V15_VDDHIGH_SW2 GANAIO ONOFF Note: Watchdog reset is being taken care of internally. 3 2 DNP R373 0402_CC (14) HDR 2X4 2 4 6 8 (6) MCIMX6SLEVK-P3 board ICAP Classification: Drawing Title: 3 BAT54A-7-F D19 GND C197 16PF 0603_CC 50V XTALO XTALI 1.0M HSIC_STROBE_GPIO BAT54A-7-F D20 R59 DNP 0 0603_CC R393 10K 0402_CC 1 CLK1P CLK1N AC23 AD23 24MHz P3V15_VDDHIGH_SW2 R38 0 0402_CC R60 0 0402_CC RTC_XTALI RTC_XTALO AB19 AA19 J136 XTALI XTALO 1 3 HSIC_DAT_GPIO 5 HSIC_STROBE_GPIO 7 GANAIO AD22 WDOG_B PMIC_ON_REQ (4) PMIC_STBY_REQ (4) POR_B (4,6,8,11,13) ONOFF (6) BOOT_MODE0 (13) BOOT_MODE1 (13) TAMPER JTAG_TRSTB (14) JTAG_TDI (14) JTAG_TMS (14) JTAG_TCK (14) JTAG_TDO (14) JTAG_MOD (14) 1 AD21 AC21 F18 Y18 AD15 AD16 AC16 W18 AC15 AB15 U15 AA15 W14 Y15 AA14 W15 Y14 TAMPER CLK1P CLK1N RTC_XTALI RTC_XTALO XTALI XTALO GANAIO WDOG TAMPER PMIC_ON_REQ PMIC_STBY_REQ POR ONOFF BOOT_MODE0 BOOT_MODE1 TEST_MODE MCIMX6L8DVN10AA ANATOP WDOG SYSTEM JTAG 3 (14) (6) POR Reset C195 18pF 0402_CC 25V Y1 2 32.768kHz RTC_XTALO RTC_XTALI Control U1A HSIC_STROBE HSIC_DAT 32.768kHz GND DNP 128-0711-20 J19 UART_RX UART_TX SD2 Write Protect SD2 Card Detect SPDIF Primary Use On/Off (8) (8) (8) (8) (8) (8) (8,11) (8) (8) (8) (8) (8) (8) (8,11) (8,11) (8) (8) (8) (8) (8) (8) (8) (8) (8) (8) (8) (8) 2 2 8 3 i.MX6SL A B C D Schematic AN5113 Application Note Rev. 1.0 4/2015 Freescale Semiconductor Freescale Semiconductor A B C D DRAM_RESET ZQPAD DRAM_CS1 DRAM_SDODT1 DRAM_SDCKE1 DRAM_CS0 DRAM_SDODT0 DRAM_SDCKE0 DRAM_SDCLK_0 DRAM_SDCLK_0 DRAM_CAS DRAM_RAS DRAM_SDBA0 DRAM_SDBA1 DRAM_SDBA2 DRAM_WE DRAM_A0 DRAM_A1 DRAM_A2 DRAM_A3 DRAM_A4 DRAM_A5 DRAM_A6 DRAM_A7 DRAM_A8 DRAM_A9 DRAM_A10 DRAM_A11 DRAM_A12 DRAM_A13 DRAM_A14 DRAM_A15 DRAM_D24 DRAM_D25 DRAM_D26 DRAM_D27 DRAM_D28 DRAM_D29 DRAM_D30 DRAM_D31 DRAM_SDQS3 DRAM_SDQS3 DRAM_DQM3 DRAM_D16 DRAM_D17 DRAM_D18 DRAM_D19 DRAM_D20 DRAM_D21 DRAM_D22 DRAM_D23 DRAM_SDQS2 DRAM_SDQS2 DRAM_DQM2 DRAM_D08 DRAM_D09 DRAM_D10 DRAM_D11 DRAM_D12 DRAM_D13 DRAM_D14 DRAM_D15 DRAM_SDQS1 DRAM_SDQS1 DRAM_DQM1 DRAM_D00 DRAM_D01 DRAM_D02 DRAM_D03 DRAM_D04 DRAM_D05 DRAM_D06 DRAM_D07 DRAM_SDQS0 DRAM_SDQS0 DRAM_DQM0 DRAM_VREF 5 MCIMX6L8DVN10AA U1F DDR DRAM_D24 DRAM_D25 DRAM_D26 DRAM_D27 DRAM_D28 DRAM_D29 DRAM_D30 DRAM_D31 DRAM_SDQS3_P DRAM_SDQS3_N DRAM_DQM3 DRAM_A0 DRAM_A1 DRAM_A2 DRAM_A3 DRAM_A4 DRAM_A5 DRAM_A6 DRAM_A7 DRAM_A8 DRAM_A9 A3 B4 B5 A5 B6 A6 B7 A8 B3 A2 C3 U4 U5 T3 T4 N4 M3 M4 H4 J3 J4 J2 T2 U2 H5 R2 K2 DRAM_SDCKE1 IMX_RAM_CALIBRATION D6 H2 DRAM_CS1 DRAM_SDCKE0 DRAM_SDCLK0_P DRAM_SDCLK0_N L2 E4 M2 N2 Y4 P2 L1 M1 DRAM_CS0 DRAM_D16 DRAM_D17 DRAM_D18 DRAM_D19 DRAM_D20 DRAM_D21 DRAM_D22 DRAM_D23 DRAM_SDQS2_P DRAM_SDQS2_N DRAM_DQM2 AD8 AC7 AD6 AC6 AD5 AC5 AC4 AD3 AC3 AD2 AB3 P1 N1 J1 T1 H1 U1 DRAM_D8 DRAM_D9 DRAM_D10 DRAM_D11 DRAM_D12 DRAM_D13 DRAM_D14 DRAM_D15 DRAM_SDQS1_P DRAM_SDQS1_N DRAM_DQM1 E2 E1 E3 D3 C1 C2 B1 B2 F1 F2 G2 C211 0.01uF 0201_CC 6.3V DRAM_D0 DRAM_D1 DRAM_D2 DRAM_D3 DRAM_D4 DRAM_D5 DRAM_D6 DRAM_D7 DRAM_SDQS0_P DRAM_SDQS0_N DRAM_DQM0 GND DRAM_VREF AC2 AC1 AB2 AB1 AA3 Y3 Y1 Y2 W2 W1 V2 N5 i.MX6SL 5 GND R93 240 RC0402_25 1% GND R414 10K 0402_CC 4 4 GND R416 10K 0402_CC GND GND R88 240 RC0402_25 1% DRAM_ZQ0 AB3 AB4 DRAM_CS0 DRAM_CS1 P1 V1 AB7 A12 A15 A18 C23 F23 J23 P23 U23 Y23 AC12 AC15 AC18 A21 B10 C1 M2 M23 R1 AA1 AB11 AC5 AC9 AC21 AC3 AC4 DRAM_SDCKE0 DRAM_SDCKE1 Y2 Y1 N23 L23 AB20 B20 DRAM_DQM0 DRAM_DQM1 DRAM_DQM2 DRAM_DQM3 DRAM_SDCLK0_P DRAM_SDCLK0_N R23 P22 J22 K23 AB18 AC19 B18 A19 AC6 AB6 AC7 AB8 AB9 W1 V2 U1 T2 T1 AA23 Y22 W22 W23 V23 U22 T22 T23 H22 H23 G23 F22 E22 E23 D23 C22 AB12 AC13 AB14 AC14 AB15 AC16 AB17 AC17 B17 A17 A16 B15 B14 A14 A13 B12 DRAM_SDQS0_P DRAM_SDQS0_N DRAM_SDQS1_P DRAM_SDQS1_N DRAM_SDQS2_P DRAM_SDQS2_N DRAM_SDQS3_P DRAM_SDQS3_N DRAM_A0 DRAM_A1 DRAM_A2 DRAM_A3 DRAM_A4 DRAM_A5 DRAM_A6 DRAM_A7 DRAM_A8 DRAM_A9 DRAM_D0 DRAM_D1 DRAM_D2 DRAM_D3 DRAM_D4 DRAM_D5 DRAM_D6 DRAM_D7 DRAM_D8 DRAM_D9 DRAM_D10 DRAM_D11 DRAM_D12 DRAM_D13 DRAM_D14 DRAM_D15 DRAM_D16 DRAM_D17 DRAM_D18 DRAM_D19 DRAM_D20 DRAM_D21 DRAM_D22 DRAM_D23 DRAM_D24 DRAM_D25 DRAM_D26 DRAM_D27 DRAM_D28 DRAM_D29 DRAM_D30 DRAM_D31 Micron DNU1 DNU2 DNU3 DNU4 DNU5 DNU6 DNU7 DNU8 DNU9 DNU10 DNU11 DNU12 DNU13 DNU14 DNU15 DNU16 NC_A3 NC_A4 NC_A5 NC_A6 NC_A7 NC_A8 NC_A9 NC_B4 NC_B5 NC_B6 NC_B7 NC_B8 NC_B9 NC_D1 NC_D2 NC_E1 NC_E2 NC_F1 NC_F2 NC_G1 NC_G2 NC_H1 NC_H2 NC_J1 NC_J2 NC_K1 NC_K2 NC_L1 NC_L2 NC_M1 NC_N1 NC_A10 NC_AC10 NC_AC11 VDDCA1 VDDCA2 VDDCA3 VREFCA VREFDQ VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDD2_1 VDD2_2 VDD2_3 VDD2_4 VDD2_5 VDD2_6 VDD2_7 VDD2_8 VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 A1 A2 A22 A23 B1 B2 B22 B23 AB1 AB2 AB22 AB23 AC1 AC2 AC22 AC23 A3 A4 A5 A6 A7 A8 A9 B4 B5 B6 B7 B8 B9 D1 D2 E1 E2 F1 F2 G1 G2 H1 H2 J1 J2 K1 K2 L1 L2 M1 N1 A10 AC10 AC11 U2 W2 AC8 P2 M22 B13 B16 B19 D22 G22 K22 R22 V22 AA22 AB13 AB16 AB19 B11 B21 C2 L22 R2 AA2 AB10 AB21 A11 A20 B3 N2 N22 AB5 AC20 DRAM_ZQ1 3 DNP R94 240 RC0402_25 1% C125 0.01uF 0201_CC 6.3V C118 0.01uF 0201_CC 6.3V C116 0.01uF 0201_CC 6.3V C114 0.01uF 0201_CC 6.3V GND GND P1V2_DDR_SW3 GND GND P1V2_DDR_SW3 GND P1V8_VLDO1 MT42L256M32D2LG-25 WT:A MT42L256M32D2 ZQ VSSCA1 VSSCA2 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10/NC VSS11 CS0 CS1 CKE0 CKE1 CK CK DM0 DM1 DM2 DM3 DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 U2 8Gb 400MHz clock LPDDR2 3 GND C121 0.1UF 0402_CC 16V C113 0.1UF 0402_CC 16V C109 0.1UF 0402_CC 16V C122 0.1UF 0402_CC 16V C117 22UF 0603_CC 6.3V C110 22UF 0603_CC 6.3V C212 0.1UF 0402_CC 16V DRAM_VREF C213 0.01uF 0201_CC 6.3V C120 0.1UF 0402_CC 16V C112 0.1UF 0402_CC 16V C108 0.1UF 0402_CC 16V C123 0.1UF 0402_CC 16V C408 22UF DNP 0603_CC 6.3V 2 Note: Some dual-die LPDDR2 packages require a separate ZQ at pin AC11. C126 0.1UF 0402_CC 16V C119 0.01uF 0201_CC 6.3V C111 0.1UF 0402_CC 16V C115 0.1UF 0402_CC 16V 2 C124 22UF 0603_CC 6.3V FCP: ___ FIUO: X 1 Sheet 7 SCH-28549 PDF: SPF-28549 Monday, March 30, 2015 LPDDR2 Document Number Date: of PUBI: ___ MCIMX6SLEVK-P3 board Size C Page Title: ICAP Classification: Drawing Title: 1 16 Rev A A B C D Schematic AN5113 Application Note Rev. 1.0 4/2015 9 A B C D KEY_COL3 ECSPI2_SCLK POR_B SD1_CLK SD1_CMD KEY_ROW7 KEY_COL7 SD1_DAT0 SD1_DAT1 SD1_DAT2 SD1_DAT3 SD1_DAT4 SD1_DAT5 SD1_DAT6 SD1_DAT7 R165 R166 DNP DNP R153 0 0 0 0402_CC 0402_CC 0402_CC DNP 4 GND NC7SZ08P5 U32 VCC_SDX R413 10K 0402_CC SD2_CLK SD2_CMD SD2_DAT7 SD2_DAT6 SD2_DAT0 SD2_DAT1 SD2_DAT2 SD2_DAT3 0 0402_CC 0 0402_CC 0 0402_CC R126 R122 R121 SD2_CD SD2_WP SD2_CON_CLK DNP R115 10K 0402_CC 5 2 14 15 7 8 9 1 10 11 12 13 CONN CRD 19 CLK CMD CD WP DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 J21 GND1 GND2 GND3 GND4 GND5 GND6 GND7 VSS2 VSS1 VDD S1 S2 S3 S4 S5 S6 S7 6 3 4 4-bit BOOT SD 6 5 4 GND GND C86 10V R1_C1 ON_OFF V_IN_R1 U33 S1 S2 S3 S4 S5 S6 S7 6 3 4 GND 1.0UF C137 0.1UF 0402_CC 16V 10V C138 10uF GND SH11 SH0805_40 1% R380 1.0K SOLDER SHORT VCC_SD1 10V C163 10uF FDC6331L DNP 1 2 3 VCC_SDX R2 V_OUT_C1_2 V_OUT_C1_1 VCC_SDX GND C158 0.1UF 0402_CC 16V VCC_SD1 SD3_DAT0 SD3_DAT1 SD3_DAT2 SD3_DAT3 SD3_CLK SD3_CMD REF_CLK_32K (6) (6) (6) (6) (6) (6) (6) 5 usdhc3.CD R175 0 0402_CC TP25 SD3_CON_CLK 5 2 14 15 7 8 9 1 10 11 12 13 4 CONN CRD 19 CLK CMD CD WP GND1 GND2 GND3 GND4 GND5 GND6 GND7 VSS2 VSS1 VDD For WiFi DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 J23 S1 S2 S3 S4 S5 S6 S7 6 3 4 GND GND C144 0.1UF 0402_CC 16V 10V C145 10uF VCC_SDX C146 47uF 3 VCC_SD1 SD3 - for WiFi and SD Accessories (6,8) (6,8) (6,8) (6,8) (6,8) (6,8) (6,8) (6,8) VCC_SDX GND1 GND2 GND3 GND4 GND5 GND6 GND7 VSS2 VSS1 VDD DNP R749 47K 0402_CC CONN CRD 19 CLK CMD CD WP VCC_SDX 5 2 14 15 DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 J22 low voltage IO cards requires power-cycling the card from sd1_rst_b. sd1_rst_b 2 1 VCC_SDX SD1_CON_CLK 7 8 9 1 10 11 12 13 SD2 - For Boot Code (6,11) (6,9,11) (4,6,11,13) (6) (6) (6,11) (6,11) (6) (6) (6) (6) (6) (6) (6) (6) 5 3 8-bit SD SD1 - For Primary External Card Slot 3 2 SD2_DAT2 SD2_DAT1 SD2_DAT0 (6,8) (6,8) (6,8) GND C131 0.1UF 0402_CC 16V H5 H4 H3 J6 J5 J4 J3 J2 GND C132 4.7uF 0402_CC 6.3V emmc_vddi C130 0.1UF 0402_CC 16V DAT2 DAT1 DAT0 DAT7 DAT6 DAT5 DAT4 DAT3 GND C134 0.1UF 0402_CC 16V RESET CMD U5 W5 W6 DNP U5A SDIN5C2-8G_NRND CLK GND C133 0.1UF 0402_CC 16V ECSPI1_MOSI ECSPI1_SCLK ECSPI1_SS0 (6) (6) (6) GND 2 C139 0.1UF 0402_CC 16V R123 10K 0402_CC norflash_wp DNP R124 10K 0402_CC 6 5 3 1 VCC 4 GND Q HOLD VSS W/VPP S C D 8 C135 0.1UF 0402_CC 16V C136 4.7uF 0402_CC 6.3V P3V15_VDDHIGH_SW2 Date: Size C (6) FIUO: X NC_A4 NC_A6 NC_A9 NC_A11 NC_B2 NC_B13 NC_D1 NC_D14 NC_H1 NC_H2 NC_H6 NC_H7 NC_H8 NC_H9 NC_H10 NC_H11 NC_H12 NC_H13 NC_H14 NC_J1 NC_J7 NC_J8 NC_J9 NC_J10 NC_J11 NC_J12 NC_J13 NC_J14 NC_K1 NC_K3 NC_K5 NC_K7 NC_K8 NC_K9 NC_K10 NC_K11 NC_K12 NC_K13 NC_K14 NC_L1 NC_L2 NC_L3 NC_L4 NC_L12 NC_L13 NC_L14 NC_M1 NC_M2 NC_M3 NC_M5 NC_M8 NC_M9 NC_M10 NC_M12 NC_M13 NC_M14 NC_N1 NC_N2 NC_N3 NC_N10 NC_N12 NC_N13 NC_N14 NC_P1 NC_P2 NC_P3 NC_P10 NC_P12 NC_P13 NC_P14 NC_R1 NC_R2 NC_R3 NC_R5 NC_R12 NC_R13 NC_R14 NC_T1 NC_T2 NC_T3 NC_T5 NC_T12 NC_T13 NC_T14 NC_U1 NC_U2 NC_U3 NC_U6 NC_U7 NC_U10 NC_U12 NC_U13 NC_U14 NC_V1 NC_V2 NC_V3 NC_V12 NC_V13 NC_V14 NC_W1 NC_W2 NC_W3 NC_W7 NC_W8 NC_W9 NC_W10 NC_W11 NC_W12 NC_W13 NC_W14 NC_Y1 NC_Y3 NC_Y6 NC_Y7 NC_Y8 NC_Y9 NC_Y10 NC_Y11 NC_Y12 NC_Y13 NC_Y14 NC_AA1 NC_AA2 NC_AA7 NC_AA8 NC_AA9 NC_AA10 NC_AA11 NC_AA12 NC_AA13 NC_AA14 NC_AE1 NC_AE14 NC_AG2 NC_AG13 NC_AH4 NC_AH6 NC_AH9 NC_AH11 Monday, March 30, 2015 1 Sheet 8 SCH-28549 PDF: SPF-28549 EMMC, SD and SPI NOR Document Number of PUBI: ___ DNP U5B SDIN5C2-8G_NRND MCIMX6SLEVK-P3 board ICAP Classification: Drawing Title: Page Title: 1 A4 A6 A9 A11 B2 B13 D1 D14 H1 H2 H6 H7 H8 H9 H10 H11 H12 H13 H14 J1 J7 J8 J9 J10 J11 J12 J13 J14 K1 K3 K5 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 L4 L12 L13 L14 M1 M2 M3 M5 M8 M9 M10 M12 M13 M14 N1 N2 N3 N10 N12 N13 N14 P1 P2 P3 P10 P12 P13 P14 FCP: ___ ECSPI1_MISO U13 M25P32-VMW6TG 7 2 R125 10K 0402_CC P3V15_VDDHIGH_SW2 4MB SPI NOR FLASH SD2_CLK SD2_CMD (6,8) (6,8) SD2_RST (6,11) Note: Place next to J21 SD2_DAT7 SD2_DAT6 SD2_DAT5 SD2_DAT4 SD2_DAT3 (6,8) (6,8) (6,11) (6,11) (6,8) C129 4.7uF 0402_CC 6.3V P3V15_VDDHIGH_SW2 8GB eMMC eMMC Footprint K2 VDDI 4 U9 T10 N5 M6 VCC4 VCC3 VCC2 VCC1 VSS4 VSS3 VSS2 VSS1 U8 R10 P5 M7 Y4 W4 K6 AA5 AA3 VCCQ5 VCCQ4 VCCQ3 VCCQ2 VCCQ1 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 10 Y5 Y2 K4 AA6 AA4 5 16 R1 R2 R3 R5 R12 R13 R14 T1 T2 T3 T5 T12 T13 T14 U1 U2 U3 U6 U7 U10 U12 U13 U14 V1 V2 V3 V12 V13 V14 W1 W2 W3 W7 W8 W9 W10 W11 W12 W13 W14 Y1 Y3 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 AA1 AA2 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AE1 AE14 AG2 AG13 AH4 AH6 AH9 AH11 Rev A A B C D Schematic AN5113 Application Note Rev. 1.0 4/2015 Freescale Semiconductor A B C USB_Host_VBUS USB_Host_D_N USB_Host_D_P (6) (6) (6) 2 120OHM 0603_CC C151 2.2uF CC0603 16V 4 1 GND (6,11) (6,11) 5 C154 0.1UF 0402_CC 16V SYS_5V 10V C155 10uF KEY_COL5 KEY_COL4 R192 R191 0 0402_CC 0 0402_CC R198 47K 0402_CC 90OHM L14 3 2 GND 6 7 4 usbotg2_pwr R197 47K 0402_CC 1 usbotg1_pwr hostusb_c_d_P hostusb_c_d_N USB_5V_HOST D13 ESD9L5.0ST5G Layout: Route 90ohm DIFF GND + C150 150 UF DNP CC7343A 10V USB 5V Control 1 L10 4 G GND hostusb_c_d_P D+ USB_TYPE_A D- 3 2 1 S2 OUTB OUTA FLGB 5 8 3 2 usbotg2_oc USB_5V_OTG 4 5 6 R179 330 0402_CC hostusb_c_d_N 10V C149 10uF 0 0402_CC 0 0402_CC GND USB_5V_HOST R194 R193 DNP R190 47K 0402_CC SRV05-4 U17 usbotg1_oc DNP R189 47K 0402_CC P3V15_VDDHIGH_SW2 V FLGA MIC2026-1YM GND IN ENB ENA U19 A1 A2 A3 A4 S1 J10 KEY_ROW4 ECSPI2_SCLK 3 (6,8,11) (6,11) (6,11) (6) (6) (6) 1 L11 2 120OHM 0603_CC EPDC_PWRCOM USB_OTG1_D_P USB_OTG1_D_N USBOTG1_ID R182 Layout: Route 90ohm DIFF USB_OTG1_VBUS GND 0 0402_CC C152 2.2uF CC0603 16V 2 C153 2.2uF CC0603 16V 4 1 90OHM L15 3 2 otg_usb_id otgusb_c_d_P otgusb_c_d_N USB_5V_OTG D14 ESD9L5.0ST5G S1 S3 USB Boot/Host/Device Port 2 USB Boot/Debug S2 S4 GND 10V 3 2 1 FIUO: X SRV05-4 U18 1 Sheet 9 SCH-28549 PDF: SPF-28549 Monday, March 30, 2015 Date: USB Document Number of 16 Rev A otgusb_c_d_N PUBI: ___ 4 5 6 MCIMX6SLEVK-P3 board FCP: ___ otg_usb_id 1 C148 10uF Size C Page Title: GND otgusb_c_d_P R178 330 0402_CC ICAP Classification: Drawing Title: G ID D+ D- 5V J9 MICRO USB AB 5 Micro USB-AB Receptacle 1 USB Host Port 3 2 4 3 D C A C A 4 Freescale Semiconductor 5 5 A B C D Schematic AN5113 Application Note Rev. 1.0 4/2015 11 A B C (6,11) (6,11) I2C2_SCL I2C2_SDA 5 P1V8_VLDO1 R215 DNP DNP GND 6 0 0 0402_CC 0402_CC TXS0102 OE A1 A2 5 4 CODEC_1V8 R782 1.0K DNP 1% R781 1.0K DNP 1% CODEC_1V8 GND C407 0.22UF 0201_CC 6.3V SH16 SH0805_40 SOLDER SHORT 4 2 GND 2 1 120OHM 0603_CC OUT 1 L17 L18 L19 (6) (6) (6) (6) (6) 1 C165 4.7uF 0402_CC 6.3V C215 0.1UF 0402_CC 16V C159 4.7uF 0603_CC 10V GND GND 1 AUD_MCLK AUD_TXC AUD_TXFS AUD_TXD AUD_RXD R720 2.2K 0402_CC MICBIAS C164 4.7uF 0402_CC 6.3V GND 1.0UF 10V C147 C161 4.7uF 0402_CC 6.3V C174 0.1UF 0402_CC 16V GND GND IN3R GND codec_i2c_scl codec_i2c_sda GND 10V C166 1.0UF C162 4.7uF 0402_CC 6.3V A_CODEC_1V8 MICVDD SPKVDD C160 4.7uF 0603_CC 10V layout note: Widen the trace SPKVDD Max ~0.6A CODEC_1V8 120OHM 0603_CC 2 CODEC_3V15 DNP 0 0603_CC 0 0603_CC WM-64PCT P4 2 120OHM 0603_CC or WM-63PR GND or CMC-2242PBL-A CODEC_1V8 SH15 SH0805_40 SOLDER SHORT P3V15_VDDHIGH_SW2 R780 R779 PF0100_VIN If you do not have any other devices at greater than 1.8V on the I2C bus, you can set the powers to 1.8V and bypass the level shifter. You will need to remove the 3V15 pull-ups on sheet 6 (R86 and R87). R216 B1 B2 U34 I2C2_SDA 8 1 GND I2C2_SCL I2C2_SCL I2C2_SDA C406 0.22UF 0201_CC 6.3V CODEC_3V15 7 VCCB 4 CODEC_1V8 CODEC_3V15 When bypassing the I2C level shifter you must : - change the DBVDD supply voltage to 3V15 - change the MX6SL IO pin supply voltage for all the codec digital pins - I2C2_SCL, & SDA - AUD_TXC, TXFS, TXD, RDX, & MCLK VCCA 3 GND 12 2 D 5 3 G7 F7 E1 D3 D1 D2 F1 E2 F2 E6 E7 F5 F6 D5 E5 C4 D4 D6 C6 G4 G2 A3 G3 A2 C2 WM8962 3 MCLK/XTI XTO BCLK LRCLK DACDAT ADCDAT SCLK SDA CIFMODE IN4L IN4R IN3L IN3R IN2L IN2R IN1L IN1R AVDD CPVDD PLLVDD DCVDD MICVDD DBVDD SPKVDD1 SPKVDD2 U6 VMIDC MICBIAS CLKOUT5 CLKOUT2/GPIO2 CLKOUT3/GPIO3 GPIO5 CS/GPIO6 CPCB CPVOUTN CPVOUTP CPCA SPKOUTRN SPKOUTRP SPKOUTLN SPKOUTLP HPOUTR HPOUTFB HPOUTL PLLGND SPKGND1 SPKGND2 AGND DGND CPGND C5 A4 G6 E4 F4 G1 E3 B7 A7 A6 B6 C3 B2 B3 A1 A5 B4 B5 G5 B1 C1 D7 F3 C7 GND GND GND Audio CODEC HPOUTL_ZOBEL GND DNP R204 10K 0402_CC HPOUTR DNP R205 10K 0402_CC J130 Audio Jack 10V C156 1.0UF GND GND C157 4.7uF 0402_CC 6.3V C376 2.2uF CC0603 16V 2 layout note: the positioning of C374 is very important should be as close to the WM8962 as possible. C375 2.2uF CC0603 16V GND HPOUTL 1 5 HPOUTR GND 6 4 HP_DET HPOUTL 4 3 2 1 HDR 1X4 DNP CON4 HeadPhone GND GND Layout note: Zobel Networks(c216,c217,r771,r772) close to WM8962 R772 20 RC0603 C217 0.1UF 0402_CC 16V FEC_RX_ER GND HPOUTR_ZOBEL C374 2.2uF CC0603 16V codec_vmidc MICBIAS R207 10K 0402_CC CPCB CPVOUTN CPVOUTP CPCA SPKOUTRN SPKOUTRP SPKOUTLN SPKOUTLP GND R771 20 RC0603 C216 0.1UF 0402_CC 16V (6) DNP R206 10K 0402_CC CODEC_3V15 2 4 3 2 1 5 6 FCP: ___ MECH FIUO: X 1 Sheet 10 SCH-28549 PDF: SPF-28549 Monday, March 30, 2015 Date: Audio Document Number of PUBI: ___ MCIMX6SLEVK-P3 board Size C Page Title: SIDE1 SIDE2 SM04B-SRSS-TB 4 3 2 1 CON500 ICAP Classification: Drawing Title: SPKOUTLP SPKOUTLN SPKOUTRP SPKOUTRN Speaker Out 1 16 Rev A A B C D Schematic AN5113 Application Note Rev. 1.0 4/2015 Freescale Semiconductor Freescale Semiconductor A B C D (6,11,12) (6,11,12) KEY_ROW2 (6,11,12) EPDC_PWRWAKEUP 0 (6)0402_CC R237 0 0 P1V5_VGEN2 GND 1% 5 GND CAP_TOUCH_INT SH6 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 SH8 SH5 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 SH7 QSH-060-01-L-D-A SH2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 SH4 J12 SH1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 SH3 GND (6,11) (6,11) 0 0 0 0 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC EPDC_D3 EPDC_D1 EPDC_D6 EPDC_D7 (6,11) (6,11) (6,11) (6,11) EPDC_SDOE (6,11) EPDC_D2 (6,11) epd_brightness_ctl R262 0 0402_CC EPDC_SDSHR (6,11) EPDC_PWRCOM (6,9) EPDC_PWRSTAT (6) EPDC_PWRCTRL0 (6) EPDC_PWRCTRL1 (6) EPDC_PWRCTRL2 (6) EPDC_GDCLK (6,11) EPDC_GDSP (6,11) EPDC_GDOE (6,11) EPDC_GDRL (6,11) EPDC_SDCLK (6,11) TP39 TP40 (6,11) (6,11) (6) (6) (6) (6) (6,11) CAP_TOUCH_RST R247 R248 R244 R245 EPDC_SDCE3 EPDC_SDCE2 EPDC_SDCE1 EPDC_SDCE0 EPDC_BDR1 EPDC_BDR0 EPDC_SDLE TP30 TP29 EPDC_D4 EPDC_D5 0 0 0 (6,11) 3_AXIS_INT R226 R228 R231 EPDC_SDCLK uart2_TXD uart2_RXD spdif_out SYS_5V 2 1% CONN PLUG 40 46 42 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 44 GND AF_GND CMOS_XCLK COMS_DVDD TP41 AF_VCC VCMSINK R270 COMS_AVDD Layout Note: Place next to J12 GND 41 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 43 45 J24 GND 4 2 120OHM 0603_CC R268 AF_GND GND GND 1 L22 2 GND 10V C178 1.0UF P1V5_VGEN2 P2V8_VGEN6 P1V8_VGEN4 C177 120OHM 0.1UF 0603_CC 0402_CC 16V 0 0402_CC C176 4.7uF 0402_CC 6.3V (6) (6,11,12) (6,8,11) (6,11,12) (6,11,12) (6) (6,8,11) (6,8,11) (6,10,11) (6,11) DNP 0 0402_CC PWM1 KEY_COL6 KEY_COL2 KEY_COL3 KEY_COL0 KEY_COL1 KEY_ROW6 SD2_DAT5 SD2_DAT4 I2C2_SDA (6,11) GND C179 0.1UF 0402_CC 16V P2V8_VGEN6 EPDC_GDRL C175 0.1UF 0402_CC 16V R272 DNP 10K 0402_CC 1 L21 Use Omnivision OV5642 5M Pixel Sensor with this connector (not included) I2C3_SDA I2C3_SCL CMOS_RESET_B GPIO CSI_PIXCLK CSI_VSYNC CSI_HSYNC GPIO CMOS_PWDN CSI_D9 CSI_D8 CSI_D7 CSI_D6 CSI_D5 CSI_D4 CSI_D3 CSI_D2 CSI_D1 CSI_D0 DNP CMOS_AGND CMOS_AGND 120OHM 0603_CC R90 1.0K 1 L20 Camera Expansion Connector (4,6,8,13) POR_B EPDC_PWRCTRL3 R89 1.0K DNP EPDC_VCOM0 EPDC_VCOM1 EPDC_D10 EPDC_D12 EPDC_D13 EPDC_D14 EPDC_D15 P1V5_VGEN2 (6,11) (6) (6) (6) (6) (6) (6) (6) EPDC_D11 EPDC_D9 (6) (6) EPDC_D8 (6) 0402_CC 0402_CC EPD_TOUCH_Y1 EPD_TOUCH_Y0 EPD_TOUCH_X1 EPD_TOUCH_X0 R252 R254 SYS_5V PF0100_VIN EPDC_D0 EPDC_PWRINT (6,11) (6) epd_i2c_sda epd_i2c_scl 0 0 0 R227 R236 R230 spdif_in 0 (6,11) EPDC_SDCE3 (6,11) EPDC_SDCE2 (6,11) EPDC_SDSHR (6,11) EPDC_GDCLK (6,11) EPDC_GDSP (6,11) EPDC_GDOE (6,11) EPDC_SDOE (6,11) EPDC_SDLE (6,11) EPDC_SDCLK (6,11) EPDC_D7 (6,11) EPDC_D6 (6,11) EPDC_D5 (6,11) EPDC_D4 (6,11) EPDC_D3 (6,11) EPDC_D2 (6,11) EPDC_D1 (6,11) EPDC_D0 TP31 TP33 TP35 TP37 KEY_ROW0 KEY_ROW1 P1V8_VGEN4 R225 0402_CC 0402_CC 0402_CC 4 EPDC Expansion Port P3V15_VDDHIGH_SW2 0402_CC SYS_5V P3V15_VDDHIGH_SW2 KEY_ROW3 I2C1_SDA I2C1_SCL I2C2_SCL (6,11) (4,6) (4,6) (6,10,11) PF0100_VIN 5 LCD_HSYNC I2C2_SDA I2C2_SCL LCD_CLK ECSPI2_MISO ECSPI2_MOSI ECSPI2_SCLK ECSPI2_SS0 KEY_ROW5 SD2_RST KEY_ROW0 KEY_ROW1 LCD_CLK KEY_ROW2 KEY_COL3 KEY_COL2 KEY_COL1 I2C2_SDA I2C2_SCL LCD_RESET KEY_COL0 KEY_ROW3 R265 R266 R267 R259 R260 R261 R263 R257 R249 R246 R243 R238 R240 R232 R235 R233 R229 R234 DNP 0 0 DNP 0 DNP 0 0 0 DNP 0 33 DNP 0 DNP 0 DNP 0 DNP 0 DNP 0 DNP 0 DNP 0 DNP 0 0 0 PF0100_VIN P1V8_VGEN4 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC lcdif.RD_E lcd_int hdmi_card_int lcdif.RS lcdif.CS 51EXP_i2c_sda 51EXP_i2c_scl lcdif.WR_RWN lcd_spi_sclk lcd_pwr_en SYS_5V PF0100_VIN 51EXP_spdif_out P3V15_VDDHIGH_SW2 lcd_display_clk lcd_i2c_sda lcd_i2c_scl SYS_5V P3V15_VDDHIGH_SW2 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 2 GND J13 SH6 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 SH8 SH2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 SH4 QSH-060-01-L-D-A GND SH5 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 SH7 SH1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 SH3 0 0 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC LCD_HSYNC LCD_ENABLE (6,11) (6,11) LCD_DAT0 (6,13) LCD_DAT1 (6,13) LCD_DAT2 (6,13) LCD_DAT3 (6,13) LCD_DAT4 (6,13) LCD_DAT5 (6,13) LCD_DAT6 (6,13) LCD_DAT7 (6,13) LCD_DAT8 (6,13) LCD_DAT9 (6,13) LCD_DAT10 (6,13) LCD_DAT11 (6,13) LCD_DAT12 (6,13) LCD_DAT13 (6,13) LCD_DAT14 (6,13) LCD_DAT15 (6,13) LCD_DAT16 (6,13) LCD_DAT17 (6,13) LCD_DAT18 (6,13) LCD_DAT19 (6,13) LCD_DAT20 (6,13) LCD_DAT21 (6,13) LCD_DAT22 (6,13) LCD_DAT23 (6,13) LCD_VSYNC (6,11) R264 0 0402_CC DNP 0 DNP 0 DNP 0 DNP 0 DNP 0 SD2_DAT5 SD2_DAT4 1 PWM1 KEY_ROW7 KEY_COL7 KEY_ROW4 KEY_COL4 KEY_COL5 3 2 FCP: ___ FIUO: X (6,11) (6,8) (6,8) (6,9) (6,9) (6,9) (6,8,11) (6,8,11) 1 Sheet SCH-28549 PDF: SPF-28549 Monday, March 30, 2015 Video Document Number Date: 11 of PUBI: ___ MCIMX6SLEVK-P3 board Size C Page Title: ICAP Classification: Drawing Title: One of these two peripherals MUST BE REMOVED when a developer wishes to use the other. The camera connector (J24) and the EPDC connector (J12) share the same signals and CANNOT be used at the same time. 51EXP_GPIO lcd_brightness_ctl 51EXP_CAM_PWDN 51EXP_RESET 51EXP_csi_VSYNC 51EXP_csi_HSYNC 51EXP_csi_PIXCLK 51EXP_csi_MCLK 51EXP_csi_D9 51EXP_csi_D8 51EXP_csi_D7 51EXP_csi_D6 51EXP_csi_D5 51EXP_csi_D4 51EXP_csi_D3 51EXP_csi_D2 51EXP_csi_D1 51EXP_csi_D0 R253 R255 R250 R251 R239 51EXP_uart2_TXR241 hdmi_spdif_out 51EXP_uart2_RXR242 SYS_5V LCD Expansion Port Important Note: (6,11) LCD_ENABLE (6,11) EPDC_PWRCTRL3 (6,11) LCD_VSYNC (6,11) (6,10,11) (6,10,11) (6,11) (3,6) (3,6) (6,8,9) (3,6) (6) (6,8) (6,11,12) (6,11,12) (6,11) (6,11,12) (6,8,11) (6,11,12) (6,11,12) (6,10,11) (6,10,11) (6) (6,11,12) (6,11) 3 16 Rev A A B C D Schematic AN5113 Application Note Rev. 1.0 4/2015 13 14 A B C D TP45 TP43 TP44 TP42 3.3V_1 GND7 1.5V_1 UIM_PWR UIM_DATA UIM_CLK UIM_RESET UIM_VPP CON 2X26 MINI PCI EXPRESS Reserved/UIM_C8 GND8 Reserved/UIM_C4W_DISABLE# GND3 PERST# PERn0 +3.3Vaux PERp0 GND9 GND4 1.5V_2 GND5 SMB_CLK PETn0 SMB_DATA PETp0 GND10 GND6 USB_DReserved3 USB_D+ Reserved4 GND11 Reserved5 LED_WWAN# Reserved6 LED_WLAN# Reserved7 LED_WPAN# Reserved8 1.5V_3 Reserved9 GND12 Reserved10 3.3V_2 WAKE# Reserved1 Reserved2 CLKREQ# GND1 REFCLKREFCLK+ GND2 J8 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 2 4 6 8 10 12 14 16 KEY_COL2 (6,11) 5 KEY_COL1 (6,11) KEY_ROW2 (6,11) KEY_COL0 KEY_ROW1 (6,11) (6,11) KEY_ROW0 (6,11) 1 2 4 SPST PB 2 3 SW12 1 4 SPST PB 2 3 SW9 1 4 SPST PB GND 3 SW6 Button Matrix GND 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 1 3 5 7 9 11 13 15 3 LED Red 4 A 4 SPST PB 3 SW13 4 SPST PB 3 SW10 4 SPST PB 3 SW7 R309 330 0402_CC C D18 SIM_VCC SIM_IO SIM_CLK SIM_RESET SIM_VPP GND C180 100UF CC1210 10V 3GCARD_ON 3GCARD_RST C181 100UF CC1210 10V C183 0.1UF 0402_CC 16V DNP R306 47K 0402_CC C184 0.1UF 0402_CC 16V 2 1 2 1 2 1 4 SPST PB 3 SW11 4 SPST PB 3 SW8 3 Layout: Route 90ohm DIFF DNP R305 47K 0402_CC 3GCARD_PWR C182 0.1UF 0402_CC 16V (6) (6) C192 100UF CC1210 10V DNP 2 1 2 1 PCIE_USB_Host_D_N PCIE_USB_Host_D_P AUD_RXFS AUD_RXC C140 4.7uF 0402_CC 6.3V DNP (6) (6) C191 100UF CC1210 10V DNP C210 100UF CC1210 10V DNP MMPF0100's SW2 capacitive load recommendation is <500uF total. Do not populate C140, C191, C192 and C210 3GCARD_PWR Mini-PCIe HMC (3G Modem) 4 J18 HDR 1X2 2 2 SIM_IO SIM_VPP 1 2 5 GND 6 5 4 CLK RESET VCC 3 2 1 FIUO: X Monday, March 30, 2015 Date: 1 Sheet 12 of PUBI: ___ SCH-27452 PDF: SPF-27452 Document Number Wireless MCIMX6SLEVK board FCP: ___ SIM_CLK SIM_RESET SIM_VCC Size B Page Title: ICAP Classification: Drawing Title: CON 6 SIM CARD I/O VPP GND J133 P3V15_VDDHIGH_SW2 1 16 Rev B A B C D Schematic AN5113 Application Note Rev. 1.0 4/2015 Freescale Semiconductor A B C D (4,6,8,11) R721 0 0402_CC GND 20K 0402_CC 20K 0402_CC 20K 0402_CC 20K 0402_CC R326 R328 R330 R332 20K 0402_CC 20K 0402_CC 20K 0402_CC 20K 0402_CC 20K 0402_CC 20K 0402_CC 20K 0402_CC 20K 0402_CC 20K 0402_CC 20K 0402_CC 20K 0402_CC 20K 0402_CC R343 R345 R347 R349 R353 R352 R356 R358 R360 R362 R364 R366 5 20K 20K 20K 20K R336 R335 R339 R341 0402_CC 0402_CC 0402_CC 0402_CC 20K 20K 20K 20K R318 R319 R320 R324 0402_CC 0402_CC 0402_CC 0402_CC BT_CFG_EN VCC_BT_CFG_OE POR_B GND Boot Strap Power Control 2A 1G 1A 7 2G 5 1 2 U31 P3V15_VDDHIGH_SW2 0603_CC 0 SW5 SW DIP-8 GND 0 VCC_BootStrap BT_CFG_EN 0603_CC SW4 SW DIP-8 output_pulse R41 SN74LVC2G125 2Y 3 1Y 6 R722 47K 0402_CC VCC_BT_CFG_OE VCC_BT_CFG_OE VCC_BT_CFG_OE R42 8 VCC GND 4 Boot Strap 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Freescale Semiconductor 1 2 3 4 5 6 7 8 5 4 4 10V BT_CFG28 BT_CFG29 BT_CFG30 BT_CFG31 BT_CFG24 BT_CFG25 BT_CFG26 BT_CFG27 BT_CFG12 BT_CFG13 BT_CFG14 BT_CFG15 BT_CFG8 BT_CFG9 BT_CFG10 BT_CFG11 BT_CFG4 BT_CFG5 BT_CFG6 BT_CFG7 BT_CFG0 BT_CFG1 BT_CFG2 BT_CFG3 SW3 SW DIP-8 GND C218 1.0UF 19 17 15 13 11 1 2 4 6 8 19 17 15 13 11 1 2 4 6 8 19 17 15 13 11 1 2 4 6 8 GND 2Y0 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3 VCC GND 2Y0 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3 VCC GND 2Y0 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3 VCC 74LVC244APW 2OE 2A0 2A1 2A2 2A3 1OE 1A0 1A1 1A2 1A3 U24 74LVC244APW 2OE 2A0 2A1 2A2 2A3 1OE 1A0 1A1 1A2 1A3 U23 74LVC244APW 2OE 2A0 2A1 2A2 2A3 1OE 1A0 1A1 1A2 1A3 U21 10 3 5 7 9 18 16 14 12 20 10 3 5 7 9 18 16 14 12 20 10 3 5 7 9 18 16 14 12 20 GND 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K GND R361 R363 R365 R367 R354 R355 R357 R359 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K VCC_BT_CFG_OE GND R344 R346 R348 R350 R337 R338 R340 R342 VCC_BT_CFG_OE GND R327 R329 R331 R333 R321 R322 R323 R325 VCC_BT_CFG_OE Bus isolation VCC_BT_CFG_OE 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC 0402_CC C187 0.1UF 0402_CC 16V GND 3 C185 0.1UF 0402_CC 16V GND LCD_DAT20 LCD_DAT21 LCD_DAT22 LCD_DAT23 LCD_DAT16 LCD_DAT17 LCD_DAT18 LCD_DAT19 LCD_DAT12 LCD_DAT13 LCD_DAT14 LCD_DAT15 LCD_DAT8 LCD_DAT9 LCD_DAT10 LCD_DAT11 LCD_DAT4 LCD_DAT5 LCD_DAT6 LCD_DAT7 LCD_DAT0 LCD_DAT1 LCD_DAT2 LCD_DAT3 C186 0.1UF 0402_CC 16V Note: i.MX6SL reads values approximately 300uS to 1mS after reset released. Buffers are active while unit is in reset and 1ms-10ms after reset is released. 3 (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) (6,11) VCC_BootStrap VCC_BT_CFG_OE 0603_CC R47 0603_CC R44 0 0 R311 1.0K 1% R310 1.0K 1% 1 2 4 3 SW_DIP-2/SM S1 BOOT_MODE0 BOOT_MODE1 Boot Strap Primary Switches DNP NOTE : GND GND H2 .635" LONG DNP GND H3 .635" LONG DNP GND H4 .635" LONG (6) (6) TP65 TP66 2 TP67 GND GND TEST POINTS TP68 TP69 TP70 TP71 FCP: ___ 1 FIUO: X 1 Sheet 13 SCH-28549 PDF: SPF-28549 Monday, March 30, 2015 Date: MISC Document Number of PUBI: ___ MCIMX6SLEVK-P3 board Size C Page Title: ICAP Classification: Drawing Title: TP72 Use non metalic or non conducting standoff to avoid board damage due to GND potential difference with chasis. IMPORTANT DNP H1 .635" LONG Board Mounting Holes for 4-40 Screws DNP 2 16 Rev A A B C D Schematic AN5113 Application Note Rev. 1.0 4/2015 15 A B C 5 JTAG_MOD JTAG_TDO JTAG_nSRST (6) (6) (6) JTAG_TRSTB JTAG_TDI JTAG_TMS JTAG_TCK TP75 R375 10K 0402_CC R400 4.7K 0402_CC DNP R399 10K 0402_CC P3V15_VDDHIGH_SW2 GND 2A 2OE 1A 1OE 8 2Y 1Y 3 6 C209 0.1UF 0402_CC 16V GND 4 GND D21 LED Red led8 1% R377 1.0K J_DE_B J_DBGACK JTAG_RTCK R392 100 0402_CC 1% VTREF_JTAG R395 R396 R397 10K 10K 10K 0402_CC 0402_CC 0402_CC DNP DNP R390 R391 10K 10K 0402_CC 0402_CC GND SN74LVC2G126 4 VCC debug_uart_en 5 7 2 1 U27 GND R386 R387 R389 DNP 10K 10K 1.0K R388 0402_CC 0402_CC 10K 0402_CC 1% P3V15_VDDHIGH_SW2 JTAG UART1_TXD UART1_RXD (6) (6) (6) (6) (6) (6) TP76 A C tx232 rx232 30 2 32 8 31 6 7 3 22 21 10 11 9 TXD RXD RTS# CTS# DTR# DSR# DCD# RI# CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 U28 FT232RQ RESET# NC6 OSCI OSCO 3V3OUT USBDP NC1 NC2 NC3 NC4 NC5 USBDM VCCIO VCC GND 18 23 27 28 16 14 5 12 13 25 29 15 1 19 ftdi_3v3out ftdi_reset GND debug_5v 10V C200 1.0UF R381 10K 0402_CC C206 0.1UF 0402_CC 16V 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 JTAG_PWR TST-110-05-T-D-RA J7 3 C198 0.1UF 0402_CC 16V GND (6) HSIC_STROBE_GPIO Debug LED For driver installation, please refer to http://www.ftdichip.com/Documents/InstallGuides.htm tx_led rx_led D22 LED Green led9 1% R378 1.0K 3 L23 2 debug_usb_d_P debug_usb_d_N debug_usb_5v led7_3 1 2 GND Q5 MMBT3904 led7_2 D23 LED Green led7_1 R394 330 0402_CC P3V15_VDDHIGH_SW2 GND G ID D+ D- 5V J26 MICRO USB AB 5 DEBUG_SHL_GND Layout note: 90ohm diff pairs 120OHM 0603_CC R398 10K 0402_CC C199 4.7uF 0402_CC 6.3V 1 S1 S3 2 1 P3V15_VDDHIGH_SW2 A C 2 Debug UART2USB Converter TEST GND4 GND2 GND1 AGND EP 3 4 A C 3 2 26 20 17 4 24 33 4 16 5 D 5 S2 S4 GND R409 100 0402_CC 1% FCP: ___ FIUO: X 1 Sheet 14 SCH-28549 PDF: SPF-28549 Monday, March 30, 2015 Date: UART & JTAG Document Number of PUBI: ___ MCIMX6SLEVK-P3 board Size C Page Title: ICAP Classification: Drawing Title: C14 0.1UF 0402_CC 16V 1 16 Rev A A B C D Schematic AN5113 Application Note Rev. 1.0 4/2015 Freescale Semiconductor A B C 5 FEC_TXD0 FEC_TXD1 FEC_TX_EN (6) (6) (6) FEC_REF_CLK FEC_RXD0 FEC_RXD1 FEC_CRS_DV (6) (6) (6) (6) FEC_MDIO FEC_MDC (6) (6) (6) GND 1 4 2 TP51 ENET_RST 17 18 16 8 7 11 12 13 TXD0 TXD1 TXEN 4 5 15 10V LAN8720A XTAL2 XTAL1/CLKIN RST 1 C203 10uF RXD0/MODE0 RXD1/MODE1 CRS_DV/MODE2 MDIO MDC R425 10K 0402_CC FEC3V15 TP50 GND C202 0.1UF 0402_CC 16V U8 0 SH0603 GND Q7 2N7002 enet_ctl_signal power_rail_enet GND 2 1 3 IRLML6401 Q6 3 FEC3V15 RXN RXP TXN TXP 3 RBIAS VDDCR INT/REFCLKO RXER/PHYAD0 LED2/INTSEL LED1/REGOFF GND C204 0.1UF 0402_CC 16V GND ENET_LED1 ENET_LED2 ENET_PHYAD0 ENET_INT_B ENET_VDDCR 3 2 10 14 6 GND C207 0.1UF R431 0402_CC 12.1K 16V 0402_CC 1% RX_N 22 C208 4.7uF 0402_CC 6.3V R426 10K 0402_CC FEC3V15 PHY ADDR:0x0 (default) R432 10K 0402_CC DNP R424 10K 0402_CC R418 330 0402_CC Mag_led2 2 FEC3V15 GND 13 14 11 12 7 8 5 6 3 4 C205 0.01UF 0402_CC 16V Mag_led1 R407 0 0402_CC 1 2 RX_P 24 R406 49.9 0603_CC GND R415 330 0402_CC R405 49.9 0603_CC SH8 RJ45 8 LED2_C LED2_A LED1_C LED1_A NC GND RCT RD- TDRD+ TD+ TCT J11 0 TX+ RX- GND_ENET SH0603 J8 J7 J6 J5 J4 RX+ TX- J1 J3 J2 FCP: ___ 1 FIUO: X 1 Sheet 15 SCH-28549 PDF: SPF-28549 Monday, March 30, 2015 Date: ENET Document Number of PUBI: ___ MCIMX6SLEVK-P3 board Size C Page Title: ICAP Classification: Drawing Title: GND_ENET is a small isolated GND plane which should extend under RJ45 connector LAYOUT NOTES: 1. The TX and RX diff pairs should be routed with a 100ohm differential impedance and a 50ohm single ended (characteristic) impedance. 2. The trace lengths within a TX and RX differential pair should be matched. 3. The distance between each TX and RX differential pair should be 50mils or more. TX_N GND R404 49.9 0603_CC FEC3V15 R403 49.9 0603_CC A_FEC_3V15 2 TX_P 23 20 21 Power Control R411 10K 0402_CC A_FEC_3V15 FEC3V15 Ethernet ENET_PWR_EN C201 0.1UF 0402_CC 16V R402 47K 0402_CC R408 2.2K 0402_CC FEC3V15 120OHM 0603_CC L24 C87 0.1UF 0402_CC 16V FEC3V15 FEC_TX_CLK High Level on SH7 3 2 P3V15_VDDHIGH_SW2 19 VDD1A 4 VDD2A 9 VDDIO 1 VSS 25 Chassis_GND1 Chassis_GND2 Freescale Semiconductor 9 10 D 5 16 Rev A A B C D Schematic AN5113 Application Note Rev. 1.0 4/2015 17 WDOG_B HSIC_DAT HSIC_STROBE REF_CLK_24M REF_CLK_32K PWM1 KEY_COL0 KEY_ROW0 KEY_COL1 KEY_ROW1 KEY_COL2 KEY_ROW2 KEY_COL3 KEY_ROW3 KEY_COL4 KEY_ROW4 KEY_COL5 KEY_ROW5 KEY_COL6 KEY_ROW6 KEY_COL7 KEY_ROW7 EPDC_D0 EPDC_D1 EPDC_D2 EPDC_D3 EPDC_D4 EPDC_D5 EPDC_D6 EPDC_D7 EPDC_D8 EPDC_D9 EPDC_D10 EPDC_D11 EPDC_D12 EPDC_D13 EPDC_D14 EPDC_D15 EPDC_SDCLK EPDC_SDLE EPDC_SDOE EPDC_SDSHR EPDC_SDCE0 EPDC_SDCE1 EPDC_SDCE2 EPDC_SDCE3 EPDC_GDCLK EPDC_GDOE EPDC_GDRL EPDC_GDSP EPDC_VCOM0 EPDC_VCOM1 EPDC_BDR0 EPDC_BDR1 EPDC_PWRCTRL0 EPDC_PWRCTRL1 EPDC_PWRCTRL2 EPDC_PWRCTRL3 EPDC_PWRCOM EPDC_PWRINT EPDC_PWRSTAT EPDC_PWRWAKEUP LCD_CLK LCD_ENABLE LCD_HSYNC LCD_VSYNC LCD_RESET LCD_DAT0 LCD_DAT1 LCD_DAT2 LCD_DAT3 LCD_DAT4 LCD_DAT5 LCD_DAT6 LCD_DAT7 LCD_DAT8 LCD_DAT9 LCD_DAT10 LCD_DAT11 LCD_DAT12 LCD_DAT13 LCD_DAT14 LCD_DAT15 LCD_DAT16 LCD_DAT17 LCD_DAT18 LCD_DAT19 LCD_DAT20 LCD_DAT21 LCD_DAT22 LCD_DAT23 AUD_RXFS AUD_RXC AUD_RXD AUD_TXC AUD_TXFS AUD_TXD AUD_MCLK UART1_RXD UART1_TXD I2C1_SCL I2C1_SDA I2C2_SCL I2C2_SDA ECSPI1_SCLK ECSPI1_MOSI ECSPI1_MISO ECSPI1_SS0 ECSPI2_SCLK ECSPI2_MOSI ECSPI2_MISO ECSPI2_SS0 SD1_CLK SD1_CMD SD1_DAT0 SD1_DAT1 SD1_DAT2 SD1_DAT3 SD1_DAT4 SD1_DAT5 SD1_DAT6 SD1_DAT7 SD2_RST SD2_CLK SD2_CMD SD2_DAT0 SD2_DAT1 SD2_DAT2 SD2_DAT3 SD2_DAT4 SD2_DAT5 SD2_DAT6 SD2_DAT7 SD3_CLK SD3_CMD SD3_DAT0 SD3_DAT1 SD3_DAT2 SD3_DAT3 FEC_MDIO FEC_TX_CLK FEC_RX_ER FEC_CRS_DV FEC_RXD1 FEC_TXD0 FEC_MDC FEC_RXD0 FEC_TX_EN FEC_TXD1 FEC_REF_CLK wdog1.WDOG_B usb.H_DATA usb.H_STROBE anatop.ANATOP_24M_OUT anatop.ANATOP_32K_OUT pwm1.PWMO kpp.COL[0] kpp.ROW[0] kpp.COL[1] kpp.ROW[1] kpp.COL[2] kpp.ROW[2] kpp.COL[3] kpp.ROW[3] kpp.COL[4] kpp.ROW[4] kpp.COL[5] kpp.ROW[5] kpp.COL[6] kpp.ROW[6] kpp.COL[7] kpp.ROW[7] epdc.SDDO[0] epdc.SDDO[1] epdc.SDDO[2] epdc.SDDO[3] epdc.SDDO[4] epdc.SDDO[5] epdc.SDDO[6] epdc.SDDO[7] epdc.SDDO[8] epdc.SDDO[9] epdc.SDDO[10] epdc.SDDO[11] epdc.SDDO[12] epdc.SDDO[13] epdc.SDDO[14] epdc.SDDO[15] epdc.SDCLK epdc.SDLE epdc.SDOE epdc.SDSHR epdc.SDCE[0] epdc.SDCE[1] epdc.SDCE[2] epdc.SDCE[3] epdc.GDCLK epdc.GDOE epdc.GDRL epdc.GDSP epdc.VCOM[0] epdc.VCOM[1] epdc.BDR[0] epdc.BDR[1] epdc.PWRCTRL[0] epdc.PWRCTRL[1] epdc.PWRCTRL[2] epdc.PWRCTRL[3] epdc.PWRCOM epdc.PWRIRQ epdc.PWRSTAT epdc.PWRWAKE lcdif.CLK lcdif.ENABLE lcdif.HSYNC lcdif.VSYNC lcdif.RESET lcdif.DAT[0] lcdif.DAT[1] lcdif.DAT[2] lcdif.DAT[3] lcdif.DAT[4] lcdif.DAT[5] lcdif.DAT[6] lcdif.DAT[7] lcdif.DAT[8] lcdif.DAT[9] lcdif.DAT[10] lcdif.DAT[11] lcdif.DAT[12] lcdif.DAT[13] lcdif.DAT[14] lcdif.DAT[15] lcdif.DAT[16] lcdif.DAT[17] lcdif.DAT[18] lcdif.DAT[19] lcdif.DAT[20] lcdif.DAT[21] lcdif.DAT[22] lcdif.DAT[23] audmux.AUD3_RXFS audmux.AUD3_RXC audmux.AUD3_RXD audmux.AUD3_TXC audmux.AUD3_TXFS audmux.AUD3_TXD audmux.AUDIO_CLK_OUT uart1.RXD_MUX uart1.TXD_MUX i2c1.SCL i2c1.SDA i2c2.SCL i2c2.SDA ecspi1.SCLK ecspi1.MOSI ecspi1.MISO ecspi1.SS0 ecspi2.SCLK ecspi2.MOSI ecspi2.MISO ecspi2.SS0 usdhc1.CLK usdhc1.CMD usdhc1.DAT0 usdhc1.DAT1 usdhc1.DAT2 usdhc1.DAT3 usdhc1.DAT4 usdhc1.DAT5 usdhc1.DAT6 usdhc1.DAT7 usdhc2.RST usdhc2.CLK usdhc2.CMD usdhc2.DAT0 usdhc2.DAT1 usdhc2.DAT2 usdhc2.DAT3 usdhc2.DAT4 usdhc2.DAT5 usdhc2.DAT6 usdhc2.DAT7 usdhc3.CLK usdhc3.CMD usdhc3.DAT0 usdhc3.DAT1 usdhc3.DAT2 usdhc3.DAT3 fec.MDIO fec.TX_CLK fec.RX_ER fec.RX_DV fec.RDATA[1] fec.TDATA[0] fec.MDC fec.RDATA[0] fec.TX_EN fec.TDATA[1] fec.REF_OUT wdog1.WDOG_RST_B_DEB i2c1.SCL i2c1.SDA i2c3.SCL i2c3.SDA ccm.CLKO i2c2.SCL i2c2.SDA ecspi4.MOSI ecspi4.MISO ecspi4.SS0 ecspi4.SCLK audmux.AUD6_RXFS audmux.AUD6_RXC audmux.AUD6_RXD audmux.AUD6_TXC audmux.AUD6_TXFS audmux.AUD6_TXD uart4.RXD_MUX uart4.TXD_MUX uart4.RTS uart4.CTS ecspi4.MOSI ecspi4.MISO ecspi4.SS0 ecspi4.SCLK ecspi4.SS1 ecspi4.SS2 ecspi4.SS3 ecspi4.RDY ecspi3.MOSI ecspi3.MISO ecspi3.SS0 ecspi3.SCLK uart2.RXD_MUX uart2.TXD_MUX uart2.RTS uart2.CTS ecspi2.MOSI ecspi2.MISO ecspi2.SS0 ecspi2.SCLK ecspi2.SS1 wdog2.WDOG_B i2c3.SCL i2c3.SDA ecspi2.SS2 ecspi2.SS3 ecspi2.RDY pwm4.PWMO audmux.AUD5_RXFS audmux.AUD5_RXD usdhc4.CLK usdhc4.CMD audmux.AUD5_RXC audmux.AUD5_TXFS audmux.AUD5_TXD audmux.AUD5_TXC usdhc4.DAT0 usdhc4.DAT1 usdhc4.DAT2 usdhc4.DAT3 usdhc4.DAT4 usdhc4.DAT5 usdhc4.DAT6 usdhc4.DAT7 weim.WEIM_DTACK_B ecspi1.MOSI ecspi1.MISO ecspi1.SS0 ecspi1.SCLK ecspi1.SS1 ecspi1.SS2 ecspi1.SS3 ecspi1.RDY kpp.COL[0] kpp.ROW[0] kpp.COL[1] kpp.ROW[1] kpp.COL[2] kpp.ROW[2] kpp.COL[3] kpp.ROW[3] kpp.COL[4] kpp.ROW[4] kpp.COL[5] kpp.ROW[5] kpp.COL[6] kpp.ROW[6] kpp.COL[7] kpp.ROW[7] i2c1.SCL i2c1.SDA ecspi3.MOSI ecspi3.MISO pwm3.PWMO ecspi3.SCLK pwm4.PWMO pwm1.PWMO pwm2.PWMO uart1.RTS uart1.CTS audmux.AUD4_RXFS audmux.AUD4_RXC audmux.AUD4_TXD audmux.AUD4_TXC audmux.AUD4_TXFS audmux.AUD4_RXD spdif.SPDIF_EXT_CLK sdma.SDMA_EXT_EVENT[1] sdma.SDMA_EXT_EVENT[0] ecspi1.SS3 fec.MDIO fec.TX_CLK fec.RX_ER fec.RX_DV fec.RDATA[1] fec.TDATA[0] fec.MDC fec.RDATA[0] fec.TX_EN fec.TDATA[1] fec.REF_OUT audmux.AUD4_RXFS audmux.AUD4_RXC audmux.AUD4_RXD audmux.AUD4_TXC audmux.AUD4_TXFS audmux.AUD4_TXD usdhc3.DAT4 usdhc3.DAT5 usdhc3.DAT6 usdhc3.DAT7 audmux.AUD5_RXFS audmux.AUD5_RXC audmux.AUD5_RXD audmux.AUD5_TXC audmux.AUD5_TXFS audmux.AUD5_TXD usdhc4.CLK usdhc4.CMD usdhc4.DAT0 usdhc4.DAT1 usdhc4.DAT2 usdhc4.DAT3 usdhc4.DAT4 usdhc4.DAT5 usdhc4.DAT6 usdhc4.DAT7 usdhc4.RST uart5.RI pwm1.PWMO pwm2.PWMO pwm3.PWMO pwm4.PWMO audmux.AUDIO_CLK_OUT lcdif.DAT[0] lcdif.DAT[1] lcdif.DAT[2] lcdif.DAT[3] lcdif.DAT[4] lcdif.DAT[5] lcdif.DAT[6] lcdif.DAT[7] lcdif.DAT[8] lcdif.DAT[9] lcdif.DAT[10] lcdif.DAT[11] lcdif.DAT[12] lcdif.DAT[13] lcdif.DAT[14] lcdif.DAT[15] lcdif.DAT[24] lcdif.DAT[25] lcdif.DAT[26] lcdif.DAT[27] lcdif.DAT[28] lcdif.DAT[29] lcdif.DAT[30] lcdif.DAT[31] epdc.PWRCTRL[0] epdc.PWRCTRL[1] epdc.PWRCTRL[2] epdc.PWRCTRL[3] epdc.PWRCOM epdc.PWRIRQ epdc.PWRSTAT epdc.PWRWAKE i2c2.SCL i2c2.SDA tcon.XDIOR epdc.SDCE[4] pwm3.PWMO pwm4.PWMO pwm1.PWMO pwm2.PWMO tcon.YCKR tcon.YOER tcon.YDIOUR tcon.YDIODR uart3.RXD_MUX uart3.TXD_MUX uart3.RTS uart3.CTS lcdif.DAT[16] lcdif.DAT[17] lcdif.DAT[18] lcdif.DAT[19] lcdif.DAT[20] lcdif.DAT[21] lcdif.DAT[22] lcdif.DAT[23] lcdif.WR_RWN lcdif.RD_E lcdif.CS lcdif.RS lcdif.BUSY anatop.USBOTG2_ID anatop.USBOTG1_ID epit2.EPITO uart5.DSR csi.VSYNC csi.HSYNC csi.PIXCLK csi.MCLK csi.D[9] csi.D[8] csi.D[7] csi.D[6] csi.D[5] csi.D[4] csi.D[3] csi.D[2] csi.D[1] csi.D[0] csi.D[15] csi.D[14] csi.D[13] csi.D[12] csi.D[11] csi.D[10] uart3.RXD_MUX uart3.TXD_MUX uart4.RXD_MUX uart4.TXD_MUX uart4.RTS uart4.CTS ecspi3.RDY uart4.RXD_MUX uart4.TXD_MUX ecspi3.SS2 ecspi3.SS3 spdif.IN1 spdif.OUT1 uart5.RXD_MUX uart5.TXD_MUX uart5.RTS uart5.CTS uart3.RXD_MUX uart3.TXD_MUX uart3.RTS uart3.CTS kpp.COL[0] kpp.ROW[0] kpp.COL[1] kpp.ROW[1] kpp.COL[2] kpp.ROW[2] kpp.COL[3] kpp.ROW[3] kpp.COL[4] kpp.ROW[4] wdog2.WDOG_B ecspi3.SCLK ecspi3.SS0 ecspi3.MOSI ecspi3.MISO fec.COL fec.RX_CLK uart2.RXD_MUX uart2.TXD_MUX uart2.RTS uart2.CTS kpp.COL[5] kpp.ROW[5] kpp.COL[6] kpp.ROW[6] kpp.COL[7] kpp.ROW[7] audmux.AUD6_RXFS audmux.AUD6_RXC audmux.AUD6_RXD audmux.AUD6_TXC audmux.AUD6_TXFS audmux.AUD6_TXD audmux.AUDIO_CLK_OUT anatop.USBOTG1_ID spdif.IN1 spdif.OUT1 wdog1.WDOG_B anatop.ANATOP_24M_OUT anatop.ANATOP_32K_OUT anatop.USBOTG2_ID anatop.USBOTG1_ID fec.REF_OUT weim.WEIM_DA_A[0] weim.WEIM_DA_A[1] weim.WEIM_DA_A[2] weim.WEIM_DA_A[3] weim.WEIM_DA_A[4] weim.WEIM_DA_A[5] weim.WEIM_DA_A[6] weim.WEIM_DA_A[7] weim.WEIM_DA_A[8] weim.WEIM_DA_A[9] weim.WEIM_DA_A[10] weim.WEIM_DA_A[11] weim.WEIM_DA_A[12] weim.WEIM_DA_A[13] weim.WEIM_DA_A[14] weim.WEIM_DA_A[15] csi.D[0] csi.D[1] csi.D[2] csi.D[3] csi.D[4] csi.D[5] csi.D[6] csi.D[7] weim.WEIM_A[16] weim.WEIM_A[17] weim.WEIM_A[18] weim.WEIM_A[19] weim.WEIM_A[20] weim.WEIM_A[21] weim.WEIM_A[22] weim.WEIM_A[23] csi.D[8] csi.D[9] csi.D[10] csi.D[11] weim.WEIM_CS[2] weim.WEIM_LBA weim.WEIM_EB[0] weim.WEIM_EB[1] csi.PIXCLK csi.HSYNC csi.MCLK csi.VSYNC weim.WEIM_A[24] weim.WEIM_A[25] weim.WEIM_A[26] weim.WEIM_CRE weim.WEIM_RW weim.WEIM_OE weim.WEIM_CS[0] weim.WEIM_CS[1] weim.WEIM_BCLK weim.ACLK_FREERUN weim.WEIM_WAIT weim.WEIM_DTACK_B weim.WEIM_RW weim.WEIM_OE weim.WEIM_CS[0] weim.WEIM_CS[1] weim.WEIM_WAIT pwm1.PWMO pwm2.PWMO pwm3.PWMO pwm4.PWMO wdog2.WDOG_RST_B_DEB weim.WEIM_CS[3] weim.WEIM_D[0] weim.WEIM_D[1] weim.WEIM_D[2] weim.WEIM_D[3] weim.WEIM_D[4] weim.WEIM_D[5] weim.WEIM_D[6] weim.WEIM_D[7] weim.WEIM_D[8] weim.WEIM_D[9] weim.WEIM_D[10] weim.WEIM_D[11] weim.WEIM_D[12] weim.WEIM_D[13] weim.WEIM_D[14] weim.WEIM_D[15] weim.WEIM_EB[3] weim.WEIM_EB[2] fec.MDIO fec.TX_CLK fec.RX_ER fec.RX_DV fec.RDATA[1] fec.TDATA[0] fec.MDC fec.COL fec.RX_CLK fec.RDATA[0] fec.TX_EN fec.TDATA[1] fec.REF_OUT epdc.VCOM[0] epdc.VCOM[1] epdc.BDR[0] epdc.BDR[1] csi.PIXCLK csi.HSYNC csi.MCLK csi.VSYNC epdc.SDCE[4] epdc.SDCE[5] epdc.SDCE[6] epdc.SDCE[7] epdc.SDCE[8] epdc.SDCE[9] epdc.SDCLKN epdc.SDOED epdc.SDOEZ ccm.PMIC_RDY spdif.OUT1 csi.D[0] csi.D[1] csi.D[2] csi.D[3] csi.D[4] csi.D[5] csi.D[6] csi.D[7] csi.D[8] csi.D[9] csi.D[10] csi.D[11] csi.D[12] csi.D[13] csi.D[14] csi.D[15] ecspi4.SS0 ecspi4.SCLK ecspi4.MOSI ecspi4.MISO ecspi4.SS1 ecspi4.SS2 usdhc1.RST usdhc1.VSELECT usdhc1.WP usdhc1.CD pwm4.PWMO 18 ccm.PMIC_RDY usdhc1.LCTL csi.MCLK usdhc1.CD usdhc1.WP usdhc3.DAT4 usdhc3.DAT5 usdhc3.DAT6 usdhc3.DAT7 usdhc4.DAT6 usdhc4.DAT7 usdhc4.CLK usdhc4.CMD usdhc4.DAT0 usdhc4.DAT1 usdhc4.DAT2 usdhc4.DAT3 usdhc4.DAT4 usdhc4.DAT5 tcon.E_DATA[0] tcon.E_DATA[1] tcon.E_DATA[2] tcon.E_DATA[3] tcon.E_DATA[4] tcon.E_DATA[5] tcon.E_DATA[6] tcon.E_DATA[7] tcon.E_DATA[8] tcon.E_DATA[9] tcon.E_DATA[10] tcon.E_DATA[11] tcon.E_DATA[12] tcon.E_DATA[13] tcon.E_DATA[14] tcon.E_DATA[15] tcon.CL tcon.LD tcon.XDIOL tcon.XDIOR tcon.YCKR tcon.YOER tcon.YDIOUR tcon.YDIODR tcon.YCKL tcon.YOEL tcon.YDIOUL tcon.YDIODL tcon.VCOM[0] tcon.VCOM[1] tcon.RL tcon.UD tcon.YCKL tcon.YOEL tcon.YDIOUL tcon.YDIODL anatop.USBOTG1_ID anatop.USBOTG2_ID kitten.EVENTI kitten.EVENTO pwm4.PWMO uart2.RXD_MUX uart2.TXD_MUX uart2.RTS uart2.CTS uart5.DTR audmux.AUD4_RXFS audmux.AUD4_RXC audmux.AUD4_RXD audmux.AUD4_TXC audmux.AUD4_TXFS audmux.AUD4_TXD audmux.AUDIO_CLK_OUT ecspi2.SCLK ecspi2.MOSI ecspi2.MISO ecspi2.SS1 uart5.RTS uart5.CTS uart5.RXD_MUX uart5.TXD_MUX i2c2.SCL i2c2.SDA gpt.CAPIN1 gpt.CAPIN2 gpt.CMPOUT1 gpt.CMPOUT2 gpt.CMPOUT3 gpt.CLKIN i2c3.SCL i2c3.SDA usdhc1.LCTL usdhc2.LCTL usdhc3.LCTL usdhc4.LCTL wdog2.WDOG_RST_B_DEB uart5.RXD_MUX uart5.TXD_MUX usdhc3.RST usdhc3.VSELECT usdhc3.WP usdhc3.CD usdhc2.RST usdhc2.VSELECT usdhc2.WP usdhc2.CD usdhc1.RST usdhc1.VSELECT usdhc1.WP usdhc1.CD mshc.SCLK mshc.BS mshc.DATA[0] mshc.DATA[1] mshc.DATA[2] mshc.DATA[3] uart4.RXD_MUX uart4.TXD_MUX uart4.RTS uart4.CTS csi.MCLK osc32k.32K_OUT epit1.EPITO uart5.RTS uart5.CTS uart5.RXD_MUX uart5.TXD_MUX spdif.OUT1 spdif.IN1 usdhc2.WP usdhc2.CD wdog1.WDOG_RST_B_DEB anatop.USBOTG2_ID anatop.USBOTG1_ID usdhc1.VSELECT epit1.EPITO epit2.EPITO gpt.CAPIN1 gpt.CAPIN2 gpt.CMPOUT1 gpt.CMPOUT2 gpt.CMPOUT3 gpt.CLKIN usdhc3.RST usdhc3.VSELECT usdhc3.WP usdhc3.CD ccm.PMIC_RDY osc32k.32K_OUT gpio3.GPIO[18] gpio3.GPIO[19] gpio3.GPIO[20] gpio3.GPIO[21] gpio3.GPIO[22] gpio3.GPIO[23] gpio3.GPIO[24] gpio3.GPIO[25] gpio3.GPIO[26] gpio3.GPIO[27] gpio3.GPIO[28] gpio3.GPIO[29] gpio3.GPIO[30] gpio3.GPIO[31] gpio4.GPIO[0] gpio4.GPIO[1] gpio4.GPIO[2] gpio4.GPIO[3] gpio4.GPIO[4] gpio4.GPIO[5] gpio4.GPIO[6] gpio4.GPIO[7] gpio1.GPIO[7] gpio1.GPIO[8] gpio1.GPIO[9] gpio1.GPIO[10] gpio1.GPIO[11] gpio1.GPIO[12] gpio1.GPIO[13] gpio1.GPIO[14] gpio1.GPIO[15] gpio1.GPIO[16] gpio1.GPIO[17] gpio1.GPIO[18] gpio1.GPIO[19] gpio1.GPIO[20] gpio1.GPIO[21] gpio1.GPIO[22] gpio1.GPIO[23] gpio1.GPIO[24] gpio1.GPIO[25] gpio1.GPIO[26] gpio1.GPIO[27] gpio1.GPIO[28] gpio1.GPIO[29] gpio1.GPIO[30] gpio1.GPIO[31] gpio2.GPIO[0] gpio2.GPIO[1] gpio2.GPIO[2] gpio2.GPIO[3] gpio2.GPIO[4] gpio2.GPIO[5] gpio2.GPIO[6] gpio2.GPIO[7] gpio2.GPIO[8] gpio2.GPIO[9] gpio2.GPIO[10] gpio2.GPIO[11] gpio2.GPIO[12] gpio2.GPIO[13] gpio2.GPIO[14] gpio2.GPIO[15] gpio2.GPIO[16] gpio2.GPIO[17] gpio2.GPIO[18] gpio2.GPIO[19] gpio2.GPIO[20] gpio2.GPIO[21] gpio2.GPIO[22] gpio2.GPIO[23] gpio2.GPIO[24] gpio2.GPIO[25] gpio2.GPIO[26] gpio2.GPIO[27] gpio2.GPIO[28] gpio2.GPIO[29] gpio2.GPIO[30] gpio2.GPIO[31] gpio3.GPIO[0] gpio3.GPIO[1] gpio3.GPIO[2] gpio3.GPIO[3] gpio3.GPIO[4] gpio3.GPIO[5] gpio3.GPIO[6] gpio3.GPIO[7] gpio3.GPIO[8] gpio3.GPIO[9] gpio3.GPIO[10] gpio3.GPIO[11] gpio1.GPIO[0] gpio1.GPIO[1] gpio1.GPIO[2] gpio1.GPIO[3] gpio1.GPIO[4] gpio1.GPIO[5] gpio1.GPIO[6] gpio3.GPIO[16] gpio3.GPIO[17] gpio3.GPIO[12] gpio3.GPIO[13] gpio3.GPIO[14] gpio3.GPIO[15] gpio4.GPIO[8] gpio4.GPIO[9] gpio4.GPIO[10] gpio4.GPIO[11] gpio4.GPIO[12] gpio4.GPIO[13] gpio4.GPIO[14] gpio4.GPIO[15] gpio5.GPIO[15] gpio5.GPIO[14] gpio5.GPIO[11] gpio5.GPIO[8] gpio5.GPIO[13] gpio5.GPIO[6] gpio5.GPIO[12] gpio5.GPIO[9] gpio5.GPIO[7] gpio5.GPIO[10] gpio4.GPIO[27] gpio5.GPIO[5] gpio5.GPIO[4] gpio5.GPIO[1] gpio4.GPIO[30] gpio5.GPIO[3] gpio4.GPIO[28] gpio5.GPIO[2] gpio4.GPIO[31] gpio4.GPIO[29] gpio5.GPIO[0] gpio5.GPIO[18] gpio5.GPIO[21] gpio5.GPIO[19] gpio5.GPIO[20] gpio5.GPIO[16] gpio5.GPIO[17] gpio4.GPIO[20] gpio4.GPIO[21] gpio4.GPIO[19] gpio4.GPIO[25] gpio4.GPIO[18] gpio4.GPIO[24] gpio4.GPIO[23] gpio4.GPIO[17] gpio4.GPIO[22] gpio4.GPIO[16] gpio4.GPIO[26] usdhc1.RST usdhc1.VSELECT usb.USBOTG1_PWR usb.USBOTG1_OC usb.USBOTG2_PWR usb.USBOTG2_OC usdhc3.RST usdhc3.VSELECT usdhc1.WP usdhc1.CD anatop.USBPHY1_TSTI_TX_HS_MODE anatop.USBPHY1_TSTI_TX_LS_MODE anatop.USBPHY1_TSTI_TX_DN anatop.USBPHY1_TSTI_TX_DP anatop.USBPHY1_TSTI_TX_EN anatop.USBPHY1_TSTI_TX_HIZ anatop.USBPHY2_TSTO_RX_DISCON_DET anatop.USBPHY2_TSTO_RX_FS_RXD usdhc4.RST usdhc4.VSELECT usdhc4.WP usdhc4.CD ecspi3.SS1 ecspi3.SS2 ecspi3.SS3 ecspi3.RDY anatop.USBPHY2_TSTO_RX_HS_RXD anatop.USBPHY2_TSTO_RX_SQUELCH anatop.USBPHY2_TSTO_PLL_CLK20DIV anatop.USBPHY1_TSTO_RX_DISCON_DET anatop.USBPHY1_TSTO_PLL_CLK20DIV anatop.USBPHY1_TSTO_RX_FS_RXD anatop.USBPHY1_TSTO_RX_HS_RXD anatop.USBPHY1_TSTO_RX_SQUELCH usdhc2.RST usdhc2.VSELECT usdhc2.WP usdhc2.CD epdc.SDCE[5] epdc.SDCE[6] epdc.SDCE[7] epdc.SDCE[8] usdhc4.RST usdhc4.VSELECT usdhc4.WP usdhc4.CD usdhc3.RST usdhc3.VSELECT usdhc3.WP usdhc3.CD src.EARLY_RST ocotp_ctrl_wrapper.FUSE_LATCHED kitten.TRCLK kitten.TRCTL ccm.PMIC_RDY kitten.TRACE[0] kitten.TRACE[1] kitten.TRACE[2] kitten.TRACE[3] kitten.TRACE[4] kitten.TRACE[5] kitten.TRACE[6] kitten.TRACE[7] kitten.TRACE[8] kitten.TRACE[9] kitten.TRACE[10] kitten.TRACE[11] kitten.TRACE[12] kitten.TRACE[13] kitten.TRACE[14] kitten.TRACE[15] kitten.TRACE[16] kitten.TRACE[17] kitten.TRACE[18] kitten.TRACE[19] kitten.TRACE[20] kitten.TRACE[21] kitten.TRACE[22] kitten.TRACE[23] ecspi3.SS0 ecspi3.SS1 src.INT_BOOT src.SYSTEM_RST anatop.ANATOP_TESTI[0] anatop.ANATOP_TESTI[1] spdif.SPDIF_EXT_CLK anatop.ANATOP_TESTI[2] anatop.ANATOP_TESTI[3] ecspi1.SS1 ecspi1.SS2 ecspi1.RDY anatop.ANATOP_TESTO[0] usb.USBOTG2_OC ccm.PLL2_BYP ccm.PLL3_BYP usb.USBOTG2_PWR usb.USBOTG2_OC anatop.ANATOP_TESTO[1] usb.USBOTG1_OC usb.USBOTG1_PWR anatop.ANATOP_TESTO[2] anatop.ANATOP_TESTO[3] anatop.ANATOP_TESTO[4] anatop.ANATOP_TESTO[5] anatop.ANATOP_TESTO[6] anatop.ANATOP_TESTO[7] anatop.ANATOP_TESTO[8] anatop.ANATOP_TESTO[9] anatop.ANATOP_TESTO[10] anatop.ANATOP_TESTO[11] anatop.ANATOP_TESTO[12] anatop.ANATOP_TESTO[13] anatop.ANATOP_TESTO[14] anatop.ANATOP_TESTO[15] mmdc.MMDC_DEBUG[39] mmdc.MMDC_DEBUG[38] mmdc.MMDC_DEBUG[37] mmdc.MMDC_DEBUG[36] mmdc.MMDC_DEBUG[35] mmdc.MMDC_DEBUG[34] mmdc.MMDC_DEBUG[33] usb.USBOTG1_PWR usb.USBOTG2_PWR sjc.JTAG_ACT sjc.DE_B usb.USBOTG2_OC usb.USBOTG1_OC kitten.TRACE[26] kitten.TRACE[27] kitten.TRACE[25] kitten.TRACE[31] fec.COL kitten.TRACE[30] kitten.TRACE[29] kitten.TRACE[24] kitten.TRACE[28] fec.RX_CLK spdif.SPDIF_EXT_CLK usdhc3.WP usdhc3.CD epit1.EPITO mmdc.MMDC_DEBUG[49] observe_mux.OUT[3] observe_mux.OUT[4] tpsmp.HDATA[0] tpsmp.HDATA[1] tpsmp.HDATA[2] tpsmp.HDATA[3] tpsmp.HDATA[4] tpsmp.HDATA[5] tpsmp.HDATA[6] tpsmp.HDATA[7] tpsmp.HDATA[8] tpsmp.HDATA[9] tpsmp.HDATA[10] tpsmp.HDATA[11] tpsmp.HDATA[12] tpsmp.HDATA[13] tpsmp.HDATA[14] tpsmp.HDATA[15] observe_mux.OUT[0] observe_mux.OUT[1] tpsmp.HDATA[28] tpsmp.HDATA[29] tpsmp.HDATA[30] tpsmp.HDATA[31] mmdc.MMDC_DEBUG[40] mmdc.MMDC_DEBUG[32] mmdc.MMDC_DEBUG[31] mmdc.MMDC_DEBUG[30] mmdc.MMDC_DEBUG[29] mmdc.MMDC_DEBUG[28] mmdc.MMDC_DEBUG[27] mmdc.MMDC_DEBUG[26] mmdc.MMDC_DEBUG[25] mmdc.MMDC_DEBUG[24] mmdc.MMDC_DEBUG[23] mmdc.MMDC_DEBUG[22] mmdc.MMDC_DEBUG[21] mmdc.MMDC_DEBUG[20] mmdc.MMDC_DEBUG[19] mmdc.MMDC_DEBUG[18] mmdc.MMDC_DEBUG[17] mmdc.MMDC_DEBUG[16] mmdc.MMDC_DEBUG[15] mmdc.MMDC_DEBUG[14] mmdc.MMDC_DEBUG[13] mmdc.MMDC_DEBUG[12] mmdc.MMDC_DEBUG[11] mmdc.MMDC_DEBUG[10] mmdc.MMDC_DEBUG[9] mmdc.MMDC_DEBUG[8] mmdc.MMDC_DEBUG[7] mmdc.MMDC_DEBUG[6] mmdc.MMDC_DEBUG[5] mmdc.MMDC_DEBUG[4] mmdc.MMDC_DEBUG[3] mmdc.MMDC_DEBUG[2] mmdc.MMDC_DEBUG[1] mmdc.MMDC_DEBUG[0] tpsmp.HTRANS[0] tpsmp.HTRANS[1] tpsmp.HDATA[16] tpsmp.HDATA[17] tpsmp.HDATA_DIR src.BT_CFG[0] src.BT_CFG[1] src.BT_CFG[2] src.BT_CFG[3] src.BT_CFG[4] src.BT_CFG[5] src.BT_CFG[6] src.BT_CFG[7] src.BT_CFG[8] src.BT_CFG[9] src.BT_CFG[10] src.BT_CFG[11] src.BT_CFG[12] src.BT_CFG[13] src.BT_CFG[14] src.BT_CFG[15] src.BT_CFG[24] src.BT_CFG[25] src.BT_CFG[26] src.BT_CFG[27] src.BT_CFG[28] src.BT_CFG[29] src.BT_CFG[30] src.BT_CFG[31] pl301_sim_mx6sl_per1.HPROT[1] pl301_sim_mx6sl_per1.HREADYOUT pl301_sim_mx6sl_per1.HRESP tpsmp.HDATA[24] tpsmp.HDATA[25] tpsmp.HDATA[26] tpsmp.HDATA[27] tpsmp.CLK uart5.DCD pl301_sim_mx6sl_per1.HSIZE[0] pl301_sim_mx6sl_per1.HSIZE[1] pl301_sim_mx6sl_per1.HSIZE[2] pl301_sim_mx6sl_per1.HWRITE tpsmp.HDATA[18] tpsmp.HDATA[19] tpsmp.HDATA[20] pl301_sim_mx6sl_per1.HADDR[23] tpsmp.HDATA[21] tpsmp.HDATA[22] tpsmp.HDATA[23] pl301_sim_mx6sl_per1.HADDR[24] pl301_sim_mx6sl_per1.HADDR[25] pl301_sim_mx6sl_per1.HADDR[26] pl301_sim_mx6sl_per1.HADDR[27] pl301_sim_mx6sl_per1.HADDR[28] pl301_sim_mx6sl_per1.HADDR[29] pl301_sim_mx6sl_per1.HADDR[30] pl301_sim_mx6sl_per1.HADDR[31] pl301_sim_mx6sl_per1.HPROT[3] pl301_sim_mx6sl_per1.HPROT[2] pl301_sim_mx6sl_per1.HMASTLOCK pl301_sim_mx6sl_per1.HBURST[2] pl301_sim_mx6sl_per1.HPROT[1] pl301_sim_mx6sl_per1.HADDR[21] pl301_sim_mx6sl_per1.HPROT[0] pl301_sim_mx6sl_per1.HBURST[1] pl301_sim_mx6sl_per1.HADDR[22] pl301_sim_mx6sl_per1.HBURST[0] pl301_sim_mx6sl_per1.HADDR[10] pl301_sim_mx6sl_per1.HADDR[20] pl301_sim_mx6sl_per1.HADDR[19] pl301_sim_mx6sl_per1.HADDR[16] pl301_sim_mx6sl_per1.HADDR[13] pl301_sim_mx6sl_per1.HADDR[18] pl301_sim_mx6sl_per1.HADDR[11] pl301_sim_mx6sl_per1.HADDR[17] pl301_sim_mx6sl_per1.HADDR[14] pl301_sim_mx6sl_per1.HADDR[12] pl301_sim_mx6sl_per1.HADDR[15] pl301_sim_mx6sl_per1.HADDR[4] pl301_sim_mx6sl_per1.HADDR[5] pl301_sim_mx6sl_per1.HADDR[3] pl301_sim_mx6sl_per1.HADDR[9] pl301_sim_mx6sl_per1.HADDR[2] pl301_sim_mx6sl_per1.HADDR[8] pl301_sim_mx6sl_per1.HADDR[7] pl301_sim_mx6sl_per1.HADDR[1] pl301_sim_mx6sl_per1.HADDR[6] pl301_sim_mx6sl_per1.HADDR[0] observe_mux.OUT[2] Schematic AN5113 Application Note Rev. 1.0 4/2015 Freescale Semiconductor Revision History 5 Revision History Revision Date 1.0 4/2015 Description of Changes Initial release AN5113 Application Note Rev. 1.0 4/2015 Freescale Semiconductor 19 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. Home Page: freescale.com There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based Web Support: freescale.com/support Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no on the information in this document. warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2015 Freescale Semiconductor, Inc. Document Number: AN5113 Rev. 1.0 4/2015