NVD5862N Power MOSFET 60 V, 5.7 mW, 98 A, Single N−Channel Features • • • • • Low RDS(on) to Minimize Conduction Losses High Current Capability Avalanche Energy Specified AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com V(BR)DSS RDS(on) ID 60 V 5.7 mW @ 10 V 98 A MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current RqJC (Note 1) Power Dissipation RqJC (Note 1) Continuous Drain Current RqJA (Notes 1 & 2) Power Dissipation RqJA (Notes 1 & 2) Pulsed Drain Current TC = 25°C Steady State Symbol Value Unit VDSS 60 V VGS "20 V ID 98 A TC = 100°C TC = 25°C Steady State PD ID 13 4.1 TA = 25°C, tp = 10 ms IDM 367 A TA = 25°C IDmaxpkg 60 A TJ, Tstg −55 to 175 °C IS 96 A EAS 205 mJ TL 260 °C TA = 100°C Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, IL(pk) = 37 A, L = 0.3 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) W 2.0 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter 4 A 18 PD Current Limited by Package (Note 3) S W 115 58 TA = 100°C TA = 25°C N−Channel G 69 TC = 100°C TA = 25°C D Symbol Value Unit Junction−to−Case − Steady State (Drain) RqJC 1.3 °C/W Junction−to−Ambient − Steady State (Note 2) RqJA 37 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Continuous DC current rating. Maximum current for pulses as long as 1 second are higher but are dependent on pulse duration and duty cycle. 1 2 3 DPAK CASE 369C (Surface Mount) STYLE 2 MARKING DIAGRAMS & PIN ASSIGNMENT 4 Drain YWW V58 62NG Parameter 2 1 Drain 3 Gate Source Y = Year WW = Work Week V5862N = Device Code G = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2015 June, 2015 − Rev. 2 1 Publication Order Number: NVD5862N/D NVD5862N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 60 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Parameter Typ Max Unit OFF CHARACTERISTICS V 47 Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA VGS = 0 V, VDS = 60 V mV/°C TJ = 25°C 1.0 TJ = 125°C mA 100 ±100 nA 4.0 V ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance Forward Transconductance 2.0 −9.7 RDS(on) VGS = 10 V, ID = 48 A 4.4 gFS VDS = 15 V, ID = 10 A 18 mV/°C 5.7 mW S CHARGES, CAPACITANCES AND GATE RESISTANCES Input Capacitance Ciss VGS = 0 V, f = 1.0 MHz, VDS = 25 V 5050 6000 500 600 420 pF Output Capacitance Coss Reverse Transfer Capacitance Crss 300 Total Gate Charge QG(TOT) 82 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 27 RG 0.6 W td(on) 18 ns Gate Resistance VGS = 10 V, VDS = 48 V, ID = 48 A nC 5.2 24 SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time tr Turn−Off Delay Time Fall Time td(off) VGS = 10 V, VDD = 48 V, ID = 48 A, RG = 2.5 W tf 70 35 60 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD TJ = 25°C 0.9 TJ = 100°C 0.75 tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 48 A 1.2 38 VGS = 0 V, dIs/dt = 100 A/ms, IS = 48 A QRR V ns 20 18 40 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperatures. ORDERING INFORMATION Order Number NVD5862NT4G Package Shipping† DPAK (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 2 NVD5862N TYPICAL CHARACTERISTICS 200 200 160 6.0 V 120 5.8 V 5.6 V 80 40 VDS ≥ 5 V 180 6.2 V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) TJ = 25°C VGS = 10 V 5.2 V 160 140 120 100 80 TJ = 25°C 60 40 20 0 1 2 3 4 5 4 5 6 7 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics ID = 45 A TJ = 25°C 0.025 0.020 0.015 0.010 0.005 0.000 4 5 6 7 8 9 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) VGS, GATE−TO−SOURCE VOLTAGE (V) 0.030 10 0.006 VGS = 10 V TJ = 25°C 0.005 0.004 0.003 10 20 30 40 50 60 70 80 90 VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate Voltage Figure 4. On−Resistance vs. Drain Current 100 100000 2.2 2.0 TJ = −55°C VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS = 0 V ID = 45 A VGS = 10 V 1.8 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 TJ = 125°C 0 3 1.6 TJ = 150°C 10000 1.4 1.2 1.0 TJ = 125°C 0.8 0.6 −50 1000 −25 0 25 50 75 100 125 150 175 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 60 NVD5862N TYPICAL CHARACTERISTICS 10 6000 C, CAPACITANCE (pF) 5000 VGS, GATE−TO−SOURCE VOLTAGE (V) VGS = 0 V TJ = 25°C Ciss 4000 3000 2000 Coss 1000 0 0 Crss 10 20 30 40 50 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 60 QT 9 8 7 6 Qgs 4 3 VDS = 48 V ID = 48 A TJ = 25°C 2 1 0 0 10 Figure 7. Capacitance Variation IS, SOURCE CURRENT (A) 100 t, TIME (ns) 80 90 100 VDD = 48 V ID = 48 A VGS = 10 V tr td(on) tf td(off) 10 1 10 VGS = 0 V TJ = 25°C 80 60 40 20 0 0.50 1 100 0.60 0.70 0.80 0.90 1.00 1.10 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 1000 225 1 ms 10 ms dc 100 100 ms 10 ms 10 VGS = 10 V SINGLE PULSE TC = 25°C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 1 ID = 37 A 200 AVALANCHE ENERGY (mJ) ID, DRAIN CURRENT (A) 20 30 40 50 60 70 Qg, TOTAL GATE CHARGE (nC) Figure 8. Gate−to−Source vs. Total Charge 1000 1 Qgd 5 175 150 125 100 75 50 25 10 100 0 25 50 75 100 125 150 175 VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature www.onsemi.com 4 NVD5862N TYPICAL CHARACTERISTICS RqJC(t) (°C/W) EFFECTIVE TRANSIENT THERMAL RESISTANCE 10 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 0.001 0.000001 0.00001 0.0001 0.001 0.01 t, PULSE TIME (s) Figure 13. Thermal Response www.onsemi.com 5 0.1 1 10 NVD5862N PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE E A E C A b3 B c2 4 L3 D 1 2 Z Z H DETAIL A 3 L4 NOTE 7 b2 e b TOP VIEW c SIDE VIEW 0.005 (0.13) M NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z BOTTOM VIEW BOTTOM VIEW ALTERNATE CONSTRUCTION C H L2 GAUGE PLANE C L L1 DETAIL A SEATING PLANE A1 ROTATED 905 CW SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− 6.17 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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