NVTFS4823N D

NVTFS4823N
Power MOSFET
30 V, 10.5 mW, 30 A, Single N−Channel
Features
•
•
•
•
•
•
Small Footprint (3.3x3.3 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
NVTFS4823NWF − Wettable Flanks Product
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
"20
V
ID
30
A
Continuous Drain Current RYJ−mb (Notes 1,
2, 3, 4)
Power Dissipation
RYJ−mb (Notes 1, 2, 3)
Continuous Drain Current RqJA (Notes 1, 3,
& 4)
Power Dissipation
RqJA (Notes 1, 3)
Pulsed Drain Current
Tmb = 25°C
Steady
State
Tmb = 100°C
Tmb = 25°C
21
PD
21
ID
13
Tmb = 100°C
TA = 25°C
Steady
State
17.5 mW @ 4.5 V
TA = 25°C
TA = 25°C, tp = 10 ms
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 24 V, VGS = 10 V,
IL(pk) = 24 A, L = 0.1 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
G (4)
W
S (1, 2, 3)
A
MARKING DIAGRAM
W
3.1
TA = 100°C
Operating Junction and Storage Temperature
1.6
IDM
198
A
TJ, Tstg
−55 to
175
°C
IS
19
A
EAS
28.8
mJ
TL
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
Junction−to−Mounting Board (top) − Steady
State (Note 2, 3)
Junction−to−Ambient − Steady State (Note 3)
N−Channel
9.0
PD
30 A
D (5 − 8)
11
TA = 100°C
ID MAX
10.5 mW @ 10 V
30 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
RDS(on) MAX
Symbol
Value
Unit
RYJ−mb
7.0
°C/W
RqJA
47
1
WDFN8
(m8FL)
CASE 511AB
XXXX
A
Y
WW
G
1
S
S
S
G
XXXX
AYWWG
G
D
D
D
D
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
4. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 2
1
Publication Order Number:
NVTFS4823N/D
NVTFS4823N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Condition
Min
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
VGS = 0 V,
VDS = 30 V
V
TJ = 25°C
1.0
TJ = 125°C
10
mA
IGSS
VDS = 0 V, VGS = "20 V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250 mA
2.5
V
Drain−to−Source On Resistance
RDS(on)
VGS = 10 V, ID = 15 A
8.1
10.5
mW
VGS = 4.5 V, ID = 15 A
13.5
17.5
VDS = 1.5 V, ID = 20 A
34
S
750
pF
"100
nA
ON CHARACTERISTICS (Note 5)
Forward Transconductance
gFS
1.5
CHARGES AND CAPACITANCES
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
VGS = 0 V, f = 1.0 MHz, VDS = 12 V
175
Crss
100
Total Gate Charge
QG(TOT)
6.0
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
VGS = 4.5 V, VDS = 15 V, ID = 15 A
nC
0.8
2.4
2.4
VGS = 10 V, VDS = 15 V, ID = 15 A
12
nC
12
ns
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(on)
tr
td(off)
VGS = 4.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
22
14
4
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.85
TJ = 125°C
0.72
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 15 A
12
VGS = 0 V,
dIS/dt = 100 A/ms,
IS = 15 A
QRR
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2
V
ns
6.0
6.0
5.0
5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
1.1
nC
NVTFS4823N
TYPICAL CHARACTERISTICS
10 V
5.5 V
ID, DRAIN CURRENT (A)
50
60
TJ = 25°C
VDS ≥ 10 V
4.1 V
VGS = 4.5 V
ID, DRAIN CURRENT (A)
60
3.8 V
40
30
3.5 V
20
3.2 V
10
50
40
30
20
TJ = 125°C
10
TJ = 25°C
2.9 V
0.020
0.019
0.018
0.017
0.016
0.015
0.014
0.013
0.012
0.011
0.010
0.009
0.008
0.007
0.006
0
1
2
3
4
5
1
4
5
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 2. Transfer Characteristics
4
5
6
7
8
9
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
0.025
TJ = 25°C
0.020
VGS = 4.5 V
0.015
0.010
VGS = 10 V
0.005
0
5
10
15
20
25
30
35
40
45
50
55
60
ID, DRAIN CURRENT (A)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.8
10000
VGS = 0 V
ID = 15 A
VGS = 10 V
1.6
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
3
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.4
1.2
1.0
0.8
0.6
TJ = −55°C
2
Figure 1. On−Region Characteristics
ID = 15 A
TJ = 25°C
3
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
50
25
0
25
50
75
100
125
150
175
TJ = 150°C
1000
TJ = 125°C
100
10
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
30
NVTFS4823N
TYPICAL CHARACTERISTICS
10
VGS, GATE−TO−SOURCE VOLTAGE
(V)
1200
VGS = 0 V
C, CAPACITANCE (pF)
1000
TJ = 25°C
Ciss
800
600
400
Coss
200
0
Crss
0
5
10
15
20
25
DRAIN−TO−SOURCE VOLTAGE (V)
30
QT
8
6
4
Qgs
VDS = 15 V
ID = 15 A
TJ = 25°C
2
0
0
2
Figure 7. Capacitance Variation
IS, SOURCE CURRENT (A)
100
t, TIME (ns)
10
12
40
VDD = 15 V
ID = 10 A
VGS = 10 V
tr
td(off)
10
td(on)
tf
1.0
1
10
VGS = 0 V
TJ = 25°C
30
20
10
0
100
0.5
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
EAS, SINGLE PULSE DRAIN−TO−
SOURCE AVALANCHE ENERGY (mJ)
VGS = 10 V
Single Pulse
TC = 25°C
10 ms
10
100 ms
10 ms
1 ms
RDS(on) Limit
Thermal Limit
Package Limit
0.1
0.1
dc
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.7
0.8
0.9
1.0
Figure 10. Diode Forward Voltage vs. Current
1000
100
0.6
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
RG, GATE RESISTANCE (W)
ID, DRAIN CURRENT (A)
4
6
8
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source Voltage vs. Total
Charge
1000
1
Qgd
100
30
ID = 24 A
25
20
15
10
5
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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4
200
NVTFS4823N
TYPICAL CHARACTERISTICS
RqJA(t) (°C/W) EFFECTIVE TRANSIENT
THERMAL RESISTANCE
100
Duty Cycle = 0.5
10
0.1
0.2
0.1
0.05
0.02
0.01
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Marking
Package
Shipping†
NVTFS4823NTAG
4823
WDFN8
(Pb−Free)
1500 / Tape & Reel
NVTFS4823NWFTAG
23WF
WDFN8
(Pb−Free)
1500 / Tape & Reel
NVTFS4823NTWG
4823
WDFN8
(Pb−Free)
5000 / Tape & Reel
NVTFS4823NWFTWG
23WF
WDFN8
(Pb−Free)
5000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NVTFS4823N
PACKAGE DIMENSIONS
WDFN8 3.3x3.3, 0.65P
CASE 511AB
ISSUE D
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH
PROTRUSIONS OR GATE BURRS.
0.20 C
D
A
D1
B
2X
0.20 C
8 7 6 5
4X
E1 E
q
c
1 2 3 4
A1
TOP VIEW
0.10 C
A
e
SIDE VIEW
0.10
8X b
C A B
0.05
C
4X
L
C
6X
0.10 C
DETAIL A
SEATING
PLANE
DETAIL A
8X
e/2
1
0.42
4
INCHES
NOM
0.030
−−−
0.012
0.008
0.130 BSC
0.116
0.120
0.078
0.083
0.130 BSC
0.116
0.120
0.058
0.063
0.009
0.012
0.026 BSC
0.012
0.016
0.026
0.032
0.012
0.017
0.002
0.005
0.055
0.059
0_
−−−
MIN
0.028
0.000
0.009
0.006
MAX
0.031
0.002
0.016
0.010
0.124
0.088
0.124
0.068
0.016
0.020
0.037
0.022
0.008
0.063
12 _
0.65
PITCH
PACKAGE
OUTLINE
4X
0.66
M
E3
8
G
MILLIMETERS
MIN
NOM
MAX
0.70
0.75
0.80
0.00
−−−
0.05
0.23
0.30
0.40
0.15
0.20
0.25
3.30 BSC
2.95
3.05
3.15
1.98
2.11
2.24
3.30 BSC
2.95
3.05
3.15
1.47
1.60
1.73
0.23
0.30
0.40
0.65 BSC
0.30
0.41
0.51
0.65
0.80
0.95
0.30
0.43
0.56
0.06
0.13
0.20
1.40
1.50
1.60
0_
−−−
12 _
SOLDERING FOOTPRINT*
K
E2
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
E3
e
G
K
L
L1
M
q
5
D2
BOTTOM VIEW
3.60
L1
0.75
2.30
0.57
0.47
2.37
3.46
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NVTFS4823N/D