NB7V32M D

NB7V32M
1.8V / 2.5V, 10GHz ÷2 Clock
Divider with CML Outputs
Multi−Level Inputs w/ Internal
Termination
http://onsemi.com
Description
The NB7V32M is a differential B2 Clock divider with
asynchronous reset. The differential Clock inputs incorporate internal
50 W termination resistors and will accept LVPECL, CML and LVDS
logic levels.
The NB7V32M produces a B2 output copy of an input Clock
operating up to 10 GHz with minimal jitter.
The RESET Pin is asserted on the rising edge. Upon power−up, the
internal flip−flops will attain a random state; the Reset allows for the
synchronization of multiple NB7V32M’s in a system.
The 16 mA differential CML output provides matching internal
50 W termination which guarantees 400 mV output swing when
externally receiver terminated with 50 W to VCC .
The NB7V32M is the 1.8 V/2.5 V version of the NB7L32M
(2.5 V/3.3 V) and is offered in a low profile 3 mm x 3 mm 16−pin
QFN package. The NB7V32M is a member of the GigaComm™
family of high performance clock products. Application notes,
models, and support documentation are available at
www.onsemi.com.
MARKING
DIAGRAM*
1
16
NB7V
32M
ALYWG
G
1
QFN−16
MN SUFFIX
CASE 485G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Features
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 10 GHz, typical
Random Clock Jitter < 0.8 ps RMS
200 ps Typical Propagation Delay
35 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV Peak−to−Peak, Typical
Operating Range: VCC = 1.71 V to 2.625 V with GND = 0 V
Internal 50 W Input Termination Resistors
QFN−16 Package, 3 mm x 3 mm
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices
R
RESET
VTCLK
50W
CLK
B2
CLK
Q
Q
50W
VTCLK
VREFAC
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
August, 2010 − Rev. 5
1
Publication Order Number:
NB7V32M/D
NB7V32M
VCC
16
R
15
VCC VCC
14
Exposed Pad (EP)
VTCLK 1
12
VCC
11
Q
3
10
Q
VTCLK 4
9
VCC
CLK
Table 1. TRUTH TABLE
13
2
5
6
7
CLK
R
Q
Q
x
x
H
L
H
Z
W
L
CLK B 2
CLK B 2
Z = LOW to HIGH Transition
W = HIGH to LOW Transition
x = Don’t Care
NB7V32M
CLK
CLK
8
VREFAC GND GND GND
Figure 2. Pin Configuration (Top View)
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTCLK
−
2
CLK
LVPECL, CML,
LVDS Input
Non−inverted Differential CLK Input. (Note 1)
3
CLK
LVPECL, CML,
LVDS Input
Inverted Differential CLK Input. (Note 1)
4
VTCLK
−
Internal 50 W Termination Pin for CLK
5
VREFAC
−
Internally Generated Output Voltage Reference for Capacitor−Coupled Inputs, only
6
GND
−
Negative Supply Voltage
7
GND
−
Negative Supply Voltage
8
GND
−
Negative Supply Voltage
9
VCC
−
Positive Supply Voltage. (Note 2)
10
Q
CML Output
Inverted Differential Output
11
Q
CML Output
Non−Inverted Differential Output
12
VCC
−
Positive Supply Voltage. (Note 2)
13
VCC
−
Positive Supply Voltage. (Note 2)
14
VCC
−
Positive Supply Voltage. (Note 2)
15
R
LVCMOS Input
16
VCC
−
Positive Supply Voltage. (Note 2)
−
EP
−
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected
to GND on the PC board.
Internal 50 W Termination Pin for CLK
Asynchronous Reset Input. Internal 75 kW pulldown to GND.
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage or left open,
and if no signal is applied on CLK/CLK input, then the device will be susceptible to self−oscillation. Q/Q outputs have internal 50 W source
termination resistors.
2. VCC and GND pins must be externally connected to a power supply for proper operation.
http://onsemi.com
2
NB7V32M
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Value
Human Body Model
Machine Model
Moisture Sensitivity
16−QFN
Flammability Rating
Oxygen Index: 28 to 34
> 4 kV
> 200 V
Level 1
UL 94 V−0 @ 0.125 in
Transistor Count
164
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
Positive Power Supply
GND = 0 V
3.0
V
VIN
Positive Input Voltage
GND = 0 V
−0.5 to VCC + 0.5 V
V
Differential Input Voltage |D − D|
1.89
V
Input Current Through RT (50 W Resistor)
$40
mA
Output Current Through RT (50 W Resistor)
$40
mA
VINPP
IIN
IOUT
IVREFAC
Parameter
Condition 1
Condition 2
VREFAC Sink/Source Current
$1.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
(Note 3)
QFN−16
QFN−16
42
35
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
(Note 3)
QFN−16
4
°C/W
Tsol
Wave Solder Pb−Free
265
°C
0 lfpm
500 lfpm
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
http://onsemi.com
3
NB7V32M
Table 5. DC CHARACTERISTICS POSITIVE CML OUTPUT VCC = 1.71 V to 2.625 V; GND = 0 V; TA = −40°C to 85°C (Note 4)
Min
Characteristic
Symbol
Typ
Max
90
80
100
90
Unit
POWER SUPPLY CURRENT
ICC
Power Supply Current (Inputs and Outputs Open)
VCC = 2.5 V $ 5%
VCC = 1.8 V $ 5%
mA
CML OUTPUTS
VOH
Output HIGH Voltage (Note 5)
VOL
Output LOW Voltage (Note 5)
VCC = 2.5 V
VCC = 1.8 V
VCC – 30
2470
1770
VCC – 1
2490
1790
VCC
2500
1800
VCC = 2.5 V
VCC = 2.5 V
VCC – 600
1900
VCC – 500
2000
VCC – 400
2100
VCC = 1.8 V
VCC = 1.8 V
VCC – 550
1250
VCC – 450
1350
VCC – 350
1450
mV
mV
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Note 6) (Figures 5 and 7)
Vth
Input Threshold Reference Voltage Range (Note 7)
1050
VCC − 100
mV
VIH
Single−Ended Input HIGH Voltage
Vth + 100
VCC
mV
VIL
Single−Ended Input LOW Voltage
GND
Vth − 100
mV
VISE
Single−Ended Input Voltage (VIH − VIL)
200
1200
mV
VCC – 850
VCC – 750
VCC – 500
VCC – 450
VREFAC
VREFAC
Output Reference Voltage @ 100 mA for capacitor− coupled inputs, only
VCC = 2.5 V
(Note 8) VCC = 1.8 V
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 9) (Note 9)
VIHD
Differential Input HIGH Voltage
1100
VCC
mV
VILD
Differential Input LOW Voltage
GND
VCC − 100
mV
VID
Differential Input Voltage (VIHD − VILD)
100
1200
mV
VCMR
Input Common Mode Range (Differential Configuration, Note 10) (Figure 9)
1050
VCC − 50
mV
IIH
Input HIGH Current (VTCLK/VTCLK Open)
−150
150
uA
IIL
Input LOW Current (VTCLK/VTCLK Open)
−150
150
uA
CONTROL INPUT (Reset Pin)
VIH
Input HIGH Voltage for Control Pin
VCC − 200
VCC
mV
VIL
Input LOW Voltage for Control Pin
GND
200
mV
IIH
Input HIGH Current
−150
150
uA
IIL
Input LOW Current
−150
150
uA
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor (@ 10 mA)
45
50
55
W
RTOUT
Internal Output Termination Resistor (@ 10 mA)
45
50
55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC.
5. CML outputs loaded with 50 W to VCC for proper operation.
6. Vth, VIH, VIL and VISE parameters must be complied with simultaneously.
7. Vth is applied to the complementary input when operating in single−ended mode.
8. VREFAC will not be less than GND + 1050 mV.
9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
http://onsemi.com
4
NB7V32M
10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential
input signal.
Table 6. AC CHARACTERISTICS VCC = 1.71 V to 2.625 V; GND = 0 V; TA = −40°C to 85°C (Note 11)
Symbol
Characteristic
Min
Typ
fMAX
Maximum Input Clock Frequency
VOUTPP
Output Voltage Amplitude (@ VINPPmin)
(Note 12) (Figure 3)
tPLH,
tPHL
Propagation Delay to Differential Outputs, @
1 GHz, measured at differential cross−point
tPLH TC
Propagation Delay Temperature Coefficient
tskew
Duty Cycle Skew (Note 13)
Device − Device skew (tpdmax – tpdmin)
tRR
Reset Recovery (See Figure 11)
300
135
tPW
Minimum Pulse Width R
500
200
tDC
Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 10 GHz
45
tJITTER
RJ – Output Random Jitter (Note 14) fin v 10 GHz
VINPP
Input Voltage Swing (Differential Configuration) (Figure 10) (Note 15)
tr, tf
Output Rise/Fall Times @ 1 GHz (20% − 80%), Q, Q
Max
10
Unit
GHz
fin ≤ 10GHz
280
400
CLK/CLK to Q, Q
R to Q, Q
150
200
200
mV
275
50
ps
Dfs/°C
20
50
ps
50
55
%
0.2
0.8
ps
RMS
1200
mV
60
ps
100
35
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 1 GHz, VINPPmin, 50% duty−cycle clock source. All output loading with external 50 W to VCC. Input edge rates 40 ps
(20% − 80%).
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Duty cycle skew is defined only for differential operation when the delays are measured from cross−point of the inputs to the cross−point
of the outputs. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz. Skew
is measured between outputs under identical transitions and conditions.
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Input voltage swing is a single−ended measurement operating in differential mode.
OUTPUT VOLTAGE AMPLITUDE
(mV)
500
VCC
450
VTCLK
Q AMP (mV)
400
50 W
RC
RC
CLK
350
I
300
CLK
250
50 W
200
0
2
4
6
8
10
VTCLK
fin, Clock Input Frequency (GHz)
Figure 3. CLOCK Output Voltage Amplitude
(VOUTPP) vs. Input Frequency (fin) at Ambient
Temperature (Typ)
Figure 4. Input Structure
http://onsemi.com
5
NB7V32M
CLK
VIH
Vth
CLK
VIL
CLK
CLK
Vth
Figure 5. Differential Input Driven
Single−Ended
VCC
Vthmax
Figure 6. Differential Inputs
Driven Differentially
VIHmax
VILmax
VIH
Vth
VIL
Vth
VILD
VILmin
GND
Figure 7. Vth Diagram
VCC
Figure 8. Differential Inputs Driven Differentially
VIHDmax
VCMmax
CLK
VILDmax
CLK
VCMR
CLK
GND
VIHD
CLK
VIHmin
Vthmin
VCMmin
VID = |VIHD(CLK) − VILD(CLK)|
CLK
VINPP = VIH(CLK) − VIL(CLK)
CLK
VIHDtyp
VID = VIHD − VILD
Q
VILDtyp
VOUTPP = VOH(Q) − VOL(Q)
Q
VIHDmin
tPHL
VILDmin
tPLH
Figure 9. VCMR Diagram
Figure 10. AC Reference Measurement
50%
50%
VOUTPP = VOH(Q) − VOL(Q)
Q
tPLH
tPHL
50%
50%
CLK
R
tRR(MIN)
50%
Figure 11. AC Reference Measurement (Timing Diagram)
http://onsemi.com
6
VINPP = VIH(CLK) − VIL(CLK)
NB7V32M
VCC
VCC
VCC
ZO = 50 W
LVPECL
Driver
Vth
ZO = 50 W
VCC
ZO = 50 W CLK
NB7V32M
CLK
50 W
VTCLK
VTCLK
VTCLK
LVDS
Driver
VTCLK
ZO = 50 W
50 W
CLK
50 W
50 W
CLK
Vth = VCC − 2 V
VEE
NB7V32M
GND
VEE
GND
Figure 12. LVPECL Interface
Figure 13. LVDS Interface
VCC
VCC
ZO = 50 W
CML
Driver
VCC
CLK
NB7V32M
50 W
VTCLK
VTCLK
ZO = 50 W
VT = VT = VCC
50 W
CLK
GND
GND
Figure 14. Standard 50 W Load CML Interface
VCC
ZO = 50 W CLK
Differential
Driver
VCC
VCC
Vth
VTCLK
VTCLK
ZO = 50 W
VCC
ZO = 50 W
NB7V32M
50 W
Single−Ended
Driver
50 W
Vth
VTCLK
VTCLK
CLK
NB7V32M
50 W
50 W
CLK
Vth = VREFAC
GND
CLK
Vth = VREFAC
GND
GND
GND
Figure 16. Capacitor−Coupled Single−Ended Interface
(VTCLK/VTCLK Connected to VREFAC; VREFAC Bypassed
to Ground with 0.1 mF Capacitor)
Figure 15. Capacitor−Coupled Differential Interface
(VTCLK/VTCLK Connected to VREFAC; VREFAC Bypassed
to Ground with 0.1 mF Capacitor)
http://onsemi.com
7
NB7V32M
NB7V32M
Receiver
VCC
VCC (Receiver)
50 W
50 W
Q 50 W
50 W
Q
16 mA
GND
Figure 17. Typical CML Output Structure and Termination
VCC
50 W
Z = 50 W
DUT
Driver
Device
50 W
Q
D
Receiver
Device
Z = 50 W
Q
D
Figure 18. Typical Termination for CML Output Driver and Device Evaluation
ORDERING INFORMATION
Package
Shipping†
NB7V32MMNG
QFN−16
(Pb−free)
123 Units / Rail
NB7V32MMNTXG
QFN−16
(Pb−free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
8
NB7V32M
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G−01
ISSUE E
D
ÇÇÇ
ÇÇÇ
ÇÇÇ
PIN 1
LOCATION
2X
A
B
L
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
ÉÉ
ÉÉ
ÉÉ
EXPOSED Cu
0.10 C
TOP VIEW
DETAIL B
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
0.10 C
2X
L
(A3)
ÇÇ
ÉÉ
A1
DETAIL B
A
0.05 C
A3
MOLD CMPD
ALTERNATE
CONSTRUCTIONS
NOTE 4
A1
SIDE VIEW
C
SEATING
PLANE
L
DETAIL A
D2
16X
9
16X
0.58
PACKAGE
OUTLINE
8
4
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.18 TYP
0.30
0.50
0.00
0.15
RECOMMENDED
SOLDERING FOOTPRINT*
0.10 C A B
16X
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
1
E2
K
2X
2X
1.84 3.30
1
16
e
e/2
BOTTOM VIEW
16X
16X
0.30
b
0.10 C A B
0.05 C
0.50
PITCH
NOTE 3
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
The products described herein (NB7V32M), may be covered by U.S. patents including 6,362,644. There may be other patents pending.
GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
9
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
NB7V32M/D