ESDR7534 Low Capacitance TVS for LVDS Interfaces The ESDR7534 transient voltage suppressor is designed to protect high speed data lines from ESD, EFT, and lightning. www.onsemi.com Features • Low Capacitance (2 pF Maximum Between I/O Lines and GND) • Protection for the Following IEC Standards: • IEC 61000−4−2 (ESD) Level 4 − ±30 kV (Contact); ±30 kV (Air) This is a Pb−Free Device PIN CONFIGURATION AND SCHEMATIC CH4 VP CH3 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Peak Power Dissipation (Note 1) Ppk 300 W Maximum Peak Pulse Current 2 x 10 mS @ TA = 25°C IPP 10 A Operating Junction Temperature Range TJ −55 to +125 °C Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Seconds) TL 260 °C IEC 61000−4−2 Contact (ESD) ESD 30 kV IEC 61000−4−2 Air (ESD) ESD 30 kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Ppk calculated. Ppk = VC x IPP. CH1 VN CH2 (Top View) MARKING DIAGRAM 7RMG G SC−88 S7 SUFFIX CASE 419B 1 7R = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) Table 1. PIN DESCRIPTIONS ORDERING INFORMATION 4−Channel, 6−Lead SC70−6 Pin Name Type Description 1 CH1 I/O 2 VN GND 3 CH2 I/O ESD Channel 4 CH3 I/O ESD Channel 5 VP PWR 6 CH4 I/O ESD Channel Negative Voltage Supply Rail Package Shipping† ESDR7534W1T2G SC−88 (Pb−Free) 3,000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Positive Voltage Supply Rail ESD Channel © Semiconductor Components Industries, LLC, 2015 March, 2015 − Rev. 3 Device 1 Publication Order Number: ESDR7534/D ESDR7534 ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) Symbol IF Parameter IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM Working Peak Reverse Voltage IR VC VBR VRWM Maximum Reverse Leakage Current @ VRWM VBR Breakdown Voltage @ IT IT Test Current IF Forward Current VF Forward Voltage @ IF Ppk Peak Power Dissipation C V IR VF IT IPP Uni−Directional TVS Capacitance @ VR = 0 and f = 1.0 MHz *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TA=25°C unless otherwise specified) Parameter Symbol Reverse Working Voltage VRWM Breakdown Voltage VBR Conditions Min Typ 6.0 8.0 (Note 1) IT = 1 mA, (Note 2) Max Unit 5.0 V 9.5 V Reverse Leakage Current IR VRWM = 5 V 3.0 mA Forward Voltage VF IF = 100 mA 1.6 V Clamping Voltage VC IPP = 10 A (2 x 10 ms Waveform) 30 V Maximum Peak Pulse Current IPP 2 x 10 ms Waveform 10 A Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and GND 1.3 2.0 pF Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins, VP floating 0.7 1.0 pF 1. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 2. VBR is measured at pulse test current IT. Peak Value 100 15.0 tr = rise time to peak value [2 ms] tf = decay time to half value [10 ms] 12.5 Vclamp (V) Ipp - PEAK PULSE CURRENT - %Ipp Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Half Value 50 10.0 7.5 5.0 2.5 0 0 0 tr 0 tf 2 4 6 8 10 12 14 16 18 TIME (ms) Ipp (A) Figure 1. Exponential Decay Pulse Waveform Figure 2. Clamping Voltage vs. Peak Pulse Current (tp = 2 x 10 ms, R = 8 W) www.onsemi.com 2 20 ESDR7534 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger 1.E−02 5 1.E−03 4 CAPACITANCE (pF) CURRENT (A) 1.E−04 1.E−05 1.E−06 1.E−07 1.E−08 1.E−09 3 2 1 1.E−10 1.E−11 −1 0 1 2 3 4 5 6 7 8 9 0 −1 0 1 2 3 4 VOLTAGE (V) VBias (V) Figure 5. IV Characteristic Curve Figure 6. CV Characteristic Curve www.onsemi.com 3 5 ESDR7534 APPLICATIONS INFORMATION Option 2 The new ESDR7534 is a low capacitance TVS diode array designed to protect sensitive electronics such as communications systems, computers, and computer peripherals against damage due to ESD events or transient overvoltage conditions. Because of its low capacitance, it can be used in high speed I/O data lines. The integrated design of the ESDR7534 offers low capacitance steering diodes and an internal TVS diode (VP diode) integrated in a single package. If a transient condition occurs, the steering diodes will drive the transient to the positive rail of the power supply or to ground. The TVS device protects the power line against overvoltage conditions to avoid damage to the power supply and any downstream components. Protection of four data lines with bias and power supply isolation resistor. I/O 1 I/O 2 VCC 1 6 10 k 2 5 3 4 I/O 3 ESDR7534 Configuration Options I/O 4 The ESDR7534 is able to protect up to four data lines against transient overvoltage conditions by driving them to a fixed reference point for clamping purposes. The steering diodes will be forward biased whenever the voltage on the protected line exceeds the reference voltage (Vf or VCC + Vf). The diodes will force the transient current to bypass the sensitive circuit. Data lines are connected at pins 1, 3, 4 and 6. The negative reference is connected at pin 2. This pin must be connected directly to ground by using a ground plane to minimize the PCB’s ground inductance. It is very important to reduce the PCB trace lengths as much as possible to minimize parasitic inductances. The ESDR7534 can be isolated from the power supply by connecting a series resistor between pin 5 and VCC. A 10 kW resistor is recommended for this application. This will maintain a bias on the VP and steering diodes, reducing their capacitance. Option 3 Protection of four data lines using the VP diode as reference. I/O 1 I/O 2 Option 1 1 6 Protection of four data lines and the power supply using VCC as reference. 2 5 3 4 I/O 1 I/O 2 NC I/O 3 1 6 2 5 3 4 I/O 4 In applications lacking a positive supply reference or those cases in which a fully isolated power supply is required, the VP can be used as the reference. For these applications, pin 5 is not connected. In this configuration, the steering diodes will conduct whenever the voltage on the protected line exceeds the VBR of the I/O (CHX) pin. VCC I/O 3 I/O 4 For this configuration, connect pin 5 directly to the positive supply rail (VCC), the data lines are referenced to the supply voltage. The VP diode prevents overvoltage on the supply rail. Biasing of the steering diodes reduces their capacitance. www.onsemi.com 4 ESDR7534 PACKAGE DIMENSIONS SC−88/SC−70−6/SOT−363 CASE 419B−02 ISSUE Y 2X aaa H D D H A D 6 5 GAGE PLANE 4 L L2 E1 E 1 2 DETAIL A 3 aaa C 2X bbb H D 2X 3 TIPS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END. 4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY AND DATUM H. 5. DATUMS A AND B ARE DETERMINED AT DATUM H. 6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. e B 6X DIM A A1 A2 b C D E E1 e L L2 aaa bbb ccc ddd b ddd TOP VIEW M A2 C A-B D DETAIL A A 6X ccc C A1 C SIDE VIEW SEATING PLANE c MILLIMETERS MIN NOM MAX −−− −−− 1.10 0.00 −−− 0.10 0.70 0.90 1.00 0.15 0.20 0.25 0.08 0.15 0.22 1.80 2.00 2.20 2.00 2.10 2.20 1.15 1.25 1.35 0.65 BSC 0.26 0.36 0.46 0.15 BSC 0.15 0.30 0.10 0.10 INCHES NOM MAX −−− 0.043 −−− 0.004 0.035 0.039 0.008 0.010 0.006 0.009 0.078 0.086 0.082 0.086 0.049 0.053 0.026 BSC 0.010 0.014 0.018 0.006 BSC 0.006 0.012 0.004 0.004 MIN −−− 0.000 0.027 0.006 0.003 0.070 0.078 0.045 END VIEW RECOMMENDED SOLDERING FOOTPRINT* 6X 6X 0.30 0.66 2.50 0.65 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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