NUP4114 Series, SZNUP4114HMR6T1G Transient Voltage Suppressors ESD Protection Diodes with Low Clamping Voltage http://onsemi.com The NUP4114 transient voltage suppressors are designed to protect high speed data lines from ESD. Ultra−low capacitance and high level of ESD protection make these devices well suited for use in USB 2.0 high speed applications. 5 1 4 3 6 Features • Low Clamping Voltage • Small Body Outline Dimensions on SC−88 Package: • • • • • • • • 0.082″ x 0.078″ (2.10 mm x 1.25 mm) Low Body Height: 0.043″ (1.10 mm) Stand−off Voltage: 5.5 V Low Leakage Response Time is Typically < 1.0 ns IEC61000−4−2 Level 4 ESD Protection These Devices are Pb−Free and are RoHS Compliant AEC−Q101 Qualified and PPAP Capable − SZNUP4114 SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements 2 MARKING DIAGRAMS 6 SC−88 W1 SUFFIX CASE 419B 1 1 6 SC−88 W1 SUFFIX CASE 419B Typical Applications • • • • • • • LVDS USB 2.0 High Speed Data Line and Power Line Protection Digital Video Interface (DVI) and HDMI Monitors and Flat Panel Displays High Speed Communication Line Protection Notebook Computers Gigabit Ethernet 1 6 1 6 Rating Symbol Value Unit Operating Junction Temperature Range TJ −40 to +125 °C Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Seconds) TL 260 °C ±8 ±15 kV Contact Air X4 MG G 1 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) IEC 61000−4−2 (ESD) X2 MG G Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1 TSOP−6 CASE 318G STYLE 12 SOT−563 CASE 463A P4H MG G 1 1 P4MG G XXX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2012 May, 2012 − Rev. 2 1 Publication Order Number: NUP4114/D NUP4114 Series, SZNUP4114HMR6T1G ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) Symbol IF Parameter IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR Working Peak Reverse Voltage VBR Test Current IF Forward Current VF Forward Voltage @ IF Ppk Peak Power Dissipation V IR VF IT Breakdown Voltage @ IT IT C VC VBR VRWM Maximum Reverse Leakage Current @ VRWM IPP Uni−Directional TVS Capacitance @ VR = 0 and f = 1.0 MHz *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Reverse Working Voltage Breakdown Voltage Symbol VRWM VBR Conditions Min Typ (Note 1) IT = 1 mA, (Note 2) Max Unit 5.5 V 5.5 V Reverse Leakage Current IR VRWM = 5.5 V 1.0 mA Clamping Voltage VC IPP = 5 A (Note 3) 9.0 V Clamping Voltage VC IPP = 8 A (Note 3) 10 V Clamping Voltage VC IPP = 1 A (Note 4) 10 V ESD Clamping Voltage VC Per IEC61000−4−2 (Note 5) Maximum Peak Pulse Current IPP 8x20 ms Waveform (Note 3) 12 A Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and GND 0.6 pF Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins 0.3 pF 8.3 See Figures 1 & 2 1. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 2. VBR is measured at pulse test current IT. 3. Nonrepetitive current pulse (Pin 5 to Pin 2) 4. Nonrepetitive current pulse (I/O to GND). 5. For test procedure see Figures 3 and 4 and Application Note AND8307/D. 6. Include SZ−prefix devices where applicable. Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 http://onsemi.com 2 NUP4114 Series, SZNUP4114HMR6T1G IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 5. 8 X 20 ms Pulse Waveform http://onsemi.com 3 80 NUP4114 Series, SZNUP4114HMR6T1G Figure 6. 500 MHz Data Pattern ORDERING INFORMATION Marking Package Shipping† NUP4114UCLW1T2G X2 SC−88 (Pb−Free) 3000 / Tape & Reel NUP4114UCW1T2G X4 SC−88 (Pb−Free) 3000 / Tape & Reel NUP4114UPXV6T1G P4 SOT−563 (Pb−Free) 4000 / Tape & Reel NUP4114HMR6T1G P4H TSOP−6 (Pb−Free) 3000 / Tape & Reel SZNUP4114HMR6T1G P4H TSOP−6 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 NUP4114 Series, SZNUP4114HMR6T1G APPLICATIONS INFORMATION Option 2 The new NUP4114 is a low capacitance TVS diode array designed to protect sensitive electronics such as communications systems, computers, and computer peripherals against damage due to ESD events or transient overvoltage conditions. Because of its low capacitance, it can be used in high speed I/O data lines. The integrated design of the NUP4114 offers low capacitance steering diodes and a TVS diode integrated in a single package (TSOP−6). If a transient condition occurs, the steering diodes will drive the transient to the positive rail of the power supply or to ground. The TVS device protects the power line against overvoltage conditions to avoid damage to the power supply and any downstream components. Protection of four data lines with bias and power supply isolation resistor. I/O 1 I/O 2 VCC 1 6 2 5 3 4 10 k I/O 3 NUP4114 Configuration Options I/O 4 The NUP4114 is able to protect up to four data lines against transient overvoltage conditions by driving them to a fixed reference point for clamping purposes. The steering diodes will be forward biased whenever the voltage on the protected line exceeds the reference voltage (Vf or VCC + Vf). The diodes will force the transient current to bypass the sensitive circuit. Data lines are connected at pins 1, 3, 4 and 6. The negative reference is connected at pin 2. This pin must be connected directly to ground by using a ground plane to minimize the PCB’s ground inductance. It is very important to reduce the PCB trace lengths as much as possible to minimize parasitic inductances. The NUP4114 can be isolated from the power supply by connecting a series resistor between pin 5 and VCC. A 10 kW resistor is recommended for this application. This will maintain a bias on the internal TVS and steering diodes, reducing their capacitance. Option 3 Protection of four data lines using the internal TVS diode as reference. I/O 1 I/O 2 Option 1 1 6 Protection of four data lines and the power supply using VCC as reference. 2 5 3 4 I/O 1 I/O 2 NC I/O 3 1 6 2 5 3 4 I/O 4 In applications lacking a positive supply reference or those cases in which a fully isolated power supply is required, the internal TVS can be used as the reference. For these applications, pin 5 is not connected. In this configuration, the steering diodes will conduct whenever the voltage on the protected line exceeds the working voltage of the TVS plus one diode drop (VC = Vf + VTVS). VCC I/O 3 I/O 4 ESD Protection of Power Supply Lines For this configuration, connect pin 5 directly to the positive supply rail (VCC), the data lines are referenced to the supply voltage. The internal TVS diode prevents overvoltage on the supply rail. Biasing of the steering diodes reduces their capacitance. When using diodes for data line protection, referencing to a supply rail provides advantages. Biasing the diodes reduces their capacitance and minimizes signal distortion. http://onsemi.com 5 NUP4114 Series, SZNUP4114HMR6T1G layout. Taking care to minimize the effects of parasitic inductance will provide significant benefits in transient immunity. Even with good board layout, some disadvantages are still present when discrete diodes are used to suppress ESD events across datalines and the supply rail. Discrete diodes with good transient power capability will have larger die and therefore higher capacitance. This capacitance becomes problematic as transmission frequencies increase. Reducing capacitance generally requires reducing die size. These small die will have higher forward voltage characteristics at typical ESD transient current levels. This voltage combined with the smaller die can result in device failure. The ON Semiconductor NUP4114 was developed to overcome the disadvantages encountered when using discrete diodes for ESD protection. This device integrates a TVS diode within a network of steering diodes. Implementing this topology with discrete devices does have disadvantages. This configuration is shown below: Power Supply IESDpos VCC Protected Data Line Device D1 IESDpos D2 IESDneg IESDneg VF + VCC −VF Looking at the figure above, it can be seen that when a positive ESD condition occurs, diode D1 will be forward biased while diode D2 will be forward biased when a negative ESD condition occurs. For slower transient conditions, this system may be approximated as follows: For positive pulse conditions: Vc = VCC + VfD1 For negative pulse conditions: Vc = −VfD2 ESD events can have rise times on the order of some number of nanoseconds. Under these conditions, the effect of parasitic inductance must be considered. A pictorial representation of this is shown below. Power Supply 5 1 Figure 7. NUP4114 Equivalent Circuit During an ESD condition, the ESD current will be driven to ground through the TVS diode as shown below. VCC Protected Device IESDpos 4 2 IESDpos D1 3 6 Power Supply IESDneg VCC Data Line D2 D1 VC = VCC + Vf + (L diESD/dt) IESDneg Protected Device IESDpos Data Line D2 VC = −Vf − (L diESD/dt) An approximation of the clamping voltage for these fast transients would be: For positive pulse conditions: Vc = VCC + Vf + (L diESD/dt) For negative pulse conditions: Vc = −Vf – (L diESD/dt) As shown in the formulas, the clamping voltage (Vc) not only depends on the Vf of the steering diodes but also on the L diESD/dt factor. A relatively small trace inductance can result in hundreds of volts appearing on the supply rail. This endangers both the power supply and anything attached to that rail. This highlights the importance of good board The resulting clamping voltage on the protected IC will be: Vc = VF + VTVS. The clamping voltage of the TVS diode depends on the magnitude of the ESD current. The steering diodes are fast switching devices with unique forward voltage and low capacitance characteristics. http://onsemi.com 6 NUP4114 Series, SZNUP4114HMR6T1G PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE U D H 6 E1 5 ÉÉÉ 1 NOTE 5 2 L2 4 GAUGE PLANE E 3 L b A1 C DETAIL Z e 0.05 M A SEATING PLANE c DETAIL Z NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. DIM A A1 b c D E E1 e L L2 M MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 6X 3.20 0.95 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 NUP4114 Series, SZNUP4114HMR6T1G PACKAGE DIMENSIONS SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE W D e 6 5 4 HE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419B−01 OBSOLETE, NEW STANDARD 419B−02. −E− 1 2 DIM A A1 A3 b C D E e L HE 3 b 6 PL 0.2 (0.008) M E M A3 MILLIMETERS MIN NOM MAX 0.80 0.95 1.10 0.00 0.05 0.10 0.20 REF 0.10 0.21 0.30 0.10 0.14 0.25 1.80 2.00 2.20 1.15 1.25 1.35 0.65 BSC 0.10 0.20 0.30 2.00 2.10 2.20 C A A1 L SOLDERING FOOTPRINT* 0.50 0.0197 0.65 0.025 0.65 0.025 0.40 0.0157 1.9 0.0748 SCALE 20:1 mm Ǔ ǒinches SC−88/SC70−6/SOT−363 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 INCHES NOM MAX 0.037 0.043 0.002 0.004 0.008 REF 0.004 0.008 0.012 0.004 0.005 0.010 0.070 0.078 0.086 0.045 0.049 0.053 0.026 BSC 0.004 0.008 0.012 0.078 0.082 0.086 MIN 0.031 0.000 NUP4114 Series, SZNUP4114HMR6T1G PACKAGE DIMENSIONS SOT−563, 6 LEAD CASE 463A−01 ISSUE F D −X− 6 5 1 e 2 A 4 L E −Y− 3 b NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. DIM A b C D E e L HE HE C 5 PL 6 0.08 (0.003) M X Y MILLIMETERS MIN NOM MAX 0.50 0.55 0.60 0.17 0.22 0.27 0.08 0.12 0.18 1.50 1.60 1.70 1.10 1.20 1.30 0.5 BSC 0.10 0.20 0.30 1.50 1.60 1.70 INCHES NOM MAX 0.021 0.023 0.009 0.011 0.005 0.007 0.062 0.066 0.047 0.051 0.02 BSC 0.004 0.008 0.012 0.059 0.062 0.066 MIN 0.020 0.007 0.003 0.059 0.043 SOLDERING FOOTPRINT* 0.3 0.0118 0.45 0.0177 1.35 0.0531 1.0 0.0394 0.5 0.5 0.0197 0.0197 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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