NUP4201MR6 Transient Voltage Suppressors ESD Protection Diodes with Low Clamping Voltage The NUP4201MR6 transient voltage suppressor is designed to protect high speed data lines from ESD, EFT, and lighting. Features • • • • • • • Low Clamping Voltage Stand−Off Voltage: 5 V Low Leakage TSOP−6 is footprint compatible with SC−74, SC−59 6 Lead and SOT−23 6 Lead Protection for the Following IEC Standards: IEC 61000−4−2 Level 4 ESD Protection UL Flammability Rating of 94 V−0 Pb−Free Package is Available Typical Applications • • • • http://onsemi.com TSOP−6 LOW CAPACITANCE DIODE TVS ARRAY 500 WATTS PEAK POWER 6 VOLTS PIN CONFIGURATION AND SCHEMATIC I/O 1 6 I/O VN 2 5 VP I/O 3 4 I/O High Speed Communication Line Protection USB 1.1 and 2.0 Power and Data Line Protection Digital Video Interface (DVI) Monitors and Flat Panel Displays 6 1 TSOP−6 CASE 318G PLASTIC MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Value Unit Peak Power Dissipation 8 x 20 mS @ TA = 25°C (Note 1) Ppk 500 W Operating Junction Temperature Range TJ −40 to +125 °C Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Seconds) NUP4201MR6T1 NUP4201MR6T1G TL 235 260 °C °C Human Body Model (HBM) Machine Model (MM) IEC 61000−4−2 Air (ESD) IEC 61000−4−2 Contact (ESD) ESD 16000 400 20000 20000 V IEC 61000−4−4 (5/50 ns) EFT 40 A Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Non−repetitive current pulse per Figure 5 (Pin 5 to Pin 2) September, 2009 − Rev. 5 63 G G 63 = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation may vary depending upon manufacturing location. ORDERING INFORMATION Device NUP4201MR6T1 NUP4201MR6T1G Package Shipping TSOP−6 3000/Tape & Reel TSOP−6 3000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2009 MARKING DIAGRAM M Symbol 1 Publication Order Number: NUP4201MR6/D NUP4201MR6 ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) Symbol IF Parameter IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR Working Peak Reverse Voltage VBR Test Current IF Forward Current VF Forward Voltage @ IF Ppk Peak Power Dissipation V IR VF IT Breakdown Voltage @ IT IT C VC VBR VRWM Maximum Reverse Leakage Current @ VRWM IPP Uni−Directional TVS Capacitance @ VR = 0 and f = 1.0 MHz *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TJ=25°C unless otherwise specified) Parameter Reverse Working Voltage Breakdown Voltage Symbol VRWM VBR Conditions Min Typ (Note 2) IT=1 mA, (Note 3) Max Unit 5.0 V 6.0 V Reverse Leakage Current IR VRWM = 5 V 5.0 mA Clamping Voltage VC IPP = 5 A (Note 4) 12.5 V Clamping Voltage VC IPP = 8 A (Note 4) 20 V Maximum Peak Pulse Current IPP 8x20 ms Waveform (Note 4) 25 A Junction Capacitance CJ VR = 0 V, f=1 MHz between I/O Pins and GND 3.0 5.0 pF Junction Capacitance CJ VR = 0 V, f=1 MHz between I/O Pins 1.5 3.0 pF Clamping Voltage VC @ IPP = 1 A (Notes 5 and 6) 16.6 V Clamping Voltage VC Per IEC 61000−4−2 (Note 7) Figure 1 and 2 V 2. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 3. VBR is measured at pulse test current IT. 4. Non−repetitive current pulse per Figure 5 (Pin 5 to Pin 2) 5. Non−repetitive current pulse per FIgure 5 (Any I/O Pins) 6. Surge current waveform per Figure 5. 7. For test procedure see Figures 3 and 4 and Application Note AND8307/D. Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 http://onsemi.com 2 NUP4201MR6 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 5. 8 X 20 ms Pulse Waveform http://onsemi.com 3 80 NUP4201MR6 TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) PEAK POWER DISSIPATION (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 150 175 200 TA, AMBIENT TEMPERATURE (°C) 5.0 20 4.5 18 4.0 16 CLAMPING VOLTAGE (V) JUNCTION CAPACITANCE (pF) Figure 6. Pulse Derating Curve 3.5 3.0 I/O−Ground 2.5 2.0 I/O lines 1.5 1.0 12 10 8 6 4 2 0.5 0.0 14 0 1 2 3 4 0 5 0 VBR, REVERSE VOLTAGE (V) 10 20 30 40 50 PEAK PULSE CURRENT (A) Figure 8. Clamping Voltage vs. Peak Pulse Current (8 x 20 ms Waveform) Figure 7. Junction Capacitance vs Reverse Voltage http://onsemi.com 4 NUP4201MR6 APPLICATIONS INFORMATION Option 2 Protection of four data lines with bias and power supply isolation resistor. The new NUP4201MR6 is a low capacitance TVS diode array designed to protect sensitive electronics such as communications systems, computers, and computer peripherals against damage due to ESD events or transient overvoltage conditions. Because of its low capacitance, it can be used in high speed I/O data lines. The integrated design of the NUP4201MR6 offers surge rated, low capacitance steering diodes and a TVS diode integrated in a single package (TSOP−6). If a transient condition occurs, the steering diodes will drive the transient to the positive rail of the power supply or to ground. The TVS device protects the power line against overvoltage conditions to avoid damage to the power supply and any downstream components. I/O 1 I/O 2 VCC 1 6 2 5 3 4 10 k I/O 3 I/O 4 NUP4201MR6 Configuration Options The NUP4201MR6 is able to protect up to four data lines against transient overvoltage conditions by driving them to a fixed reference point for clamping purposes. The steering diodes will be forward biased whenever the voltage on the protected line exceeds the reference voltage (Vf or VCC + Vf). The diodes will force the transient current to bypass the sensitive circuit. Data lines are connected at pins 1, 3, 4 and 6. The negative reference is connected at pin 2. These pins must be connected directly to ground by using a ground plane to minimize the PCB’s ground inductance. It is very important to reduce the PCB trace lengths as much as possible to minimize parasitic inductances. The NUP4201MR6 can be isolated from the power supply by connecting a series resistor between pin 5 and VCC. A 10 kW resistor is recommended for this application. This will maintain a bias on the internal TVS and steering diodes, reducing their capacitance. Option 3 Protection of four data lines using the internal TVS diode as reference. I/O 1 I/O 2 Option 1 Protection of four data lines and the power supply using VCC as reference. I/O 1 I/O 2 1 6 2 5 3 4 NC I/O 3 I/O 4 1 6 2 5 3 4 In applications lacking a positive supply reference or those cases in which a fully isolated power supply is required, the internal TVS can be used as the reference. For these applications, pin 5 is not connected. In this configuration, the steering diodes will conduct whenever the voltage on the protected line exceeds the working voltage of the TVS plus one diode drop (Vc = Vf + VTVS). VCC I/O 3 I/O 4 ESD Protection of Power Supply Lines When using diodes for data line protection, referencing to a supply rail provides advantages. Biasing the diodes reduces their capacitance and minimizes signal distortion. Implementing this topology with discrete devices does have disadvantages. This configuration is shown below: For this configuration, connect pin 5 directly to the positive supply rail (VCC), the data lines are referenced to the supply voltage. The internal TVS diode prevents overvoltage on the supply rail. Biasing of the steering diodes reduces their capacitance. http://onsemi.com 5 NUP4201MR6 Power Supply IESDpos VCC Protected Data Line Device inductance will provide significant benefits in transient immunity. Even with good board layout, some disadvantages are still present when discrete diodes are used to suppress ESD events across datalines and the supply rail. Discrete diodes with good transient power capability will have larger die and therefore higher capacitance. This capacitance becomes problematic as transmission frequencies increase. Reducing capacitance generally requires reducing die size. These small die will have higher forward voltage characteristics at typical ESD transient current levels. This voltage combined with the smaller die can result in device failure. The ON Semiconductor NUP4201MR6 was developed to overcome the disadvantages encountered when using discrete diodes for ESD protection. This device integrates a TVS diode within a network of steering diodes. D1 IESDpos IESDneg D2 IESDneg VF + VCC −VF Looking at the figure above, it can be seen that when a positive ESD condition occurs, diode D1 will be forward biased while diode D2 will be forward biased when a negative ESD condition occurs. For slower transient conditions, this system may be approximated as follows: For positive pulse conditions: Vc = VCC + VfD1 For negative pulse conditions: Vc = −VfD2 ESD events can have rise times on the order of some number of nanoseconds. Under these conditions, the effect of parasitic inductance must be considered. A pictorial representation of this is shown below. Power Supply D3 D5 D7 D2 D4 D6 D8 IESDpos 0 Figure 9. NUP4201MR6 Equivalent Circuit VCC Protected Device D1 D1 IESDpos D2 VC = VCC + Vf + (L diESD/dt) IESDneg During an ESD condition, the ESD current will be driven to ground through the TVS diode as shown below. IESDneg Data Line Power Supply VCC D1 VC = −Vf − (L diESD/ dt) Protected Device An approximation of the clamping voltage for these fast transients would be: For positive pulse conditions: Vc = VCC + Vf + (L diESD/dt) For negative pulse conditions: Vc = −Vf – (L diESD/dt) As shown in the formulas, the clamping voltage (Vc) not only depends on the Vf of the steering diodes but also on the L diESD/dt factor. A relatively small trace inductance can result in hundreds of volts appearing on the supply rail. This endangers both the power supply and anything attached to that rail. This highlights the importance of good board layout. Taking care to minimize the effects of parasitic IESDpos Data Line D2 The resulting clamping voltage on the protected IC will be: Vc = VF + VTVS. The clamping voltage of the TVS diode is provided in Figure 8 and depends on the magnitude of the ESD current. The steering diodes are fast switching devices with unique forward voltage and low capacitance characteristics. http://onsemi.com 6 NUP4201MR6 TYPICAL APPLICATIONS UPSTREAM USB PORT VBUS VBUS VBUS VBUS D+ RT D+ RT D− VBUS GND USB Controller D− VBUS NUP4201MR6 CT CT DOWNSTREAM USB PORT GND VBUS NUP2201DT1 VBUS RT D+ RT D− GND CT CT DOWNSTREAM USB PORT Figure 10. ESD Protection for USB Port RJ45 Connector TX+ TX+ TX− TX− PHY Ethernet (10/100) RX+ Coupling Transformers RX+ RX− RX− NUP4201MR6 VCC GND N/C N/C Figure 11. Protection for Ethernet 10/100 (Differential mode) http://onsemi.com 7 NUP4201MR6 R1 RTIP R3 R2 RRING T1 VCC T1/E1 TRANCEIVER NUP4201MR6 R4 TTIP R5 TRING T2 Figure 12. TI/E1 Interface Protection http://onsemi.com 8 NUP4201MR6 PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. D 6 HE 1 5 4 2 3 E b DIM A A1 b c D E e L HE q e A 0.05 (0.002) q c L A1 MIN 0.90 0.01 0.25 0.10 2.90 1.30 0.85 0.20 2.50 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 1.50 1.70 0.95 1.05 0.40 0.60 2.75 3.00 10° − MIN 0.035 0.001 0.010 0.004 0.114 0.051 0.034 0.008 0.099 0° INCHES NOM 0.039 0.002 0.014 0.007 0.118 0.059 0.037 0.016 0.108 − MAX 0.043 0.004 0.020 0.010 0.122 0.067 0.041 0.024 0.118 10° SOLDERING FOOTPRINT* 2.4 0.094 1.9 0.075 0.95 0.037 0.95 0.037 0.7 0.028 1.0 0.039 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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