NTMFS4946N D

NTMFS4946N
Power MOSFET
30 V, 100 A, Single N−Channel, SO−8 FL
Features
•
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
Thermally Enhanced SO8 Package
These are Pb−Free Device
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V(BR)DSS
Applications
• CPU Power Delivery
• DC−DC Converters
• Low Side Switching
RDS(ON) MAX
3.4 mW @ 10 V
30 V
Symbol
D (5,6)
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
ID
20.3
A
Continuous Drain
Current RqJA
(Note 1)
TA = 25°C
Power Dissipation
RqJA (Note 1)
TA = 25°C
PD
2.25
Continuous Drain
Current RqJA v
10 sec
TA = 25°C
ID
32.8
Power Dissipation
RqJA, t v 10 sec
Continuous Drain
Current RqJA
(Note 2)
TA = 85°C
N−CHANNEL MOSFET
A
23.7
TA = 25°C
PD
5.90
W
TA = 25°C
ID
12.7
A
TA = 85°C
9.2
PD
0.89
Continuous Drain
Current RqJC
(Note 1)
TC = 25°C
ID
100
Power Dissipation
RqJC (Note 1)
TC = 25°C
PD
55.5
W
TA = 25°C
IDM
200
A
TA = 25°C
IDmaxpkg
100
A
TJ,
TSTG
−55 to
+150
°C
IS
55
A
Drain to Source dV/dt
dV/dt
6
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 50 V, VGS = 10 V,
IL = 37 Apk, L = 0.3 mH, RG = 25 W)
EAS
205
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
TL
260
TC = 85°C
Current limited by package
Operating Junction and Storage
Temperature
Source Current (Body Diode)
W
A
72
June, 2012 − Rev. 2
1
1
SO−8 FLAT LEAD
CASE 488AA
STYLE 1
A
Y
W
ZZ
S
S
S
G
4946N
AYWZZ
D
D
D
= Assembly Location
= Year
= Work Week
= Lot Traceability
ORDERING INFORMATION
Device
Package
Shipping†
NTMFS4946NT1G
SO−8FL
(Pb−Free)
1500 /
Tape & Reel
mJ
NTMFS4946NT3G
SO−8FL
(Pb−Free)
5000 /
Tape & Reel
°C
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
© Semiconductor Components Industries, LLC, 2012
MARKING
DIAGRAM
D
TA = 25°C
tp=10ms
S (1,2,3)
W
Power Dissipation
RqJA (Note 2)
Pulsed Drain
Current
G (4)
14.6
TA = 85°C
Steady
State
100 A
5.1 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
ID MAX
Publication Order Number:
NTMFS4946N/D
NTMFS4946N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Junction−to−Case (Drain)
Parameter
RqJC
2.25
Junction−to−Ambient – Steady State (Note 1)
RqJA
55.6
Junction−to−Ambient – Steady State (Note 2)
RqJA
140.8
Junction−to−Ambient − t v 10 sec
RqJA
21.2
Unit
°C/W
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Parameter
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
25
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25 °C
1
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.5
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
VGS(TH)/TJ
RDS(on)
1.45
1.8
5.2
VGS = 10 V to
11.5 V
ID = 30 A
2.5
ID = 15 A
2.4
VGS = 4.5 V
ID = 30 A
3.8
ID = 15 A
3.8
gFS
VDS = 1.5 V, ID = 30 A
mV/°C
3.4
5.1
85
mW
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
3250
VGS = 0 V, f = 1 MHz, VDS = 12 V
562
CRSS
289
Total Gate Charge
QG(TOT)
21.8
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
VGS = 4.5 V, VDS = 15 V; ID = 30 A
3.2
8.1
pF
32
nC
7.4
QG(TOT)
VGS = 11.5 V, VDS = 15 V,
ID = 30 A
53
nC
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
18.9
tr
td(OFF)
VGS = 4.5 V, VDS = 15 V, ID = 15 A,
RG = 3.0 W
tf
34
24.6
9.4
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
ns
NTMFS4946N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS (Note 4)
td(ON)
Turn−On Delay Time
Rise Time
10.7
tr
Turn−Off Delay Time
td(OFF)
Fall Time
18.9
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
ns
34.2
tf
7.1
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
VGS = 0 V,
IS = 30 A
TJ = 25°C
0.8
TJ = 125°C
0.66
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
1.0
V
21.6
11.4
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 30 A
ns
10.2
QRR
8.5
nC
Source Inductance
LS
0.65
nH
Drain Inductance
LD
Gate Inductance
LG
Gate Resistance
RG
PACKAGE PARASITIC VALUES
0.005
TA = 25°C
1.84
0.5
1.4
2.2
W
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
TYPICAL CHARACTERISTICS
ID, DRAIN CURRENT (A)
180
160
10 V
VGS = 4.2 V
TJ = 25°C
140
5.0 V
3.8 V
120
4.5 V
3.6 V
100
3.4 V
80
3.2 V
60
3.0 V
40
20
0
140
4.0 V
160
ID, DRAIN CURRENT (A)
200
2.8 V
2.6 V
0
1
2
3
4
5
VDS ≥ 10 V
120
100
80
60
TJ = 125°C
40
TJ = 25°C
20
0
6
TJ = −55°C
0
1
2
3
4
5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
TYPICAL CHARACTERISTICS
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3
6
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
NTMFS4946N
0.010
ID = 30 A
TJ = 25°C
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
2
3
4
6
5
7
8
9
11
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
0.007
0.006
0.005
VGS = 4.5 V
0.004
VGS = 11.5 V
0.003
0.002
0.001
0
10
15
25
30
35
40
45
50
55
60
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.75
10,000
VGS = 0 V
IDSS, LEAKAGE (nA)
ID = 30 A
VGS = 10 V
1.50
1.25
TJ = 150°C
1000
1.00
TJ = 125°C
0.75
0.50
−50
−25
0
25
50
75
100
125
100
150
2
4
TJ, JUNCTION TEMPERATURE (°C)
VGS, GATE−TO−SOURCE VOLTAGE (V)
12
11
10
3000
2500
2000
TJ = 25°C
1500
Coss
1000
Crss
500
0
0
5
10
15
20
10
12
14
16
20
18
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
Ciss
3500
8
25
20
QT
18
16
VGS
9
8
14
VDS
12
7
6
10
5
4
Qgs
8
Qgd
3
6
ID = 30 A
TJ = 25°C
2
1
0
0
5
10
15
20
25
30
35
40
45
4
2
50
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
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4
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
4000
6
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
C, CAPACITANCE (pF)
20
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
TJ = 25°C
0
NTMFS4946N
TYPICAL CHARACTERISTICS
VDS = 15 V
ID = 15 A
VGS = 11.5 V
IS, SOURCE CURRENT (A)
1000
tf
t, TIME (ns)
100
td(off)
tr
td(on)
10
1
0.5
0.6
0.7
0.8
0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
10 ms
100 ms
10
1 ms
10 ms
dc
1
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
0.4
RG, GATE RESISTANCE (W)
VGS = 20 V
Single Pulse
TC = 25°C
100
0.1
gFS (S)
100
VGS = 0 V
TJ = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
10
100
220
200
ID = 37 A
180
160
140
120
100
80
60
40
20
0
25
50
75
100
125
150
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ, STARTING JUNCTION TEMPERATURE(°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
1000
100
100°C
125°C
Id (A)
ID, DRAIN CURRENT (A)
1000
10
EAS, SINGLE PULSE DRAIN−TO−
SOURCE AVALANCHE ENERGY (mJ)
1
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
25°C
10
VDS = 1.5 V
0
10
20
30
40
50
60
70
80
90
1
100
0.1
1
10
100
1000
DRAIN CURRENT (A)
PULSE WIDTH (ms)
Figure 13. gFS vs. Drain Current
Figure 14. Id vs. Pulse Width
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5
10,000
NTMFS4946N
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE G
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
0.20 C
D
2
A
B
D1
2X
0.20 C
4X
E1
2
3
q
E
2
1
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
c
A1
4
TOP VIEW
C
3X
e
0.10 C
SEATING
PLANE
DETAIL A
A
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
0.10 C
SIDE VIEW
SOLDERING FOOTPRINT*
DETAIL A
3X
8X
0.10
C A B
0.05
c
4X
e/2
1
4
0.965
K
G
0.750
1.000
L
PIN 5
(EXPOSED PAD)
4X
1.270
b
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.15 BSC
4.50
4.90
5.10
3.50
−−−
4.22
6.15 BSC
5.50
5.80
6.10
3.45
−−−
4.30
1.27 BSC
0.51
0.61
0.71
1.20
1.35
1.50
0.51
0.61
0.71
0.05
0.17
0.20
3.00
3.40
3.80
0_
−−−
12 _
1.330
2X
0.905
2X
E2
L1
M
0.495
4.530
3.200
0.475
D2
2X
BOTTOM VIEW
1.530
4.560
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTMFS4946N/D