AND8327/D Stability Analysis in Multiple Loop Systems Prepared by Christophe Basso, Stéphanie Conseil, Nicolas Cyr http://onsemi.com Loop stability analysis usually starts from an open-loop Bode plot of the plant under study, e.g. the power stage of a buck or a flyback converter. From this diagram, the designer can extract phase and gain data within the frequency range of interest. His job then consists in identifying a compensator structure which will lead to the selected crossover frequency affected by the right phase margin. The final step requires the study of the total loop gain, the power plant followed by the compensator, showing that the poles/zeros placed on the compensator ensure stability once the loop is closed. If this operation is rather straightforward with single loops, the operation becomes more complicated with converters implementing weighted feedback. This paper capitalizes on the Ref. [1] work and explores different ways to apply the technique to power converters featuring multiple feedback paths. The TL431, a Multiple Loop System The TL431 alone, can be modeled as a multiple loop feedback system. Figure 1 shows a TL431 classically wired in a type-2 configuration, as described in Ref. [2]. From this schematic, one can identify so-called slow and fast lanes. Vout Vdd Rpullup 20 k FB Rled 1k R2 10 k Fast Lane Slow Lane U2B C2 1 nF C1 100 nF U2A U1 TL431 Primary Side R3 10 k Secondary Side Figure 1. A TL431 Wired in a Classical Configuration, Observing the dc Voltage of a Converter The TL431 can be seen as a programmable zener also called a shunt regulator. When the output voltage changes, e.g. because of a load variation, the information is conveyed to the inverting input of the TL431 via R2/R3 and asks the programmable zener to pump more or less current into the optocoupler LED. It does so by adjusting its cathode voltage. By this way, the feedback signal observed on the primary side also changes and instructs the controller to alter its operating point. If the output voltage variations are too fast, the frequency sensed by R2 exceeds the pole position introduced by C1 and the ac contribution of this path to the feedback signal becomes null: the TL431 no longer changes its operating point and the LED cathode is now fixed. However, as the LED cathode is fixed, the anode still senses an output voltage variation via Rled. This current variation propagates via the optocoupler and affects the feedback © Semiconductor Components Industries, LLC, 2008 April, 2008 - Rev. 0 voltage. Therefore, even if you increase C1, it has no effect in rolling off the loop gain since Rled always senses the output voltage. The transfer function of such a system can be written in the following form [2]: ǒ Ǔ V FB(s) + G1(s) 1 ) 1 V out(s) sR 2C 1 (eq. 1) where G1(s) represents the mid-band gain brought by the optocoupler CTR, the LED and the pull-up resistors associated to the capacitor C2. From this expression, we can actually see the presence of two loops by developing Equation1: V FB(s) G (s) + G1(s) ) 1 V out(s) sR 2C 1 1 (eq. 2) Publication Order Number: AND8327/D AND8327/D The loop gain of such a system could be measured by breaking the loop at the feedback point. Unfortunately, depending on the converter configuration, this solution can sometimes be difficult to implement. The best is then to measure the loop gain from the secondary side. In this particular example, both the fast and slow lanes share a similar entry point. The total loop gain could therefore be measured as suggested by Figure 2: In this schematic, it is not possible to sweep both inputs together as they are separated by the LC filter. Fortunately, we can apply the superposition theorem as we are dealing with a linear system. At first, we will sweep the slow lane while keeping the fast lane to a bias level, totally disconnected from the output voltage. A dc voltage supplied by an external source will do. This is what Figure 4 shows. The precision of the 5 V source is not relevant here as it only serves bias purposes. The ac source actually represents an injection transformer, classically used in loop stability studies. The A and B probes go to a network analyzer which will compute Vout V1 AC = 1 + Rled 1k R2 10 k Fast Lane Slow Lane U2B ǒǓ 20 log10 B , A displaying a loop gain equal to G1(s) sR 2C 1 C1 100 nF L1 Vout U1 TL431 Vsweep AC = 1 V R3 10 k + + Vext 5V Figure 2. When Both Slow and Fast Lanes are Connected Together, the Measurement is Easy to Run Fast Lane A stimulus source is inserted in series with the output voltage and both slow and fast lanes are ac swept. The voltage observed on the feedback pin is therefore proportional to both inputs and is representative of what Equations1 and 2 predict. In Figure 3, we can see the presence of a LC filter, added to remove unwanted high frequency spikes, typical of a flyback converter. U2B U1 TL431 L1 Fast Lane U2B U1 TL431 R2 10 k C1 100 nF A R2 10 k Slow Lane + Cout 220 mF R3 10 k Then, once the plot is saved, the configuration needs to be changed to the other input, as suggested by Figure 5. In this circuit, the upper R2 terminal is connected to a dc voltage whose value must equal the regulated voltage whereas the fast lane input is now ac swept: Slow Lane + Cout 220 mF C1 100 nF B Figure 4. The Fast Lane is ac Disconnected from the Circuit and Only the Slow Lane Receives a Stimulus Vout Rled 1k Rled 1k R3 10 k Figure 3. The Presence of the LC Filter Splits Both Lanes http://onsemi.com 2 AND8327/D L1 Vout Vsweep AC = 1 V Vext 5V + (eq. 5) Im(V FB) + A 1 sin ö 1 ) A 2 sin ö 2 + Y (eq. 6) The rotating vector obtained at the end will be of the following form: + B Re(V FB) + A 1 cos ö 1 ) A 2 cos ö 2 + X Rled 1k R2 10 k V FB + X ) jY Fast Lane Slow Lane Where we can now extract a module and an argument: (eq. 8) ø V ø+ ǸY 2 ) X 2 A U2B U1 TL431 FB + Cout 220 mF C1 100 nF (eq. 7) ǒǓ arg V FB + tan *1 Y X (eq. 9) Plotting 20log10 of Equation 8 and the phase returned by Equation9 should give the Bode plot we are looking for. R3 10 k SPICE Application Before rushing to the laboratory to apply this technique, let's give it a try with a SPICE simulation and check that our equations give the correct answers. Figure 6 depicts the TL431 circuit ready to be ac swept, both inputs being connected together. The sweep technique uses an old trick with L1 and C3 which open the loop in ac but keep it closed in dc. The closed path in dc helps to automatically adjust the voltage on the upper terminal of R2 to obtain a 2.5 V on the feedback output, right in the middle of the available dynamic. This ensures a circuit properly biased without the need to tweak anything else. The bias points appearing in Figure6 confirms the right values. Once the ac sweep is run the Bode diagram appears in Figure 7 and confirms the presence of an origin pole, a low frequency zero, a high frequency pole and a mid-band gain in between. The phase boost peaks to 134° at a frequency of 380 Hz where the gain reaches 23dB. Now, let us separate the two lanes by applying the technique we described earlier. The exploration of the fast lane requires a simple dc bias on the divider network, again provided by the operational amplifier. Figure8 portrays the circuit we have implemented. The modulation signal enters the fast lane through the ac source Vsweep whereas L1 and C4 prevent any injection in the slow lane: both loops are fully decoupled from each others. For the slow lane sweep, Figure 9 shows the adopted sketch: the upper LED resistor is simply hooked to a dc source and the ac stimulus now sweeps the slow lane through the LC network. Again, there is no ac link between both inputs. Figure 5. The Fast Lane is Now ac Swept as the Slow Lane is Simply dc Biased The dc adjustment might be a little difficult given the open-loop gain brought by the TL431 and the sensitivity on the external bias. The network analyzer still computes 20log10(B/A) for the fast lane but this time, it plots a loop gain equal to G1(s). Combining Signals Together Once we have both slow and fast lanes loop plots on the screen, how can we combine them? Can we just sum up the gain and phase diagrams, respectively expressed in dB and degrees? Certainly not, it would correspond to cascaded gain blocks and not paralleled paths. We need to vector sum both output signals and reconstruct the final signal which expresses the combination of both loops. Using Euler notation, we can express the slow lane signal by a rotating vector affected by a module A1 and a phase ϕ1: V out,slow + A 1(cosö 1 ) j sin ö 1) (eq. 3) Using a similar notation, we can write the fast lane expression: V out,fast + A 2(cosö 2 ) j sin ö 2) (eq. 4) To reconstruct and plot the final gain curve combining both signals − the signal observed on the feedback pin once all loops are closed − we need to separate the real and imaginary portions of the two lanes and sum them together: http://onsemi.com 3 AND8327/D 5.0 V Vdd 5 + Rpullup 20 k FB 10 L1 4.99 V 4 Rled 1k R2 10 k 1 2.49 V 4.86 V VFB 3 2.5 V C3 1 kF 4.99 V 9 X3 AMPSIMP 7 + - 2.5 V 8 FB 2.5 V + V2 2.5 0V X1 Optocoupler C2 10 n 1 kH + Vsweep AC = 1 3.78 V 100 nF C1 6 U1 TL431 R3 10 k Figure 6. The Type 2 Compensator Based on a TL431 and Adapted for a SPICE Simulation 1 vdbfb 2 ph_vfb Plot1 vdbfb in db(volts) 60.0 Loop gain (dB) 40.0 20.0 23 dB 0 1 -20.0 Plot2 ph_vfb in degrees 150 Phase (°) 130 110 41° 90.0 2 70.0 10 100 1k frequency in hertz 10k Figure 7. ac Results of the Type 2 Compensator, Highlighting the Presence of Two Poles and One Zero http://onsemi.com 4 100k AND8327/D Vsweep AC = 1 5 Vdd + 5.0 V 5.0 V 5 + Rpullup 20 k FB 10 C4 L1 1 kH 4.99 V 2 1 kF Rled 1k R2 10 k 8 FB 2.5 V + V2 2.5 3 1 2.49 V 4.87 V VFB 4.99 V 4 X3 AMPSIMP + 9 - X1 Optocoupler 2.5 V C2 10 n 3.79 V 100 nF C1 6 U1 TL431 R3 10 k Figure 8. The Fast Lane Sweep Requires a Clear Separation between Both Lanes Vbias 5 Vdd + 5.0 V 5 + Rpullup 20 k FB 10 5.0 V 4.99 V 4 Rled 1k R2 10 k 3 1 C2 10 n 4.99 V 8 + V2 2.5 + Vsweep AC = 1 3.79 V C1 C3 1 kF 0V X1 Optocoupler 2.5 V 1 kH 7 2.49 V 4.87 V VFB L1 2 X3 AMPSIMP + FB 9 2.5 V 100 nF 6 U1 TL431 R3 10 k Figure 9. In the Slow Lane Sweep, the Fast Lane Input Goes to a Fixed dc Bias SPICE offers the possibility to extract the imaginary and real parts from an ac simulation. This is what Figure10 shows where the real curves of both the fast and slow sweeps have been gathered in the upper portion. The lower section of the figure contains the imaginary portions of both lanes. The graphical viewer can easily manipulate waveforms and the sum of both imaginary and real curves already appears on the picture. http://onsemi.com 5 AND8327/D Plot2 sum, im_slow, im_fast in volts Plot1 sum, re_fast, re_slow in volts 1 re_fast 2 im_fast 3 re_slow 4 im_slow 5 sum 5.00 6 sum Re_slow 5 1 3 -5.00 Re_fast -15.0 -25.0 -35.0 Re_fast + Re_slow (Y) 160 120 Im_slow + Im_fast (X) 80.0 40.0 0 10 Im_fast 6 2 4 Im_slow 100 1k 10k 100k frequency in hertz Figure 10. This Plot Gathers the Real and Imaginary Portions of the Feedback Signal Collected when the Fast and Slow Lanes are Separately ac Swept Once we reached that point, we can apply Equations8 and9 via the graphical viewer internal script. The resulting waveforms are displayed on Figures 11 and 12 then compared to Figure 7. They are identical gain wise (Figure11), despite different signs on the phase in Figure12 (the tan-1 function is modulo 180°). http://onsemi.com 6 AND8327/D 0 200 -10.0 100 sum#a in volts Plot1 sum in volts 1 p -20.0 -30.0 -40.0 5 sum 6 sum#a 0 6 X -100 -200 60.0 20log10 Y 2 + X 2 40.0 pin unknown Plot3 5 Y 20.0 23 dB 0 p=20*log((sqrt(w5*w5+w6*w6))) plot ”p” -20.0 10 100 1 1k frequency in hertz 10k 100k Figure 11. Once Mathematical Calculations are Made, the Amplitude Response Reveals the Classical Type 2 Function we are Looking For 1 p Plot1 sum in volts -10.0 -20.0 -30.0 -40.0 200 sum#a in volts 0 5 sum 6 sum#a Y 5 100 0 X 6 -100 -200 1 Plot3 pin unknown -50.0 p=atan(w6/w5) plot ”p” -60.0 -70.0 -80.0 41° ǒǓ tan *1 X Y -90.0 10 100 1k frequency in hertz 10k 100k Figure 12. Calculating the Argument Leads to a Similar Result for the Phase, Showing a Boost of 415 http://onsemi.com 7 AND8327/D Combining Data with a Network Analyzer, a Real Case Example To check the validity of our assumptions, we have built a 65W power supply based on a classical UC3843 controller. The internal op-amp is disabled via a pull-up resistor HV-bulk C4 100 mF 400 V + R19 47 k C11 + R3 47 k R7 20 k R6 6k 1 CMP Ref 8 2 FB IN 4 Rt 1N4937 R1 R16 10 GND 5 X2 C10 470 n L2 + 2.2 nF D8 330 R18 47 k U1 UC3843 U3B MBR20100 D5 + C5a 1.2 mF 25 V Type = Y1 C13 R17 47 k Vcc 7 3 CS DRV 6 M1 SPP11N60S5 R8 1k 2.2 m C7 220 mF 25 V R24 C3 C12 1 Meg 1 Meg C16 4.7 nF 220 p 85 - 260 Vac C15 10 nF Vout C5b 1.2 mF 25 V R14 4.7 k R12 10 k U3A R10 56 k 47 n C6 1k 220 mF + Gnd R5 + R23 T1 86H-6232 0.18 : 1 : 0.25 D2 Vref IC4 KBU4K 2 x 10 mH Schaffner RN122-1.5/02 C2 10 n 400 V R13 47 k MUR160 1 nF - L1 connected to the reference voltage. Figure 13 shows the adopted schematic: R6a 1 R6b 1 IC2 TL431 R9 10 k Gnd Figure 13. The Schematic of the 19 V/3 A Adapter Features a UC3843 with a TL431 on the Secondary Side The output voltage is regulated by a TL431 wired in a type2 configuration. The fast lane (optocoupler lane) and the slow lane (TL431 resistor divider) are separated by an LC filter which is placed to further attenuate the various high-frequency output spikes inherent to the flyback stages. In order to measure the loop response of our adapter with a network analyzer, we are going to use the method described in the first part of this document. The main advantage of this method lies in the measurement operations confined on the isolated secondary side only. We will first start by sweeping the slow lane, while the fast lane is biased to 19 V (output voltage value) with a dc voltage source (Figure 14): OUT Cout 2.4 m Lfilt 2.2 m Cfilt 100 m Gnd Vdd 19 V Rpullup 20 k Loop Output R6 33 Network Analyzer Source Rled 1k Loop Input FB Ch A Isolator Rupper 66 k Czero Cpole 1n RLoad Gnd 47 n Rlower 10 k Gnd Figure 14. The Slow Lane is Individually Biased while the Second Loop is ac Swept http://onsemi.com 8 Ch B AND8327/D ǒ The injection voltage source is implemented with a wideband isolation device and a 33 W resistor. Voltage probes are used to measure the loop input and output signals with respect to ground. The network analyzer directly computes Ǔ 20log 10 ChB ChA We obtained the Bode plots shown in Figure 15. Slow lane loop response 180 100 slow lane - gain Mag (dB) 144 60 108 40 72 20 36 0 0 -20 -36 -40 -72 -60 -108 -80 -144 -100 1.00E+01 Phase (°) slow lane - phase 80 -180 1.00E+02 1.00E+03 1.00E+04 1.00E+05 Freq (Hz) Figure 15. Slow Lane Loop Response Obtained with the Network Analyzer fp + Ǔ ǒ Ǔ (eq. 11) and 1 y 1 + 10 A 1ń20 sin ö 1 p 180 pR loadC out where Rload is the output load resistor and Cout is the sum of C5a and C5b (Figure 13). After fp, the power stage gain decreases with a -2 slope until it reaches the 8 kHz pole formed by (Rpullup, Cpole) of our type 2 compensator: f pc + ǒ x 1 + 10 A 1ń20 cos ö 1 p 180 The slow lane loop gain starts with a -1 slope because of the origin pole formed by (Rupper = R12+R10, Czero = C6). The power stage pole fp is around 20 Hz and corresponds to: (eq. 12) The Excel syntax corresponding to these equations are: x 1 + POWER(10; A 1ń20) @ COS(ö 1 @ PI()ń180) (eq. 13) x 2 + POWER(10; A 1ń20) @ SIN(ö 1 @ PI()ń180) (eq. 14) Further to slow lane measurement, we have to run the same operation for the fast lane loop. We inject the ac signal in the fast lane while the slow lane is disconnected from the output voltage and biased with a dc voltage source. This dc voltage must be manually adjusted to fix the operating point corresponding to the output load used. As the TL431 is very sensitive to small voltage variations, we can use a resistor between the dc source and the resistor divider to adjust the output voltage (See Figure 16). 1 2pR pullupC pole Now that we have the slow lane loop plot, we can paste the network analyzer data into excel. We have a 3-column data table with the frequency (Hz), magnitude (dB) and phase (degrees). Using Euler notation, we will calculate the real and the imaginary part of the slow lane vector: V out,slow + A 1(cosö 1 ) j sin ö 1) + x 1 ) jy 1 (eq. 10) Excel will compute the following formulas: http://onsemi.com 9 AND8327/D Lfilt Cfilt 100 m Loop Output Network Analyzer Ch B Ch A OUT 2.2 m R6 33 Source Isolator Vdd RLoad Gnd Gnd Loop Input DC Voltage Rled 1k Rpullup 20 k R7 ~19 V 20 k FB Rupper 66 k Czero 47 n Cpole 1n Rlower 10 k Gnd Figure 16. For the fast lane sweep, the slow lane is ac-decoupled from the converter output. Care must be taken to avoid output runaway during this measurement! Figure 17 details the fast lane loop response. The power stage pole fp is around 20 Hz and corresponds to: fp + f pc + 1 2pR pullupC pole On Figure 13 schematic, Cpole corresponds to C11 and the Rpullup resistor is R7. 1 pR loadC out After fp, the power stage gain decreases with a -1 slope until it reaches the 8 kHz pole formed by (Rpullup, Cpole) of our type 2 compensator: Fast lane loop response 180 100 fast lane - gain 144 fast lane - phase 60 108 40 72 20 36 0 0 -20 -36 -40 -72 -60 -108 -80 -144 -100 -180 1.00E+01 1.00E+02 1.00E+03 Freq (Hz) 1.00E+04 1.00E+05 Figure 17. Fast Lane Loop Response Obtained with the Network Analyzer. The Slow Lane is Externally Biased with a dc Power Supply http://onsemi.com 10 Phase (°) Mag (dB) 80 AND8327/D Once the network analyzer data has been exported to Excel, we compute the real and the imaginary parts of the fast lane loop vector: ǒ Ǔ ǒ Ǔ x 2 + 10 A 2ń20 cos ö 2 p 180 y 2 + 10 A 2ń20 sin ö 2 p 180 V FB + (x 1 ) x 2) ) j(y 1 ) y 2) + X ) jY (eq. 17) Finally, we extract the final loop gain and phase by entering Equations 8 and 9 in Excel: Loop gain + 20 * LOG(SQRT(X ƞ 2 ) Y ƞ 2); 10) (eq. 18) (eq. 15) Loop phase + DEGREES(ATAN(YńX)) (eq. 16) (eq. 19) Figure 18 shows the reconstructed loop gain and phase plots. Then we can sum the real and the imaginary contributions to obtain the total loop vector: Loop gain and phase 60 Final Mag (dB) Final Phase 40 120 20 0 -30 Phase (deg) 70 20 Magnitude (dB) 170 -20 -80 -40 -130 -60 -180 10 100 1000 10000 100000 Freq (Hz) Figure 18. The Final Bode Plot Combines the Information Obtained from Individual Loop Measurements Weighted Feedback on a Forward Converter Because the arctangent function is defined on a ]-90°; +90°[ interval, some parts of the resulting curve could exhibit a negative phase rotation caused by the calculation. We have corrected these particular points by adding 180° to their phase calculation result. The reconstructed Bode plot shows a clean response and does not differ from classical loop analysis carried on a current-mode converter. Let's now apply a similar methodology to a multi-output power supply: in such an application, two different voltage outputs are regulated using a common TL431, using a weighted sum configuration (see Figure 19). The resistors connecting each output to the TL431 reference pin are calculated taking into account a relative weight of each output in the feedback. http://onsemi.com 11 AND8327/D Vdd Vout 1 Rled Slow Lane 1 Rpullup Fast Lane Vout 2 R2 U2B R1 Slow Lane 2 C1 C2 U2A U1 TL431 R3 Primary Side Secondary Side Figure 19. The TL431 Wired in a Two-output Weighted Feedback Configuration This technique offers a way to improve cross-regulation in a multi-output converter by affecting a weight to certain outputs whose precision or load constraints are more important than the others. Of course, the sum of all weight must equal 100% at the end. In the ATX world, weighted feedback is often encountered in the so-called Silver boxes 350 V D5 1N4148 C1 220 n C21 1m C22 220 m R2 IRF350 1k T4 D3 MUR460 D4 MUR460 D6 1N4148 R4 R12d CS C7d 180 p 5k 1k R7 10 C3 1n R5 1k R9 27 M2 R12x 47 k Q2 D7 D8 R13 1k R6 0.3 ISO1 SFH610A C4d 1n C10 4.7 m 100 n D9 TL431 Figure 20. Schematic of the Two-switch Forward Power Supply featuring a Weighted Feedback with TL431 http://onsemi.com 12 5 V/ 15 A C7 2200 m C20 2200 m L3 0.47 m 12 V/ 15 A C8 2200 m C19 1200 m R100 10 R14 1k FB VCC C6 470 p C5 470 p 2N2907 L4 0.47 m L1 R10 27 MBR40H100 IRF350 47 Vdd MBR4045 M1 R11 47 k Q1 2N2907 D1 1N5818 DRV C4 1n R8 10 R3 47 T6 and Figure 20 represents a simplified two-output version of such a converter. In this 2-switch forward converter, the two outputs (5 V and 12 V) are also coupled via their respective output inductors. Each output contributes to 50% in the control loop, which uses a TL431 featuring a type 2 compensation. R101 10 R31 62 k C9 R16 10 k R12 25.8 k AND8327/D There are 2 loops we need to measure: one is a combination of the fast and slow lanes observing the +12 V output. The other one is the +5 V loop entering the TL431 via the slow lane. We have mentioned before that measuring the loop at the feedback input of the controller is not practical. As demonstrated in Ref. [3], in order to correctly measure the gain and phase of the feedback loop, the ac stimulus must be injected between a low impedance node (on the power supply output side) and a high impedance node (on the control side). When the injection is done as described previously, i.e. between the output of the power supply and the feedback circuitry, the condition is optimal: the output impedance of the observed point is low, and the input impedance of the feedback path is high. But if we want to open the loop between the optocoupler and the feedback pin of the controller, the conditions are not favorable: the output impedance of the optocoupler is high (this is the pull up resistor in a common-emitter configuration), whereas the input impedance of the FB pin can sometimes be affected by internal dividers or pull-up resistors (it was 5 kW in our example). We can anyway find a way to perform this measurement by inserting a buffer between the optocoupler and the controller as Figure 21 illustrates. Using an NPN transistor in a common-collector configuration, the output impedance is made low compared to the input impedance of the feedback pin. Figure 21. An NPN Buffer Allows Performing the Loop Gain Measurement on the Primary Side The result is plotted on Figure 22. This loop measurement done at the feedback pin is clearly not correct: the gain plateaus at low frequencies; and the phase increases again at higher frequencies, so much that the gain margin cannot be measured. This is clearly not a valid measurement. NPN buffer - gain Gain (dB) NPN buffer - phase Phase 80 180 60 135 40 90 20 45 0 0 -20 -45 -40 -90 -60 -135 -80 10 100 1000 10000 -180 F (Hz) 100000 Figure 22. Bode Plot Obtained using the NPN Buffer on the Primary Side http://onsemi.com 13 AND8327/D Figures23 and 24. Combining the two using the Excel® spreadsheet delivers the result of Figure 25. We will now measure one of the two loops independently, while biasing the other one with an external dc supply, as we did before. Individual measurement results are shown on fast + 12 V lanes gain fast + 12 V lanes phase Gain (dB) Phase 80 180 60 135 40 90 20 45 0 0 -20 -45 -40 -90 -60 -135 -80 10 100 1000 10000 -180 100000 F (Hz) Figure 23. Fast Lane and 12 V Slow Lane Loop Response Obtained with the Network Analyzer 5 V slow lane gain Gain (dB) Phase 5 V slow lane phase 80 180 60 135 40 90 20 45 0 0 -20 -45 -40 -90 -60 -135 -80 10 100 1000 10000 -180 100000 Figure 24. 5 V Slow Lane Loop Response Obtained with the Network Analyzer http://onsemi.com 14 F (Hz) AND8327/D Combined loops gain Gain (dB) Phase Combined loops phase 80 180 60 135 40 90 20 45 0 0 -20 -45 -40 -90 -60 -135 -80 -180 10 100 1000 10000 100000 F (Hz) Figure 25. The Final Bode Plot Combines the Information Obtained from Individual Loop Measurements As expected, the 2-loop measurement is now valid over the whole frequency range, with a constant slope of −20dB per decade for the gain at low frequency, and a phase that keeps on decreasing after the crossover frequency. To verify the validity of the approach, we have gathered Figure25 and Figure22 on a common graph which appears on Figure26. The gain and the phase curves in the vicinity of the cross over frequency are similar. Combined loops - gain NPN buffer - gain Combined loops - phase NPN buffer - phase Gain (dB) Phase 80 180 60 135 40 90 20 45 0 0 -20 -45 -40 -90 -60 -135 -80 -180 10 100 1000 10000 100000 F (Hz) Figure 26. Comparing the Combined Bode Plot Obtained from Individual Loop Measurements to the Primary Measurement (with NPN Buffer) http://onsemi.com 15 AND8327/D Conclusion References Measuring the frequency response of a multi-loop switch-mode power supply can be a real challenge, especially when all the regulation circuitry is kept on the secondary side. This is often the case with modern current mode controllers where the feedback input directly controls the peak current. Hopefully a simple method exists which combines individually measured loops with a simple mathematical manipulation. As demonstrated in this paper, this method is applicable to a wide range of applications. 1. D. Venable, “Stability Testing of Multi Loop Converters”, Venable technical paper #11 2. C. Basso, “Switch Mode Power Supplies: SPICE Simulations and Practical Designs”, McGraw-Hill, 2008 3. Middlebrook, R. D., “Measurement of Loop Gain in Feedback Systems, International J. of Electronics”, vol. 38, no. 1, pp. 485-512, April1975 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operat‐ ing parameters, including “Typicals” must be validated for each customer application by customer's technical experts. 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