AND8334/D
Understanding Loop
Compensation with
Monolithic Switchers
Prepared by: Christophe Basso
ON Semiconductor
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Introduction
Sensing the Inductor Current
Monolithic switchers, such as members of the NCP101X
or the NCP1027 series, associate a current-mode controller
and a power MOSFET on a single-die construction. Unlike
traditional solutions implementing an external sensing
resistor, these switchers embed everything inside the
package and can sometimes puzzle the power supply
designer looking for a familiar configuration. This
application note details what is inside these switchers and
will guide you on how to stabilize them using proven
compensation techniques.
All members of the NCP101X and NCP1027 series
implement the fixed-frequency peak current mode control
technique. This technique implies the cycle-by-cycle
sensing of the inductor current, its peak being controlled by
the feedback loop. The current information is usually
conveyed to the controller via a sensing element, the sense
resistor. Figure 1 represents a simplified view of a
current-mode controller using an external sense resistor:
dc rail
clock
L
Vdd
FB
S
Rpullup
R
DRV
Q
Q
CS
+
-
Cpole
/3
Rsense
VCS
1V
Figure 1. An External Sense Resistor Monitors the Current Circulating
in the Primary Inductor of this Flyback Power Supply
output reaches the target) or in short-circuit conditions. In
the vast majority of controllers, i.e. the NCP1200 series, this
voltage is clamped to 1 V. In that case, the maximum
inductor current IL is limited to:
The clock initiates a switching cycle by turning the
MOSFET on. The inductor current builds-up until it reaches
a level imposed by the feedback loop via the internal divider
by 3. At this point of time, the current sense comparator trips
and turns the MOSFET off until a new clock cycle occurs.
By adjusting the feedback level, the control loop has a means
to set the inductor peak current to cope with the input / output
operating conditions. A kind of active zener diode makes
sure the maximum voltage excursion across the sense
resistor cannot exceed a certain voltage in case the loop is
open. This happens during the startup sequence (until the
© Semiconductor Components Industries, LLC, 2008
July, 2008 − Rev. 0
I L,peak +
V CS
R sense
(eq. 1)
The internal divider by 3 increases the voltage excursion
on the optocoupler collector up to 3 V to offer a better
dynamics on the feedback pin while also improving the
converter noise immunity.
1
Publication Order Number:
AND8334/D
AND8334/D
The Need for Internal Sensing
away a small portion of the drain current at no power
dissipation expenses. Ref. [1] describes the technique for
discrete components. In a NCP101X switcher, the internal
schematic for the feedback section appears in Figure 2. We
can clearly see a similar configuration except that the
equivalent sense resistor is extremely small (178 mW) and
thus requires an internal voltage limit of 80 mV. For this
particular version, the NCP1014, the maximum peak current
is limited to:
In a monolithic switcher, there is no external sense
resistor. Why? First because the proprietary
ON Semiconductor Very High Voltage Integrated Circuit
(VHVIC) technology does not lend itself to the classical
positive current sensing technique as it appears on Figure 1.
Second, integration pushes the semiconductor vendors to
pack more elements inside the silicon die. The sense resistor
was a natural candidate for this move and is now part of the
controller. However, we are not exactly dealing with a sense
resistor. The retained technique is called Kelvin sensing. A
specific cell is added to the power MOSFET and “steals”
I L,peak +
80 m
+ 450 mA
178 m
(eq. 2)
D
+
4
Vref
reset
RFB
18 k
FB
/ 24
+
Cpole
80 mV
Req
178 m
VCS
GND
Figure 2. In a Monolithic Switcher, the Sense Resistor is Internal to
the Device. Here, an Example with the NCP101X Series
For other switcher versions within the 101X family, the internal equivalent sense resistor changes. We will have:
Device
Peak Current
Equivalent Sense Resistor
NCP1014
450 mA
178 mW
NCP1013
350 mA
228 mW
NCP1011/12
250 mA
320 mW
NCP1010
100 mA
800 mW
The NCP1027 series slightly differs in terms of
implementation but the idea remains the same. Figure 3
portrays the simplified internal circuitry of this recent
switcher where the internal equivalent sense resistor reaches
387 mW. In this particular case, the maximum peak current
is given by:
I L,peak +
310 m
+ 800 mA
387 m
D
+
FB
4
Vref
RFB
16 k
reset
/ 6.4
Cpole
+
310 mV
VCS
GND
Req
387 m
Figure 3. The NCP1027 Arrangement Follows That of the NCP101X Series. Here, a Simplified View
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2
(eq. 3)
AND8334/D
Small-Signal Modeling of the Switcher
D is the operating duty-cycle
Rsense is the internal sense resistor as described above
M is the conversion ratio
The fact that all functions (sensing, switching etc.) are
internally performed, does not change the small-signal
transfer function of a converter implementing such a
switcher. What is important are the values of some of the key
elements inside the switcher. These are the pull-up resistor,
the internal divider ratio and, finally, the equivalent sense
resistor value. Once we have these values on hand, we can
start looking at the small-signal response of the converter
under study. The technical literature abounds with
ready-to-use results of popular converter transfer functions.
Ref. [2] details some of them on page 225. For a flyback
converter, we need to identify the static gain G0, the various
frequency poles and zeros fp1/fz1 plus a right-half-plane zero
fz2 (RHPZ) if operated in CCM. First, we need to
differentiate the operating mode, Discontinuous
Conduction Mode (DCM) or Continuous Conduction Mode
(CCM) which influences the static gain G0 but also the
position of the poles and zeros.
DCM
G0 +
1
G FBR sense
f p1 +
1
ǸL R 2 F
p load sw
1
2pR ESRC out
G0 +
R load
R senseG FBN
Compensating a CCM Converter
Let us assume we have a CCM flyback converter
operating with the following component values:
Vin,min = 120 V
Vout = 12 V
Pout = 10 W
Rload = 14.4 W
Fsw = 65 kHz
(eq. 4)
Cout = 3000 mF
RESR = 100 mW
Lp = 3 mH
N = 0.177
For various considerations, we have selected a NCP1027
to perform the switching task. From its data-sheet
specifications and the above lines, we will extract the
relevant information we need:
GFB = 6.4
(eq. 6)
CCM
f p1 +
1
(1*D) 2
) 2M ) 1
tL
(1*D) 3
)1)D
tL
2pR loadC out
f z1 +
1
2pR ESRC out
f z2 +
(1 * D) 2 R load
2pDL pN 2
2L pN 2
R loadT sw
Please note that the CCM equations ignore the presence of
ramp compensation and do not include the presence of the
sub harmonic poles located at half the switching frequency.
Regarding the DCM equations, we did not consider the
presence of the high frequency pole and the RHPZ though
they exist in discontinuous.
(eq. 5)
pR loadC out
f z1 +
tL +
(eq. 7)
Rsense = 387 mW
Rpullup = 16 kW
We now have two choices: either we go through analytical
calculations only and we draw our Bode plot by hand or,
second option, we can use a dedicated SPICE model to avoid
using equations. Let’s try to combine both approaches, at
least to confirm that our SPICE model delivers results we
can trust for the analysis! From Equations 7 to 10, we have:
(eq. 8)
(eq. 9)
(eq. 10)
Where:
Lp is the primary inductance of the flyback transformer
N is the flyback transformer turns ratio Np:Ns
Cout is the output capacitor
GFB represents the internal feedback to current sense divider
RESR is the output capacitor equivalent series resistor
M+
D+
V out
12
+
12 ) 0.177
V out ) NV in
tL +
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3
V out
12
+
+ 0.564
0.177 120
NV in
(eq. 11)
+ 0.361
(eq. 12)
2 L pN 2
2 3 m 0.177 2
+
+ 0.848
R loadT sw
14.4 15.4 m
(eq. 13)
120
AND8334/D
G0 +
R load
R senseG FBN
1
(1−D) 2
) 2M ) 1
tL
+
0.387
14.4
6.4
1
0.177
(1−0.361) 2
)2
0.848
0.564 ) 1
+ 12.58
20 log 10 G 0 + 22 dB
(1−D) 3
)1)D
tL
f p1 +
2pR loadC out
f z1 +
f z2 +
+
(eq. 15)
(1−0.361) 3
) 1 ) 0.361
0.848
6.28
1
+
2pR ESRC out
6.28
14.4
1
100 m
(eq. 14)
+ 6.2 Hz
(eq. 16)
+ 530.5 Hz
(eq. 17)
3m
3m
(1 * D) 2 R load
(1 * 0.361) 2 14.4
+
+ 27 kHz
2
6.28 0.361 3 m 0.177 2
2pDL pN
(eq. 18)
With these results on hand, we can now try to run a simulation using an auto-toggling average model as the one derived in
Ref. [2]. Its open-loop configuration appears in Figure 4:
PWM switch CM
368 mV 6 a
DC
duty−cycle
parameters
Vout=12
Pout=10
5
vc
9
2
p
c
AC = 0
Vin
0V
120 X9
13
PWMCM
L = Lp
L1
830 mV
Fs = Fsw {Lp}
Ri = Ri
V5 830 m
Se = Se
120 V
Lp=3m
Ri=387m
Se=0
Fsw=65k
X3
GAIN
K = 156 m
129 mV
Gain
Rload=Vout^2/Pout
X2x
XFMR
D1 mbrd360t4
RATIO = −N
3
−70.1 V
4
10
12.4 V
R10
100m
12 V
1
C5
100 u
12 V
vout
Rload
{Rload}
N=177m
Figure 4. The Open-Loop Configuration of a Flyback Converter Using the NCP1027
You can note a slightly higher duty-cycle (36.8%) linked to the presence of the output diode whose forward drop affects the
efficiency. Figure 5 displays the Bode plot obtained when using the above configuration.
vdbout 8
7
180
ph_vout
21.9 dB
20
|H(s)|
0
10
vdbout in db(volts)
plot1
ph_vout in degrees
90
arg H(s) = −16°
arg H(s)
Sub harmonic
poles
0
−90
−10
−180
−20
f = 45°
f p1 = 6 Hz
|H(s)| = −16.7 dB
7
8
1
10
100
1k
frequency in hertz
3 kHz
10k
100k
Figure 5. The Open-loop Bode Plot Obtained from Figure 4 Simulation which Confirms our Calculations
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4
AND8334/D
example, 30% of the RHPZ implies a possible cross over
frequency up to 8 kHz. For the sake of simplicity, we will
limit our needs to a cross over value of 3 kHz where the
power stage phase lag is minimum. The idea is now to
extract the power stage insertion loss at 3 kHz and provide
the necessary compensation gain to reach 0 dB at 3 kHz.
From Figure 5, the gain loss is around –16.7 dB (0.146).
Analytically, we could also derive it this way:
Please note the presence of sub harmonic pole properly
predicted by the model despite a duty-cycle below 50%.
However, no damping is necessary in our case thus ramp
compensation is not needed.
The RHPZ expressed by Equation 18 limits the available
bandwidth. Practically, in a CCM design, we recommend a
cross over frequency which stays below 30% of the worse
case RHPZ position. Beyond this value, the phase stress
induced by the zero might become difficult to manage. In our
ȧ
ȧ ǒ1 * Ǔǒ1 ) Ǔȧ
ȧ
s
ȧ
ȧ
|H(s)| [ G 0
Ǹ
1)
s
s z2
s z1
1)s
s
p1
Ǹ
ȧ+ G
ȧ
1)
ŤH(3 kHz)Ť + 12.6
3k
27 k
Ǹ
fc
f z2
2
Ǹ
0
ǒ Ǔ
ǒ Ǔ Ǹ1 ) ǒ Ǔ
fc
f z1
1)
2
Ǹ
1)
1)
ǒ Ǔ
3k
6.2
ǒ Ǔ
2
3k
530
ǒ Ǔ
fc
f p2
2
(eq. 19)
2
2
+ 0.149
(eq. 20)
What is also important to know is the phase shift induced by the power stage at 3 kHz. From the Bode plot, we read –18°.
We can also obtain it analytically keeping in mind that Equation 19 does not include the sub harmonic poles contribution:
arg H(f c) + tan *1
ǒ Ǔ
ǒ Ǔ
ǒ Ǔ
fc
f
f
) tan *1 * c * tan *1 c
f z1
f z2
f p1
Based on these above numbers, we will need to provide
+16.7 dB of gain (≈7) at the selected 3 kHz frequency and
almost no phase boost given the weak phase rotation brought
by the power stage.
+ −16 o
(eq. 21)
Vout
Rpullup
FB
Rled
Compensating with the TL431
Rupper
The TL431 lends itself very well for a type−2
compensation where we need a pole at the origin, a single
pole and a single zero. The configuration of such system
appears in Figure 6. As shown in Ref. [2], it is possible to
show that the poles and zeros locations around Figure 6
configuration obey the following expressions:
G+
R pullup
R LED
CTR
1
2pR upperC zero
(eq. 23)
fz +
1
(eq. 24)
1
2pR pullupC pole
(eq. 25)
fp +
Cpole
Czero
U2
TL431
(eq. 22)
f po +
2pR upperC zero
U1
Rbias
1k
Rlower
Figure 6. A TL431 is used to implement a type-2
compensator. For noise immunity reasons, make
sure the Cpole capacitor is wired very close to the
switcher FB and GND pins.
The first thing to fix is the divider ratio Rupper and Rlower.
If we select a 250 mA bridge current (noise immunity is
correct and input bias errors are minimized), the network
values are easily found:
Where Rpullup is the internal pull-up resistor and CTR is the
optocoupler Current Transfer Ratio.
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R lower + 2.5 + 10 kW
250 m
(eq. 26)
R upper + 12 * 2.5 + 38 kW
250 m
(eq. 27)
AND8334/D
method was obtained [2], we first compute the necessary
phase boost:
If we consider a CTR of 1 for our optocoupler, we can
already calculate the LED resistor value:
R LED +
R pullup
G
CTR +
16 k
7
Boost + PM * PS * 90
1 + 2.3 kW (eq. 28)
(eq. 29)
Where PM is the phase margin we are looking for (70° in
our example). PS represents the phase shift brought by the
power stage at the cross over frequency (–16°) and –90
accounts for the origin pole phase rotation. Once the
numbers are plugged in, we find a boost of:
RLED not only fixes the loop gain but it also limits the
current excursion in the optocoupler LED when the TL431
is fully biased (Vout above the target). In that case, as its
cathode-anode voltage drops to 2.5 V, RLED must be
designed to offer enough current capability in the LED
during these transient events. It thus becomes another design
parameter. For 12 V output voltages, this is usually not a
problem, but for 5 V designs, it can be a challenge especially
for low CTR optocouplers. Please note the presence of Rbias
which makes sure the TL431 receives, at least, a 1 mA bias
current whatever the primary feedback current value is. This
added bias current is important to make sure the TL431
operates in a favorable zone where its open-loop gain is the
highest.
Finally, the optocoupler includes a pole whose position
depends on the pull-up resistor and other factors. This pole
lags the phase and can degrade the margin when it appears
in the loop path. It is the designer duty to make sure the
needed phase margin is not compromised once this
optocoupler is installed.
To boost the phase at the crossover frequency, we have to
install poles and zeros. The k-factor offers a possible method
to automatically calculate the poles and zeros location based
on a selected cross over frequency and a desired phase boost,
right at this point. The method works fine for 1st order
systems, such as DCM or CCM flyback converter operating
in current mode. Even if the k-factor is not a panacea, it will
at least help the inexperienced user find a stable point
quickly. Once the component values are found, you will
need to go in the laboratory and perform a bandwidth
measurement anyway to make sure the assumptions we took
during the calculations lead to the adequate phase/gain
margins. Without entering into the details on how the
Boost + 70 ) 16 * 90 + −4 o
(eq. 30)
A value below 0 in this particular example shows that no
phase boost is actually needed since the power stage phase
shift is low at the cross over point. As a matter of fact, a
simple type 1 would do the compensation job here which
corresponds to a k of 1. Let’s proceed with the calculation of
the k coefficient value:
ǒ
Ǔ
k + tan boost ) 45 [ 1
2
(eq. 31)
The k-factor now recommends to evenly spread the pole
and the zero by choosing the cross over frequency as the
geometric mean between them. As no phase boost is
required and k is 1, the pole and zero will simply be
coincident at 3 kHz:
f p + kf c + 1
fz +
3 k + 3 kHz
3k
fc
+
+ 3 kHz
1
k
(eq. 32)
(eq. 33)
Applying Equations 23 − 25, we obtain the following
values on the TL431:
C zero +
1
+
2pR upperf z
6.28
1
38 k
3k
C pole +
1
+
2pR pullupf p
6.28
1
16 k
3k
+ 1.4 nF (eq. 34)
+ 3.3 nF (eq. 35)
We can now take these values and capture a fully
closed-loop circuitry as it appears in Figure 7:
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AND8334/D
PWM switch CM
parameters
6
Vout=12
Pout=10
2
Ibridge=250u
Rlower=2.5/Ibridge
Rupper=(Vout−2.5)/Ibridge
a
vc
DC
duty−cycle
X2x
XFMR
D1
RATIO = −N
p
c
AC = 0
Vin
120 X9
13
PWMCM
L = Lp
L1
Fs = Fsw {Lp}
Ri = Ri
Se = Se
Lp=3m
Ri=387m
Se=0
Fsw=65k
Rload=Vout^2/Pout
N=177m
3
4
vout
mbrd360t4
vout
R10
100m
Rload
{Rload}
1
8
C5
3m
B1
Voltage
V(err)/6.4 > 0.31 ?
0.31 : V(err)/6.4
Vdd
5
vout
5
fc=3k
pm=70
Gfc=−17
pfc=−16
Rpullup
{Rpullup}
G=10^(−Gfc/20)
boost=pm−(pfc)−90
pi=3.14159
K=tan((boost/2+45)*pi/180)
Verr
11
LoL
err
Fzero=fc/k
Fpole=k*fc
18
X7
Optocoupler
Cpole = 1/
(6.28*pole*pullup)
CTR = CTR
1kH
Cpole2
{Cpole}
Rpullup=16k
RLED=CTR*Rpullup/G
Czero=1/(2*pi*Fzero*Rupper)
Cpole=1/(2*pi*Fpole*Rpullup)
14
15
CoL
1kF
9
Vstim
AC = 1
CTR=1
Pole=60k
Rled
{Rled}
10
Rupper2
{Rupper}
Czero1 {Czero}
X10
TL431_G
Rlower2
{Rlower}
Figure 7. The Complete Converter Featuring the TL431 used to Control the Feedback Loop
In this sheet, all parameters calculations are automated on the left side. The optocoupler parameters are purposely disabled for
the simplicity of the analysis. They should actually be characterized and the associated pole must take place in the loop study [2].
52 ph_verr
50 vdberr
90
40
0
vdberr in db(volts)
80
plot1
ph_verr in degrees
180
|T(s)|
PM = 65°
0
arg T(s)
fc ≈ 3 kHz
−90
−40
50
−180
−80
52
10
100
1k
frequency in hertz
10k
100k
Figure 8. The Compensated Loop Gain T(s) once the Type-1 Circuit has been Implemented with the TL431
As Figure 8 testifies, the compensated loop gain looks stable with a phase margin of 65° at the crossover frequency.
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AND8334/D
Compensating with the TL431, DCM
“If I do not have the time to run simulations and analytical
calculations?” Well, it is not advised to proceed this way but
a simple quick and dirty compensation is to place a 100 nF
capacitor for Czero, put RLED to 1 kW and Cpole to 10 nF. It
won’t be an optimally compensated design, but it should at
least help you debug the board during the test experiments.
Of course, you will still have to measure the loop and make
sure enough phase margin is provided at the cross over point
whatever input and output conditions.
R load
L p,crit +
2F swN 2
ǒ
V in
V in )
V
Ǔ
out
N
In DCM, the converter remains a 1st order system and
there are no sub harmonic poles. Let’s assume we have the
following converter design, actually similar to the previous
one but where the primary inductor has been reduced. What
inductor value shall we use to enter DCM? Let’s calculate
the critical value:
2
+
2
ǒ
120
14.4
65 k 0.177 2 120 ) 12
0.177
Ǔ
2
+ 1.4 mH
(eq. 36)
We can select a 1 mH inductor which will give us a static gain G0 of 18.8 dB (D = 0.3 in DCM). Reconstructing the full Bode
plot this time using Mathcad® (Figure 9) and involving the RHPZ with the second pole (Equations 4, 5 and 6), it gives us a
gain loss at 3 kHz of –18 dB (0.126) with a phase deficit of −17°.
20
10
20 @ log(|Gfly(i @ 2p @ f)|, 10)
50
0
0
−10
−50
−20
−30
arg(Gfly(i @ 2p @ f)) @ 180
p
10
100
1 X 103
f
1 X 104
1 X 105
Figure 9. The Flyback Operated in DCM gives a First Order Response in the Low Frequency Portion
Vout
The method we disclosed in the previous lines still
applies. We need to calculate the LED resistor to compensate
the –18 dB loss which corresponds to a gain of +18 dB or a
factor 8:
R LED +
R pullup
G
CTR +
16 k
8
FB
R2
470
D1
1N962
1 + 2 kW (eq. 37)
C1
10 n
Given the low deficit of phase at the 3-kHz cross over
frequency, we still use a type-1 compensator where both
poles and zeros are coincident. Therefore, Equations 34 and
35 results are still valid for this DCM converter.
Primary Regulation with a Switcher
Q1
2N3904
R1
820
Figure 10. A Simple Transistor Can do the Feedback
Job in a Non-isolated Converter configuration
Primary regulation is often used in low-cost ac-dc or dc-dc
applications. Despite the signal polarity on the feedback pin,
a simple inversion can put it the right way. We have two
options to generate an inverted signal. Figure 10 portrays an
inversion made through a simple NPN transistor. Wired in
a common-emitter configuration, the feedback pin is pulled
down when the zener voltage is exceeded. The LED current
and the collector current are now linked by the transistor beta
which not only changes in temperature but also varies
widely from lot to lot.
The lower side resistor R1 adjusts the bias current in the
zener diode. It is recommended to check its data-sheet in
order to select a current making it working far from its knee,
e.g. with a bias current around the milliampere. R2 sets the
dc gain of the stage together with the pull-up resistor and the
transistor beta. It also offsets the output voltage by the bias
current:
V out + V BE )
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V BE
R ) VZ
R1 2
(eq. 38)
AND8334/D
A possible alternative to improve the performance and the
stability lies in using a current-mirror as described by
Figure 11.
In this case, the zener current is simply conveyed on Q1
collector without any gain if both transistors are properly
paired. The best is to use a dual transistor device (e.g. a
BC846BDW1T1G) where both transistors share a common
die temperature and ensure the best performance for this
kind of application. On the example, a 820 W resistor
imposes a zener current of roughly 0.65/820 = 790 mA which
can be further tweaked if necessary.
This configuration can also be applied to a buck converter
such a the ones used in white goods applications where
isolation is not necessary. Figure 12 details the approach:
DRAIN
Vin
Vout
FB
R2
470
BC846BDW1T1
C1
10 n
Q1
Figure 11. A Current Mirror Duplicates the LED
Current as a Simple Optocoupler Device would Do
FB
1N4937
12 V
C10
1 nF
VCC
Q6
2N2222
Q5
2N2222
R9
1k
GND
+
C1
R1
820
Q2
D5
D6
+
Cbulk
D1
1N962
+
C7
10 mF
Lbuck
D7
1N4937
10 mF
+
Vout
C9
47 mF
Figure 12. The Current Mirror can also be Implemented in a Buck
Configuration, Here with a NCP101X Switcher
Conclusion
References:
The stabilization of ON Semiconductor switcher series
NCP101X or NCP1027 does not differ that much from other
current-mode controllers as long as one understands the
internal implementation. Once the designer knows the
values of the current sense resistor and its associated
feedback divider, the loop stability study can be quickly
undertaken via classical analytical design techniques or by
using a SPICE simulator and the available small-signal
models.
1. “Current Sensing Power MOSFETs”, Application
Note AND8093D, ON Semiconductor
2. C. Basso, “Switch Mode Power Supplies: SPICE
Simulations and Practical Designs”, McGraw-Hill
2008
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